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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * i.MX drm driver - LVDS display bridge
4 *
5 * Copyright (C) 2012 Sascha Hauer, Pengutronix
6 */
7
8#include <linux/clk.h>
9#include <linux/component.h>
10#include <linux/i2c.h>
11#include <linux/media-bus-format.h>
12#include <linux/mfd/syscon.h>
13#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/of_graph.h>
17#include <linux/regmap.h>
18#include <linux/videodev2.h>
19
20#include <video/of_display_timing.h>
21#include <video/of_videomode.h>
22
23#include <drm/drm_atomic.h>
24#include <drm/drm_atomic_helper.h>
25#include <drm/drm_bridge.h>
26#include <drm/drm_edid.h>
27#include <drm/drm_managed.h>
28#include <drm/drm_of.h>
29#include <drm/drm_panel.h>
30#include <drm/drm_print.h>
31#include <drm/drm_probe_helper.h>
32#include <drm/drm_simple_kms_helper.h>
33
34#include "imx-drm.h"
35
36#define DRIVER_NAME "imx-ldb"
37
38#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
39#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
40#define LDB_CH0_MODE_EN_MASK (3 << 0)
41#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
42#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
43#define LDB_CH1_MODE_EN_MASK (3 << 2)
44#define LDB_SPLIT_MODE_EN (1 << 4)
45#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
46#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
47#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
48#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
49#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
50#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
51#define LDB_BGREF_RMODE_INT (1 << 15)
52
53struct imx_ldb_channel;
54
55struct imx_ldb_encoder {
56 struct drm_connector connector;
57 struct drm_encoder encoder;
58 struct imx_ldb_channel *channel;
59};
60
61struct imx_ldb;
62
63struct imx_ldb_channel {
64 struct imx_ldb *ldb;
65
66 /* Defines what is connected to the ldb, only one at a time */
67 struct drm_panel *panel;
68 struct drm_bridge *bridge;
69
70 struct device_node *child;
71 struct i2c_adapter *ddc;
72 int chno;
73 void *edid;
74 struct drm_display_mode mode;
75 int mode_valid;
76 u32 bus_format;
77 u32 bus_flags;
78};
79
80static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c)
81{
82 return container_of(c, struct imx_ldb_encoder, connector)->channel;
83}
84
85static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e)
86{
87 return container_of(e, struct imx_ldb_encoder, encoder)->channel;
88}
89
90struct bus_mux {
91 int reg;
92 int shift;
93 int mask;
94};
95
96struct imx_ldb {
97 struct regmap *regmap;
98 struct device *dev;
99 struct imx_ldb_channel channel[2];
100 struct clk *clk[2]; /* our own clock */
101 struct clk *clk_sel[4]; /* parent of display clock */
102 struct clk *clk_parent[4]; /* original parent of clk_sel */
103 struct clk *clk_pll[2]; /* upstream clock we can adjust */
104 u32 ldb_ctrl;
105 const struct bus_mux *lvds_mux;
106};
107
108static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch,
109 u32 bus_format)
110{
111 struct imx_ldb *ldb = imx_ldb_ch->ldb;
112 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
113
114 switch (bus_format) {
115 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
116 break;
117 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
118 if (imx_ldb_ch->chno == 0 || dual)
119 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
120 if (imx_ldb_ch->chno == 1 || dual)
121 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
122 break;
123 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
124 if (imx_ldb_ch->chno == 0 || dual)
125 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
126 LDB_BIT_MAP_CH0_JEIDA;
127 if (imx_ldb_ch->chno == 1 || dual)
128 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
129 LDB_BIT_MAP_CH1_JEIDA;
130 break;
131 }
132}
133
134static int imx_ldb_connector_get_modes(struct drm_connector *connector)
135{
136 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
137 int num_modes;
138
139 num_modes = drm_panel_get_modes(imx_ldb_ch->panel, connector);
140 if (num_modes > 0)
141 return num_modes;
142
143 if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
144 imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
145
146 if (imx_ldb_ch->edid) {
147 drm_connector_update_edid_property(connector,
148 imx_ldb_ch->edid);
149 num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
150 }
151
152 if (imx_ldb_ch->mode_valid) {
153 struct drm_display_mode *mode;
154
155 mode = drm_mode_duplicate(connector->dev, &imx_ldb_ch->mode);
156 if (!mode)
157 return -EINVAL;
158 mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
159 drm_mode_probed_add(connector, mode);
160 num_modes++;
161 }
162
163 return num_modes;
164}
165
166static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
167 unsigned long serial_clk, unsigned long di_clk)
168{
169 int ret;
170
171 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
172 clk_get_rate(ldb->clk_pll[chno]), serial_clk);
173 clk_set_rate(ldb->clk_pll[chno], serial_clk);
174
175 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
176 clk_get_rate(ldb->clk_pll[chno]));
177
178 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
179 clk_get_rate(ldb->clk[chno]),
180 (long int)di_clk);
181 clk_set_rate(ldb->clk[chno], di_clk);
182
183 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
184 clk_get_rate(ldb->clk[chno]));
185
186 /* set display clock mux to LDB input clock */
187 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
188 if (ret)
189 dev_err(ldb->dev,
190 "unable to set di%d parent clock to ldb_di%d\n", mux,
191 chno);
192}
193
194static void imx_ldb_encoder_enable(struct drm_encoder *encoder)
195{
196 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
197 struct imx_ldb *ldb = imx_ldb_ch->ldb;
198 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
199 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
200
201 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
202 dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
203 return;
204 }
205
206 drm_panel_prepare(imx_ldb_ch->panel);
207
208 if (dual) {
209 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);
210 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);
211
212 clk_prepare_enable(ldb->clk[0]);
213 clk_prepare_enable(ldb->clk[1]);
214 } else {
215 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);
216 }
217
218 if (imx_ldb_ch == &ldb->channel[0] || dual) {
219 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
220 if (mux == 0 || ldb->lvds_mux)
221 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
222 else if (mux == 1)
223 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
224 }
225 if (imx_ldb_ch == &ldb->channel[1] || dual) {
226 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
227 if (mux == 1 || ldb->lvds_mux)
228 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
229 else if (mux == 0)
230 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
231 }
232
233 if (ldb->lvds_mux) {
234 const struct bus_mux *lvds_mux = NULL;
235
236 if (imx_ldb_ch == &ldb->channel[0])
237 lvds_mux = &ldb->lvds_mux[0];
238 else if (imx_ldb_ch == &ldb->channel[1])
239 lvds_mux = &ldb->lvds_mux[1];
240
241 regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
242 mux << lvds_mux->shift);
243 }
244
245 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
246
247 drm_panel_enable(imx_ldb_ch->panel);
248}
249
250static void
251imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder,
252 struct drm_crtc_state *crtc_state,
253 struct drm_connector_state *connector_state)
254{
255 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
256 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
257 struct imx_ldb *ldb = imx_ldb_ch->ldb;
258 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
259 unsigned long serial_clk;
260 unsigned long di_clk = mode->clock * 1000;
261 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
262 u32 bus_format = imx_ldb_ch->bus_format;
263
264 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
265 dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
266 return;
267 }
268
269 if (mode->clock > 170000) {
270 dev_warn(ldb->dev,
271 "%s: mode exceeds 170 MHz pixel clock\n", __func__);
272 }
273 if (mode->clock > 85000 && !dual) {
274 dev_warn(ldb->dev,
275 "%s: mode exceeds 85 MHz pixel clock\n", __func__);
276 }
277
278 if (!IS_ALIGNED(mode->hdisplay, 8)) {
279 dev_warn(ldb->dev,
280 "%s: hdisplay does not align to 8 byte\n", __func__);
281 }
282
283 if (dual) {
284 serial_clk = 3500UL * mode->clock;
285 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
286 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
287 } else {
288 serial_clk = 7000UL * mode->clock;
289 imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
290 di_clk);
291 }
292
293 /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
294 if (imx_ldb_ch == &ldb->channel[0] || dual) {
295 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
296 ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
297 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
298 ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
299 }
300 if (imx_ldb_ch == &ldb->channel[1] || dual) {
301 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
302 ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
303 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
304 ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
305 }
306
307 if (!bus_format) {
308 struct drm_connector *connector = connector_state->connector;
309 struct drm_display_info *di = &connector->display_info;
310
311 if (di->num_bus_formats)
312 bus_format = di->bus_formats[0];
313 }
314 imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format);
315}
316
317static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
318{
319 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
320 struct imx_ldb *ldb = imx_ldb_ch->ldb;
321 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
322 int mux, ret;
323
324 drm_panel_disable(imx_ldb_ch->panel);
325
326 if (imx_ldb_ch == &ldb->channel[0] || dual)
327 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
328 if (imx_ldb_ch == &ldb->channel[1] || dual)
329 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
330
331 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
332
333 if (dual) {
334 clk_disable_unprepare(ldb->clk[0]);
335 clk_disable_unprepare(ldb->clk[1]);
336 }
337
338 if (ldb->lvds_mux) {
339 const struct bus_mux *lvds_mux = NULL;
340
341 if (imx_ldb_ch == &ldb->channel[0])
342 lvds_mux = &ldb->lvds_mux[0];
343 else if (imx_ldb_ch == &ldb->channel[1])
344 lvds_mux = &ldb->lvds_mux[1];
345
346 regmap_read(ldb->regmap, lvds_mux->reg, &mux);
347 mux &= lvds_mux->mask;
348 mux >>= lvds_mux->shift;
349 } else {
350 mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
351 }
352
353 /* set display clock mux back to original input clock */
354 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
355 if (ret)
356 dev_err(ldb->dev,
357 "unable to set di%d parent clock to original parent\n",
358 mux);
359
360 drm_panel_unprepare(imx_ldb_ch->panel);
361}
362
363static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder,
364 struct drm_crtc_state *crtc_state,
365 struct drm_connector_state *conn_state)
366{
367 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
368 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
369 struct drm_display_info *di = &conn_state->connector->display_info;
370 u32 bus_format = imx_ldb_ch->bus_format;
371
372 /* Bus format description in DT overrides connector display info. */
373 if (!bus_format && di->num_bus_formats) {
374 bus_format = di->bus_formats[0];
375 imx_crtc_state->bus_flags = di->bus_flags;
376 } else {
377 bus_format = imx_ldb_ch->bus_format;
378 imx_crtc_state->bus_flags = imx_ldb_ch->bus_flags;
379 }
380 switch (bus_format) {
381 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
382 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
383 break;
384 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
385 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
386 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
387 break;
388 default:
389 return -EINVAL;
390 }
391
392 imx_crtc_state->di_hsync_pin = 2;
393 imx_crtc_state->di_vsync_pin = 3;
394
395 return 0;
396}
397
398
399static const struct drm_connector_funcs imx_ldb_connector_funcs = {
400 .fill_modes = drm_helper_probe_single_connector_modes,
401 .destroy = imx_drm_connector_destroy,
402 .reset = drm_atomic_helper_connector_reset,
403 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
404 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
405};
406
407static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
408 .get_modes = imx_ldb_connector_get_modes,
409};
410
411static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
412 .atomic_mode_set = imx_ldb_encoder_atomic_mode_set,
413 .enable = imx_ldb_encoder_enable,
414 .disable = imx_ldb_encoder_disable,
415 .atomic_check = imx_ldb_encoder_atomic_check,
416};
417
418static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
419{
420 char clkname[16];
421
422 snprintf(clkname, sizeof(clkname), "di%d", chno);
423 ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
424 if (IS_ERR(ldb->clk[chno]))
425 return PTR_ERR(ldb->clk[chno]);
426
427 snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
428 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
429
430 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
431}
432
433static int imx_ldb_register(struct drm_device *drm,
434 struct imx_ldb_channel *imx_ldb_ch)
435{
436 struct imx_ldb *ldb = imx_ldb_ch->ldb;
437 struct imx_ldb_encoder *ldb_encoder;
438 struct drm_connector *connector;
439 struct drm_encoder *encoder;
440 int ret;
441
442 ldb_encoder = drmm_simple_encoder_alloc(drm, struct imx_ldb_encoder,
443 encoder, DRM_MODE_ENCODER_LVDS);
444 if (IS_ERR(ldb_encoder))
445 return PTR_ERR(ldb_encoder);
446
447 ldb_encoder->channel = imx_ldb_ch;
448 connector = &ldb_encoder->connector;
449 encoder = &ldb_encoder->encoder;
450
451 ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child);
452 if (ret)
453 return ret;
454
455 ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
456 if (ret)
457 return ret;
458
459 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
460 ret = imx_ldb_get_clk(ldb, 1);
461 if (ret)
462 return ret;
463 }
464
465 drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs);
466
467 if (imx_ldb_ch->bridge) {
468 ret = drm_bridge_attach(encoder, imx_ldb_ch->bridge, NULL, 0);
469 if (ret)
470 return ret;
471 } else {
472 /*
473 * We want to add the connector whenever there is no bridge
474 * that brings its own, not only when there is a panel. For
475 * historical reasons, the ldb driver can also work without
476 * a panel.
477 */
478 drm_connector_helper_add(connector,
479 &imx_ldb_connector_helper_funcs);
480 drm_connector_init_with_ddc(drm, connector,
481 &imx_ldb_connector_funcs,
482 DRM_MODE_CONNECTOR_LVDS,
483 imx_ldb_ch->ddc);
484 drm_connector_attach_encoder(connector, encoder);
485 }
486
487 return 0;
488}
489
490struct imx_ldb_bit_mapping {
491 u32 bus_format;
492 u32 datawidth;
493 const char * const mapping;
494};
495
496static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
497 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" },
498 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" },
499 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
500};
501
502static u32 of_get_bus_format(struct device *dev, struct device_node *np)
503{
504 const char *bm;
505 u32 datawidth = 0;
506 int ret, i;
507
508 ret = of_property_read_string(np, "fsl,data-mapping", &bm);
509 if (ret < 0)
510 return ret;
511
512 of_property_read_u32(np, "fsl,data-width", &datawidth);
513
514 for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
515 if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
516 datawidth == imx_ldb_bit_mappings[i].datawidth)
517 return imx_ldb_bit_mappings[i].bus_format;
518 }
519
520 dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
521
522 return -ENOENT;
523}
524
525static struct bus_mux imx6q_lvds_mux[2] = {
526 {
527 .reg = IOMUXC_GPR3,
528 .shift = 6,
529 .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
530 }, {
531 .reg = IOMUXC_GPR3,
532 .shift = 8,
533 .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
534 }
535};
536
537/*
538 * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
539 * of_match_device will walk through this list and take the first entry
540 * matching any of its compatible values. Therefore, the more generic
541 * entries (in this case fsl,imx53-ldb) need to be ordered last.
542 */
543static const struct of_device_id imx_ldb_dt_ids[] = {
544 { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
545 { .compatible = "fsl,imx53-ldb", .data = NULL, },
546 { }
547};
548MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
549
550static int imx_ldb_panel_ddc(struct device *dev,
551 struct imx_ldb_channel *channel, struct device_node *child)
552{
553 struct device_node *ddc_node;
554 const u8 *edidp;
555 int ret;
556
557 ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
558 if (ddc_node) {
559 channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
560 of_node_put(ddc_node);
561 if (!channel->ddc) {
562 dev_warn(dev, "failed to get ddc i2c adapter\n");
563 return -EPROBE_DEFER;
564 }
565 }
566
567 if (!channel->ddc) {
568 int edid_len;
569
570 /* if no DDC available, fallback to hardcoded EDID */
571 dev_dbg(dev, "no ddc available\n");
572
573 edidp = of_get_property(child, "edid", &edid_len);
574 if (edidp) {
575 channel->edid = kmemdup(edidp, edid_len, GFP_KERNEL);
576 if (!channel->edid)
577 return -ENOMEM;
578 } else if (!channel->panel) {
579 /* fallback to display-timings node */
580 ret = of_get_drm_display_mode(child,
581 &channel->mode,
582 &channel->bus_flags,
583 OF_USE_NATIVE_MODE);
584 if (!ret)
585 channel->mode_valid = 1;
586 }
587 }
588 return 0;
589}
590
591static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
592{
593 struct drm_device *drm = data;
594 struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
595 int ret;
596 int i;
597
598 for (i = 0; i < 2; i++) {
599 struct imx_ldb_channel *channel = &imx_ldb->channel[i];
600
601 if (!channel->ldb)
602 continue;
603
604 ret = imx_ldb_register(drm, channel);
605 if (ret)
606 return ret;
607 }
608
609 return 0;
610}
611
612static const struct component_ops imx_ldb_ops = {
613 .bind = imx_ldb_bind,
614};
615
616static int imx_ldb_probe(struct platform_device *pdev)
617{
618 struct device *dev = &pdev->dev;
619 struct device_node *np = dev->of_node;
620 const struct of_device_id *of_id = of_match_device(imx_ldb_dt_ids, dev);
621 struct device_node *child;
622 struct imx_ldb *imx_ldb;
623 int dual;
624 int ret;
625 int i;
626
627 imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
628 if (!imx_ldb)
629 return -ENOMEM;
630
631 imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
632 if (IS_ERR(imx_ldb->regmap)) {
633 dev_err(dev, "failed to get parent regmap\n");
634 return PTR_ERR(imx_ldb->regmap);
635 }
636
637 /* disable LDB by resetting the control register to POR default */
638 regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0);
639
640 imx_ldb->dev = dev;
641
642 if (of_id)
643 imx_ldb->lvds_mux = of_id->data;
644
645 dual = of_property_read_bool(np, "fsl,dual-channel");
646 if (dual)
647 imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
648
649 /*
650 * There are three different possible clock mux configurations:
651 * i.MX53: ipu1_di0_sel, ipu1_di1_sel
652 * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
653 * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
654 * Map them all to di0_sel...di3_sel.
655 */
656 for (i = 0; i < 4; i++) {
657 char clkname[16];
658
659 sprintf(clkname, "di%d_sel", i);
660 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
661 if (IS_ERR(imx_ldb->clk_sel[i])) {
662 ret = PTR_ERR(imx_ldb->clk_sel[i]);
663 imx_ldb->clk_sel[i] = NULL;
664 break;
665 }
666
667 imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
668 }
669 if (i == 0)
670 return ret;
671
672 for_each_child_of_node(np, child) {
673 struct imx_ldb_channel *channel;
674 int bus_format;
675
676 ret = of_property_read_u32(child, "reg", &i);
677 if (ret || i < 0 || i > 1) {
678 ret = -EINVAL;
679 goto free_child;
680 }
681
682 if (!of_device_is_available(child))
683 continue;
684
685 if (dual && i > 0) {
686 dev_warn(dev, "dual-channel mode, ignoring second output\n");
687 continue;
688 }
689
690 channel = &imx_ldb->channel[i];
691 channel->ldb = imx_ldb;
692 channel->chno = i;
693
694 /*
695 * The output port is port@4 with an external 4-port mux or
696 * port@2 with the internal 2-port mux.
697 */
698 ret = drm_of_find_panel_or_bridge(child,
699 imx_ldb->lvds_mux ? 4 : 2, 0,
700 &channel->panel, &channel->bridge);
701 if (ret && ret != -ENODEV)
702 goto free_child;
703
704 /* panel ddc only if there is no bridge */
705 if (!channel->bridge) {
706 ret = imx_ldb_panel_ddc(dev, channel, child);
707 if (ret)
708 goto free_child;
709 }
710
711 bus_format = of_get_bus_format(dev, child);
712 if (bus_format == -EINVAL) {
713 /*
714 * If no bus format was specified in the device tree,
715 * we can still get it from the connected panel later.
716 */
717 if (channel->panel && channel->panel->funcs &&
718 channel->panel->funcs->get_modes)
719 bus_format = 0;
720 }
721 if (bus_format < 0) {
722 dev_err(dev, "could not determine data mapping: %d\n",
723 bus_format);
724 ret = bus_format;
725 goto free_child;
726 }
727 channel->bus_format = bus_format;
728 channel->child = child;
729 }
730
731 platform_set_drvdata(pdev, imx_ldb);
732
733 return component_add(&pdev->dev, &imx_ldb_ops);
734
735free_child:
736 of_node_put(child);
737 return ret;
738}
739
740static int imx_ldb_remove(struct platform_device *pdev)
741{
742 struct imx_ldb *imx_ldb = platform_get_drvdata(pdev);
743 int i;
744
745 for (i = 0; i < 2; i++) {
746 struct imx_ldb_channel *channel = &imx_ldb->channel[i];
747
748 kfree(channel->edid);
749 i2c_put_adapter(channel->ddc);
750 }
751
752 component_del(&pdev->dev, &imx_ldb_ops);
753 return 0;
754}
755
756static struct platform_driver imx_ldb_driver = {
757 .probe = imx_ldb_probe,
758 .remove = imx_ldb_remove,
759 .driver = {
760 .of_match_table = imx_ldb_dt_ids,
761 .name = DRIVER_NAME,
762 },
763};
764
765module_platform_driver(imx_ldb_driver);
766
767MODULE_DESCRIPTION("i.MX LVDS driver");
768MODULE_AUTHOR("Sascha Hauer, Pengutronix");
769MODULE_LICENSE("GPL");
770MODULE_ALIAS("platform:" DRIVER_NAME);