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1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/delay.h>
30#include <linux/hdmi.h>
31#include <linux/i2c.h>
32#include <linux/slab.h>
33#include <linux/string_helpers.h>
34
35#include <drm/display/drm_hdcp_helper.h>
36#include <drm/display/drm_hdmi_helper.h>
37#include <drm/display/drm_scdc_helper.h>
38#include <drm/drm_atomic_helper.h>
39#include <drm/drm_crtc.h>
40#include <drm/drm_edid.h>
41#include <drm/drm_probe_helper.h>
42#include <drm/intel/intel_lpe_audio.h>
43
44#include <media/cec-notifier.h>
45
46#include "g4x_hdmi.h"
47#include "i915_drv.h"
48#include "i915_reg.h"
49#include "intel_atomic.h"
50#include "intel_audio.h"
51#include "intel_connector.h"
52#include "intel_cx0_phy.h"
53#include "intel_ddi.h"
54#include "intel_de.h"
55#include "intel_display_driver.h"
56#include "intel_display_types.h"
57#include "intel_dp.h"
58#include "intel_gmbus.h"
59#include "intel_hdcp.h"
60#include "intel_hdcp_regs.h"
61#include "intel_hdcp_shim.h"
62#include "intel_hdmi.h"
63#include "intel_lspcon.h"
64#include "intel_panel.h"
65#include "intel_pfit.h"
66#include "intel_snps_phy.h"
67
68static void
69assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
70{
71 struct intel_display *display = to_intel_display(intel_hdmi);
72 u32 enabled_bits;
73
74 enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
75
76 drm_WARN(display->drm,
77 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits,
78 "HDMI port enabled, expecting disabled\n");
79}
80
81static void
82assert_hdmi_transcoder_func_disabled(struct intel_display *display,
83 enum transcoder cpu_transcoder)
84{
85 drm_WARN(display->drm,
86 intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &
87 TRANS_DDI_FUNC_ENABLE,
88 "HDMI transcoder function enabled, expecting disabled\n");
89}
90
91static u32 g4x_infoframe_index(unsigned int type)
92{
93 switch (type) {
94 case HDMI_PACKET_TYPE_GAMUT_METADATA:
95 return VIDEO_DIP_SELECT_GAMUT;
96 case HDMI_INFOFRAME_TYPE_AVI:
97 return VIDEO_DIP_SELECT_AVI;
98 case HDMI_INFOFRAME_TYPE_SPD:
99 return VIDEO_DIP_SELECT_SPD;
100 case HDMI_INFOFRAME_TYPE_VENDOR:
101 return VIDEO_DIP_SELECT_VENDOR;
102 default:
103 MISSING_CASE(type);
104 return 0;
105 }
106}
107
108static u32 g4x_infoframe_enable(unsigned int type)
109{
110 switch (type) {
111 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
112 return VIDEO_DIP_ENABLE_GCP;
113 case HDMI_PACKET_TYPE_GAMUT_METADATA:
114 return VIDEO_DIP_ENABLE_GAMUT;
115 case DP_SDP_VSC:
116 return 0;
117 case DP_SDP_ADAPTIVE_SYNC:
118 return 0;
119 case HDMI_INFOFRAME_TYPE_AVI:
120 return VIDEO_DIP_ENABLE_AVI;
121 case HDMI_INFOFRAME_TYPE_SPD:
122 return VIDEO_DIP_ENABLE_SPD;
123 case HDMI_INFOFRAME_TYPE_VENDOR:
124 return VIDEO_DIP_ENABLE_VENDOR;
125 case HDMI_INFOFRAME_TYPE_DRM:
126 return 0;
127 default:
128 MISSING_CASE(type);
129 return 0;
130 }
131}
132
133static u32 hsw_infoframe_enable(unsigned int type)
134{
135 switch (type) {
136 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
137 return VIDEO_DIP_ENABLE_GCP_HSW;
138 case HDMI_PACKET_TYPE_GAMUT_METADATA:
139 return VIDEO_DIP_ENABLE_GMP_HSW;
140 case DP_SDP_VSC:
141 return VIDEO_DIP_ENABLE_VSC_HSW;
142 case DP_SDP_ADAPTIVE_SYNC:
143 return VIDEO_DIP_ENABLE_AS_ADL;
144 case DP_SDP_PPS:
145 return VDIP_ENABLE_PPS;
146 case HDMI_INFOFRAME_TYPE_AVI:
147 return VIDEO_DIP_ENABLE_AVI_HSW;
148 case HDMI_INFOFRAME_TYPE_SPD:
149 return VIDEO_DIP_ENABLE_SPD_HSW;
150 case HDMI_INFOFRAME_TYPE_VENDOR:
151 return VIDEO_DIP_ENABLE_VS_HSW;
152 case HDMI_INFOFRAME_TYPE_DRM:
153 return VIDEO_DIP_ENABLE_DRM_GLK;
154 default:
155 MISSING_CASE(type);
156 return 0;
157 }
158}
159
160static i915_reg_t
161hsw_dip_data_reg(struct intel_display *display,
162 enum transcoder cpu_transcoder,
163 unsigned int type,
164 int i)
165{
166 switch (type) {
167 case HDMI_PACKET_TYPE_GAMUT_METADATA:
168 return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i);
169 case DP_SDP_VSC:
170 return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i);
171 case DP_SDP_ADAPTIVE_SYNC:
172 return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i);
173 case DP_SDP_PPS:
174 return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i);
175 case HDMI_INFOFRAME_TYPE_AVI:
176 return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i);
177 case HDMI_INFOFRAME_TYPE_SPD:
178 return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i);
179 case HDMI_INFOFRAME_TYPE_VENDOR:
180 return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i);
181 case HDMI_INFOFRAME_TYPE_DRM:
182 return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i);
183 default:
184 MISSING_CASE(type);
185 return INVALID_MMIO_REG;
186 }
187}
188
189static int hsw_dip_data_size(struct intel_display *display,
190 unsigned int type)
191{
192 switch (type) {
193 case DP_SDP_VSC:
194 return VIDEO_DIP_VSC_DATA_SIZE;
195 case DP_SDP_ADAPTIVE_SYNC:
196 return VIDEO_DIP_ASYNC_DATA_SIZE;
197 case DP_SDP_PPS:
198 return VIDEO_DIP_PPS_DATA_SIZE;
199 case HDMI_PACKET_TYPE_GAMUT_METADATA:
200 if (DISPLAY_VER(display) >= 11)
201 return VIDEO_DIP_GMP_DATA_SIZE;
202 else
203 return VIDEO_DIP_DATA_SIZE;
204 default:
205 return VIDEO_DIP_DATA_SIZE;
206 }
207}
208
209static void g4x_write_infoframe(struct intel_encoder *encoder,
210 const struct intel_crtc_state *crtc_state,
211 unsigned int type,
212 const void *frame, ssize_t len)
213{
214 struct intel_display *display = to_intel_display(encoder);
215 const u32 *data = frame;
216 u32 val = intel_de_read(display, VIDEO_DIP_CTL);
217 int i;
218
219 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
220 "Writing DIP with CTL reg disabled\n");
221
222 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
223 val |= g4x_infoframe_index(type);
224
225 val &= ~g4x_infoframe_enable(type);
226
227 intel_de_write(display, VIDEO_DIP_CTL, val);
228
229 for (i = 0; i < len; i += 4) {
230 intel_de_write(display, VIDEO_DIP_DATA, *data);
231 data++;
232 }
233 /* Write every possible data byte to force correct ECC calculation. */
234 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
235 intel_de_write(display, VIDEO_DIP_DATA, 0);
236
237 val |= g4x_infoframe_enable(type);
238 val &= ~VIDEO_DIP_FREQ_MASK;
239 val |= VIDEO_DIP_FREQ_VSYNC;
240
241 intel_de_write(display, VIDEO_DIP_CTL, val);
242 intel_de_posting_read(display, VIDEO_DIP_CTL);
243}
244
245static void g4x_read_infoframe(struct intel_encoder *encoder,
246 const struct intel_crtc_state *crtc_state,
247 unsigned int type,
248 void *frame, ssize_t len)
249{
250 struct intel_display *display = to_intel_display(encoder);
251 u32 *data = frame;
252 int i;
253
254 intel_de_rmw(display, VIDEO_DIP_CTL,
255 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
256
257 for (i = 0; i < len; i += 4)
258 *data++ = intel_de_read(display, VIDEO_DIP_DATA);
259}
260
261static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
262 const struct intel_crtc_state *pipe_config)
263{
264 struct intel_display *display = to_intel_display(encoder);
265 u32 val = intel_de_read(display, VIDEO_DIP_CTL);
266
267 if ((val & VIDEO_DIP_ENABLE) == 0)
268 return 0;
269
270 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
271 return 0;
272
273 return val & (VIDEO_DIP_ENABLE_AVI |
274 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
275}
276
277static void ibx_write_infoframe(struct intel_encoder *encoder,
278 const struct intel_crtc_state *crtc_state,
279 unsigned int type,
280 const void *frame, ssize_t len)
281{
282 struct intel_display *display = to_intel_display(encoder);
283 const u32 *data = frame;
284 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
285 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
286 u32 val = intel_de_read(display, reg);
287 int i;
288
289 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
290 "Writing DIP with CTL reg disabled\n");
291
292 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
293 val |= g4x_infoframe_index(type);
294
295 val &= ~g4x_infoframe_enable(type);
296
297 intel_de_write(display, reg, val);
298
299 for (i = 0; i < len; i += 4) {
300 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),
301 *data);
302 data++;
303 }
304 /* Write every possible data byte to force correct ECC calculation. */
305 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
306 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);
307
308 val |= g4x_infoframe_enable(type);
309 val &= ~VIDEO_DIP_FREQ_MASK;
310 val |= VIDEO_DIP_FREQ_VSYNC;
311
312 intel_de_write(display, reg, val);
313 intel_de_posting_read(display, reg);
314}
315
316static void ibx_read_infoframe(struct intel_encoder *encoder,
317 const struct intel_crtc_state *crtc_state,
318 unsigned int type,
319 void *frame, ssize_t len)
320{
321 struct intel_display *display = to_intel_display(encoder);
322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
323 u32 *data = frame;
324 int i;
325
326 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),
327 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
328
329 for (i = 0; i < len; i += 4)
330 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));
331}
332
333static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
334 const struct intel_crtc_state *pipe_config)
335{
336 struct intel_display *display = to_intel_display(encoder);
337 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
338 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
339 u32 val = intel_de_read(display, reg);
340
341 if ((val & VIDEO_DIP_ENABLE) == 0)
342 return 0;
343
344 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
345 return 0;
346
347 return val & (VIDEO_DIP_ENABLE_AVI |
348 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
349 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
350}
351
352static void cpt_write_infoframe(struct intel_encoder *encoder,
353 const struct intel_crtc_state *crtc_state,
354 unsigned int type,
355 const void *frame, ssize_t len)
356{
357 struct intel_display *display = to_intel_display(encoder);
358 const u32 *data = frame;
359 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
360 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
361 u32 val = intel_de_read(display, reg);
362 int i;
363
364 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
365 "Writing DIP with CTL reg disabled\n");
366
367 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
368 val |= g4x_infoframe_index(type);
369
370 /* The DIP control register spec says that we need to update the AVI
371 * infoframe without clearing its enable bit */
372 if (type != HDMI_INFOFRAME_TYPE_AVI)
373 val &= ~g4x_infoframe_enable(type);
374
375 intel_de_write(display, reg, val);
376
377 for (i = 0; i < len; i += 4) {
378 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),
379 *data);
380 data++;
381 }
382 /* Write every possible data byte to force correct ECC calculation. */
383 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
384 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);
385
386 val |= g4x_infoframe_enable(type);
387 val &= ~VIDEO_DIP_FREQ_MASK;
388 val |= VIDEO_DIP_FREQ_VSYNC;
389
390 intel_de_write(display, reg, val);
391 intel_de_posting_read(display, reg);
392}
393
394static void cpt_read_infoframe(struct intel_encoder *encoder,
395 const struct intel_crtc_state *crtc_state,
396 unsigned int type,
397 void *frame, ssize_t len)
398{
399 struct intel_display *display = to_intel_display(encoder);
400 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
401 u32 *data = frame;
402 int i;
403
404 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),
405 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
406
407 for (i = 0; i < len; i += 4)
408 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));
409}
410
411static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
412 const struct intel_crtc_state *pipe_config)
413{
414 struct intel_display *display = to_intel_display(encoder);
415 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
416 u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe));
417
418 if ((val & VIDEO_DIP_ENABLE) == 0)
419 return 0;
420
421 return val & (VIDEO_DIP_ENABLE_AVI |
422 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
423 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
424}
425
426static void vlv_write_infoframe(struct intel_encoder *encoder,
427 const struct intel_crtc_state *crtc_state,
428 unsigned int type,
429 const void *frame, ssize_t len)
430{
431 struct intel_display *display = to_intel_display(encoder);
432 const u32 *data = frame;
433 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
434 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
435 u32 val = intel_de_read(display, reg);
436 int i;
437
438 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
439 "Writing DIP with CTL reg disabled\n");
440
441 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
442 val |= g4x_infoframe_index(type);
443
444 val &= ~g4x_infoframe_enable(type);
445
446 intel_de_write(display, reg, val);
447
448 for (i = 0; i < len; i += 4) {
449 intel_de_write(display,
450 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
451 data++;
452 }
453 /* Write every possible data byte to force correct ECC calculation. */
454 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
455 intel_de_write(display,
456 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
457
458 val |= g4x_infoframe_enable(type);
459 val &= ~VIDEO_DIP_FREQ_MASK;
460 val |= VIDEO_DIP_FREQ_VSYNC;
461
462 intel_de_write(display, reg, val);
463 intel_de_posting_read(display, reg);
464}
465
466static void vlv_read_infoframe(struct intel_encoder *encoder,
467 const struct intel_crtc_state *crtc_state,
468 unsigned int type,
469 void *frame, ssize_t len)
470{
471 struct intel_display *display = to_intel_display(encoder);
472 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
473 u32 *data = frame;
474 int i;
475
476 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe),
477 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
478
479 for (i = 0; i < len; i += 4)
480 *data++ = intel_de_read(display,
481 VLV_TVIDEO_DIP_DATA(crtc->pipe));
482}
483
484static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
485 const struct intel_crtc_state *pipe_config)
486{
487 struct intel_display *display = to_intel_display(encoder);
488 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
489 u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe));
490
491 if ((val & VIDEO_DIP_ENABLE) == 0)
492 return 0;
493
494 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
495 return 0;
496
497 return val & (VIDEO_DIP_ENABLE_AVI |
498 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
499 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
500}
501
502void hsw_write_infoframe(struct intel_encoder *encoder,
503 const struct intel_crtc_state *crtc_state,
504 unsigned int type,
505 const void *frame, ssize_t len)
506{
507 struct intel_display *display = to_intel_display(encoder);
508 const u32 *data = frame;
509 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
510 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder);
511 int data_size;
512 int i;
513 u32 val = intel_de_read(display, ctl_reg);
514
515 data_size = hsw_dip_data_size(display, type);
516
517 drm_WARN_ON(display->drm, len > data_size);
518
519 val &= ~hsw_infoframe_enable(type);
520 intel_de_write(display, ctl_reg, val);
521
522 for (i = 0; i < len; i += 4) {
523 intel_de_write(display,
524 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2),
525 *data);
526 data++;
527 }
528 /* Write every possible data byte to force correct ECC calculation. */
529 for (; i < data_size; i += 4)
530 intel_de_write(display,
531 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2),
532 0);
533
534 /* Wa_14013475917 */
535 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr &&
536 !crtc_state->has_panel_replay && type == DP_SDP_VSC))
537 val |= hsw_infoframe_enable(type);
538
539 if (type == DP_SDP_VSC)
540 val |= VSC_DIP_HW_DATA_SW_HEA;
541
542 intel_de_write(display, ctl_reg, val);
543 intel_de_posting_read(display, ctl_reg);
544}
545
546void hsw_read_infoframe(struct intel_encoder *encoder,
547 const struct intel_crtc_state *crtc_state,
548 unsigned int type, void *frame, ssize_t len)
549{
550 struct intel_display *display = to_intel_display(encoder);
551 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
552 u32 *data = frame;
553 int i;
554
555 for (i = 0; i < len; i += 4)
556 *data++ = intel_de_read(display,
557 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2));
558}
559
560static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
561 const struct intel_crtc_state *pipe_config)
562{
563 struct intel_display *display = to_intel_display(encoder);
564 u32 val = intel_de_read(display,
565 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder));
566 u32 mask;
567
568 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
569 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
570 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
571
572 if (DISPLAY_VER(display) >= 10)
573 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
574
575 if (HAS_AS_SDP(display))
576 mask |= VIDEO_DIP_ENABLE_AS_ADL;
577
578 return val & mask;
579}
580
581static const u8 infoframe_type_to_idx[] = {
582 HDMI_PACKET_TYPE_GENERAL_CONTROL,
583 HDMI_PACKET_TYPE_GAMUT_METADATA,
584 DP_SDP_VSC,
585 DP_SDP_ADAPTIVE_SYNC,
586 HDMI_INFOFRAME_TYPE_AVI,
587 HDMI_INFOFRAME_TYPE_SPD,
588 HDMI_INFOFRAME_TYPE_VENDOR,
589 HDMI_INFOFRAME_TYPE_DRM,
590};
591
592u32 intel_hdmi_infoframe_enable(unsigned int type)
593{
594 int i;
595
596 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
597 if (infoframe_type_to_idx[i] == type)
598 return BIT(i);
599 }
600
601 return 0;
602}
603
604u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
605 const struct intel_crtc_state *crtc_state)
606{
607 struct intel_display *display = to_intel_display(encoder);
608 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
609 u32 val, ret = 0;
610 int i;
611
612 val = dig_port->infoframes_enabled(encoder, crtc_state);
613
614 /* map from hardware bits to dip idx */
615 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
616 unsigned int type = infoframe_type_to_idx[i];
617
618 if (HAS_DDI(display)) {
619 if (val & hsw_infoframe_enable(type))
620 ret |= BIT(i);
621 } else {
622 if (val & g4x_infoframe_enable(type))
623 ret |= BIT(i);
624 }
625 }
626
627 return ret;
628}
629
630/*
631 * The data we write to the DIP data buffer registers is 1 byte bigger than the
632 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
633 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
634 * used for both technologies.
635 *
636 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
637 * DW1: DB3 | DB2 | DB1 | DB0
638 * DW2: DB7 | DB6 | DB5 | DB4
639 * DW3: ...
640 *
641 * (HB is Header Byte, DB is Data Byte)
642 *
643 * The hdmi pack() functions don't know about that hardware specific hole so we
644 * trick them by giving an offset into the buffer and moving back the header
645 * bytes by one.
646 */
647static void intel_write_infoframe(struct intel_encoder *encoder,
648 const struct intel_crtc_state *crtc_state,
649 enum hdmi_infoframe_type type,
650 const union hdmi_infoframe *frame)
651{
652 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
653 u8 buffer[VIDEO_DIP_DATA_SIZE];
654 ssize_t len;
655
656 if ((crtc_state->infoframes.enable &
657 intel_hdmi_infoframe_enable(type)) == 0)
658 return;
659
660 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
661 return;
662
663 /* see comment above for the reason for this offset */
664 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
665 if (drm_WARN_ON(encoder->base.dev, len < 0))
666 return;
667
668 /* Insert the 'hole' (see big comment above) at position 3 */
669 memmove(&buffer[0], &buffer[1], 3);
670 buffer[3] = 0;
671 len++;
672
673 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
674}
675
676void intel_read_infoframe(struct intel_encoder *encoder,
677 const struct intel_crtc_state *crtc_state,
678 enum hdmi_infoframe_type type,
679 union hdmi_infoframe *frame)
680{
681 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
682 u8 buffer[VIDEO_DIP_DATA_SIZE];
683 int ret;
684
685 if ((crtc_state->infoframes.enable &
686 intel_hdmi_infoframe_enable(type)) == 0)
687 return;
688
689 dig_port->read_infoframe(encoder, crtc_state,
690 type, buffer, sizeof(buffer));
691
692 /* Fill the 'hole' (see big comment above) at position 3 */
693 memmove(&buffer[1], &buffer[0], 3);
694
695 /* see comment above for the reason for this offset */
696 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
697 if (ret) {
698 drm_dbg_kms(encoder->base.dev,
699 "Failed to unpack infoframe type 0x%02x\n", type);
700 return;
701 }
702
703 if (frame->any.type != type)
704 drm_dbg_kms(encoder->base.dev,
705 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
706 frame->any.type, type);
707}
708
709static bool
710intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
711 struct intel_crtc_state *crtc_state,
712 struct drm_connector_state *conn_state)
713{
714 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
715 const struct drm_display_mode *adjusted_mode =
716 &crtc_state->hw.adjusted_mode;
717 struct drm_connector *connector = conn_state->connector;
718 int ret;
719
720 if (!crtc_state->has_infoframe)
721 return true;
722
723 crtc_state->infoframes.enable |=
724 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
725
726 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
727 adjusted_mode);
728 if (ret)
729 return false;
730
731 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
732 frame->colorspace = HDMI_COLORSPACE_YUV420;
733 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
734 frame->colorspace = HDMI_COLORSPACE_YUV444;
735 else
736 frame->colorspace = HDMI_COLORSPACE_RGB;
737
738 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);
739
740 /* nonsense combination */
741 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
742 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
743
744 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
745 drm_hdmi_avi_infoframe_quant_range(frame, connector,
746 adjusted_mode,
747 crtc_state->limited_color_range ?
748 HDMI_QUANTIZATION_RANGE_LIMITED :
749 HDMI_QUANTIZATION_RANGE_FULL);
750 } else {
751 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
752 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
753 }
754
755 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
756
757 /* TODO: handle pixel repetition for YCBCR420 outputs */
758
759 ret = hdmi_avi_infoframe_check(frame);
760 if (drm_WARN_ON(encoder->base.dev, ret))
761 return false;
762
763 return true;
764}
765
766static bool
767intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
768 struct intel_crtc_state *crtc_state,
769 struct drm_connector_state *conn_state)
770{
771 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
772 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
773 int ret;
774
775 if (!crtc_state->has_infoframe)
776 return true;
777
778 crtc_state->infoframes.enable |=
779 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
780
781 if (IS_DGFX(i915))
782 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
783 else
784 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
785
786 if (drm_WARN_ON(encoder->base.dev, ret))
787 return false;
788
789 frame->sdi = HDMI_SPD_SDI_PC;
790
791 ret = hdmi_spd_infoframe_check(frame);
792 if (drm_WARN_ON(encoder->base.dev, ret))
793 return false;
794
795 return true;
796}
797
798static bool
799intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
800 struct intel_crtc_state *crtc_state,
801 struct drm_connector_state *conn_state)
802{
803 struct hdmi_vendor_infoframe *frame =
804 &crtc_state->infoframes.hdmi.vendor.hdmi;
805 const struct drm_display_info *info =
806 &conn_state->connector->display_info;
807 int ret;
808
809 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
810 return true;
811
812 crtc_state->infoframes.enable |=
813 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
814
815 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
816 conn_state->connector,
817 &crtc_state->hw.adjusted_mode);
818 if (drm_WARN_ON(encoder->base.dev, ret))
819 return false;
820
821 ret = hdmi_vendor_infoframe_check(frame);
822 if (drm_WARN_ON(encoder->base.dev, ret))
823 return false;
824
825 return true;
826}
827
828static bool
829intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
830 struct intel_crtc_state *crtc_state,
831 struct drm_connector_state *conn_state)
832{
833 struct intel_display *display = to_intel_display(encoder);
834 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
835 int ret;
836
837 if (DISPLAY_VER(display) < 10)
838 return true;
839
840 if (!crtc_state->has_infoframe)
841 return true;
842
843 if (!conn_state->hdr_output_metadata)
844 return true;
845
846 crtc_state->infoframes.enable |=
847 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
848
849 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
850 if (ret < 0) {
851 drm_dbg_kms(display->drm,
852 "couldn't set HDR metadata in infoframe\n");
853 return false;
854 }
855
856 ret = hdmi_drm_infoframe_check(frame);
857 if (drm_WARN_ON(display->drm, ret))
858 return false;
859
860 return true;
861}
862
863static void g4x_set_infoframes(struct intel_encoder *encoder,
864 bool enable,
865 const struct intel_crtc_state *crtc_state,
866 const struct drm_connector_state *conn_state)
867{
868 struct intel_display *display = to_intel_display(encoder);
869 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
870 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
871 i915_reg_t reg = VIDEO_DIP_CTL;
872 u32 val = intel_de_read(display, reg);
873 u32 port = VIDEO_DIP_PORT(encoder->port);
874
875 assert_hdmi_port_disabled(intel_hdmi);
876
877 /* If the registers were not initialized yet, they might be zeroes,
878 * which means we're selecting the AVI DIP and we're setting its
879 * frequency to once. This seems to really confuse the HW and make
880 * things stop working (the register spec says the AVI always needs to
881 * be sent every VSync). So here we avoid writing to the register more
882 * than we need and also explicitly select the AVI DIP and explicitly
883 * set its frequency to every VSync. Avoiding to write it twice seems to
884 * be enough to solve the problem, but being defensive shouldn't hurt us
885 * either. */
886 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
887
888 if (!enable) {
889 if (!(val & VIDEO_DIP_ENABLE))
890 return;
891 if (port != (val & VIDEO_DIP_PORT_MASK)) {
892 drm_dbg_kms(display->drm,
893 "video DIP still enabled on port %c\n",
894 (val & VIDEO_DIP_PORT_MASK) >> 29);
895 return;
896 }
897 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
898 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
899 intel_de_write(display, reg, val);
900 intel_de_posting_read(display, reg);
901 return;
902 }
903
904 if (port != (val & VIDEO_DIP_PORT_MASK)) {
905 if (val & VIDEO_DIP_ENABLE) {
906 drm_dbg_kms(display->drm,
907 "video DIP already enabled on port %c\n",
908 (val & VIDEO_DIP_PORT_MASK) >> 29);
909 return;
910 }
911 val &= ~VIDEO_DIP_PORT_MASK;
912 val |= port;
913 }
914
915 val |= VIDEO_DIP_ENABLE;
916 val &= ~(VIDEO_DIP_ENABLE_AVI |
917 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
918
919 intel_de_write(display, reg, val);
920 intel_de_posting_read(display, reg);
921
922 intel_write_infoframe(encoder, crtc_state,
923 HDMI_INFOFRAME_TYPE_AVI,
924 &crtc_state->infoframes.avi);
925 intel_write_infoframe(encoder, crtc_state,
926 HDMI_INFOFRAME_TYPE_SPD,
927 &crtc_state->infoframes.spd);
928 intel_write_infoframe(encoder, crtc_state,
929 HDMI_INFOFRAME_TYPE_VENDOR,
930 &crtc_state->infoframes.hdmi);
931}
932
933/*
934 * Determine if default_phase=1 can be indicated in the GCP infoframe.
935 *
936 * From HDMI specification 1.4a:
937 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
938 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
939 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
940 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
941 * phase of 0
942 */
943static bool gcp_default_phase_possible(int pipe_bpp,
944 const struct drm_display_mode *mode)
945{
946 unsigned int pixels_per_group;
947
948 switch (pipe_bpp) {
949 case 30:
950 /* 4 pixels in 5 clocks */
951 pixels_per_group = 4;
952 break;
953 case 36:
954 /* 2 pixels in 3 clocks */
955 pixels_per_group = 2;
956 break;
957 case 48:
958 /* 1 pixel in 2 clocks */
959 pixels_per_group = 1;
960 break;
961 default:
962 /* phase information not relevant for 8bpc */
963 return false;
964 }
965
966 return mode->crtc_hdisplay % pixels_per_group == 0 &&
967 mode->crtc_htotal % pixels_per_group == 0 &&
968 mode->crtc_hblank_start % pixels_per_group == 0 &&
969 mode->crtc_hblank_end % pixels_per_group == 0 &&
970 mode->crtc_hsync_start % pixels_per_group == 0 &&
971 mode->crtc_hsync_end % pixels_per_group == 0 &&
972 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
973 mode->crtc_htotal/2 % pixels_per_group == 0);
974}
975
976static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
977 const struct intel_crtc_state *crtc_state,
978 const struct drm_connector_state *conn_state)
979{
980 struct intel_display *display = to_intel_display(encoder);
981 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
983 i915_reg_t reg;
984
985 if ((crtc_state->infoframes.enable &
986 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
987 return false;
988
989 if (HAS_DDI(display))
990 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
991 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
992 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
993 else if (HAS_PCH_SPLIT(dev_priv))
994 reg = TVIDEO_DIP_GCP(crtc->pipe);
995 else
996 return false;
997
998 intel_de_write(display, reg, crtc_state->infoframes.gcp);
999
1000 return true;
1001}
1002
1003void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
1004 struct intel_crtc_state *crtc_state)
1005{
1006 struct intel_display *display = to_intel_display(encoder);
1007 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1008 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1009 i915_reg_t reg;
1010
1011 if ((crtc_state->infoframes.enable &
1012 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1013 return;
1014
1015 if (HAS_DDI(display))
1016 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
1017 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1018 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1019 else if (HAS_PCH_SPLIT(dev_priv))
1020 reg = TVIDEO_DIP_GCP(crtc->pipe);
1021 else
1022 return;
1023
1024 crtc_state->infoframes.gcp = intel_de_read(display, reg);
1025}
1026
1027static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1028 struct intel_crtc_state *crtc_state,
1029 struct drm_connector_state *conn_state)
1030{
1031 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1032
1033 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1034 return;
1035
1036 crtc_state->infoframes.enable |=
1037 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1038
1039 /* Indicate color indication for deep color mode */
1040 if (crtc_state->pipe_bpp > 24)
1041 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1042
1043 /* Enable default_phase whenever the display mode is suitably aligned */
1044 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1045 &crtc_state->hw.adjusted_mode))
1046 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1047}
1048
1049static void ibx_set_infoframes(struct intel_encoder *encoder,
1050 bool enable,
1051 const struct intel_crtc_state *crtc_state,
1052 const struct drm_connector_state *conn_state)
1053{
1054 struct intel_display *display = to_intel_display(encoder);
1055 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1056 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1057 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1058 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1059 u32 val = intel_de_read(display, reg);
1060 u32 port = VIDEO_DIP_PORT(encoder->port);
1061
1062 assert_hdmi_port_disabled(intel_hdmi);
1063
1064 /* See the big comment in g4x_set_infoframes() */
1065 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1066
1067 if (!enable) {
1068 if (!(val & VIDEO_DIP_ENABLE))
1069 return;
1070 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1071 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1072 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1073 intel_de_write(display, reg, val);
1074 intel_de_posting_read(display, reg);
1075 return;
1076 }
1077
1078 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1079 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,
1080 "DIP already enabled on port %c\n",
1081 (val & VIDEO_DIP_PORT_MASK) >> 29);
1082 val &= ~VIDEO_DIP_PORT_MASK;
1083 val |= port;
1084 }
1085
1086 val |= VIDEO_DIP_ENABLE;
1087 val &= ~(VIDEO_DIP_ENABLE_AVI |
1088 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1089 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1090
1091 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1092 val |= VIDEO_DIP_ENABLE_GCP;
1093
1094 intel_de_write(display, reg, val);
1095 intel_de_posting_read(display, reg);
1096
1097 intel_write_infoframe(encoder, crtc_state,
1098 HDMI_INFOFRAME_TYPE_AVI,
1099 &crtc_state->infoframes.avi);
1100 intel_write_infoframe(encoder, crtc_state,
1101 HDMI_INFOFRAME_TYPE_SPD,
1102 &crtc_state->infoframes.spd);
1103 intel_write_infoframe(encoder, crtc_state,
1104 HDMI_INFOFRAME_TYPE_VENDOR,
1105 &crtc_state->infoframes.hdmi);
1106}
1107
1108static void cpt_set_infoframes(struct intel_encoder *encoder,
1109 bool enable,
1110 const struct intel_crtc_state *crtc_state,
1111 const struct drm_connector_state *conn_state)
1112{
1113 struct intel_display *display = to_intel_display(encoder);
1114 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1115 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1116 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1117 u32 val = intel_de_read(display, reg);
1118
1119 assert_hdmi_port_disabled(intel_hdmi);
1120
1121 /* See the big comment in g4x_set_infoframes() */
1122 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1123
1124 if (!enable) {
1125 if (!(val & VIDEO_DIP_ENABLE))
1126 return;
1127 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1128 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1129 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1130 intel_de_write(display, reg, val);
1131 intel_de_posting_read(display, reg);
1132 return;
1133 }
1134
1135 /* Set both together, unset both together: see the spec. */
1136 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1137 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1138 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1139
1140 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1141 val |= VIDEO_DIP_ENABLE_GCP;
1142
1143 intel_de_write(display, reg, val);
1144 intel_de_posting_read(display, reg);
1145
1146 intel_write_infoframe(encoder, crtc_state,
1147 HDMI_INFOFRAME_TYPE_AVI,
1148 &crtc_state->infoframes.avi);
1149 intel_write_infoframe(encoder, crtc_state,
1150 HDMI_INFOFRAME_TYPE_SPD,
1151 &crtc_state->infoframes.spd);
1152 intel_write_infoframe(encoder, crtc_state,
1153 HDMI_INFOFRAME_TYPE_VENDOR,
1154 &crtc_state->infoframes.hdmi);
1155}
1156
1157static void vlv_set_infoframes(struct intel_encoder *encoder,
1158 bool enable,
1159 const struct intel_crtc_state *crtc_state,
1160 const struct drm_connector_state *conn_state)
1161{
1162 struct intel_display *display = to_intel_display(encoder);
1163 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1164 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1165 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1166 u32 val = intel_de_read(display, reg);
1167 u32 port = VIDEO_DIP_PORT(encoder->port);
1168
1169 assert_hdmi_port_disabled(intel_hdmi);
1170
1171 /* See the big comment in g4x_set_infoframes() */
1172 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1173
1174 if (!enable) {
1175 if (!(val & VIDEO_DIP_ENABLE))
1176 return;
1177 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1178 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1179 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1180 intel_de_write(display, reg, val);
1181 intel_de_posting_read(display, reg);
1182 return;
1183 }
1184
1185 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1186 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,
1187 "DIP already enabled on port %c\n",
1188 (val & VIDEO_DIP_PORT_MASK) >> 29);
1189 val &= ~VIDEO_DIP_PORT_MASK;
1190 val |= port;
1191 }
1192
1193 val |= VIDEO_DIP_ENABLE;
1194 val &= ~(VIDEO_DIP_ENABLE_AVI |
1195 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1196 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1197
1198 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1199 val |= VIDEO_DIP_ENABLE_GCP;
1200
1201 intel_de_write(display, reg, val);
1202 intel_de_posting_read(display, reg);
1203
1204 intel_write_infoframe(encoder, crtc_state,
1205 HDMI_INFOFRAME_TYPE_AVI,
1206 &crtc_state->infoframes.avi);
1207 intel_write_infoframe(encoder, crtc_state,
1208 HDMI_INFOFRAME_TYPE_SPD,
1209 &crtc_state->infoframes.spd);
1210 intel_write_infoframe(encoder, crtc_state,
1211 HDMI_INFOFRAME_TYPE_VENDOR,
1212 &crtc_state->infoframes.hdmi);
1213}
1214
1215void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder,
1216 const struct intel_crtc_state *crtc_state,
1217 const struct drm_connector_state *conn_state)
1218{
1219 struct intel_display *display = to_intel_display(encoder);
1220 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
1221 crtc_state->cpu_transcoder);
1222 u32 val = intel_de_read(display, reg);
1223
1224 if ((crtc_state->infoframes.enable &
1225 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) == 0 &&
1226 (val & VIDEO_DIP_ENABLE_DRM_GLK) == 0)
1227 return;
1228
1229 val &= ~(VIDEO_DIP_ENABLE_DRM_GLK);
1230
1231 intel_de_write(display, reg, val);
1232 intel_de_posting_read(display, reg);
1233
1234 intel_write_infoframe(encoder, crtc_state,
1235 HDMI_INFOFRAME_TYPE_DRM,
1236 &crtc_state->infoframes.drm);
1237}
1238
1239static void hsw_set_infoframes(struct intel_encoder *encoder,
1240 bool enable,
1241 const struct intel_crtc_state *crtc_state,
1242 const struct drm_connector_state *conn_state)
1243{
1244 struct intel_display *display = to_intel_display(encoder);
1245 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
1246 crtc_state->cpu_transcoder);
1247 u32 val = intel_de_read(display, reg);
1248
1249 assert_hdmi_transcoder_func_disabled(display,
1250 crtc_state->cpu_transcoder);
1251
1252 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1253 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1254 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1255 VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL);
1256
1257 if (!enable) {
1258 intel_de_write(display, reg, val);
1259 intel_de_posting_read(display, reg);
1260 return;
1261 }
1262
1263 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1264 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1265
1266 intel_de_write(display, reg, val);
1267 intel_de_posting_read(display, reg);
1268
1269 intel_write_infoframe(encoder, crtc_state,
1270 HDMI_INFOFRAME_TYPE_AVI,
1271 &crtc_state->infoframes.avi);
1272 intel_write_infoframe(encoder, crtc_state,
1273 HDMI_INFOFRAME_TYPE_SPD,
1274 &crtc_state->infoframes.spd);
1275 intel_write_infoframe(encoder, crtc_state,
1276 HDMI_INFOFRAME_TYPE_VENDOR,
1277 &crtc_state->infoframes.hdmi);
1278 intel_write_infoframe(encoder, crtc_state,
1279 HDMI_INFOFRAME_TYPE_DRM,
1280 &crtc_state->infoframes.drm);
1281}
1282
1283void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1284{
1285 struct intel_display *display = to_intel_display(hdmi);
1286 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1287
1288 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1289 return;
1290
1291 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n",
1292 enable ? "Enabling" : "Disabling");
1293
1294 drm_dp_dual_mode_set_tmds_output(display->drm,
1295 hdmi->dp_dual_mode.type, ddc, enable);
1296}
1297
1298static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1299 unsigned int offset, void *buffer, size_t size)
1300{
1301 struct intel_hdmi *hdmi = &dig_port->hdmi;
1302 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1303 int ret;
1304 u8 start = offset & 0xff;
1305 struct i2c_msg msgs[] = {
1306 {
1307 .addr = DRM_HDCP_DDC_ADDR,
1308 .flags = 0,
1309 .len = 1,
1310 .buf = &start,
1311 },
1312 {
1313 .addr = DRM_HDCP_DDC_ADDR,
1314 .flags = I2C_M_RD,
1315 .len = size,
1316 .buf = buffer
1317 }
1318 };
1319 ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs));
1320 if (ret == ARRAY_SIZE(msgs))
1321 return 0;
1322 return ret >= 0 ? -EIO : ret;
1323}
1324
1325static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1326 unsigned int offset, void *buffer, size_t size)
1327{
1328 struct intel_hdmi *hdmi = &dig_port->hdmi;
1329 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1330 int ret;
1331 u8 *write_buf;
1332 struct i2c_msg msg;
1333
1334 write_buf = kzalloc(size + 1, GFP_KERNEL);
1335 if (!write_buf)
1336 return -ENOMEM;
1337
1338 write_buf[0] = offset & 0xff;
1339 memcpy(&write_buf[1], buffer, size);
1340
1341 msg.addr = DRM_HDCP_DDC_ADDR;
1342 msg.flags = 0;
1343 msg.len = size + 1;
1344 msg.buf = write_buf;
1345
1346 ret = i2c_transfer(ddc, &msg, 1);
1347 if (ret == 1)
1348 ret = 0;
1349 else if (ret >= 0)
1350 ret = -EIO;
1351
1352 kfree(write_buf);
1353 return ret;
1354}
1355
1356static
1357int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1358 u8 *an)
1359{
1360 struct intel_display *display = to_intel_display(dig_port);
1361 struct intel_hdmi *hdmi = &dig_port->hdmi;
1362 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1363 int ret;
1364
1365 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1366 DRM_HDCP_AN_LEN);
1367 if (ret) {
1368 drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n",
1369 ret);
1370 return ret;
1371 }
1372
1373 ret = intel_gmbus_output_aksv(ddc);
1374 if (ret < 0) {
1375 drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret);
1376 return ret;
1377 }
1378 return 0;
1379}
1380
1381static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1382 u8 *bksv)
1383{
1384 struct intel_display *display = to_intel_display(dig_port);
1385
1386 int ret;
1387 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1388 DRM_HDCP_KSV_LEN);
1389 if (ret)
1390 drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n",
1391 ret);
1392 return ret;
1393}
1394
1395static
1396int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1397 u8 *bstatus)
1398{
1399 struct intel_display *display = to_intel_display(dig_port);
1400
1401 int ret;
1402 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1403 bstatus, DRM_HDCP_BSTATUS_LEN);
1404 if (ret)
1405 drm_dbg_kms(display->drm,
1406 "Read bstatus over DDC failed (%d)\n",
1407 ret);
1408 return ret;
1409}
1410
1411static
1412int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1413 bool *repeater_present)
1414{
1415 struct intel_display *display = to_intel_display(dig_port);
1416 int ret;
1417 u8 val;
1418
1419 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1420 if (ret) {
1421 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n",
1422 ret);
1423 return ret;
1424 }
1425 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1426 return 0;
1427}
1428
1429static
1430int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1431 u8 *ri_prime)
1432{
1433 struct intel_display *display = to_intel_display(dig_port);
1434
1435 int ret;
1436 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1437 ri_prime, DRM_HDCP_RI_LEN);
1438 if (ret)
1439 drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n",
1440 ret);
1441 return ret;
1442}
1443
1444static
1445int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1446 bool *ksv_ready)
1447{
1448 struct intel_display *display = to_intel_display(dig_port);
1449 int ret;
1450 u8 val;
1451
1452 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1453 if (ret) {
1454 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n",
1455 ret);
1456 return ret;
1457 }
1458 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1459 return 0;
1460}
1461
1462static
1463int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1464 int num_downstream, u8 *ksv_fifo)
1465{
1466 struct intel_display *display = to_intel_display(dig_port);
1467 int ret;
1468 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1469 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1470 if (ret) {
1471 drm_dbg_kms(display->drm,
1472 "Read ksv fifo over DDC failed (%d)\n", ret);
1473 return ret;
1474 }
1475 return 0;
1476}
1477
1478static
1479int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1480 int i, u32 *part)
1481{
1482 struct intel_display *display = to_intel_display(dig_port);
1483 int ret;
1484
1485 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1486 return -EINVAL;
1487
1488 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1489 part, DRM_HDCP_V_PRIME_PART_LEN);
1490 if (ret)
1491 drm_dbg_kms(display->drm,
1492 "Read V'[%d] over DDC failed (%d)\n",
1493 i, ret);
1494 return ret;
1495}
1496
1497static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1498 enum transcoder cpu_transcoder)
1499{
1500 struct intel_display *display = to_intel_display(connector);
1501 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1502 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1503 u32 scanline;
1504 int ret;
1505
1506 for (;;) {
1507 scanline = intel_de_read(display,
1508 PIPEDSL(display, crtc->pipe));
1509 if (scanline > 100 && scanline < 200)
1510 break;
1511 usleep_range(25, 50);
1512 }
1513
1514 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1515 false, TRANS_DDI_HDCP_SIGNALLING);
1516 if (ret) {
1517 drm_err(display->drm,
1518 "Disable HDCP signalling failed (%d)\n", ret);
1519 return ret;
1520 }
1521
1522 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1523 true, TRANS_DDI_HDCP_SIGNALLING);
1524 if (ret) {
1525 drm_err(display->drm,
1526 "Enable HDCP signalling failed (%d)\n", ret);
1527 return ret;
1528 }
1529
1530 return 0;
1531}
1532
1533static
1534int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1535 enum transcoder cpu_transcoder,
1536 bool enable)
1537{
1538 struct intel_display *display = to_intel_display(dig_port);
1539 struct intel_hdmi *hdmi = &dig_port->hdmi;
1540 struct intel_connector *connector = hdmi->attached_connector;
1541 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1542 int ret;
1543
1544 if (!enable)
1545 usleep_range(6, 60); /* Bspec says >= 6us */
1546
1547 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1548 cpu_transcoder, enable,
1549 TRANS_DDI_HDCP_SIGNALLING);
1550 if (ret) {
1551 drm_err(display->drm, "%s HDCP signalling failed (%d)\n",
1552 enable ? "Enable" : "Disable", ret);
1553 return ret;
1554 }
1555
1556 /*
1557 * WA: To fix incorrect positioning of the window of
1558 * opportunity and enc_en signalling in KABYLAKE.
1559 */
1560 if (IS_KABYLAKE(dev_priv) && enable)
1561 return kbl_repositioning_enc_en_signal(connector,
1562 cpu_transcoder);
1563
1564 return 0;
1565}
1566
1567static
1568bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1569 struct intel_connector *connector)
1570{
1571 struct intel_display *display = to_intel_display(dig_port);
1572 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1573 enum port port = dig_port->base.port;
1574 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1575 int ret;
1576 union {
1577 u32 reg;
1578 u8 shim[DRM_HDCP_RI_LEN];
1579 } ri;
1580
1581 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1582 if (ret)
1583 return false;
1584
1585 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1586
1587 /* Wait for Ri prime match */
1588 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1589 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1590 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1591 drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n",
1592 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1593 port)));
1594 return false;
1595 }
1596 return true;
1597}
1598
1599static
1600bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1601 struct intel_connector *connector)
1602{
1603 struct intel_display *display = to_intel_display(dig_port);
1604 int retry;
1605
1606 for (retry = 0; retry < 3; retry++)
1607 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1608 return true;
1609
1610 drm_err(display->drm, "Link check failed\n");
1611 return false;
1612}
1613
1614struct hdcp2_hdmi_msg_timeout {
1615 u8 msg_id;
1616 u16 timeout;
1617};
1618
1619static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1620 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1621 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1622 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1623 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1624 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1625};
1626
1627static
1628int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1629 u8 *rx_status)
1630{
1631 return intel_hdmi_hdcp_read(dig_port,
1632 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1633 rx_status,
1634 HDCP_2_2_HDMI_RXSTATUS_LEN);
1635}
1636
1637static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1638{
1639 int i;
1640
1641 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1642 if (is_paired)
1643 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1644 else
1645 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1646 }
1647
1648 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1649 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1650 return hdcp2_msg_timeout[i].timeout;
1651 }
1652
1653 return -EINVAL;
1654}
1655
1656static int
1657hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1658 u8 msg_id, bool *msg_ready,
1659 ssize_t *msg_sz)
1660{
1661 struct intel_display *display = to_intel_display(dig_port);
1662 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1663 int ret;
1664
1665 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1666 if (ret < 0) {
1667 drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n",
1668 ret);
1669 return ret;
1670 }
1671
1672 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1673 rx_status[0]);
1674
1675 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1676 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1677 *msg_sz);
1678 else
1679 *msg_ready = *msg_sz;
1680
1681 return 0;
1682}
1683
1684static ssize_t
1685intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1686 u8 msg_id, bool paired)
1687{
1688 struct intel_display *display = to_intel_display(dig_port);
1689 bool msg_ready = false;
1690 int timeout, ret;
1691 ssize_t msg_sz = 0;
1692
1693 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1694 if (timeout < 0)
1695 return timeout;
1696
1697 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1698 msg_id, &msg_ready,
1699 &msg_sz),
1700 !ret && msg_ready && msg_sz, timeout * 1000,
1701 1000, 5 * 1000);
1702 if (ret)
1703 drm_dbg_kms(display->drm,
1704 "msg_id: %d, ret: %d, timeout: %d\n",
1705 msg_id, ret, timeout);
1706
1707 return ret ? ret : msg_sz;
1708}
1709
1710static
1711int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector,
1712 void *buf, size_t size)
1713{
1714 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1715 unsigned int offset;
1716
1717 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1718 return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1719}
1720
1721static
1722int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector,
1723 u8 msg_id, void *buf, size_t size)
1724{
1725 struct intel_display *display = to_intel_display(connector);
1726 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1727 struct intel_hdmi *hdmi = &dig_port->hdmi;
1728 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1729 unsigned int offset;
1730 ssize_t ret;
1731
1732 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1733 hdcp->is_paired);
1734 if (ret < 0)
1735 return ret;
1736
1737 /*
1738 * Available msg size should be equal to or lesser than the
1739 * available buffer.
1740 */
1741 if (ret > size) {
1742 drm_dbg_kms(display->drm,
1743 "msg_sz(%zd) is more than exp size(%zu)\n",
1744 ret, size);
1745 return -EINVAL;
1746 }
1747
1748 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1749 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1750 if (ret)
1751 drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n",
1752 msg_id, ret);
1753
1754 return ret;
1755}
1756
1757static
1758int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1759 struct intel_connector *connector)
1760{
1761 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1762 int ret;
1763
1764 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1765 if (ret)
1766 return ret;
1767
1768 /*
1769 * Re-auth request and Link Integrity Failures are represented by
1770 * same bit. i.e reauth_req.
1771 */
1772 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1773 ret = HDCP_REAUTH_REQUEST;
1774 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1775 ret = HDCP_TOPOLOGY_CHANGE;
1776
1777 return ret;
1778}
1779
1780static
1781int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector,
1782 bool *capable)
1783{
1784 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1785 u8 hdcp2_version;
1786 int ret;
1787
1788 *capable = false;
1789 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1790 &hdcp2_version, sizeof(hdcp2_version));
1791 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1792 *capable = true;
1793
1794 return ret;
1795}
1796
1797static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1798 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1799 .read_bksv = intel_hdmi_hdcp_read_bksv,
1800 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1801 .repeater_present = intel_hdmi_hdcp_repeater_present,
1802 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1803 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1804 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1805 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1806 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1807 .check_link = intel_hdmi_hdcp_check_link,
1808 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1809 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1810 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1811 .hdcp_2_2_get_capability = intel_hdmi_hdcp2_get_capability,
1812 .protocol = HDCP_PROTOCOL_HDMI,
1813};
1814
1815static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1816{
1817 struct intel_display *display = to_intel_display(encoder);
1818 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1819 int max_tmds_clock, vbt_max_tmds_clock;
1820
1821 if (DISPLAY_VER(display) >= 13 || IS_ALDERLAKE_S(dev_priv))
1822 max_tmds_clock = 600000;
1823 else if (DISPLAY_VER(display) >= 10)
1824 max_tmds_clock = 594000;
1825 else if (DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv))
1826 max_tmds_clock = 300000;
1827 else if (DISPLAY_VER(display) >= 5)
1828 max_tmds_clock = 225000;
1829 else
1830 max_tmds_clock = 165000;
1831
1832 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata);
1833 if (vbt_max_tmds_clock)
1834 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1835
1836 return max_tmds_clock;
1837}
1838
1839static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1840 const struct drm_connector_state *conn_state)
1841{
1842 struct intel_connector *connector = hdmi->attached_connector;
1843
1844 return connector->base.display_info.is_hdmi &&
1845 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1846}
1847
1848static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
1849{
1850 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
1851}
1852
1853static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1854 bool respect_downstream_limits,
1855 bool has_hdmi_sink)
1856{
1857 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1858 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1859
1860 if (respect_downstream_limits) {
1861 struct intel_connector *connector = hdmi->attached_connector;
1862 const struct drm_display_info *info = &connector->base.display_info;
1863
1864 if (hdmi->dp_dual_mode.max_tmds_clock)
1865 max_tmds_clock = min(max_tmds_clock,
1866 hdmi->dp_dual_mode.max_tmds_clock);
1867
1868 if (info->max_tmds_clock)
1869 max_tmds_clock = min(max_tmds_clock,
1870 info->max_tmds_clock);
1871 else if (!has_hdmi_sink)
1872 max_tmds_clock = min(max_tmds_clock, 165000);
1873 }
1874
1875 return max_tmds_clock;
1876}
1877
1878static enum drm_mode_status
1879hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1880 int clock, bool respect_downstream_limits,
1881 bool has_hdmi_sink)
1882{
1883 struct intel_display *display = to_intel_display(hdmi);
1884 struct drm_i915_private *dev_priv = to_i915(display->drm);
1885 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1886
1887 if (clock < 25000)
1888 return MODE_CLOCK_LOW;
1889 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1890 has_hdmi_sink))
1891 return MODE_CLOCK_HIGH;
1892
1893 /* GLK DPLL can't generate 446-480 MHz */
1894 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1895 return MODE_CLOCK_RANGE;
1896
1897 /* BXT/GLK DPLL can't generate 223-240 MHz */
1898 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1899 clock > 223333 && clock < 240000)
1900 return MODE_CLOCK_RANGE;
1901
1902 /* CHV DPLL can't generate 216-240 MHz */
1903 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1904 return MODE_CLOCK_RANGE;
1905
1906 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
1907 if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200)
1908 return MODE_CLOCK_RANGE;
1909
1910 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
1911 if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800)
1912 return MODE_CLOCK_RANGE;
1913
1914 /*
1915 * SNPS PHYs' MPLLB table-based programming can only handle a fixed
1916 * set of link rates.
1917 *
1918 * FIXME: We will hopefully get an algorithmic way of programming
1919 * the MPLLB for HDMI in the future.
1920 */
1921 if (DISPLAY_VER(display) >= 14)
1922 return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
1923 else if (IS_DG2(dev_priv))
1924 return intel_snps_phy_check_hdmi_link_rate(clock);
1925
1926 return MODE_OK;
1927}
1928
1929int intel_hdmi_tmds_clock(int clock, int bpc,
1930 enum intel_output_format sink_format)
1931{
1932 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1933 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1934 clock /= 2;
1935
1936 /*
1937 * Need to adjust the port link by:
1938 * 1.5x for 12bpc
1939 * 1.25x for 10bpc
1940 */
1941 return DIV_ROUND_CLOSEST(clock * bpc, 8);
1942}
1943
1944static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc)
1945{
1946 switch (bpc) {
1947 case 12:
1948 return !HAS_GMCH(display);
1949 case 10:
1950 return DISPLAY_VER(display) >= 11;
1951 case 8:
1952 return true;
1953 default:
1954 MISSING_CASE(bpc);
1955 return false;
1956 }
1957}
1958
1959static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
1960 int bpc, bool has_hdmi_sink,
1961 enum intel_output_format sink_format)
1962{
1963 const struct drm_display_info *info = &connector->display_info;
1964 const struct drm_hdmi_info *hdmi = &info->hdmi;
1965
1966 switch (bpc) {
1967 case 12:
1968 if (!has_hdmi_sink)
1969 return false;
1970
1971 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1972 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1973 else
1974 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
1975 case 10:
1976 if (!has_hdmi_sink)
1977 return false;
1978
1979 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1980 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1981 else
1982 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
1983 case 8:
1984 return true;
1985 default:
1986 MISSING_CASE(bpc);
1987 return false;
1988 }
1989}
1990
1991static enum drm_mode_status
1992intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1993 bool has_hdmi_sink,
1994 enum intel_output_format sink_format)
1995{
1996 struct intel_display *display = to_intel_display(connector->dev);
1997 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1998 enum drm_mode_status status = MODE_OK;
1999 int bpc;
2000
2001 /*
2002 * Try all color depths since valid port clock range
2003 * can have holes. Any mode that can be used with at
2004 * least one color depth is accepted.
2005 */
2006 for (bpc = 12; bpc >= 8; bpc -= 2) {
2007 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
2008
2009 if (!intel_hdmi_source_bpc_possible(display, bpc))
2010 continue;
2011
2012 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format))
2013 continue;
2014
2015 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
2016 if (status == MODE_OK)
2017 return MODE_OK;
2018 }
2019
2020 /* can never happen */
2021 drm_WARN_ON(display->drm, status == MODE_OK);
2022
2023 return status;
2024}
2025
2026static enum drm_mode_status
2027intel_hdmi_mode_valid(struct drm_connector *connector,
2028 struct drm_display_mode *mode)
2029{
2030 struct intel_display *display = to_intel_display(connector->dev);
2031 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2032 struct drm_i915_private *dev_priv = to_i915(display->drm);
2033 enum drm_mode_status status;
2034 int clock = mode->clock;
2035 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq;
2036 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
2037 bool ycbcr_420_only;
2038 enum intel_output_format sink_format;
2039
2040 status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
2041 if (status != MODE_OK)
2042 return status;
2043
2044 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2045 clock *= 2;
2046
2047 if (clock > max_dotclk)
2048 return MODE_CLOCK_HIGH;
2049
2050 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2051 if (!has_hdmi_sink)
2052 return MODE_CLOCK_LOW;
2053 clock *= 2;
2054 }
2055
2056 /*
2057 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
2058 * enumerated only if FRL is supported. Current platforms do not support
2059 * FRL so prune the higher resolution modes that require doctclock more
2060 * than 600MHz.
2061 */
2062 if (clock > 600000)
2063 return MODE_CLOCK_HIGH;
2064
2065 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
2066
2067 if (ycbcr_420_only)
2068 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2069 else
2070 sink_format = INTEL_OUTPUT_FORMAT_RGB;
2071
2072 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format);
2073 if (status != MODE_OK) {
2074 if (ycbcr_420_only ||
2075 !connector->ycbcr_420_allowed ||
2076 !drm_mode_is_420_also(&connector->display_info, mode))
2077 return status;
2078
2079 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2080 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format);
2081 if (status != MODE_OK)
2082 return status;
2083 }
2084
2085 return intel_mode_valid_max_plane_size(dev_priv, mode, 1);
2086}
2087
2088bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
2089 int bpc, bool has_hdmi_sink)
2090{
2091 struct drm_atomic_state *state = crtc_state->uapi.state;
2092 struct drm_connector_state *connector_state;
2093 struct drm_connector *connector;
2094 int i;
2095
2096 for_each_new_connector_in_state(state, connector, connector_state, i) {
2097 if (connector_state->crtc != crtc_state->uapi.crtc)
2098 continue;
2099
2100 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink,
2101 crtc_state->sink_format))
2102 return false;
2103 }
2104
2105 return true;
2106}
2107
2108static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
2109{
2110 struct intel_display *display = to_intel_display(crtc_state);
2111 const struct drm_display_mode *adjusted_mode =
2112 &crtc_state->hw.adjusted_mode;
2113
2114 if (!intel_hdmi_source_bpc_possible(display, bpc))
2115 return false;
2116
2117 /* Display Wa_1405510057:icl,ehl */
2118 if (intel_hdmi_is_ycbcr420(crtc_state) &&
2119 bpc == 10 && DISPLAY_VER(display) == 11 &&
2120 (adjusted_mode->crtc_hblank_end -
2121 adjusted_mode->crtc_hblank_start) % 8 == 2)
2122 return false;
2123
2124 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink);
2125}
2126
2127static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2128 struct intel_crtc_state *crtc_state,
2129 int clock, bool respect_downstream_limits)
2130{
2131 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2132 int bpc;
2133
2134 /*
2135 * pipe_bpp could already be below 8bpc due to FDI
2136 * bandwidth constraints. HDMI minimum is 8bpc however.
2137 */
2138 bpc = max(crtc_state->pipe_bpp / 3, 8);
2139
2140 /*
2141 * We will never exceed downstream TMDS clock limits while
2142 * attempting deep color. If the user insists on forcing an
2143 * out of spec mode they will have to be satisfied with 8bpc.
2144 */
2145 if (!respect_downstream_limits)
2146 bpc = 8;
2147
2148 for (; bpc >= 8; bpc -= 2) {
2149 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,
2150 crtc_state->sink_format);
2151
2152 if (hdmi_bpc_possible(crtc_state, bpc) &&
2153 hdmi_port_clock_valid(intel_hdmi, tmds_clock,
2154 respect_downstream_limits,
2155 crtc_state->has_hdmi_sink) == MODE_OK)
2156 return bpc;
2157 }
2158
2159 return -EINVAL;
2160}
2161
2162static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2163 struct intel_crtc_state *crtc_state,
2164 bool respect_downstream_limits)
2165{
2166 struct intel_display *display = to_intel_display(encoder);
2167 const struct drm_display_mode *adjusted_mode =
2168 &crtc_state->hw.adjusted_mode;
2169 int bpc, clock = adjusted_mode->crtc_clock;
2170
2171 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2172 clock *= 2;
2173
2174 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2175 respect_downstream_limits);
2176 if (bpc < 0)
2177 return bpc;
2178
2179 crtc_state->port_clock =
2180 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format);
2181
2182 /*
2183 * pipe_bpp could already be below 8bpc due to
2184 * FDI bandwidth constraints. We shouldn't bump it
2185 * back up to the HDMI minimum 8bpc in that case.
2186 */
2187 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2188
2189 drm_dbg_kms(display->drm,
2190 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2191 bpc, crtc_state->pipe_bpp);
2192
2193 return 0;
2194}
2195
2196bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2197 const struct drm_connector_state *conn_state)
2198{
2199 const struct intel_digital_connector_state *intel_conn_state =
2200 to_intel_digital_connector_state(conn_state);
2201 const struct drm_display_mode *adjusted_mode =
2202 &crtc_state->hw.adjusted_mode;
2203
2204 /*
2205 * Our YCbCr output is always limited range.
2206 * crtc_state->limited_color_range only applies to RGB,
2207 * and it must never be set for YCbCr or we risk setting
2208 * some conflicting bits in TRANSCONF which will mess up
2209 * the colors on the monitor.
2210 */
2211 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2212 return false;
2213
2214 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2215 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2216 return crtc_state->has_hdmi_sink &&
2217 drm_default_rgb_quant_range(adjusted_mode) ==
2218 HDMI_QUANTIZATION_RANGE_LIMITED;
2219 } else {
2220 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2221 }
2222}
2223
2224static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2225 const struct intel_crtc_state *crtc_state,
2226 const struct drm_connector_state *conn_state)
2227{
2228 struct drm_connector *connector = conn_state->connector;
2229 const struct intel_digital_connector_state *intel_conn_state =
2230 to_intel_digital_connector_state(conn_state);
2231
2232 if (!crtc_state->has_hdmi_sink)
2233 return false;
2234
2235 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2236 return connector->display_info.has_audio;
2237 else
2238 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2239}
2240
2241static enum intel_output_format
2242intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state,
2243 struct intel_connector *connector,
2244 bool ycbcr_420_output)
2245{
2246 if (!crtc_state->has_hdmi_sink)
2247 return INTEL_OUTPUT_FORMAT_RGB;
2248
2249 if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
2250 return INTEL_OUTPUT_FORMAT_YCBCR420;
2251 else
2252 return INTEL_OUTPUT_FORMAT_RGB;
2253}
2254
2255static enum intel_output_format
2256intel_hdmi_output_format(const struct intel_crtc_state *crtc_state)
2257{
2258 return crtc_state->sink_format;
2259}
2260
2261static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2262 struct intel_crtc_state *crtc_state,
2263 const struct drm_connector_state *conn_state,
2264 bool respect_downstream_limits)
2265{
2266 struct intel_display *display = to_intel_display(encoder);
2267 struct intel_connector *connector = to_intel_connector(conn_state->connector);
2268 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2269 const struct drm_display_info *info = &connector->base.display_info;
2270 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2271 int ret;
2272
2273 crtc_state->sink_format =
2274 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only);
2275
2276 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) {
2277 drm_dbg_kms(display->drm,
2278 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2279 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2280 }
2281
2282 crtc_state->output_format = intel_hdmi_output_format(crtc_state);
2283 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2284 if (ret) {
2285 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2286 !crtc_state->has_hdmi_sink ||
2287 !connector->base.ycbcr_420_allowed ||
2288 !drm_mode_is_420_also(info, adjusted_mode))
2289 return ret;
2290
2291 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2292 crtc_state->output_format = intel_hdmi_output_format(crtc_state);
2293 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2294 }
2295
2296 return ret;
2297}
2298
2299static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state)
2300{
2301 return crtc_state->uapi.encoder_mask &&
2302 !is_power_of_2(crtc_state->uapi.encoder_mask);
2303}
2304
2305static bool source_supports_scrambling(struct intel_encoder *encoder)
2306{
2307 /*
2308 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and
2309 * scrambling is supported.
2310 * But there seem to be cases where certain platforms that support
2311 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is
2312 * capped by VBT to less than 340MHz.
2313 *
2314 * In such cases when an HDMI2.0 sink is connected, it creates a
2315 * problem : the platform and the sink both support scrambling but the
2316 * HDMI 1.4 retimer chip doesn't.
2317 *
2318 * So go for scrambling, based on the max tmds clock taking into account,
2319 * restrictions coming from VBT.
2320 */
2321 return intel_hdmi_source_max_tmds_clock(encoder) > 340000;
2322}
2323
2324bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder,
2325 const struct intel_crtc_state *crtc_state,
2326 const struct drm_connector_state *conn_state)
2327{
2328 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
2329
2330 return intel_has_hdmi_sink(hdmi, conn_state) &&
2331 !intel_hdmi_is_cloned(crtc_state);
2332}
2333
2334int intel_hdmi_compute_config(struct intel_encoder *encoder,
2335 struct intel_crtc_state *pipe_config,
2336 struct drm_connector_state *conn_state)
2337{
2338 struct intel_display *display = to_intel_display(encoder);
2339 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2340 struct drm_connector *connector = conn_state->connector;
2341 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2342 int ret;
2343
2344 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2345 return -EINVAL;
2346
2347 if (!connector->interlace_allowed &&
2348 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2349 return -EINVAL;
2350
2351 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2352
2353 if (pipe_config->has_hdmi_sink)
2354 pipe_config->has_infoframe = true;
2355
2356 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2357 pipe_config->pixel_multiplier = 2;
2358
2359 pipe_config->has_audio =
2360 intel_hdmi_has_audio(encoder, pipe_config, conn_state) &&
2361 intel_audio_compute_config(encoder, pipe_config, conn_state);
2362
2363 /*
2364 * Try to respect downstream TMDS clock limits first, if
2365 * that fails assume the user might know something we don't.
2366 */
2367 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
2368 if (ret)
2369 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
2370 if (ret) {
2371 drm_dbg_kms(display->drm,
2372 "unsupported HDMI clock (%d kHz), rejecting mode\n",
2373 pipe_config->hw.adjusted_mode.crtc_clock);
2374 return ret;
2375 }
2376
2377 if (intel_hdmi_is_ycbcr420(pipe_config)) {
2378 ret = intel_panel_fitting(pipe_config, conn_state);
2379 if (ret)
2380 return ret;
2381 }
2382
2383 pipe_config->limited_color_range =
2384 intel_hdmi_limited_color_range(pipe_config, conn_state);
2385
2386 if (conn_state->picture_aspect_ratio)
2387 adjusted_mode->picture_aspect_ratio =
2388 conn_state->picture_aspect_ratio;
2389
2390 pipe_config->lane_count = 4;
2391
2392 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) {
2393 if (scdc->scrambling.low_rates)
2394 pipe_config->hdmi_scrambling = true;
2395
2396 if (pipe_config->port_clock > 340000) {
2397 pipe_config->hdmi_scrambling = true;
2398 pipe_config->hdmi_high_tmds_clock_ratio = true;
2399 }
2400 }
2401
2402 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2403 conn_state);
2404
2405 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2406 drm_dbg_kms(display->drm, "bad AVI infoframe\n");
2407 return -EINVAL;
2408 }
2409
2410 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2411 drm_dbg_kms(display->drm, "bad SPD infoframe\n");
2412 return -EINVAL;
2413 }
2414
2415 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2416 drm_dbg_kms(display->drm, "bad HDMI infoframe\n");
2417 return -EINVAL;
2418 }
2419
2420 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2421 drm_dbg_kms(display->drm, "bad DRM infoframe\n");
2422 return -EINVAL;
2423 }
2424
2425 return 0;
2426}
2427
2428void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder)
2429{
2430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2431
2432 /*
2433 * Give a hand to buggy BIOSen which forget to turn
2434 * the TMDS output buffers back on after a reboot.
2435 */
2436 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2437}
2438
2439static void
2440intel_hdmi_unset_edid(struct drm_connector *connector)
2441{
2442 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2443
2444 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2445 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2446
2447 drm_edid_free(to_intel_connector(connector)->detect_edid);
2448 to_intel_connector(connector)->detect_edid = NULL;
2449}
2450
2451static void
2452intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector)
2453{
2454 struct intel_display *display = to_intel_display(connector->dev);
2455 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2456 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2457 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2458 struct i2c_adapter *ddc = connector->ddc;
2459 enum drm_dp_dual_mode_type type;
2460
2461 type = drm_dp_dual_mode_detect(display->drm, ddc);
2462
2463 /*
2464 * Type 1 DVI adaptors are not required to implement any
2465 * registers, so we can't always detect their presence.
2466 * Ideally we should be able to check the state of the
2467 * CONFIG1 pin, but no such luck on our hardware.
2468 *
2469 * The only method left to us is to check the VBT to see
2470 * if the port is a dual mode capable DP port.
2471 */
2472 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2473 if (!connector->force &&
2474 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) {
2475 drm_dbg_kms(display->drm,
2476 "Assuming DP dual mode adaptor presence based on VBT\n");
2477 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2478 } else {
2479 type = DRM_DP_DUAL_MODE_NONE;
2480 }
2481 }
2482
2483 if (type == DRM_DP_DUAL_MODE_NONE)
2484 return;
2485
2486 hdmi->dp_dual_mode.type = type;
2487 hdmi->dp_dual_mode.max_tmds_clock =
2488 drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc);
2489
2490 drm_dbg_kms(display->drm,
2491 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2492 drm_dp_get_dual_mode_type_name(type),
2493 hdmi->dp_dual_mode.max_tmds_clock);
2494
2495 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */
2496 if ((DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv)) &&
2497 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) {
2498 drm_dbg_kms(display->drm,
2499 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
2500 hdmi->dp_dual_mode.max_tmds_clock = 0;
2501 }
2502}
2503
2504static bool
2505intel_hdmi_set_edid(struct drm_connector *connector)
2506{
2507 struct intel_display *display = to_intel_display(connector->dev);
2508 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2509 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2510 struct i2c_adapter *ddc = connector->ddc;
2511 intel_wakeref_t wakeref;
2512 const struct drm_edid *drm_edid;
2513 bool connected = false;
2514
2515 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2516
2517 drm_edid = drm_edid_read_ddc(connector, ddc);
2518
2519 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) {
2520 drm_dbg_kms(display->drm,
2521 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2522 intel_gmbus_force_bit(ddc, true);
2523 drm_edid = drm_edid_read_ddc(connector, ddc);
2524 intel_gmbus_force_bit(ddc, false);
2525 }
2526
2527 /* Below we depend on display info having been updated */
2528 drm_edid_connector_update(connector, drm_edid);
2529
2530 to_intel_connector(connector)->detect_edid = drm_edid;
2531
2532 if (drm_edid_is_digital(drm_edid)) {
2533 intel_hdmi_dp_dual_mode_detect(connector);
2534
2535 connected = true;
2536 }
2537
2538 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2539
2540 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier,
2541 connector->display_info.source_physical_address);
2542
2543 return connected;
2544}
2545
2546static enum drm_connector_status
2547intel_hdmi_detect(struct drm_connector *connector, bool force)
2548{
2549 struct intel_display *display = to_intel_display(connector->dev);
2550 enum drm_connector_status status = connector_status_disconnected;
2551 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2552 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2553 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2554 intel_wakeref_t wakeref;
2555
2556 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
2557 connector->base.id, connector->name);
2558
2559 if (!intel_display_device_enabled(dev_priv))
2560 return connector_status_disconnected;
2561
2562 if (!intel_display_driver_check_access(dev_priv))
2563 return connector->status;
2564
2565 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2566
2567 if (DISPLAY_VER(display) >= 11 &&
2568 !intel_digital_port_connected(encoder))
2569 goto out;
2570
2571 intel_hdmi_unset_edid(connector);
2572
2573 if (intel_hdmi_set_edid(connector))
2574 status = connector_status_connected;
2575
2576out:
2577 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2578
2579 if (status != connector_status_connected)
2580 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2581
2582 return status;
2583}
2584
2585static void
2586intel_hdmi_force(struct drm_connector *connector)
2587{
2588 struct intel_display *display = to_intel_display(connector->dev);
2589 struct drm_i915_private *i915 = to_i915(connector->dev);
2590
2591 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
2592 connector->base.id, connector->name);
2593
2594 if (!intel_display_driver_check_access(i915))
2595 return;
2596
2597 intel_hdmi_unset_edid(connector);
2598
2599 if (connector->status != connector_status_connected)
2600 return;
2601
2602 intel_hdmi_set_edid(connector);
2603}
2604
2605static int intel_hdmi_get_modes(struct drm_connector *connector)
2606{
2607 /* drm_edid_connector_update() done in ->detect() or ->force() */
2608 return drm_edid_connector_add_modes(connector);
2609}
2610
2611static int
2612intel_hdmi_connector_register(struct drm_connector *connector)
2613{
2614 int ret;
2615
2616 ret = intel_connector_register(connector);
2617 if (ret)
2618 return ret;
2619
2620 return ret;
2621}
2622
2623static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2624{
2625 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2626
2627 cec_notifier_conn_unregister(n);
2628
2629 intel_connector_unregister(connector);
2630}
2631
2632static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2633 .detect = intel_hdmi_detect,
2634 .force = intel_hdmi_force,
2635 .fill_modes = drm_helper_probe_single_connector_modes,
2636 .atomic_get_property = intel_digital_connector_atomic_get_property,
2637 .atomic_set_property = intel_digital_connector_atomic_set_property,
2638 .late_register = intel_hdmi_connector_register,
2639 .early_unregister = intel_hdmi_connector_unregister,
2640 .destroy = intel_connector_destroy,
2641 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2642 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2643};
2644
2645static int intel_hdmi_connector_atomic_check(struct drm_connector *connector,
2646 struct drm_atomic_state *state)
2647{
2648 struct intel_display *display = to_intel_display(connector->dev);
2649
2650 if (HAS_DDI(display))
2651 return intel_digital_connector_atomic_check(connector, state);
2652 else
2653 return g4x_hdmi_connector_atomic_check(connector, state);
2654}
2655
2656static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2657 .get_modes = intel_hdmi_get_modes,
2658 .mode_valid = intel_hdmi_mode_valid,
2659 .atomic_check = intel_hdmi_connector_atomic_check,
2660};
2661
2662static void
2663intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2664{
2665 struct intel_display *display = to_intel_display(intel_hdmi);
2666
2667 intel_attach_force_audio_property(connector);
2668 intel_attach_broadcast_rgb_property(connector);
2669 intel_attach_aspect_ratio_property(connector);
2670
2671 intel_attach_hdmi_colorspace_property(connector);
2672 drm_connector_attach_content_type_property(connector);
2673
2674 if (DISPLAY_VER(display) >= 10)
2675 drm_connector_attach_hdr_output_metadata_property(connector);
2676
2677 if (!HAS_GMCH(display))
2678 drm_connector_attach_max_bpc_property(connector, 8, 12);
2679}
2680
2681/*
2682 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2683 * @encoder: intel_encoder
2684 * @connector: drm_connector
2685 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2686 * or reset the high tmds clock ratio for scrambling
2687 * @scrambling: bool to Indicate if the function needs to set or reset
2688 * sink scrambling
2689 *
2690 * This function handles scrambling on HDMI 2.0 capable sinks.
2691 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2692 * it enables scrambling. This should be called before enabling the HDMI
2693 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2694 * detect a scrambled clock within 100 ms.
2695 *
2696 * Returns:
2697 * True on success, false on failure.
2698 */
2699bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2700 struct drm_connector *connector,
2701 bool high_tmds_clock_ratio,
2702 bool scrambling)
2703{
2704 struct intel_display *display = to_intel_display(encoder);
2705 struct drm_scrambling *sink_scrambling =
2706 &connector->display_info.hdmi.scdc.scrambling;
2707
2708 if (!sink_scrambling->supported)
2709 return true;
2710
2711 drm_dbg_kms(display->drm,
2712 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2713 connector->base.id, connector->name,
2714 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10);
2715
2716 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2717 return drm_scdc_set_high_tmds_clock_ratio(connector, high_tmds_clock_ratio) &&
2718 drm_scdc_set_scrambling(connector, scrambling);
2719}
2720
2721static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder)
2722{
2723 enum port port = encoder->port;
2724 u8 ddc_pin;
2725
2726 switch (port) {
2727 case PORT_B:
2728 ddc_pin = GMBUS_PIN_DPB;
2729 break;
2730 case PORT_C:
2731 ddc_pin = GMBUS_PIN_DPC;
2732 break;
2733 case PORT_D:
2734 ddc_pin = GMBUS_PIN_DPD_CHV;
2735 break;
2736 default:
2737 MISSING_CASE(port);
2738 ddc_pin = GMBUS_PIN_DPB;
2739 break;
2740 }
2741 return ddc_pin;
2742}
2743
2744static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder)
2745{
2746 enum port port = encoder->port;
2747 u8 ddc_pin;
2748
2749 switch (port) {
2750 case PORT_B:
2751 ddc_pin = GMBUS_PIN_1_BXT;
2752 break;
2753 case PORT_C:
2754 ddc_pin = GMBUS_PIN_2_BXT;
2755 break;
2756 default:
2757 MISSING_CASE(port);
2758 ddc_pin = GMBUS_PIN_1_BXT;
2759 break;
2760 }
2761 return ddc_pin;
2762}
2763
2764static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder)
2765{
2766 enum port port = encoder->port;
2767 u8 ddc_pin;
2768
2769 switch (port) {
2770 case PORT_B:
2771 ddc_pin = GMBUS_PIN_1_BXT;
2772 break;
2773 case PORT_C:
2774 ddc_pin = GMBUS_PIN_2_BXT;
2775 break;
2776 case PORT_D:
2777 ddc_pin = GMBUS_PIN_4_CNP;
2778 break;
2779 case PORT_F:
2780 ddc_pin = GMBUS_PIN_3_BXT;
2781 break;
2782 default:
2783 MISSING_CASE(port);
2784 ddc_pin = GMBUS_PIN_1_BXT;
2785 break;
2786 }
2787 return ddc_pin;
2788}
2789
2790static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder)
2791{
2792 struct intel_display *display = to_intel_display(encoder);
2793 enum port port = encoder->port;
2794
2795 if (intel_encoder_is_combo(encoder))
2796 return GMBUS_PIN_1_BXT + port;
2797 else if (intel_encoder_is_tc(encoder))
2798 return GMBUS_PIN_9_TC1_ICP + intel_encoder_to_tc(encoder);
2799
2800 drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port));
2801 return GMBUS_PIN_2_BXT;
2802}
2803
2804static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder)
2805{
2806 enum phy phy = intel_encoder_to_phy(encoder);
2807 u8 ddc_pin;
2808
2809 switch (phy) {
2810 case PHY_A:
2811 ddc_pin = GMBUS_PIN_1_BXT;
2812 break;
2813 case PHY_B:
2814 ddc_pin = GMBUS_PIN_2_BXT;
2815 break;
2816 case PHY_C:
2817 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2818 break;
2819 default:
2820 MISSING_CASE(phy);
2821 ddc_pin = GMBUS_PIN_1_BXT;
2822 break;
2823 }
2824 return ddc_pin;
2825}
2826
2827static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder)
2828{
2829 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2830 enum phy phy = intel_encoder_to_phy(encoder);
2831
2832 WARN_ON(encoder->port == PORT_C);
2833
2834 /*
2835 * Pin mapping for RKL depends on which PCH is present. With TGP, the
2836 * final two outputs use type-c pins, even though they're actually
2837 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2838 * all outputs.
2839 */
2840 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2841 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2842
2843 return GMBUS_PIN_1_BXT + phy;
2844}
2845
2846static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder)
2847{
2848 struct intel_display *display = to_intel_display(encoder);
2849 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2850 enum phy phy = intel_encoder_to_phy(encoder);
2851
2852 drm_WARN_ON(display->drm, encoder->port == PORT_A);
2853
2854 /*
2855 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP,
2856 * final two outputs use type-c pins, even though they're actually
2857 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2858 * all outputs.
2859 */
2860 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2861 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2862
2863 return GMBUS_PIN_1_BXT + phy;
2864}
2865
2866static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder)
2867{
2868 return intel_encoder_to_phy(encoder) + 1;
2869}
2870
2871static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder)
2872{
2873 enum phy phy = intel_encoder_to_phy(encoder);
2874
2875 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C);
2876
2877 /*
2878 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2879 * except first combo output.
2880 */
2881 if (phy == PHY_A)
2882 return GMBUS_PIN_1_BXT;
2883
2884 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2885}
2886
2887static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder)
2888{
2889 enum port port = encoder->port;
2890 u8 ddc_pin;
2891
2892 switch (port) {
2893 case PORT_B:
2894 ddc_pin = GMBUS_PIN_DPB;
2895 break;
2896 case PORT_C:
2897 ddc_pin = GMBUS_PIN_DPC;
2898 break;
2899 case PORT_D:
2900 ddc_pin = GMBUS_PIN_DPD;
2901 break;
2902 default:
2903 MISSING_CASE(port);
2904 ddc_pin = GMBUS_PIN_DPB;
2905 break;
2906 }
2907 return ddc_pin;
2908}
2909
2910static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder)
2911{
2912 struct intel_display *display = to_intel_display(encoder);
2913 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2914 u8 ddc_pin;
2915
2916 if (IS_ALDERLAKE_S(dev_priv))
2917 ddc_pin = adls_encoder_to_ddc_pin(encoder);
2918 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2919 ddc_pin = dg1_encoder_to_ddc_pin(encoder);
2920 else if (IS_ROCKETLAKE(dev_priv))
2921 ddc_pin = rkl_encoder_to_ddc_pin(encoder);
2922 else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(dev_priv))
2923 ddc_pin = gen9bc_tgp_encoder_to_ddc_pin(encoder);
2924 else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
2925 HAS_PCH_TGP(dev_priv))
2926 ddc_pin = mcc_encoder_to_ddc_pin(encoder);
2927 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2928 ddc_pin = icl_encoder_to_ddc_pin(encoder);
2929 else if (HAS_PCH_CNP(dev_priv))
2930 ddc_pin = cnp_encoder_to_ddc_pin(encoder);
2931 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2932 ddc_pin = bxt_encoder_to_ddc_pin(encoder);
2933 else if (IS_CHERRYVIEW(dev_priv))
2934 ddc_pin = chv_encoder_to_ddc_pin(encoder);
2935 else
2936 ddc_pin = g4x_encoder_to_ddc_pin(encoder);
2937
2938 return ddc_pin;
2939}
2940
2941static struct intel_encoder *
2942get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
2943{
2944 struct intel_display *display = to_intel_display(encoder);
2945 struct intel_encoder *other;
2946
2947 for_each_intel_encoder(display->drm, other) {
2948 struct intel_connector *connector;
2949
2950 if (other == encoder)
2951 continue;
2952
2953 if (!intel_encoder_is_dig_port(other))
2954 continue;
2955
2956 connector = enc_to_dig_port(other)->hdmi.attached_connector;
2957
2958 if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin))
2959 return other;
2960 }
2961
2962 return NULL;
2963}
2964
2965static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2966{
2967 struct intel_display *display = to_intel_display(encoder);
2968 struct intel_encoder *other;
2969 const char *source;
2970 u8 ddc_pin;
2971
2972 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata);
2973 source = "VBT";
2974
2975 if (!ddc_pin) {
2976 ddc_pin = intel_hdmi_default_ddc_pin(encoder);
2977 source = "platform default";
2978 }
2979
2980 if (!intel_gmbus_is_valid_pin(display, ddc_pin)) {
2981 drm_dbg_kms(display->drm,
2982 "[ENCODER:%d:%s] Invalid DDC pin %d\n",
2983 encoder->base.base.id, encoder->base.name, ddc_pin);
2984 return 0;
2985 }
2986
2987 other = get_encoder_by_ddc_pin(encoder, ddc_pin);
2988 if (other) {
2989 drm_dbg_kms(display->drm,
2990 "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n",
2991 encoder->base.base.id, encoder->base.name, ddc_pin,
2992 other->base.base.id, other->base.name);
2993 return 0;
2994 }
2995
2996 drm_dbg_kms(display->drm,
2997 "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n",
2998 encoder->base.base.id, encoder->base.name,
2999 ddc_pin, source);
3000
3001 return ddc_pin;
3002}
3003
3004void intel_infoframe_init(struct intel_digital_port *dig_port)
3005{
3006 struct intel_display *display = to_intel_display(dig_port);
3007 struct drm_i915_private *dev_priv =
3008 to_i915(dig_port->base.base.dev);
3009
3010 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3011 dig_port->write_infoframe = vlv_write_infoframe;
3012 dig_port->read_infoframe = vlv_read_infoframe;
3013 dig_port->set_infoframes = vlv_set_infoframes;
3014 dig_port->infoframes_enabled = vlv_infoframes_enabled;
3015 } else if (IS_G4X(dev_priv)) {
3016 dig_port->write_infoframe = g4x_write_infoframe;
3017 dig_port->read_infoframe = g4x_read_infoframe;
3018 dig_port->set_infoframes = g4x_set_infoframes;
3019 dig_port->infoframes_enabled = g4x_infoframes_enabled;
3020 } else if (HAS_DDI(display)) {
3021 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) {
3022 dig_port->write_infoframe = lspcon_write_infoframe;
3023 dig_port->read_infoframe = lspcon_read_infoframe;
3024 dig_port->set_infoframes = lspcon_set_infoframes;
3025 dig_port->infoframes_enabled = lspcon_infoframes_enabled;
3026 } else {
3027 dig_port->write_infoframe = hsw_write_infoframe;
3028 dig_port->read_infoframe = hsw_read_infoframe;
3029 dig_port->set_infoframes = hsw_set_infoframes;
3030 dig_port->infoframes_enabled = hsw_infoframes_enabled;
3031 }
3032 } else if (HAS_PCH_IBX(dev_priv)) {
3033 dig_port->write_infoframe = ibx_write_infoframe;
3034 dig_port->read_infoframe = ibx_read_infoframe;
3035 dig_port->set_infoframes = ibx_set_infoframes;
3036 dig_port->infoframes_enabled = ibx_infoframes_enabled;
3037 } else {
3038 dig_port->write_infoframe = cpt_write_infoframe;
3039 dig_port->read_infoframe = cpt_read_infoframe;
3040 dig_port->set_infoframes = cpt_set_infoframes;
3041 dig_port->infoframes_enabled = cpt_infoframes_enabled;
3042 }
3043}
3044
3045void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
3046 struct intel_connector *intel_connector)
3047{
3048 struct intel_display *display = to_intel_display(dig_port);
3049 struct drm_connector *connector = &intel_connector->base;
3050 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3051 struct intel_encoder *intel_encoder = &dig_port->base;
3052 struct drm_device *dev = intel_encoder->base.dev;
3053 enum port port = intel_encoder->port;
3054 struct cec_connector_info conn_info;
3055 u8 ddc_pin;
3056
3057 drm_dbg_kms(display->drm,
3058 "Adding HDMI connector on [ENCODER:%d:%s]\n",
3059 intel_encoder->base.base.id, intel_encoder->base.name);
3060
3061 if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A))
3062 return;
3063
3064 if (drm_WARN(dev, dig_port->max_lanes < 4,
3065 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3066 dig_port->max_lanes, intel_encoder->base.base.id,
3067 intel_encoder->base.name))
3068 return;
3069
3070 ddc_pin = intel_hdmi_ddc_pin(intel_encoder);
3071 if (!ddc_pin)
3072 return;
3073
3074 drm_connector_init_with_ddc(dev, connector,
3075 &intel_hdmi_connector_funcs,
3076 DRM_MODE_CONNECTOR_HDMIA,
3077 intel_gmbus_get_adapter(display, ddc_pin));
3078
3079 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3080
3081 if (DISPLAY_VER(display) < 12)
3082 connector->interlace_allowed = true;
3083
3084 connector->stereo_allowed = true;
3085
3086 if (DISPLAY_VER(display) >= 10)
3087 connector->ycbcr_420_allowed = true;
3088
3089 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
3090 intel_connector->base.polled = intel_connector->polled;
3091
3092 if (HAS_DDI(display))
3093 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3094 else
3095 intel_connector->get_hw_state = intel_connector_get_hw_state;
3096
3097 intel_hdmi_add_properties(intel_hdmi, connector);
3098
3099 intel_connector_attach_encoder(intel_connector, intel_encoder);
3100 intel_hdmi->attached_connector = intel_connector;
3101
3102 if (is_hdcp_supported(display, port)) {
3103 int ret = intel_hdcp_init(intel_connector, dig_port,
3104 &intel_hdmi_hdcp_shim);
3105 if (ret)
3106 drm_dbg_kms(display->drm,
3107 "HDCP init failed, skipping.\n");
3108 }
3109
3110 cec_fill_conn_info_from_drm(&conn_info, connector);
3111
3112 intel_hdmi->cec_notifier =
3113 cec_notifier_conn_register(dev->dev, port_identifier(port),
3114 &conn_info);
3115 if (!intel_hdmi->cec_notifier)
3116 drm_dbg_kms(display->drm, "CEC notifier get failed\n");
3117}
3118
3119/*
3120 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3121 * @vactive: Vactive of a display mode
3122 *
3123 * @return: appropriate dsc slice height for a given mode.
3124 */
3125int intel_hdmi_dsc_get_slice_height(int vactive)
3126{
3127 int slice_height;
3128
3129 /*
3130 * Slice Height determination : HDMI2.1 Section 7.7.5.2
3131 * Select smallest slice height >=96, that results in a valid PPS and
3132 * requires minimum padding lines required for final slice.
3133 *
3134 * Assumption : Vactive is even.
3135 */
3136 for (slice_height = 96; slice_height <= vactive; slice_height += 2)
3137 if (vactive % slice_height == 0)
3138 return slice_height;
3139
3140 return 0;
3141}
3142
3143/*
3144 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3145 * and dsc decoder capabilities
3146 *
3147 * @crtc_state: intel crtc_state
3148 * @src_max_slices: maximum slices supported by the DSC encoder
3149 * @src_max_slice_width: maximum slice width supported by DSC encoder
3150 * @hdmi_max_slices: maximum slices supported by sink DSC decoder
3151 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3152 *
3153 * @return: num of dsc slices that can be supported by the dsc encoder
3154 * and decoder.
3155 */
3156int
3157intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
3158 int src_max_slices, int src_max_slice_width,
3159 int hdmi_max_slices, int hdmi_throughput)
3160{
3161/* Pixel rates in KPixels/sec */
3162#define HDMI_DSC_PEAK_PIXEL_RATE 2720000
3163/*
3164 * Rates at which the source and sink are required to process pixels in each
3165 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
3166 */
3167#define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000
3168#define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000
3169
3170/* Spec limits the slice width to 2720 pixels */
3171#define MAX_HDMI_SLICE_WIDTH 2720
3172 int kslice_adjust;
3173 int adjusted_clk_khz;
3174 int min_slices;
3175 int target_slices;
3176 int max_throughput; /* max clock freq. in khz per slice */
3177 int max_slice_width;
3178 int slice_width;
3179 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3180
3181 if (!hdmi_throughput)
3182 return 0;
3183
3184 /*
3185 * Slice Width determination : HDMI2.1 Section 7.7.5.1
3186 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
3187 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
3188 * dividing adjusted clock value by 10.
3189 */
3190 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3191 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3192 kslice_adjust = 10;
3193 else
3194 kslice_adjust = 5;
3195
3196 /*
3197 * As per spec, the rate at which the source and the sink process
3198 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
3199 * This depends upon the pixel clock rate and output formats
3200 * (kslice adjust).
3201 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
3202 * at max 340MHz, otherwise they can be processed at max 400MHz.
3203 */
3204
3205 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
3206
3207 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
3208 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3209 else
3210 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3211
3212 /*
3213 * Taking into account the sink's capability for maximum
3214 * clock per slice (in MHz) as read from HF-VSDB.
3215 */
3216 max_throughput = min(max_throughput, hdmi_throughput * 1000);
3217
3218 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3219 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3220
3221 /*
3222 * Keep on increasing the num of slices/line, starting from min_slices
3223 * per line till we get such a number, for which the slice_width is
3224 * just less than max_slice_width. The slices/line selected should be
3225 * less than or equal to the max horizontal slices that the combination
3226 * of PCON encoder and HDMI decoder can support.
3227 */
3228 slice_width = max_slice_width;
3229
3230 do {
3231 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3232 target_slices = 1;
3233 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3234 target_slices = 2;
3235 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3236 target_slices = 4;
3237 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3238 target_slices = 8;
3239 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3240 target_slices = 12;
3241 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3242 target_slices = 16;
3243 else
3244 return 0;
3245
3246 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3247 if (slice_width >= max_slice_width)
3248 min_slices = target_slices + 1;
3249 } while (slice_width >= max_slice_width);
3250
3251 return target_slices;
3252}
3253
3254/*
3255 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3256 * source and sink capabilities.
3257 *
3258 * @src_fraction_bpp: fractional bpp supported by the source
3259 * @slice_width: dsc slice width supported by the source and sink
3260 * @num_slices: num of slices supported by the source and sink
3261 * @output_format: video output format
3262 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3263 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3264 *
3265 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3266 */
3267int
3268intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3269 int output_format, bool hdmi_all_bpp,
3270 int hdmi_max_chunk_bytes)
3271{
3272 int max_dsc_bpp, min_dsc_bpp;
3273 int target_bytes;
3274 bool bpp_found = false;
3275 int bpp_decrement_x16;
3276 int bpp_target;
3277 int bpp_target_x16;
3278
3279 /*
3280 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3281 * Start with the max bpp and keep on decrementing with
3282 * fractional bpp, if supported by PCON DSC encoder
3283 *
3284 * for each bpp we check if no of bytes can be supported by HDMI sink
3285 */
3286
3287 /* Assuming: bpc as 8*/
3288 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3289 min_dsc_bpp = 6;
3290 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3291 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3292 output_format == INTEL_OUTPUT_FORMAT_RGB) {
3293 min_dsc_bpp = 8;
3294 max_dsc_bpp = 3 * 8; /* 3*bpc */
3295 } else {
3296 /* Assuming 4:2:2 encoding */
3297 min_dsc_bpp = 7;
3298 max_dsc_bpp = 2 * 8; /* 2*bpc */
3299 }
3300
3301 /*
3302 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3303 * Section 7.7.34 : Source shall not enable compressed Video
3304 * Transport with bpp_target settings above 12 bpp unless
3305 * DSC_all_bpp is set to 1.
3306 */
3307 if (!hdmi_all_bpp)
3308 max_dsc_bpp = min(max_dsc_bpp, 12);
3309
3310 /*
3311 * The Sink has a limit of compressed data in bytes for a scanline,
3312 * as described in max_chunk_bytes field in HFVSDB block of edid.
3313 * The no. of bytes depend on the target bits per pixel that the
3314 * source configures. So we start with the max_bpp and calculate
3315 * the target_chunk_bytes. We keep on decrementing the target_bpp,
3316 * till we get the target_chunk_bytes just less than what the sink's
3317 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3318 *
3319 * The decrement is according to the fractional support from PCON DSC
3320 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3321 *
3322 * bpp_target_x16 = bpp_target * 16
3323 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3324 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3325 */
3326
3327 bpp_target = max_dsc_bpp;
3328
3329 /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3330 if (!src_fractional_bpp)
3331 src_fractional_bpp = 1;
3332 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3333 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3334
3335 while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3336 int bpp;
3337
3338 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3339 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3340 if (target_bytes <= hdmi_max_chunk_bytes) {
3341 bpp_found = true;
3342 break;
3343 }
3344 bpp_target_x16 -= bpp_decrement_x16;
3345 }
3346 if (bpp_found)
3347 return bpp_target_x16;
3348
3349 return 0;
3350}
1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/delay.h>
30#include <linux/hdmi.h>
31#include <linux/i2c.h>
32#include <linux/slab.h>
33#include <linux/string_helpers.h>
34
35#include <drm/display/drm_hdcp_helper.h>
36#include <drm/display/drm_hdmi_helper.h>
37#include <drm/display/drm_scdc_helper.h>
38#include <drm/drm_atomic_helper.h>
39#include <drm/drm_crtc.h>
40#include <drm/drm_edid.h>
41#include <drm/intel_lpe_audio.h>
42
43#include "i915_debugfs.h"
44#include "i915_drv.h"
45#include "i915_reg.h"
46#include "intel_atomic.h"
47#include "intel_connector.h"
48#include "intel_ddi.h"
49#include "intel_de.h"
50#include "intel_display_types.h"
51#include "intel_dp.h"
52#include "intel_gmbus.h"
53#include "intel_hdcp.h"
54#include "intel_hdcp_regs.h"
55#include "intel_hdmi.h"
56#include "intel_lspcon.h"
57#include "intel_panel.h"
58#include "intel_snps_phy.h"
59
60static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
61{
62 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
63}
64
65static void
66assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
67{
68 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi);
69 u32 enabled_bits;
70
71 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
72
73 drm_WARN(&dev_priv->drm,
74 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
75 "HDMI port enabled, expecting disabled\n");
76}
77
78static void
79assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
80 enum transcoder cpu_transcoder)
81{
82 drm_WARN(&dev_priv->drm,
83 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
84 TRANS_DDI_FUNC_ENABLE,
85 "HDMI transcoder function enabled, expecting disabled\n");
86}
87
88static u32 g4x_infoframe_index(unsigned int type)
89{
90 switch (type) {
91 case HDMI_PACKET_TYPE_GAMUT_METADATA:
92 return VIDEO_DIP_SELECT_GAMUT;
93 case HDMI_INFOFRAME_TYPE_AVI:
94 return VIDEO_DIP_SELECT_AVI;
95 case HDMI_INFOFRAME_TYPE_SPD:
96 return VIDEO_DIP_SELECT_SPD;
97 case HDMI_INFOFRAME_TYPE_VENDOR:
98 return VIDEO_DIP_SELECT_VENDOR;
99 default:
100 MISSING_CASE(type);
101 return 0;
102 }
103}
104
105static u32 g4x_infoframe_enable(unsigned int type)
106{
107 switch (type) {
108 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
109 return VIDEO_DIP_ENABLE_GCP;
110 case HDMI_PACKET_TYPE_GAMUT_METADATA:
111 return VIDEO_DIP_ENABLE_GAMUT;
112 case DP_SDP_VSC:
113 return 0;
114 case HDMI_INFOFRAME_TYPE_AVI:
115 return VIDEO_DIP_ENABLE_AVI;
116 case HDMI_INFOFRAME_TYPE_SPD:
117 return VIDEO_DIP_ENABLE_SPD;
118 case HDMI_INFOFRAME_TYPE_VENDOR:
119 return VIDEO_DIP_ENABLE_VENDOR;
120 case HDMI_INFOFRAME_TYPE_DRM:
121 return 0;
122 default:
123 MISSING_CASE(type);
124 return 0;
125 }
126}
127
128static u32 hsw_infoframe_enable(unsigned int type)
129{
130 switch (type) {
131 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
132 return VIDEO_DIP_ENABLE_GCP_HSW;
133 case HDMI_PACKET_TYPE_GAMUT_METADATA:
134 return VIDEO_DIP_ENABLE_GMP_HSW;
135 case DP_SDP_VSC:
136 return VIDEO_DIP_ENABLE_VSC_HSW;
137 case DP_SDP_PPS:
138 return VDIP_ENABLE_PPS;
139 case HDMI_INFOFRAME_TYPE_AVI:
140 return VIDEO_DIP_ENABLE_AVI_HSW;
141 case HDMI_INFOFRAME_TYPE_SPD:
142 return VIDEO_DIP_ENABLE_SPD_HSW;
143 case HDMI_INFOFRAME_TYPE_VENDOR:
144 return VIDEO_DIP_ENABLE_VS_HSW;
145 case HDMI_INFOFRAME_TYPE_DRM:
146 return VIDEO_DIP_ENABLE_DRM_GLK;
147 default:
148 MISSING_CASE(type);
149 return 0;
150 }
151}
152
153static i915_reg_t
154hsw_dip_data_reg(struct drm_i915_private *dev_priv,
155 enum transcoder cpu_transcoder,
156 unsigned int type,
157 int i)
158{
159 switch (type) {
160 case HDMI_PACKET_TYPE_GAMUT_METADATA:
161 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
162 case DP_SDP_VSC:
163 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
164 case DP_SDP_PPS:
165 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
166 case HDMI_INFOFRAME_TYPE_AVI:
167 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
168 case HDMI_INFOFRAME_TYPE_SPD:
169 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
170 case HDMI_INFOFRAME_TYPE_VENDOR:
171 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
172 case HDMI_INFOFRAME_TYPE_DRM:
173 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
174 default:
175 MISSING_CASE(type);
176 return INVALID_MMIO_REG;
177 }
178}
179
180static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
181 unsigned int type)
182{
183 switch (type) {
184 case DP_SDP_VSC:
185 return VIDEO_DIP_VSC_DATA_SIZE;
186 case DP_SDP_PPS:
187 return VIDEO_DIP_PPS_DATA_SIZE;
188 case HDMI_PACKET_TYPE_GAMUT_METADATA:
189 if (DISPLAY_VER(dev_priv) >= 11)
190 return VIDEO_DIP_GMP_DATA_SIZE;
191 else
192 return VIDEO_DIP_DATA_SIZE;
193 default:
194 return VIDEO_DIP_DATA_SIZE;
195 }
196}
197
198static void g4x_write_infoframe(struct intel_encoder *encoder,
199 const struct intel_crtc_state *crtc_state,
200 unsigned int type,
201 const void *frame, ssize_t len)
202{
203 const u32 *data = frame;
204 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
205 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
206 int i;
207
208 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
209 "Writing DIP with CTL reg disabled\n");
210
211 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
212 val |= g4x_infoframe_index(type);
213
214 val &= ~g4x_infoframe_enable(type);
215
216 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
217
218 for (i = 0; i < len; i += 4) {
219 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
220 data++;
221 }
222 /* Write every possible data byte to force correct ECC calculation. */
223 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
224 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
225
226 val |= g4x_infoframe_enable(type);
227 val &= ~VIDEO_DIP_FREQ_MASK;
228 val |= VIDEO_DIP_FREQ_VSYNC;
229
230 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
231 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
232}
233
234static void g4x_read_infoframe(struct intel_encoder *encoder,
235 const struct intel_crtc_state *crtc_state,
236 unsigned int type,
237 void *frame, ssize_t len)
238{
239 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
240 u32 val, *data = frame;
241 int i;
242
243 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
244
245 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
246 val |= g4x_infoframe_index(type);
247
248 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
249
250 for (i = 0; i < len; i += 4)
251 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
252}
253
254static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
255 const struct intel_crtc_state *pipe_config)
256{
257 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
258 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
259
260 if ((val & VIDEO_DIP_ENABLE) == 0)
261 return 0;
262
263 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
264 return 0;
265
266 return val & (VIDEO_DIP_ENABLE_AVI |
267 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
268}
269
270static void ibx_write_infoframe(struct intel_encoder *encoder,
271 const struct intel_crtc_state *crtc_state,
272 unsigned int type,
273 const void *frame, ssize_t len)
274{
275 const u32 *data = frame;
276 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
277 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
278 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
279 u32 val = intel_de_read(dev_priv, reg);
280 int i;
281
282 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
283 "Writing DIP with CTL reg disabled\n");
284
285 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
286 val |= g4x_infoframe_index(type);
287
288 val &= ~g4x_infoframe_enable(type);
289
290 intel_de_write(dev_priv, reg, val);
291
292 for (i = 0; i < len; i += 4) {
293 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
294 *data);
295 data++;
296 }
297 /* Write every possible data byte to force correct ECC calculation. */
298 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
299 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
300
301 val |= g4x_infoframe_enable(type);
302 val &= ~VIDEO_DIP_FREQ_MASK;
303 val |= VIDEO_DIP_FREQ_VSYNC;
304
305 intel_de_write(dev_priv, reg, val);
306 intel_de_posting_read(dev_priv, reg);
307}
308
309static void ibx_read_infoframe(struct intel_encoder *encoder,
310 const struct intel_crtc_state *crtc_state,
311 unsigned int type,
312 void *frame, ssize_t len)
313{
314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
315 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
316 u32 val, *data = frame;
317 int i;
318
319 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
320
321 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
322 val |= g4x_infoframe_index(type);
323
324 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
325
326 for (i = 0; i < len; i += 4)
327 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
328}
329
330static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
331 const struct intel_crtc_state *pipe_config)
332{
333 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
334 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
335 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
336 u32 val = intel_de_read(dev_priv, reg);
337
338 if ((val & VIDEO_DIP_ENABLE) == 0)
339 return 0;
340
341 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
342 return 0;
343
344 return val & (VIDEO_DIP_ENABLE_AVI |
345 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
346 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
347}
348
349static void cpt_write_infoframe(struct intel_encoder *encoder,
350 const struct intel_crtc_state *crtc_state,
351 unsigned int type,
352 const void *frame, ssize_t len)
353{
354 const u32 *data = frame;
355 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
356 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
357 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
358 u32 val = intel_de_read(dev_priv, reg);
359 int i;
360
361 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
362 "Writing DIP with CTL reg disabled\n");
363
364 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
365 val |= g4x_infoframe_index(type);
366
367 /* The DIP control register spec says that we need to update the AVI
368 * infoframe without clearing its enable bit */
369 if (type != HDMI_INFOFRAME_TYPE_AVI)
370 val &= ~g4x_infoframe_enable(type);
371
372 intel_de_write(dev_priv, reg, val);
373
374 for (i = 0; i < len; i += 4) {
375 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
376 *data);
377 data++;
378 }
379 /* Write every possible data byte to force correct ECC calculation. */
380 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
381 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
382
383 val |= g4x_infoframe_enable(type);
384 val &= ~VIDEO_DIP_FREQ_MASK;
385 val |= VIDEO_DIP_FREQ_VSYNC;
386
387 intel_de_write(dev_priv, reg, val);
388 intel_de_posting_read(dev_priv, reg);
389}
390
391static void cpt_read_infoframe(struct intel_encoder *encoder,
392 const struct intel_crtc_state *crtc_state,
393 unsigned int type,
394 void *frame, ssize_t len)
395{
396 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
397 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
398 u32 val, *data = frame;
399 int i;
400
401 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
402
403 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
404 val |= g4x_infoframe_index(type);
405
406 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
407
408 for (i = 0; i < len; i += 4)
409 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
410}
411
412static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
413 const struct intel_crtc_state *pipe_config)
414{
415 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
416 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
417 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
418
419 if ((val & VIDEO_DIP_ENABLE) == 0)
420 return 0;
421
422 return val & (VIDEO_DIP_ENABLE_AVI |
423 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
424 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
425}
426
427static void vlv_write_infoframe(struct intel_encoder *encoder,
428 const struct intel_crtc_state *crtc_state,
429 unsigned int type,
430 const void *frame, ssize_t len)
431{
432 const u32 *data = frame;
433 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
435 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
436 u32 val = intel_de_read(dev_priv, reg);
437 int i;
438
439 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
440 "Writing DIP with CTL reg disabled\n");
441
442 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
443 val |= g4x_infoframe_index(type);
444
445 val &= ~g4x_infoframe_enable(type);
446
447 intel_de_write(dev_priv, reg, val);
448
449 for (i = 0; i < len; i += 4) {
450 intel_de_write(dev_priv,
451 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
452 data++;
453 }
454 /* Write every possible data byte to force correct ECC calculation. */
455 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
456 intel_de_write(dev_priv,
457 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
458
459 val |= g4x_infoframe_enable(type);
460 val &= ~VIDEO_DIP_FREQ_MASK;
461 val |= VIDEO_DIP_FREQ_VSYNC;
462
463 intel_de_write(dev_priv, reg, val);
464 intel_de_posting_read(dev_priv, reg);
465}
466
467static void vlv_read_infoframe(struct intel_encoder *encoder,
468 const struct intel_crtc_state *crtc_state,
469 unsigned int type,
470 void *frame, ssize_t len)
471{
472 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
474 u32 val, *data = frame;
475 int i;
476
477 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
478
479 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
480 val |= g4x_infoframe_index(type);
481
482 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
483
484 for (i = 0; i < len; i += 4)
485 *data++ = intel_de_read(dev_priv,
486 VLV_TVIDEO_DIP_DATA(crtc->pipe));
487}
488
489static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
490 const struct intel_crtc_state *pipe_config)
491{
492 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
493 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
494 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
495
496 if ((val & VIDEO_DIP_ENABLE) == 0)
497 return 0;
498
499 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
500 return 0;
501
502 return val & (VIDEO_DIP_ENABLE_AVI |
503 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
504 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
505}
506
507void hsw_write_infoframe(struct intel_encoder *encoder,
508 const struct intel_crtc_state *crtc_state,
509 unsigned int type,
510 const void *frame, ssize_t len)
511{
512 const u32 *data = frame;
513 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
514 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
515 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
516 int data_size;
517 int i;
518 u32 val = intel_de_read(dev_priv, ctl_reg);
519
520 data_size = hsw_dip_data_size(dev_priv, type);
521
522 drm_WARN_ON(&dev_priv->drm, len > data_size);
523
524 val &= ~hsw_infoframe_enable(type);
525 intel_de_write(dev_priv, ctl_reg, val);
526
527 for (i = 0; i < len; i += 4) {
528 intel_de_write(dev_priv,
529 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
530 *data);
531 data++;
532 }
533 /* Write every possible data byte to force correct ECC calculation. */
534 for (; i < data_size; i += 4)
535 intel_de_write(dev_priv,
536 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
537 0);
538
539 /* Wa_14013475917 */
540 if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr &&
541 type == DP_SDP_VSC)
542 return;
543
544 val |= hsw_infoframe_enable(type);
545 intel_de_write(dev_priv, ctl_reg, val);
546 intel_de_posting_read(dev_priv, ctl_reg);
547}
548
549void hsw_read_infoframe(struct intel_encoder *encoder,
550 const struct intel_crtc_state *crtc_state,
551 unsigned int type, void *frame, ssize_t len)
552{
553 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
554 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
555 u32 *data = frame;
556 int i;
557
558 for (i = 0; i < len; i += 4)
559 *data++ = intel_de_read(dev_priv,
560 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
561}
562
563static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
564 const struct intel_crtc_state *pipe_config)
565{
566 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
567 u32 val = intel_de_read(dev_priv,
568 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
569 u32 mask;
570
571 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
572 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
573 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
574
575 if (DISPLAY_VER(dev_priv) >= 10)
576 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
577
578 return val & mask;
579}
580
581static const u8 infoframe_type_to_idx[] = {
582 HDMI_PACKET_TYPE_GENERAL_CONTROL,
583 HDMI_PACKET_TYPE_GAMUT_METADATA,
584 DP_SDP_VSC,
585 HDMI_INFOFRAME_TYPE_AVI,
586 HDMI_INFOFRAME_TYPE_SPD,
587 HDMI_INFOFRAME_TYPE_VENDOR,
588 HDMI_INFOFRAME_TYPE_DRM,
589};
590
591u32 intel_hdmi_infoframe_enable(unsigned int type)
592{
593 int i;
594
595 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
596 if (infoframe_type_to_idx[i] == type)
597 return BIT(i);
598 }
599
600 return 0;
601}
602
603u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
604 const struct intel_crtc_state *crtc_state)
605{
606 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
607 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
608 u32 val, ret = 0;
609 int i;
610
611 val = dig_port->infoframes_enabled(encoder, crtc_state);
612
613 /* map from hardware bits to dip idx */
614 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
615 unsigned int type = infoframe_type_to_idx[i];
616
617 if (HAS_DDI(dev_priv)) {
618 if (val & hsw_infoframe_enable(type))
619 ret |= BIT(i);
620 } else {
621 if (val & g4x_infoframe_enable(type))
622 ret |= BIT(i);
623 }
624 }
625
626 return ret;
627}
628
629/*
630 * The data we write to the DIP data buffer registers is 1 byte bigger than the
631 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
632 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
633 * used for both technologies.
634 *
635 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
636 * DW1: DB3 | DB2 | DB1 | DB0
637 * DW2: DB7 | DB6 | DB5 | DB4
638 * DW3: ...
639 *
640 * (HB is Header Byte, DB is Data Byte)
641 *
642 * The hdmi pack() functions don't know about that hardware specific hole so we
643 * trick them by giving an offset into the buffer and moving back the header
644 * bytes by one.
645 */
646static void intel_write_infoframe(struct intel_encoder *encoder,
647 const struct intel_crtc_state *crtc_state,
648 enum hdmi_infoframe_type type,
649 const union hdmi_infoframe *frame)
650{
651 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
652 u8 buffer[VIDEO_DIP_DATA_SIZE];
653 ssize_t len;
654
655 if ((crtc_state->infoframes.enable &
656 intel_hdmi_infoframe_enable(type)) == 0)
657 return;
658
659 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
660 return;
661
662 /* see comment above for the reason for this offset */
663 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
664 if (drm_WARN_ON(encoder->base.dev, len < 0))
665 return;
666
667 /* Insert the 'hole' (see big comment above) at position 3 */
668 memmove(&buffer[0], &buffer[1], 3);
669 buffer[3] = 0;
670 len++;
671
672 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
673}
674
675void intel_read_infoframe(struct intel_encoder *encoder,
676 const struct intel_crtc_state *crtc_state,
677 enum hdmi_infoframe_type type,
678 union hdmi_infoframe *frame)
679{
680 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
681 u8 buffer[VIDEO_DIP_DATA_SIZE];
682 int ret;
683
684 if ((crtc_state->infoframes.enable &
685 intel_hdmi_infoframe_enable(type)) == 0)
686 return;
687
688 dig_port->read_infoframe(encoder, crtc_state,
689 type, buffer, sizeof(buffer));
690
691 /* Fill the 'hole' (see big comment above) at position 3 */
692 memmove(&buffer[1], &buffer[0], 3);
693
694 /* see comment above for the reason for this offset */
695 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
696 if (ret) {
697 drm_dbg_kms(encoder->base.dev,
698 "Failed to unpack infoframe type 0x%02x\n", type);
699 return;
700 }
701
702 if (frame->any.type != type)
703 drm_dbg_kms(encoder->base.dev,
704 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
705 frame->any.type, type);
706}
707
708static bool
709intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
710 struct intel_crtc_state *crtc_state,
711 struct drm_connector_state *conn_state)
712{
713 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
714 const struct drm_display_mode *adjusted_mode =
715 &crtc_state->hw.adjusted_mode;
716 struct drm_connector *connector = conn_state->connector;
717 int ret;
718
719 if (!crtc_state->has_infoframe)
720 return true;
721
722 crtc_state->infoframes.enable |=
723 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
724
725 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
726 adjusted_mode);
727 if (ret)
728 return false;
729
730 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
731 frame->colorspace = HDMI_COLORSPACE_YUV420;
732 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
733 frame->colorspace = HDMI_COLORSPACE_YUV444;
734 else
735 frame->colorspace = HDMI_COLORSPACE_RGB;
736
737 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);
738
739 /* nonsense combination */
740 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
741 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
742
743 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
744 drm_hdmi_avi_infoframe_quant_range(frame, connector,
745 adjusted_mode,
746 crtc_state->limited_color_range ?
747 HDMI_QUANTIZATION_RANGE_LIMITED :
748 HDMI_QUANTIZATION_RANGE_FULL);
749 } else {
750 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
751 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
752 }
753
754 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
755
756 /* TODO: handle pixel repetition for YCBCR420 outputs */
757
758 ret = hdmi_avi_infoframe_check(frame);
759 if (drm_WARN_ON(encoder->base.dev, ret))
760 return false;
761
762 return true;
763}
764
765static bool
766intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
767 struct intel_crtc_state *crtc_state,
768 struct drm_connector_state *conn_state)
769{
770 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
771 int ret;
772
773 if (!crtc_state->has_infoframe)
774 return true;
775
776 crtc_state->infoframes.enable |=
777 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
778
779 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
780 if (drm_WARN_ON(encoder->base.dev, ret))
781 return false;
782
783 frame->sdi = HDMI_SPD_SDI_PC;
784
785 ret = hdmi_spd_infoframe_check(frame);
786 if (drm_WARN_ON(encoder->base.dev, ret))
787 return false;
788
789 return true;
790}
791
792static bool
793intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
794 struct intel_crtc_state *crtc_state,
795 struct drm_connector_state *conn_state)
796{
797 struct hdmi_vendor_infoframe *frame =
798 &crtc_state->infoframes.hdmi.vendor.hdmi;
799 const struct drm_display_info *info =
800 &conn_state->connector->display_info;
801 int ret;
802
803 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
804 return true;
805
806 crtc_state->infoframes.enable |=
807 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
808
809 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
810 conn_state->connector,
811 &crtc_state->hw.adjusted_mode);
812 if (drm_WARN_ON(encoder->base.dev, ret))
813 return false;
814
815 ret = hdmi_vendor_infoframe_check(frame);
816 if (drm_WARN_ON(encoder->base.dev, ret))
817 return false;
818
819 return true;
820}
821
822static bool
823intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
824 struct intel_crtc_state *crtc_state,
825 struct drm_connector_state *conn_state)
826{
827 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
828 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
829 int ret;
830
831 if (DISPLAY_VER(dev_priv) < 10)
832 return true;
833
834 if (!crtc_state->has_infoframe)
835 return true;
836
837 if (!conn_state->hdr_output_metadata)
838 return true;
839
840 crtc_state->infoframes.enable |=
841 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
842
843 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
844 if (ret < 0) {
845 drm_dbg_kms(&dev_priv->drm,
846 "couldn't set HDR metadata in infoframe\n");
847 return false;
848 }
849
850 ret = hdmi_drm_infoframe_check(frame);
851 if (drm_WARN_ON(&dev_priv->drm, ret))
852 return false;
853
854 return true;
855}
856
857static void g4x_set_infoframes(struct intel_encoder *encoder,
858 bool enable,
859 const struct intel_crtc_state *crtc_state,
860 const struct drm_connector_state *conn_state)
861{
862 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
863 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
864 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
865 i915_reg_t reg = VIDEO_DIP_CTL;
866 u32 val = intel_de_read(dev_priv, reg);
867 u32 port = VIDEO_DIP_PORT(encoder->port);
868
869 assert_hdmi_port_disabled(intel_hdmi);
870
871 /* If the registers were not initialized yet, they might be zeroes,
872 * which means we're selecting the AVI DIP and we're setting its
873 * frequency to once. This seems to really confuse the HW and make
874 * things stop working (the register spec says the AVI always needs to
875 * be sent every VSync). So here we avoid writing to the register more
876 * than we need and also explicitly select the AVI DIP and explicitly
877 * set its frequency to every VSync. Avoiding to write it twice seems to
878 * be enough to solve the problem, but being defensive shouldn't hurt us
879 * either. */
880 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
881
882 if (!enable) {
883 if (!(val & VIDEO_DIP_ENABLE))
884 return;
885 if (port != (val & VIDEO_DIP_PORT_MASK)) {
886 drm_dbg_kms(&dev_priv->drm,
887 "video DIP still enabled on port %c\n",
888 (val & VIDEO_DIP_PORT_MASK) >> 29);
889 return;
890 }
891 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
892 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
893 intel_de_write(dev_priv, reg, val);
894 intel_de_posting_read(dev_priv, reg);
895 return;
896 }
897
898 if (port != (val & VIDEO_DIP_PORT_MASK)) {
899 if (val & VIDEO_DIP_ENABLE) {
900 drm_dbg_kms(&dev_priv->drm,
901 "video DIP already enabled on port %c\n",
902 (val & VIDEO_DIP_PORT_MASK) >> 29);
903 return;
904 }
905 val &= ~VIDEO_DIP_PORT_MASK;
906 val |= port;
907 }
908
909 val |= VIDEO_DIP_ENABLE;
910 val &= ~(VIDEO_DIP_ENABLE_AVI |
911 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
912
913 intel_de_write(dev_priv, reg, val);
914 intel_de_posting_read(dev_priv, reg);
915
916 intel_write_infoframe(encoder, crtc_state,
917 HDMI_INFOFRAME_TYPE_AVI,
918 &crtc_state->infoframes.avi);
919 intel_write_infoframe(encoder, crtc_state,
920 HDMI_INFOFRAME_TYPE_SPD,
921 &crtc_state->infoframes.spd);
922 intel_write_infoframe(encoder, crtc_state,
923 HDMI_INFOFRAME_TYPE_VENDOR,
924 &crtc_state->infoframes.hdmi);
925}
926
927/*
928 * Determine if default_phase=1 can be indicated in the GCP infoframe.
929 *
930 * From HDMI specification 1.4a:
931 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
932 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
933 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
934 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
935 * phase of 0
936 */
937static bool gcp_default_phase_possible(int pipe_bpp,
938 const struct drm_display_mode *mode)
939{
940 unsigned int pixels_per_group;
941
942 switch (pipe_bpp) {
943 case 30:
944 /* 4 pixels in 5 clocks */
945 pixels_per_group = 4;
946 break;
947 case 36:
948 /* 2 pixels in 3 clocks */
949 pixels_per_group = 2;
950 break;
951 case 48:
952 /* 1 pixel in 2 clocks */
953 pixels_per_group = 1;
954 break;
955 default:
956 /* phase information not relevant for 8bpc */
957 return false;
958 }
959
960 return mode->crtc_hdisplay % pixels_per_group == 0 &&
961 mode->crtc_htotal % pixels_per_group == 0 &&
962 mode->crtc_hblank_start % pixels_per_group == 0 &&
963 mode->crtc_hblank_end % pixels_per_group == 0 &&
964 mode->crtc_hsync_start % pixels_per_group == 0 &&
965 mode->crtc_hsync_end % pixels_per_group == 0 &&
966 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
967 mode->crtc_htotal/2 % pixels_per_group == 0);
968}
969
970static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
971 const struct intel_crtc_state *crtc_state,
972 const struct drm_connector_state *conn_state)
973{
974 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
975 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
976 i915_reg_t reg;
977
978 if ((crtc_state->infoframes.enable &
979 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
980 return false;
981
982 if (HAS_DDI(dev_priv))
983 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
984 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
985 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
986 else if (HAS_PCH_SPLIT(dev_priv))
987 reg = TVIDEO_DIP_GCP(crtc->pipe);
988 else
989 return false;
990
991 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
992
993 return true;
994}
995
996void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
997 struct intel_crtc_state *crtc_state)
998{
999 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1000 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1001 i915_reg_t reg;
1002
1003 if ((crtc_state->infoframes.enable &
1004 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1005 return;
1006
1007 if (HAS_DDI(dev_priv))
1008 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1009 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1010 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1011 else if (HAS_PCH_SPLIT(dev_priv))
1012 reg = TVIDEO_DIP_GCP(crtc->pipe);
1013 else
1014 return;
1015
1016 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1017}
1018
1019static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1020 struct intel_crtc_state *crtc_state,
1021 struct drm_connector_state *conn_state)
1022{
1023 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1024
1025 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1026 return;
1027
1028 crtc_state->infoframes.enable |=
1029 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1030
1031 /* Indicate color indication for deep color mode */
1032 if (crtc_state->pipe_bpp > 24)
1033 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1034
1035 /* Enable default_phase whenever the display mode is suitably aligned */
1036 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1037 &crtc_state->hw.adjusted_mode))
1038 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1039}
1040
1041static void ibx_set_infoframes(struct intel_encoder *encoder,
1042 bool enable,
1043 const struct intel_crtc_state *crtc_state,
1044 const struct drm_connector_state *conn_state)
1045{
1046 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1047 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1048 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1049 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1050 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1051 u32 val = intel_de_read(dev_priv, reg);
1052 u32 port = VIDEO_DIP_PORT(encoder->port);
1053
1054 assert_hdmi_port_disabled(intel_hdmi);
1055
1056 /* See the big comment in g4x_set_infoframes() */
1057 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1058
1059 if (!enable) {
1060 if (!(val & VIDEO_DIP_ENABLE))
1061 return;
1062 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1063 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1064 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1065 intel_de_write(dev_priv, reg, val);
1066 intel_de_posting_read(dev_priv, reg);
1067 return;
1068 }
1069
1070 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1071 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1072 "DIP already enabled on port %c\n",
1073 (val & VIDEO_DIP_PORT_MASK) >> 29);
1074 val &= ~VIDEO_DIP_PORT_MASK;
1075 val |= port;
1076 }
1077
1078 val |= VIDEO_DIP_ENABLE;
1079 val &= ~(VIDEO_DIP_ENABLE_AVI |
1080 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1081 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1082
1083 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1084 val |= VIDEO_DIP_ENABLE_GCP;
1085
1086 intel_de_write(dev_priv, reg, val);
1087 intel_de_posting_read(dev_priv, reg);
1088
1089 intel_write_infoframe(encoder, crtc_state,
1090 HDMI_INFOFRAME_TYPE_AVI,
1091 &crtc_state->infoframes.avi);
1092 intel_write_infoframe(encoder, crtc_state,
1093 HDMI_INFOFRAME_TYPE_SPD,
1094 &crtc_state->infoframes.spd);
1095 intel_write_infoframe(encoder, crtc_state,
1096 HDMI_INFOFRAME_TYPE_VENDOR,
1097 &crtc_state->infoframes.hdmi);
1098}
1099
1100static void cpt_set_infoframes(struct intel_encoder *encoder,
1101 bool enable,
1102 const struct intel_crtc_state *crtc_state,
1103 const struct drm_connector_state *conn_state)
1104{
1105 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1106 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1107 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1108 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1109 u32 val = intel_de_read(dev_priv, reg);
1110
1111 assert_hdmi_port_disabled(intel_hdmi);
1112
1113 /* See the big comment in g4x_set_infoframes() */
1114 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1115
1116 if (!enable) {
1117 if (!(val & VIDEO_DIP_ENABLE))
1118 return;
1119 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1120 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1121 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1122 intel_de_write(dev_priv, reg, val);
1123 intel_de_posting_read(dev_priv, reg);
1124 return;
1125 }
1126
1127 /* Set both together, unset both together: see the spec. */
1128 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1129 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1130 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1131
1132 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1133 val |= VIDEO_DIP_ENABLE_GCP;
1134
1135 intel_de_write(dev_priv, reg, val);
1136 intel_de_posting_read(dev_priv, reg);
1137
1138 intel_write_infoframe(encoder, crtc_state,
1139 HDMI_INFOFRAME_TYPE_AVI,
1140 &crtc_state->infoframes.avi);
1141 intel_write_infoframe(encoder, crtc_state,
1142 HDMI_INFOFRAME_TYPE_SPD,
1143 &crtc_state->infoframes.spd);
1144 intel_write_infoframe(encoder, crtc_state,
1145 HDMI_INFOFRAME_TYPE_VENDOR,
1146 &crtc_state->infoframes.hdmi);
1147}
1148
1149static void vlv_set_infoframes(struct intel_encoder *encoder,
1150 bool enable,
1151 const struct intel_crtc_state *crtc_state,
1152 const struct drm_connector_state *conn_state)
1153{
1154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1155 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1156 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1157 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1158 u32 val = intel_de_read(dev_priv, reg);
1159 u32 port = VIDEO_DIP_PORT(encoder->port);
1160
1161 assert_hdmi_port_disabled(intel_hdmi);
1162
1163 /* See the big comment in g4x_set_infoframes() */
1164 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1165
1166 if (!enable) {
1167 if (!(val & VIDEO_DIP_ENABLE))
1168 return;
1169 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1170 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1171 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1172 intel_de_write(dev_priv, reg, val);
1173 intel_de_posting_read(dev_priv, reg);
1174 return;
1175 }
1176
1177 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1178 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1179 "DIP already enabled on port %c\n",
1180 (val & VIDEO_DIP_PORT_MASK) >> 29);
1181 val &= ~VIDEO_DIP_PORT_MASK;
1182 val |= port;
1183 }
1184
1185 val |= VIDEO_DIP_ENABLE;
1186 val &= ~(VIDEO_DIP_ENABLE_AVI |
1187 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1188 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1189
1190 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1191 val |= VIDEO_DIP_ENABLE_GCP;
1192
1193 intel_de_write(dev_priv, reg, val);
1194 intel_de_posting_read(dev_priv, reg);
1195
1196 intel_write_infoframe(encoder, crtc_state,
1197 HDMI_INFOFRAME_TYPE_AVI,
1198 &crtc_state->infoframes.avi);
1199 intel_write_infoframe(encoder, crtc_state,
1200 HDMI_INFOFRAME_TYPE_SPD,
1201 &crtc_state->infoframes.spd);
1202 intel_write_infoframe(encoder, crtc_state,
1203 HDMI_INFOFRAME_TYPE_VENDOR,
1204 &crtc_state->infoframes.hdmi);
1205}
1206
1207static void hsw_set_infoframes(struct intel_encoder *encoder,
1208 bool enable,
1209 const struct intel_crtc_state *crtc_state,
1210 const struct drm_connector_state *conn_state)
1211{
1212 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1213 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1214 u32 val = intel_de_read(dev_priv, reg);
1215
1216 assert_hdmi_transcoder_func_disabled(dev_priv,
1217 crtc_state->cpu_transcoder);
1218
1219 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1220 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1221 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1222 VIDEO_DIP_ENABLE_DRM_GLK);
1223
1224 if (!enable) {
1225 intel_de_write(dev_priv, reg, val);
1226 intel_de_posting_read(dev_priv, reg);
1227 return;
1228 }
1229
1230 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1231 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1232
1233 intel_de_write(dev_priv, reg, val);
1234 intel_de_posting_read(dev_priv, reg);
1235
1236 intel_write_infoframe(encoder, crtc_state,
1237 HDMI_INFOFRAME_TYPE_AVI,
1238 &crtc_state->infoframes.avi);
1239 intel_write_infoframe(encoder, crtc_state,
1240 HDMI_INFOFRAME_TYPE_SPD,
1241 &crtc_state->infoframes.spd);
1242 intel_write_infoframe(encoder, crtc_state,
1243 HDMI_INFOFRAME_TYPE_VENDOR,
1244 &crtc_state->infoframes.hdmi);
1245 intel_write_infoframe(encoder, crtc_state,
1246 HDMI_INFOFRAME_TYPE_DRM,
1247 &crtc_state->infoframes.drm);
1248}
1249
1250void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1251{
1252 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1253 struct i2c_adapter *adapter;
1254
1255 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1256 return;
1257
1258 adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1259
1260 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1261 enable ? "Enabling" : "Disabling");
1262
1263 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1264}
1265
1266static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1267 unsigned int offset, void *buffer, size_t size)
1268{
1269 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1270 struct intel_hdmi *hdmi = &dig_port->hdmi;
1271 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1272 hdmi->ddc_bus);
1273 int ret;
1274 u8 start = offset & 0xff;
1275 struct i2c_msg msgs[] = {
1276 {
1277 .addr = DRM_HDCP_DDC_ADDR,
1278 .flags = 0,
1279 .len = 1,
1280 .buf = &start,
1281 },
1282 {
1283 .addr = DRM_HDCP_DDC_ADDR,
1284 .flags = I2C_M_RD,
1285 .len = size,
1286 .buf = buffer
1287 }
1288 };
1289 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1290 if (ret == ARRAY_SIZE(msgs))
1291 return 0;
1292 return ret >= 0 ? -EIO : ret;
1293}
1294
1295static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1296 unsigned int offset, void *buffer, size_t size)
1297{
1298 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1299 struct intel_hdmi *hdmi = &dig_port->hdmi;
1300 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1301 hdmi->ddc_bus);
1302 int ret;
1303 u8 *write_buf;
1304 struct i2c_msg msg;
1305
1306 write_buf = kzalloc(size + 1, GFP_KERNEL);
1307 if (!write_buf)
1308 return -ENOMEM;
1309
1310 write_buf[0] = offset & 0xff;
1311 memcpy(&write_buf[1], buffer, size);
1312
1313 msg.addr = DRM_HDCP_DDC_ADDR;
1314 msg.flags = 0,
1315 msg.len = size + 1,
1316 msg.buf = write_buf;
1317
1318 ret = i2c_transfer(adapter, &msg, 1);
1319 if (ret == 1)
1320 ret = 0;
1321 else if (ret >= 0)
1322 ret = -EIO;
1323
1324 kfree(write_buf);
1325 return ret;
1326}
1327
1328static
1329int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1330 u8 *an)
1331{
1332 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1333 struct intel_hdmi *hdmi = &dig_port->hdmi;
1334 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1335 hdmi->ddc_bus);
1336 int ret;
1337
1338 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1339 DRM_HDCP_AN_LEN);
1340 if (ret) {
1341 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1342 ret);
1343 return ret;
1344 }
1345
1346 ret = intel_gmbus_output_aksv(adapter);
1347 if (ret < 0) {
1348 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1349 return ret;
1350 }
1351 return 0;
1352}
1353
1354static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1355 u8 *bksv)
1356{
1357 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1358
1359 int ret;
1360 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1361 DRM_HDCP_KSV_LEN);
1362 if (ret)
1363 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1364 ret);
1365 return ret;
1366}
1367
1368static
1369int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1370 u8 *bstatus)
1371{
1372 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1373
1374 int ret;
1375 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1376 bstatus, DRM_HDCP_BSTATUS_LEN);
1377 if (ret)
1378 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1379 ret);
1380 return ret;
1381}
1382
1383static
1384int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1385 bool *repeater_present)
1386{
1387 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1388 int ret;
1389 u8 val;
1390
1391 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1392 if (ret) {
1393 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1394 ret);
1395 return ret;
1396 }
1397 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1398 return 0;
1399}
1400
1401static
1402int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1403 u8 *ri_prime)
1404{
1405 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1406
1407 int ret;
1408 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1409 ri_prime, DRM_HDCP_RI_LEN);
1410 if (ret)
1411 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1412 ret);
1413 return ret;
1414}
1415
1416static
1417int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1418 bool *ksv_ready)
1419{
1420 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1421 int ret;
1422 u8 val;
1423
1424 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1425 if (ret) {
1426 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1427 ret);
1428 return ret;
1429 }
1430 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1431 return 0;
1432}
1433
1434static
1435int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1436 int num_downstream, u8 *ksv_fifo)
1437{
1438 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1439 int ret;
1440 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1441 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1442 if (ret) {
1443 drm_dbg_kms(&i915->drm,
1444 "Read ksv fifo over DDC failed (%d)\n", ret);
1445 return ret;
1446 }
1447 return 0;
1448}
1449
1450static
1451int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1452 int i, u32 *part)
1453{
1454 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1455 int ret;
1456
1457 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1458 return -EINVAL;
1459
1460 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1461 part, DRM_HDCP_V_PRIME_PART_LEN);
1462 if (ret)
1463 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1464 i, ret);
1465 return ret;
1466}
1467
1468static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1469 enum transcoder cpu_transcoder)
1470{
1471 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1472 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1473 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1474 u32 scanline;
1475 int ret;
1476
1477 for (;;) {
1478 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
1479 if (scanline > 100 && scanline < 200)
1480 break;
1481 usleep_range(25, 50);
1482 }
1483
1484 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1485 false, TRANS_DDI_HDCP_SIGNALLING);
1486 if (ret) {
1487 drm_err(&dev_priv->drm,
1488 "Disable HDCP signalling failed (%d)\n", ret);
1489 return ret;
1490 }
1491
1492 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1493 true, TRANS_DDI_HDCP_SIGNALLING);
1494 if (ret) {
1495 drm_err(&dev_priv->drm,
1496 "Enable HDCP signalling failed (%d)\n", ret);
1497 return ret;
1498 }
1499
1500 return 0;
1501}
1502
1503static
1504int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1505 enum transcoder cpu_transcoder,
1506 bool enable)
1507{
1508 struct intel_hdmi *hdmi = &dig_port->hdmi;
1509 struct intel_connector *connector = hdmi->attached_connector;
1510 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1511 int ret;
1512
1513 if (!enable)
1514 usleep_range(6, 60); /* Bspec says >= 6us */
1515
1516 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1517 cpu_transcoder, enable,
1518 TRANS_DDI_HDCP_SIGNALLING);
1519 if (ret) {
1520 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1521 enable ? "Enable" : "Disable", ret);
1522 return ret;
1523 }
1524
1525 /*
1526 * WA: To fix incorrect positioning of the window of
1527 * opportunity and enc_en signalling in KABYLAKE.
1528 */
1529 if (IS_KABYLAKE(dev_priv) && enable)
1530 return kbl_repositioning_enc_en_signal(connector,
1531 cpu_transcoder);
1532
1533 return 0;
1534}
1535
1536static
1537bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1538 struct intel_connector *connector)
1539{
1540 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1541 enum port port = dig_port->base.port;
1542 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1543 int ret;
1544 union {
1545 u32 reg;
1546 u8 shim[DRM_HDCP_RI_LEN];
1547 } ri;
1548
1549 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1550 if (ret)
1551 return false;
1552
1553 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1554
1555 /* Wait for Ri prime match */
1556 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1557 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1558 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1559 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1560 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1561 port)));
1562 return false;
1563 }
1564 return true;
1565}
1566
1567static
1568bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1569 struct intel_connector *connector)
1570{
1571 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1572 int retry;
1573
1574 for (retry = 0; retry < 3; retry++)
1575 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1576 return true;
1577
1578 drm_err(&i915->drm, "Link check failed\n");
1579 return false;
1580}
1581
1582struct hdcp2_hdmi_msg_timeout {
1583 u8 msg_id;
1584 u16 timeout;
1585};
1586
1587static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1588 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1589 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1590 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1591 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1592 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1593};
1594
1595static
1596int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1597 u8 *rx_status)
1598{
1599 return intel_hdmi_hdcp_read(dig_port,
1600 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1601 rx_status,
1602 HDCP_2_2_HDMI_RXSTATUS_LEN);
1603}
1604
1605static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1606{
1607 int i;
1608
1609 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1610 if (is_paired)
1611 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1612 else
1613 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1614 }
1615
1616 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1617 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1618 return hdcp2_msg_timeout[i].timeout;
1619 }
1620
1621 return -EINVAL;
1622}
1623
1624static int
1625hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1626 u8 msg_id, bool *msg_ready,
1627 ssize_t *msg_sz)
1628{
1629 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1630 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1631 int ret;
1632
1633 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1634 if (ret < 0) {
1635 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1636 ret);
1637 return ret;
1638 }
1639
1640 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1641 rx_status[0]);
1642
1643 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1644 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1645 *msg_sz);
1646 else
1647 *msg_ready = *msg_sz;
1648
1649 return 0;
1650}
1651
1652static ssize_t
1653intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1654 u8 msg_id, bool paired)
1655{
1656 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1657 bool msg_ready = false;
1658 int timeout, ret;
1659 ssize_t msg_sz = 0;
1660
1661 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1662 if (timeout < 0)
1663 return timeout;
1664
1665 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1666 msg_id, &msg_ready,
1667 &msg_sz),
1668 !ret && msg_ready && msg_sz, timeout * 1000,
1669 1000, 5 * 1000);
1670 if (ret)
1671 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1672 msg_id, ret, timeout);
1673
1674 return ret ? ret : msg_sz;
1675}
1676
1677static
1678int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1679 void *buf, size_t size)
1680{
1681 unsigned int offset;
1682
1683 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1684 return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1685}
1686
1687static
1688int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1689 u8 msg_id, void *buf, size_t size)
1690{
1691 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1692 struct intel_hdmi *hdmi = &dig_port->hdmi;
1693 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1694 unsigned int offset;
1695 ssize_t ret;
1696
1697 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1698 hdcp->is_paired);
1699 if (ret < 0)
1700 return ret;
1701
1702 /*
1703 * Available msg size should be equal to or lesser than the
1704 * available buffer.
1705 */
1706 if (ret > size) {
1707 drm_dbg_kms(&i915->drm,
1708 "msg_sz(%zd) is more than exp size(%zu)\n",
1709 ret, size);
1710 return -EINVAL;
1711 }
1712
1713 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1714 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1715 if (ret)
1716 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1717 msg_id, ret);
1718
1719 return ret;
1720}
1721
1722static
1723int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1724 struct intel_connector *connector)
1725{
1726 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1727 int ret;
1728
1729 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1730 if (ret)
1731 return ret;
1732
1733 /*
1734 * Re-auth request and Link Integrity Failures are represented by
1735 * same bit. i.e reauth_req.
1736 */
1737 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1738 ret = HDCP_REAUTH_REQUEST;
1739 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1740 ret = HDCP_TOPOLOGY_CHANGE;
1741
1742 return ret;
1743}
1744
1745static
1746int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1747 bool *capable)
1748{
1749 u8 hdcp2_version;
1750 int ret;
1751
1752 *capable = false;
1753 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1754 &hdcp2_version, sizeof(hdcp2_version));
1755 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1756 *capable = true;
1757
1758 return ret;
1759}
1760
1761static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1762 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1763 .read_bksv = intel_hdmi_hdcp_read_bksv,
1764 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1765 .repeater_present = intel_hdmi_hdcp_repeater_present,
1766 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1767 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1768 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1769 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1770 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1771 .check_link = intel_hdmi_hdcp_check_link,
1772 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1773 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1774 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1775 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1776 .protocol = HDCP_PROTOCOL_HDMI,
1777};
1778
1779static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1780{
1781 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1782 int max_tmds_clock, vbt_max_tmds_clock;
1783
1784 if (DISPLAY_VER(dev_priv) >= 10)
1785 max_tmds_clock = 594000;
1786 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1787 max_tmds_clock = 300000;
1788 else if (DISPLAY_VER(dev_priv) >= 5)
1789 max_tmds_clock = 225000;
1790 else
1791 max_tmds_clock = 165000;
1792
1793 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
1794 if (vbt_max_tmds_clock)
1795 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1796
1797 return max_tmds_clock;
1798}
1799
1800static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1801 const struct drm_connector_state *conn_state)
1802{
1803 return hdmi->has_hdmi_sink &&
1804 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1805}
1806
1807static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
1808{
1809 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
1810}
1811
1812static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1813 bool respect_downstream_limits,
1814 bool has_hdmi_sink)
1815{
1816 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1817 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1818
1819 if (respect_downstream_limits) {
1820 struct intel_connector *connector = hdmi->attached_connector;
1821 const struct drm_display_info *info = &connector->base.display_info;
1822
1823 if (hdmi->dp_dual_mode.max_tmds_clock)
1824 max_tmds_clock = min(max_tmds_clock,
1825 hdmi->dp_dual_mode.max_tmds_clock);
1826
1827 if (info->max_tmds_clock)
1828 max_tmds_clock = min(max_tmds_clock,
1829 info->max_tmds_clock);
1830 else if (!has_hdmi_sink)
1831 max_tmds_clock = min(max_tmds_clock, 165000);
1832 }
1833
1834 return max_tmds_clock;
1835}
1836
1837static enum drm_mode_status
1838hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1839 int clock, bool respect_downstream_limits,
1840 bool has_hdmi_sink)
1841{
1842 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1843 enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);
1844
1845 if (clock < 25000)
1846 return MODE_CLOCK_LOW;
1847 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1848 has_hdmi_sink))
1849 return MODE_CLOCK_HIGH;
1850
1851 /* GLK DPLL can't generate 446-480 MHz */
1852 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1853 return MODE_CLOCK_RANGE;
1854
1855 /* BXT/GLK DPLL can't generate 223-240 MHz */
1856 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1857 clock > 223333 && clock < 240000)
1858 return MODE_CLOCK_RANGE;
1859
1860 /* CHV DPLL can't generate 216-240 MHz */
1861 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1862 return MODE_CLOCK_RANGE;
1863
1864 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
1865 if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)
1866 return MODE_CLOCK_RANGE;
1867
1868 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
1869 if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)
1870 return MODE_CLOCK_RANGE;
1871
1872 /*
1873 * SNPS PHYs' MPLLB table-based programming can only handle a fixed
1874 * set of link rates.
1875 *
1876 * FIXME: We will hopefully get an algorithmic way of programming
1877 * the MPLLB for HDMI in the future.
1878 */
1879 if (IS_DG2(dev_priv))
1880 return intel_snps_phy_check_hdmi_link_rate(clock);
1881
1882 return MODE_OK;
1883}
1884
1885int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
1886{
1887 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1888 if (ycbcr420_output)
1889 clock /= 2;
1890
1891 /*
1892 * Need to adjust the port link by:
1893 * 1.5x for 12bpc
1894 * 1.25x for 10bpc
1895 */
1896 return DIV_ROUND_CLOSEST(clock * bpc, 8);
1897}
1898
1899static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc)
1900{
1901 switch (bpc) {
1902 case 12:
1903 return !HAS_GMCH(i915);
1904 case 10:
1905 return DISPLAY_VER(i915) >= 11;
1906 case 8:
1907 return true;
1908 default:
1909 MISSING_CASE(bpc);
1910 return false;
1911 }
1912}
1913
1914static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
1915 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1916{
1917 const struct drm_display_info *info = &connector->display_info;
1918 const struct drm_hdmi_info *hdmi = &info->hdmi;
1919
1920 switch (bpc) {
1921 case 12:
1922 if (!has_hdmi_sink)
1923 return false;
1924
1925 if (ycbcr420_output)
1926 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1927 else
1928 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
1929 case 10:
1930 if (!has_hdmi_sink)
1931 return false;
1932
1933 if (ycbcr420_output)
1934 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1935 else
1936 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
1937 case 8:
1938 return true;
1939 default:
1940 MISSING_CASE(bpc);
1941 return false;
1942 }
1943}
1944
1945static enum drm_mode_status
1946intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1947 bool has_hdmi_sink, bool ycbcr420_output)
1948{
1949 struct drm_i915_private *i915 = to_i915(connector->dev);
1950 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1951 enum drm_mode_status status = MODE_OK;
1952 int bpc;
1953
1954 /*
1955 * Try all color depths since valid port clock range
1956 * can have holes. Any mode that can be used with at
1957 * least one color depth is accepted.
1958 */
1959 for (bpc = 12; bpc >= 8; bpc -= 2) {
1960 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
1961
1962 if (!intel_hdmi_source_bpc_possible(i915, bpc))
1963 continue;
1964
1965 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
1966 continue;
1967
1968 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
1969 if (status == MODE_OK)
1970 return MODE_OK;
1971 }
1972
1973 /* can never happen */
1974 drm_WARN_ON(&i915->drm, status == MODE_OK);
1975
1976 return status;
1977}
1978
1979static enum drm_mode_status
1980intel_hdmi_mode_valid(struct drm_connector *connector,
1981 struct drm_display_mode *mode)
1982{
1983 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1984 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1985 enum drm_mode_status status;
1986 int clock = mode->clock;
1987 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1988 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1989 bool ycbcr_420_only;
1990
1991 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1992 return MODE_NO_DBLESCAN;
1993
1994 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1995 clock *= 2;
1996
1997 if (clock > max_dotclk)
1998 return MODE_CLOCK_HIGH;
1999
2000 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2001 if (!has_hdmi_sink)
2002 return MODE_CLOCK_LOW;
2003 clock *= 2;
2004 }
2005
2006 /*
2007 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
2008 * enumerated only if FRL is supported. Current platforms do not support
2009 * FRL so prune the higher resolution modes that require doctclock more
2010 * than 600MHz.
2011 */
2012 if (clock > 600000)
2013 return MODE_CLOCK_HIGH;
2014
2015 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
2016
2017 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only);
2018 if (status != MODE_OK) {
2019 if (ycbcr_420_only ||
2020 !connector->ycbcr_420_allowed ||
2021 !drm_mode_is_420_also(&connector->display_info, mode))
2022 return status;
2023
2024 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true);
2025 if (status != MODE_OK)
2026 return status;
2027 }
2028
2029 return intel_mode_valid_max_plane_size(dev_priv, mode, false);
2030}
2031
2032bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
2033 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
2034{
2035 struct drm_atomic_state *state = crtc_state->uapi.state;
2036 struct drm_connector_state *connector_state;
2037 struct drm_connector *connector;
2038 int i;
2039
2040 for_each_new_connector_in_state(state, connector, connector_state, i) {
2041 if (connector_state->crtc != crtc_state->uapi.crtc)
2042 continue;
2043
2044 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
2045 return false;
2046 }
2047
2048 return true;
2049}
2050
2051static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
2052{
2053 struct drm_i915_private *dev_priv =
2054 to_i915(crtc_state->uapi.crtc->dev);
2055 const struct drm_display_mode *adjusted_mode =
2056 &crtc_state->hw.adjusted_mode;
2057
2058 if (!intel_hdmi_source_bpc_possible(dev_priv, bpc))
2059 return false;
2060
2061 /* Display Wa_1405510057:icl,ehl */
2062 if (intel_hdmi_is_ycbcr420(crtc_state) &&
2063 bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2064 (adjusted_mode->crtc_hblank_end -
2065 adjusted_mode->crtc_hblank_start) % 8 == 2)
2066 return false;
2067
2068 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink,
2069 intel_hdmi_is_ycbcr420(crtc_state));
2070}
2071
2072static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2073 struct intel_crtc_state *crtc_state,
2074 int clock, bool respect_downstream_limits)
2075{
2076 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2077 bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
2078 int bpc;
2079
2080 /*
2081 * pipe_bpp could already be below 8bpc due to FDI
2082 * bandwidth constraints. HDMI minimum is 8bpc however.
2083 */
2084 bpc = max(crtc_state->pipe_bpp / 3, 8);
2085
2086 /*
2087 * We will never exceed downstream TMDS clock limits while
2088 * attempting deep color. If the user insists on forcing an
2089 * out of spec mode they will have to be satisfied with 8bpc.
2090 */
2091 if (!respect_downstream_limits)
2092 bpc = 8;
2093
2094 for (; bpc >= 8; bpc -= 2) {
2095 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
2096
2097 if (hdmi_bpc_possible(crtc_state, bpc) &&
2098 hdmi_port_clock_valid(intel_hdmi, tmds_clock,
2099 respect_downstream_limits,
2100 crtc_state->has_hdmi_sink) == MODE_OK)
2101 return bpc;
2102 }
2103
2104 return -EINVAL;
2105}
2106
2107static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2108 struct intel_crtc_state *crtc_state,
2109 bool respect_downstream_limits)
2110{
2111 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2112 const struct drm_display_mode *adjusted_mode =
2113 &crtc_state->hw.adjusted_mode;
2114 int bpc, clock = adjusted_mode->crtc_clock;
2115
2116 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2117 clock *= 2;
2118
2119 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2120 respect_downstream_limits);
2121 if (bpc < 0)
2122 return bpc;
2123
2124 crtc_state->port_clock =
2125 intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state));
2126
2127 /*
2128 * pipe_bpp could already be below 8bpc due to
2129 * FDI bandwidth constraints. We shouldn't bump it
2130 * back up to the HDMI minimum 8bpc in that case.
2131 */
2132 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2133
2134 drm_dbg_kms(&i915->drm,
2135 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2136 bpc, crtc_state->pipe_bpp);
2137
2138 return 0;
2139}
2140
2141bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2142 const struct drm_connector_state *conn_state)
2143{
2144 const struct intel_digital_connector_state *intel_conn_state =
2145 to_intel_digital_connector_state(conn_state);
2146 const struct drm_display_mode *adjusted_mode =
2147 &crtc_state->hw.adjusted_mode;
2148
2149 /*
2150 * Our YCbCr output is always limited range.
2151 * crtc_state->limited_color_range only applies to RGB,
2152 * and it must never be set for YCbCr or we risk setting
2153 * some conflicting bits in PIPECONF which will mess up
2154 * the colors on the monitor.
2155 */
2156 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2157 return false;
2158
2159 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2160 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2161 return crtc_state->has_hdmi_sink &&
2162 drm_default_rgb_quant_range(adjusted_mode) ==
2163 HDMI_QUANTIZATION_RANGE_LIMITED;
2164 } else {
2165 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2166 }
2167}
2168
2169static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2170 const struct intel_crtc_state *crtc_state,
2171 const struct drm_connector_state *conn_state)
2172{
2173 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2174 const struct intel_digital_connector_state *intel_conn_state =
2175 to_intel_digital_connector_state(conn_state);
2176
2177 if (!crtc_state->has_hdmi_sink)
2178 return false;
2179
2180 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2181 return intel_hdmi->has_audio;
2182 else
2183 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2184}
2185
2186static enum intel_output_format
2187intel_hdmi_output_format(const struct intel_crtc_state *crtc_state,
2188 struct intel_connector *connector,
2189 bool ycbcr_420_output)
2190{
2191 if (!crtc_state->has_hdmi_sink)
2192 return INTEL_OUTPUT_FORMAT_RGB;
2193
2194 if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
2195 return INTEL_OUTPUT_FORMAT_YCBCR420;
2196 else
2197 return INTEL_OUTPUT_FORMAT_RGB;
2198}
2199
2200static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2201 struct intel_crtc_state *crtc_state,
2202 const struct drm_connector_state *conn_state,
2203 bool respect_downstream_limits)
2204{
2205 struct intel_connector *connector = to_intel_connector(conn_state->connector);
2206 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2207 const struct drm_display_info *info = &connector->base.display_info;
2208 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2209 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2210 int ret;
2211
2212 crtc_state->output_format =
2213 intel_hdmi_output_format(crtc_state, connector, ycbcr_420_only);
2214
2215 if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
2216 drm_dbg_kms(&i915->drm,
2217 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2218 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
2219 }
2220
2221 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2222 if (ret) {
2223 if (intel_hdmi_is_ycbcr420(crtc_state) ||
2224 !connector->base.ycbcr_420_allowed ||
2225 !drm_mode_is_420_also(info, adjusted_mode))
2226 return ret;
2227
2228 crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector, true);
2229 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2230 }
2231
2232 return ret;
2233}
2234
2235static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state)
2236{
2237 return crtc_state->uapi.encoder_mask &&
2238 !is_power_of_2(crtc_state->uapi.encoder_mask);
2239}
2240
2241int intel_hdmi_compute_config(struct intel_encoder *encoder,
2242 struct intel_crtc_state *pipe_config,
2243 struct drm_connector_state *conn_state)
2244{
2245 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2246 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2247 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2248 struct drm_connector *connector = conn_state->connector;
2249 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2250 int ret;
2251
2252 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2253 return -EINVAL;
2254
2255 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2256 pipe_config->has_hdmi_sink =
2257 intel_has_hdmi_sink(intel_hdmi, conn_state) &&
2258 !intel_hdmi_is_cloned(pipe_config);
2259
2260 if (pipe_config->has_hdmi_sink)
2261 pipe_config->has_infoframe = true;
2262
2263 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2264 pipe_config->pixel_multiplier = 2;
2265
2266 pipe_config->has_audio =
2267 intel_hdmi_has_audio(encoder, pipe_config, conn_state);
2268
2269 /*
2270 * Try to respect downstream TMDS clock limits first, if
2271 * that fails assume the user might know something we don't.
2272 */
2273 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
2274 if (ret)
2275 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
2276 if (ret) {
2277 drm_dbg_kms(&dev_priv->drm,
2278 "unsupported HDMI clock (%d kHz), rejecting mode\n",
2279 pipe_config->hw.adjusted_mode.crtc_clock);
2280 return ret;
2281 }
2282
2283 if (intel_hdmi_is_ycbcr420(pipe_config)) {
2284 ret = intel_panel_fitting(pipe_config, conn_state);
2285 if (ret)
2286 return ret;
2287 }
2288
2289 pipe_config->limited_color_range =
2290 intel_hdmi_limited_color_range(pipe_config, conn_state);
2291
2292 if (conn_state->picture_aspect_ratio)
2293 adjusted_mode->picture_aspect_ratio =
2294 conn_state->picture_aspect_ratio;
2295
2296 pipe_config->lane_count = 4;
2297
2298 if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
2299 if (scdc->scrambling.low_rates)
2300 pipe_config->hdmi_scrambling = true;
2301
2302 if (pipe_config->port_clock > 340000) {
2303 pipe_config->hdmi_scrambling = true;
2304 pipe_config->hdmi_high_tmds_clock_ratio = true;
2305 }
2306 }
2307
2308 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2309 conn_state);
2310
2311 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2312 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2313 return -EINVAL;
2314 }
2315
2316 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2317 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2318 return -EINVAL;
2319 }
2320
2321 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2322 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2323 return -EINVAL;
2324 }
2325
2326 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2327 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2328 return -EINVAL;
2329 }
2330
2331 return 0;
2332}
2333
2334void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder)
2335{
2336 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2337
2338 /*
2339 * Give a hand to buggy BIOSen which forget to turn
2340 * the TMDS output buffers back on after a reboot.
2341 */
2342 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2343}
2344
2345static void
2346intel_hdmi_unset_edid(struct drm_connector *connector)
2347{
2348 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2349
2350 intel_hdmi->has_hdmi_sink = false;
2351 intel_hdmi->has_audio = false;
2352
2353 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2354 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2355
2356 kfree(to_intel_connector(connector)->detect_edid);
2357 to_intel_connector(connector)->detect_edid = NULL;
2358}
2359
2360static void
2361intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector)
2362{
2363 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2364 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2365 enum port port = hdmi_to_dig_port(hdmi)->base.port;
2366 struct i2c_adapter *adapter =
2367 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2368 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2369
2370 /*
2371 * Type 1 DVI adaptors are not required to implement any
2372 * registers, so we can't always detect their presence.
2373 * Ideally we should be able to check the state of the
2374 * CONFIG1 pin, but no such luck on our hardware.
2375 *
2376 * The only method left to us is to check the VBT to see
2377 * if the port is a dual mode capable DP port.
2378 */
2379 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2380 if (!connector->force &&
2381 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2382 drm_dbg_kms(&dev_priv->drm,
2383 "Assuming DP dual mode adaptor presence based on VBT\n");
2384 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2385 } else {
2386 type = DRM_DP_DUAL_MODE_NONE;
2387 }
2388 }
2389
2390 if (type == DRM_DP_DUAL_MODE_NONE)
2391 return;
2392
2393 hdmi->dp_dual_mode.type = type;
2394 hdmi->dp_dual_mode.max_tmds_clock =
2395 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2396
2397 drm_dbg_kms(&dev_priv->drm,
2398 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2399 drm_dp_get_dual_mode_type_name(type),
2400 hdmi->dp_dual_mode.max_tmds_clock);
2401
2402 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */
2403 if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
2404 !intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2405 drm_dbg_kms(&dev_priv->drm,
2406 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
2407 hdmi->dp_dual_mode.max_tmds_clock = 0;
2408 }
2409}
2410
2411static bool
2412intel_hdmi_set_edid(struct drm_connector *connector)
2413{
2414 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2415 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2416 intel_wakeref_t wakeref;
2417 struct edid *edid;
2418 bool connected = false;
2419 struct i2c_adapter *i2c;
2420
2421 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2422
2423 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2424
2425 edid = drm_get_edid(connector, i2c);
2426
2427 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2428 drm_dbg_kms(&dev_priv->drm,
2429 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2430 intel_gmbus_force_bit(i2c, true);
2431 edid = drm_get_edid(connector, i2c);
2432 intel_gmbus_force_bit(i2c, false);
2433 }
2434
2435 to_intel_connector(connector)->detect_edid = edid;
2436 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2437 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2438 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2439
2440 intel_hdmi_dp_dual_mode_detect(connector);
2441
2442 connected = true;
2443 }
2444
2445 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2446
2447 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2448
2449 return connected;
2450}
2451
2452static enum drm_connector_status
2453intel_hdmi_detect(struct drm_connector *connector, bool force)
2454{
2455 enum drm_connector_status status = connector_status_disconnected;
2456 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2457 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2458 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2459 intel_wakeref_t wakeref;
2460
2461 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2462 connector->base.id, connector->name);
2463
2464 if (!INTEL_DISPLAY_ENABLED(dev_priv))
2465 return connector_status_disconnected;
2466
2467 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2468
2469 if (DISPLAY_VER(dev_priv) >= 11 &&
2470 !intel_digital_port_connected(encoder))
2471 goto out;
2472
2473 intel_hdmi_unset_edid(connector);
2474
2475 if (intel_hdmi_set_edid(connector))
2476 status = connector_status_connected;
2477
2478out:
2479 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2480
2481 if (status != connector_status_connected)
2482 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2483
2484 /*
2485 * Make sure the refs for power wells enabled during detect are
2486 * dropped to avoid a new detect cycle triggered by HPD polling.
2487 */
2488 intel_display_power_flush_work(dev_priv);
2489
2490 return status;
2491}
2492
2493static void
2494intel_hdmi_force(struct drm_connector *connector)
2495{
2496 struct drm_i915_private *i915 = to_i915(connector->dev);
2497
2498 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2499 connector->base.id, connector->name);
2500
2501 intel_hdmi_unset_edid(connector);
2502
2503 if (connector->status != connector_status_connected)
2504 return;
2505
2506 intel_hdmi_set_edid(connector);
2507}
2508
2509static int intel_hdmi_get_modes(struct drm_connector *connector)
2510{
2511 struct edid *edid;
2512
2513 edid = to_intel_connector(connector)->detect_edid;
2514 if (edid == NULL)
2515 return 0;
2516
2517 return intel_connector_update_modes(connector, edid);
2518}
2519
2520static struct i2c_adapter *
2521intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2522{
2523 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2524 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2525
2526 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2527}
2528
2529static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2530{
2531 struct drm_i915_private *i915 = to_i915(connector->dev);
2532 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2533 struct kobject *i2c_kobj = &adapter->dev.kobj;
2534 struct kobject *connector_kobj = &connector->kdev->kobj;
2535 int ret;
2536
2537 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2538 if (ret)
2539 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2540}
2541
2542static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2543{
2544 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2545 struct kobject *i2c_kobj = &adapter->dev.kobj;
2546 struct kobject *connector_kobj = &connector->kdev->kobj;
2547
2548 sysfs_remove_link(connector_kobj, i2c_kobj->name);
2549}
2550
2551static int
2552intel_hdmi_connector_register(struct drm_connector *connector)
2553{
2554 int ret;
2555
2556 ret = intel_connector_register(connector);
2557 if (ret)
2558 return ret;
2559
2560 intel_hdmi_create_i2c_symlink(connector);
2561
2562 return ret;
2563}
2564
2565static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2566{
2567 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2568
2569 cec_notifier_conn_unregister(n);
2570
2571 intel_hdmi_remove_i2c_symlink(connector);
2572 intel_connector_unregister(connector);
2573}
2574
2575static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2576 .detect = intel_hdmi_detect,
2577 .force = intel_hdmi_force,
2578 .fill_modes = drm_helper_probe_single_connector_modes,
2579 .atomic_get_property = intel_digital_connector_atomic_get_property,
2580 .atomic_set_property = intel_digital_connector_atomic_set_property,
2581 .late_register = intel_hdmi_connector_register,
2582 .early_unregister = intel_hdmi_connector_unregister,
2583 .destroy = intel_connector_destroy,
2584 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2585 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2586};
2587
2588static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2589 .get_modes = intel_hdmi_get_modes,
2590 .mode_valid = intel_hdmi_mode_valid,
2591 .atomic_check = intel_digital_connector_atomic_check,
2592};
2593
2594static void
2595intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2596{
2597 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2598
2599 intel_attach_force_audio_property(connector);
2600 intel_attach_broadcast_rgb_property(connector);
2601 intel_attach_aspect_ratio_property(connector);
2602
2603 intel_attach_hdmi_colorspace_property(connector);
2604 drm_connector_attach_content_type_property(connector);
2605
2606 if (DISPLAY_VER(dev_priv) >= 10)
2607 drm_connector_attach_hdr_output_metadata_property(connector);
2608
2609 if (!HAS_GMCH(dev_priv))
2610 drm_connector_attach_max_bpc_property(connector, 8, 12);
2611}
2612
2613/*
2614 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2615 * @encoder: intel_encoder
2616 * @connector: drm_connector
2617 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2618 * or reset the high tmds clock ratio for scrambling
2619 * @scrambling: bool to Indicate if the function needs to set or reset
2620 * sink scrambling
2621 *
2622 * This function handles scrambling on HDMI 2.0 capable sinks.
2623 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2624 * it enables scrambling. This should be called before enabling the HDMI
2625 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2626 * detect a scrambled clock within 100 ms.
2627 *
2628 * Returns:
2629 * True on success, false on failure.
2630 */
2631bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2632 struct drm_connector *connector,
2633 bool high_tmds_clock_ratio,
2634 bool scrambling)
2635{
2636 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2637 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2638 struct drm_scrambling *sink_scrambling =
2639 &connector->display_info.hdmi.scdc.scrambling;
2640 struct i2c_adapter *adapter =
2641 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2642
2643 if (!sink_scrambling->supported)
2644 return true;
2645
2646 drm_dbg_kms(&dev_priv->drm,
2647 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2648 connector->base.id, connector->name,
2649 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10);
2650
2651 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2652 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2653 high_tmds_clock_ratio) &&
2654 drm_scdc_set_scrambling(adapter, scrambling);
2655}
2656
2657static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2658{
2659 u8 ddc_pin;
2660
2661 switch (port) {
2662 case PORT_B:
2663 ddc_pin = GMBUS_PIN_DPB;
2664 break;
2665 case PORT_C:
2666 ddc_pin = GMBUS_PIN_DPC;
2667 break;
2668 case PORT_D:
2669 ddc_pin = GMBUS_PIN_DPD_CHV;
2670 break;
2671 default:
2672 MISSING_CASE(port);
2673 ddc_pin = GMBUS_PIN_DPB;
2674 break;
2675 }
2676 return ddc_pin;
2677}
2678
2679static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2680{
2681 u8 ddc_pin;
2682
2683 switch (port) {
2684 case PORT_B:
2685 ddc_pin = GMBUS_PIN_1_BXT;
2686 break;
2687 case PORT_C:
2688 ddc_pin = GMBUS_PIN_2_BXT;
2689 break;
2690 default:
2691 MISSING_CASE(port);
2692 ddc_pin = GMBUS_PIN_1_BXT;
2693 break;
2694 }
2695 return ddc_pin;
2696}
2697
2698static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2699 enum port port)
2700{
2701 u8 ddc_pin;
2702
2703 switch (port) {
2704 case PORT_B:
2705 ddc_pin = GMBUS_PIN_1_BXT;
2706 break;
2707 case PORT_C:
2708 ddc_pin = GMBUS_PIN_2_BXT;
2709 break;
2710 case PORT_D:
2711 ddc_pin = GMBUS_PIN_4_CNP;
2712 break;
2713 case PORT_F:
2714 ddc_pin = GMBUS_PIN_3_BXT;
2715 break;
2716 default:
2717 MISSING_CASE(port);
2718 ddc_pin = GMBUS_PIN_1_BXT;
2719 break;
2720 }
2721 return ddc_pin;
2722}
2723
2724static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2725{
2726 enum phy phy = intel_port_to_phy(dev_priv, port);
2727
2728 if (intel_phy_is_combo(dev_priv, phy))
2729 return GMBUS_PIN_1_BXT + port;
2730 else if (intel_phy_is_tc(dev_priv, phy))
2731 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2732
2733 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2734 return GMBUS_PIN_2_BXT;
2735}
2736
2737static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2738{
2739 enum phy phy = intel_port_to_phy(dev_priv, port);
2740 u8 ddc_pin;
2741
2742 switch (phy) {
2743 case PHY_A:
2744 ddc_pin = GMBUS_PIN_1_BXT;
2745 break;
2746 case PHY_B:
2747 ddc_pin = GMBUS_PIN_2_BXT;
2748 break;
2749 case PHY_C:
2750 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2751 break;
2752 default:
2753 MISSING_CASE(phy);
2754 ddc_pin = GMBUS_PIN_1_BXT;
2755 break;
2756 }
2757 return ddc_pin;
2758}
2759
2760static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2761{
2762 enum phy phy = intel_port_to_phy(dev_priv, port);
2763
2764 WARN_ON(port == PORT_C);
2765
2766 /*
2767 * Pin mapping for RKL depends on which PCH is present. With TGP, the
2768 * final two outputs use type-c pins, even though they're actually
2769 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2770 * all outputs.
2771 */
2772 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2773 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2774
2775 return GMBUS_PIN_1_BXT + phy;
2776}
2777
2778static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2779{
2780 enum phy phy = intel_port_to_phy(i915, port);
2781
2782 drm_WARN_ON(&i915->drm, port == PORT_A);
2783
2784 /*
2785 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP,
2786 * final two outputs use type-c pins, even though they're actually
2787 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2788 * all outputs.
2789 */
2790 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2791 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2792
2793 return GMBUS_PIN_1_BXT + phy;
2794}
2795
2796static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2797{
2798 return intel_port_to_phy(dev_priv, port) + 1;
2799}
2800
2801static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2802{
2803 enum phy phy = intel_port_to_phy(dev_priv, port);
2804
2805 WARN_ON(port == PORT_B || port == PORT_C);
2806
2807 /*
2808 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2809 * except first combo output.
2810 */
2811 if (phy == PHY_A)
2812 return GMBUS_PIN_1_BXT;
2813
2814 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2815}
2816
2817static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2818 enum port port)
2819{
2820 u8 ddc_pin;
2821
2822 switch (port) {
2823 case PORT_B:
2824 ddc_pin = GMBUS_PIN_DPB;
2825 break;
2826 case PORT_C:
2827 ddc_pin = GMBUS_PIN_DPC;
2828 break;
2829 case PORT_D:
2830 ddc_pin = GMBUS_PIN_DPD;
2831 break;
2832 default:
2833 MISSING_CASE(port);
2834 ddc_pin = GMBUS_PIN_DPB;
2835 break;
2836 }
2837 return ddc_pin;
2838}
2839
2840static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2841{
2842 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2843 enum port port = encoder->port;
2844 u8 ddc_pin;
2845
2846 ddc_pin = intel_bios_alternate_ddc_pin(encoder);
2847 if (ddc_pin) {
2848 drm_dbg_kms(&dev_priv->drm,
2849 "Using DDC pin 0x%x for port %c (VBT)\n",
2850 ddc_pin, port_name(port));
2851 return ddc_pin;
2852 }
2853
2854 if (IS_ALDERLAKE_S(dev_priv))
2855 ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2856 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2857 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2858 else if (IS_ROCKETLAKE(dev_priv))
2859 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2860 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2861 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2862 else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
2863 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2864 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2865 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2866 else if (HAS_PCH_CNP(dev_priv))
2867 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2868 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2869 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2870 else if (IS_CHERRYVIEW(dev_priv))
2871 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2872 else
2873 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2874
2875 drm_dbg_kms(&dev_priv->drm,
2876 "Using DDC pin 0x%x for port %c (platform default)\n",
2877 ddc_pin, port_name(port));
2878
2879 return ddc_pin;
2880}
2881
2882void intel_infoframe_init(struct intel_digital_port *dig_port)
2883{
2884 struct drm_i915_private *dev_priv =
2885 to_i915(dig_port->base.base.dev);
2886
2887 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2888 dig_port->write_infoframe = vlv_write_infoframe;
2889 dig_port->read_infoframe = vlv_read_infoframe;
2890 dig_port->set_infoframes = vlv_set_infoframes;
2891 dig_port->infoframes_enabled = vlv_infoframes_enabled;
2892 } else if (IS_G4X(dev_priv)) {
2893 dig_port->write_infoframe = g4x_write_infoframe;
2894 dig_port->read_infoframe = g4x_read_infoframe;
2895 dig_port->set_infoframes = g4x_set_infoframes;
2896 dig_port->infoframes_enabled = g4x_infoframes_enabled;
2897 } else if (HAS_DDI(dev_priv)) {
2898 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
2899 dig_port->write_infoframe = lspcon_write_infoframe;
2900 dig_port->read_infoframe = lspcon_read_infoframe;
2901 dig_port->set_infoframes = lspcon_set_infoframes;
2902 dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2903 } else {
2904 dig_port->write_infoframe = hsw_write_infoframe;
2905 dig_port->read_infoframe = hsw_read_infoframe;
2906 dig_port->set_infoframes = hsw_set_infoframes;
2907 dig_port->infoframes_enabled = hsw_infoframes_enabled;
2908 }
2909 } else if (HAS_PCH_IBX(dev_priv)) {
2910 dig_port->write_infoframe = ibx_write_infoframe;
2911 dig_port->read_infoframe = ibx_read_infoframe;
2912 dig_port->set_infoframes = ibx_set_infoframes;
2913 dig_port->infoframes_enabled = ibx_infoframes_enabled;
2914 } else {
2915 dig_port->write_infoframe = cpt_write_infoframe;
2916 dig_port->read_infoframe = cpt_read_infoframe;
2917 dig_port->set_infoframes = cpt_set_infoframes;
2918 dig_port->infoframes_enabled = cpt_infoframes_enabled;
2919 }
2920}
2921
2922void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2923 struct intel_connector *intel_connector)
2924{
2925 struct drm_connector *connector = &intel_connector->base;
2926 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2927 struct intel_encoder *intel_encoder = &dig_port->base;
2928 struct drm_device *dev = intel_encoder->base.dev;
2929 struct drm_i915_private *dev_priv = to_i915(dev);
2930 struct i2c_adapter *ddc;
2931 enum port port = intel_encoder->port;
2932 struct cec_connector_info conn_info;
2933
2934 drm_dbg_kms(&dev_priv->drm,
2935 "Adding HDMI connector on [ENCODER:%d:%s]\n",
2936 intel_encoder->base.base.id, intel_encoder->base.name);
2937
2938 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2939 return;
2940
2941 if (drm_WARN(dev, dig_port->max_lanes < 4,
2942 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2943 dig_port->max_lanes, intel_encoder->base.base.id,
2944 intel_encoder->base.name))
2945 return;
2946
2947 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
2948 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2949
2950 drm_connector_init_with_ddc(dev, connector,
2951 &intel_hdmi_connector_funcs,
2952 DRM_MODE_CONNECTOR_HDMIA,
2953 ddc);
2954 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2955
2956 connector->interlace_allowed = true;
2957 connector->stereo_allowed = true;
2958
2959 if (DISPLAY_VER(dev_priv) >= 10)
2960 connector->ycbcr_420_allowed = true;
2961
2962 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2963
2964 if (HAS_DDI(dev_priv))
2965 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2966 else
2967 intel_connector->get_hw_state = intel_connector_get_hw_state;
2968
2969 intel_hdmi_add_properties(intel_hdmi, connector);
2970
2971 intel_connector_attach_encoder(intel_connector, intel_encoder);
2972 intel_hdmi->attached_connector = intel_connector;
2973
2974 if (is_hdcp_supported(dev_priv, port)) {
2975 int ret = intel_hdcp_init(intel_connector, dig_port,
2976 &intel_hdmi_hdcp_shim);
2977 if (ret)
2978 drm_dbg_kms(&dev_priv->drm,
2979 "HDCP init failed, skipping.\n");
2980 }
2981
2982 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2983 * 0xd. Failure to do so will result in spurious interrupts being
2984 * generated on the port when a cable is not attached.
2985 */
2986 if (IS_G45(dev_priv)) {
2987 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
2988 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
2989 (temp & ~0xf) | 0xd);
2990 }
2991
2992 cec_fill_conn_info_from_drm(&conn_info, connector);
2993
2994 intel_hdmi->cec_notifier =
2995 cec_notifier_conn_register(dev->dev, port_identifier(port),
2996 &conn_info);
2997 if (!intel_hdmi->cec_notifier)
2998 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
2999}
3000
3001/*
3002 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3003 * @vactive: Vactive of a display mode
3004 *
3005 * @return: appropriate dsc slice height for a given mode.
3006 */
3007int intel_hdmi_dsc_get_slice_height(int vactive)
3008{
3009 int slice_height;
3010
3011 /*
3012 * Slice Height determination : HDMI2.1 Section 7.7.5.2
3013 * Select smallest slice height >=96, that results in a valid PPS and
3014 * requires minimum padding lines required for final slice.
3015 *
3016 * Assumption : Vactive is even.
3017 */
3018 for (slice_height = 96; slice_height <= vactive; slice_height += 2)
3019 if (vactive % slice_height == 0)
3020 return slice_height;
3021
3022 return 0;
3023}
3024
3025/*
3026 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3027 * and dsc decoder capabilities
3028 *
3029 * @crtc_state: intel crtc_state
3030 * @src_max_slices: maximum slices supported by the DSC encoder
3031 * @src_max_slice_width: maximum slice width supported by DSC encoder
3032 * @hdmi_max_slices: maximum slices supported by sink DSC decoder
3033 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3034 *
3035 * @return: num of dsc slices that can be supported by the dsc encoder
3036 * and decoder.
3037 */
3038int
3039intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
3040 int src_max_slices, int src_max_slice_width,
3041 int hdmi_max_slices, int hdmi_throughput)
3042{
3043/* Pixel rates in KPixels/sec */
3044#define HDMI_DSC_PEAK_PIXEL_RATE 2720000
3045/*
3046 * Rates at which the source and sink are required to process pixels in each
3047 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
3048 */
3049#define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000
3050#define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000
3051
3052/* Spec limits the slice width to 2720 pixels */
3053#define MAX_HDMI_SLICE_WIDTH 2720
3054 int kslice_adjust;
3055 int adjusted_clk_khz;
3056 int min_slices;
3057 int target_slices;
3058 int max_throughput; /* max clock freq. in khz per slice */
3059 int max_slice_width;
3060 int slice_width;
3061 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3062
3063 if (!hdmi_throughput)
3064 return 0;
3065
3066 /*
3067 * Slice Width determination : HDMI2.1 Section 7.7.5.1
3068 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
3069 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
3070 * dividing adjusted clock value by 10.
3071 */
3072 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3073 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3074 kslice_adjust = 10;
3075 else
3076 kslice_adjust = 5;
3077
3078 /*
3079 * As per spec, the rate at which the source and the sink process
3080 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
3081 * This depends upon the pixel clock rate and output formats
3082 * (kslice adjust).
3083 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
3084 * at max 340MHz, otherwise they can be processed at max 400MHz.
3085 */
3086
3087 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
3088
3089 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
3090 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3091 else
3092 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3093
3094 /*
3095 * Taking into account the sink's capability for maximum
3096 * clock per slice (in MHz) as read from HF-VSDB.
3097 */
3098 max_throughput = min(max_throughput, hdmi_throughput * 1000);
3099
3100 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3101 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3102
3103 /*
3104 * Keep on increasing the num of slices/line, starting from min_slices
3105 * per line till we get such a number, for which the slice_width is
3106 * just less than max_slice_width. The slices/line selected should be
3107 * less than or equal to the max horizontal slices that the combination
3108 * of PCON encoder and HDMI decoder can support.
3109 */
3110 slice_width = max_slice_width;
3111
3112 do {
3113 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3114 target_slices = 1;
3115 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3116 target_slices = 2;
3117 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3118 target_slices = 4;
3119 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3120 target_slices = 8;
3121 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3122 target_slices = 12;
3123 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3124 target_slices = 16;
3125 else
3126 return 0;
3127
3128 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3129 if (slice_width >= max_slice_width)
3130 min_slices = target_slices + 1;
3131 } while (slice_width >= max_slice_width);
3132
3133 return target_slices;
3134}
3135
3136/*
3137 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3138 * source and sink capabilities.
3139 *
3140 * @src_fraction_bpp: fractional bpp supported by the source
3141 * @slice_width: dsc slice width supported by the source and sink
3142 * @num_slices: num of slices supported by the source and sink
3143 * @output_format: video output format
3144 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3145 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3146 *
3147 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3148 */
3149int
3150intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3151 int output_format, bool hdmi_all_bpp,
3152 int hdmi_max_chunk_bytes)
3153{
3154 int max_dsc_bpp, min_dsc_bpp;
3155 int target_bytes;
3156 bool bpp_found = false;
3157 int bpp_decrement_x16;
3158 int bpp_target;
3159 int bpp_target_x16;
3160
3161 /*
3162 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3163 * Start with the max bpp and keep on decrementing with
3164 * fractional bpp, if supported by PCON DSC encoder
3165 *
3166 * for each bpp we check if no of bytes can be supported by HDMI sink
3167 */
3168
3169 /* Assuming: bpc as 8*/
3170 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3171 min_dsc_bpp = 6;
3172 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3173 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3174 output_format == INTEL_OUTPUT_FORMAT_RGB) {
3175 min_dsc_bpp = 8;
3176 max_dsc_bpp = 3 * 8; /* 3*bpc */
3177 } else {
3178 /* Assuming 4:2:2 encoding */
3179 min_dsc_bpp = 7;
3180 max_dsc_bpp = 2 * 8; /* 2*bpc */
3181 }
3182
3183 /*
3184 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3185 * Section 7.7.34 : Source shall not enable compressed Video
3186 * Transport with bpp_target settings above 12 bpp unless
3187 * DSC_all_bpp is set to 1.
3188 */
3189 if (!hdmi_all_bpp)
3190 max_dsc_bpp = min(max_dsc_bpp, 12);
3191
3192 /*
3193 * The Sink has a limit of compressed data in bytes for a scanline,
3194 * as described in max_chunk_bytes field in HFVSDB block of edid.
3195 * The no. of bytes depend on the target bits per pixel that the
3196 * source configures. So we start with the max_bpp and calculate
3197 * the target_chunk_bytes. We keep on decrementing the target_bpp,
3198 * till we get the target_chunk_bytes just less than what the sink's
3199 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3200 *
3201 * The decrement is according to the fractional support from PCON DSC
3202 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3203 *
3204 * bpp_target_x16 = bpp_target * 16
3205 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3206 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3207 */
3208
3209 bpp_target = max_dsc_bpp;
3210
3211 /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3212 if (!src_fractional_bpp)
3213 src_fractional_bpp = 1;
3214 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3215 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3216
3217 while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3218 int bpp;
3219
3220 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3221 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3222 if (target_bytes <= hdmi_max_chunk_bytes) {
3223 bpp_found = true;
3224 break;
3225 }
3226 bpp_target_x16 -= bpp_decrement_x16;
3227 }
3228 if (bpp_found)
3229 return bpp_target_x16;
3230
3231 return 0;
3232}