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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#include <linux/string_helpers.h>
7
8#include "i915_drv.h"
9#include "i915_irq.h"
10#include "i915_reg.h"
11#include "intel_backlight_regs.h"
12#include "intel_cdclk.h"
13#include "intel_clock_gating.h"
14#include "intel_combo_phy.h"
15#include "intel_de.h"
16#include "intel_display_power.h"
17#include "intel_display_power_map.h"
18#include "intel_display_power_well.h"
19#include "intel_display_types.h"
20#include "intel_dmc.h"
21#include "intel_mchbar_regs.h"
22#include "intel_pch_refclk.h"
23#include "intel_pcode.h"
24#include "intel_pmdemand.h"
25#include "intel_pps_regs.h"
26#include "intel_snps_phy.h"
27#include "skl_watermark.h"
28#include "skl_watermark_regs.h"
29#include "vlv_sideband.h"
30
31#define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
32 for_each_power_well(__dev_priv, __power_well) \
33 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
34
35#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \
36 for_each_power_well_reverse(__dev_priv, __power_well) \
37 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
38
39static const char *
40intel_display_power_domain_str(enum intel_display_power_domain domain)
41{
42 switch (domain) {
43 case POWER_DOMAIN_DISPLAY_CORE:
44 return "DISPLAY_CORE";
45 case POWER_DOMAIN_PIPE_A:
46 return "PIPE_A";
47 case POWER_DOMAIN_PIPE_B:
48 return "PIPE_B";
49 case POWER_DOMAIN_PIPE_C:
50 return "PIPE_C";
51 case POWER_DOMAIN_PIPE_D:
52 return "PIPE_D";
53 case POWER_DOMAIN_PIPE_PANEL_FITTER_A:
54 return "PIPE_PANEL_FITTER_A";
55 case POWER_DOMAIN_PIPE_PANEL_FITTER_B:
56 return "PIPE_PANEL_FITTER_B";
57 case POWER_DOMAIN_PIPE_PANEL_FITTER_C:
58 return "PIPE_PANEL_FITTER_C";
59 case POWER_DOMAIN_PIPE_PANEL_FITTER_D:
60 return "PIPE_PANEL_FITTER_D";
61 case POWER_DOMAIN_TRANSCODER_A:
62 return "TRANSCODER_A";
63 case POWER_DOMAIN_TRANSCODER_B:
64 return "TRANSCODER_B";
65 case POWER_DOMAIN_TRANSCODER_C:
66 return "TRANSCODER_C";
67 case POWER_DOMAIN_TRANSCODER_D:
68 return "TRANSCODER_D";
69 case POWER_DOMAIN_TRANSCODER_EDP:
70 return "TRANSCODER_EDP";
71 case POWER_DOMAIN_TRANSCODER_DSI_A:
72 return "TRANSCODER_DSI_A";
73 case POWER_DOMAIN_TRANSCODER_DSI_C:
74 return "TRANSCODER_DSI_C";
75 case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
76 return "TRANSCODER_VDSC_PW2";
77 case POWER_DOMAIN_PORT_DDI_LANES_A:
78 return "PORT_DDI_LANES_A";
79 case POWER_DOMAIN_PORT_DDI_LANES_B:
80 return "PORT_DDI_LANES_B";
81 case POWER_DOMAIN_PORT_DDI_LANES_C:
82 return "PORT_DDI_LANES_C";
83 case POWER_DOMAIN_PORT_DDI_LANES_D:
84 return "PORT_DDI_LANES_D";
85 case POWER_DOMAIN_PORT_DDI_LANES_E:
86 return "PORT_DDI_LANES_E";
87 case POWER_DOMAIN_PORT_DDI_LANES_F:
88 return "PORT_DDI_LANES_F";
89 case POWER_DOMAIN_PORT_DDI_LANES_TC1:
90 return "PORT_DDI_LANES_TC1";
91 case POWER_DOMAIN_PORT_DDI_LANES_TC2:
92 return "PORT_DDI_LANES_TC2";
93 case POWER_DOMAIN_PORT_DDI_LANES_TC3:
94 return "PORT_DDI_LANES_TC3";
95 case POWER_DOMAIN_PORT_DDI_LANES_TC4:
96 return "PORT_DDI_LANES_TC4";
97 case POWER_DOMAIN_PORT_DDI_LANES_TC5:
98 return "PORT_DDI_LANES_TC5";
99 case POWER_DOMAIN_PORT_DDI_LANES_TC6:
100 return "PORT_DDI_LANES_TC6";
101 case POWER_DOMAIN_PORT_DDI_IO_A:
102 return "PORT_DDI_IO_A";
103 case POWER_DOMAIN_PORT_DDI_IO_B:
104 return "PORT_DDI_IO_B";
105 case POWER_DOMAIN_PORT_DDI_IO_C:
106 return "PORT_DDI_IO_C";
107 case POWER_DOMAIN_PORT_DDI_IO_D:
108 return "PORT_DDI_IO_D";
109 case POWER_DOMAIN_PORT_DDI_IO_E:
110 return "PORT_DDI_IO_E";
111 case POWER_DOMAIN_PORT_DDI_IO_F:
112 return "PORT_DDI_IO_F";
113 case POWER_DOMAIN_PORT_DDI_IO_TC1:
114 return "PORT_DDI_IO_TC1";
115 case POWER_DOMAIN_PORT_DDI_IO_TC2:
116 return "PORT_DDI_IO_TC2";
117 case POWER_DOMAIN_PORT_DDI_IO_TC3:
118 return "PORT_DDI_IO_TC3";
119 case POWER_DOMAIN_PORT_DDI_IO_TC4:
120 return "PORT_DDI_IO_TC4";
121 case POWER_DOMAIN_PORT_DDI_IO_TC5:
122 return "PORT_DDI_IO_TC5";
123 case POWER_DOMAIN_PORT_DDI_IO_TC6:
124 return "PORT_DDI_IO_TC6";
125 case POWER_DOMAIN_PORT_DSI:
126 return "PORT_DSI";
127 case POWER_DOMAIN_PORT_CRT:
128 return "PORT_CRT";
129 case POWER_DOMAIN_PORT_OTHER:
130 return "PORT_OTHER";
131 case POWER_DOMAIN_VGA:
132 return "VGA";
133 case POWER_DOMAIN_AUDIO_MMIO:
134 return "AUDIO_MMIO";
135 case POWER_DOMAIN_AUDIO_PLAYBACK:
136 return "AUDIO_PLAYBACK";
137 case POWER_DOMAIN_AUX_IO_A:
138 return "AUX_IO_A";
139 case POWER_DOMAIN_AUX_IO_B:
140 return "AUX_IO_B";
141 case POWER_DOMAIN_AUX_IO_C:
142 return "AUX_IO_C";
143 case POWER_DOMAIN_AUX_IO_D:
144 return "AUX_IO_D";
145 case POWER_DOMAIN_AUX_IO_E:
146 return "AUX_IO_E";
147 case POWER_DOMAIN_AUX_IO_F:
148 return "AUX_IO_F";
149 case POWER_DOMAIN_AUX_A:
150 return "AUX_A";
151 case POWER_DOMAIN_AUX_B:
152 return "AUX_B";
153 case POWER_DOMAIN_AUX_C:
154 return "AUX_C";
155 case POWER_DOMAIN_AUX_D:
156 return "AUX_D";
157 case POWER_DOMAIN_AUX_E:
158 return "AUX_E";
159 case POWER_DOMAIN_AUX_F:
160 return "AUX_F";
161 case POWER_DOMAIN_AUX_USBC1:
162 return "AUX_USBC1";
163 case POWER_DOMAIN_AUX_USBC2:
164 return "AUX_USBC2";
165 case POWER_DOMAIN_AUX_USBC3:
166 return "AUX_USBC3";
167 case POWER_DOMAIN_AUX_USBC4:
168 return "AUX_USBC4";
169 case POWER_DOMAIN_AUX_USBC5:
170 return "AUX_USBC5";
171 case POWER_DOMAIN_AUX_USBC6:
172 return "AUX_USBC6";
173 case POWER_DOMAIN_AUX_TBT1:
174 return "AUX_TBT1";
175 case POWER_DOMAIN_AUX_TBT2:
176 return "AUX_TBT2";
177 case POWER_DOMAIN_AUX_TBT3:
178 return "AUX_TBT3";
179 case POWER_DOMAIN_AUX_TBT4:
180 return "AUX_TBT4";
181 case POWER_DOMAIN_AUX_TBT5:
182 return "AUX_TBT5";
183 case POWER_DOMAIN_AUX_TBT6:
184 return "AUX_TBT6";
185 case POWER_DOMAIN_GMBUS:
186 return "GMBUS";
187 case POWER_DOMAIN_INIT:
188 return "INIT";
189 case POWER_DOMAIN_GT_IRQ:
190 return "GT_IRQ";
191 case POWER_DOMAIN_DC_OFF:
192 return "DC_OFF";
193 case POWER_DOMAIN_TC_COLD_OFF:
194 return "TC_COLD_OFF";
195 default:
196 MISSING_CASE(domain);
197 return "?";
198 }
199}
200
201static bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
202 enum intel_display_power_domain domain)
203{
204 struct i915_power_well *power_well;
205 bool is_enabled;
206
207 if (pm_runtime_suspended(dev_priv->drm.dev))
208 return false;
209
210 is_enabled = true;
211
212 for_each_power_domain_well_reverse(dev_priv, power_well, domain) {
213 if (intel_power_well_is_always_on(power_well))
214 continue;
215
216 if (!intel_power_well_is_enabled_cached(power_well)) {
217 is_enabled = false;
218 break;
219 }
220 }
221
222 return is_enabled;
223}
224
225/**
226 * intel_display_power_is_enabled - check for a power domain
227 * @dev_priv: i915 device instance
228 * @domain: power domain to check
229 *
230 * This function can be used to check the hw power domain state. It is mostly
231 * used in hardware state readout functions. Everywhere else code should rely
232 * upon explicit power domain reference counting to ensure that the hardware
233 * block is powered up before accessing it.
234 *
235 * Callers must hold the relevant modesetting locks to ensure that concurrent
236 * threads can't disable the power well while the caller tries to read a few
237 * registers.
238 *
239 * Returns:
240 * True when the power domain is enabled, false otherwise.
241 */
242bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
243 enum intel_display_power_domain domain)
244{
245 struct i915_power_domains *power_domains;
246 bool ret;
247
248 power_domains = &dev_priv->display.power.domains;
249
250 mutex_lock(&power_domains->lock);
251 ret = __intel_display_power_is_enabled(dev_priv, domain);
252 mutex_unlock(&power_domains->lock);
253
254 return ret;
255}
256
257static u32
258sanitize_target_dc_state(struct drm_i915_private *i915,
259 u32 target_dc_state)
260{
261 struct i915_power_domains *power_domains = &i915->display.power.domains;
262 static const u32 states[] = {
263 DC_STATE_EN_UPTO_DC6,
264 DC_STATE_EN_UPTO_DC5,
265 DC_STATE_EN_DC3CO,
266 DC_STATE_DISABLE,
267 };
268 int i;
269
270 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
271 if (target_dc_state != states[i])
272 continue;
273
274 if (power_domains->allowed_dc_mask & target_dc_state)
275 break;
276
277 target_dc_state = states[i + 1];
278 }
279
280 return target_dc_state;
281}
282
283/**
284 * intel_display_power_set_target_dc_state - Set target dc state.
285 * @dev_priv: i915 device
286 * @state: state which needs to be set as target_dc_state.
287 *
288 * This function set the "DC off" power well target_dc_state,
289 * based upon this target_dc_stste, "DC off" power well will
290 * enable desired DC state.
291 */
292void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
293 u32 state)
294{
295 struct i915_power_well *power_well;
296 bool dc_off_enabled;
297 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
298
299 mutex_lock(&power_domains->lock);
300 power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF);
301
302 if (drm_WARN_ON(&dev_priv->drm, !power_well))
303 goto unlock;
304
305 state = sanitize_target_dc_state(dev_priv, state);
306
307 if (state == power_domains->target_dc_state)
308 goto unlock;
309
310 dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well);
311 /*
312 * If DC off power well is disabled, need to enable and disable the
313 * DC off power well to effect target DC state.
314 */
315 if (!dc_off_enabled)
316 intel_power_well_enable(dev_priv, power_well);
317
318 power_domains->target_dc_state = state;
319
320 if (!dc_off_enabled)
321 intel_power_well_disable(dev_priv, power_well);
322
323unlock:
324 mutex_unlock(&power_domains->lock);
325}
326
327static void __async_put_domains_mask(struct i915_power_domains *power_domains,
328 struct intel_power_domain_mask *mask)
329{
330 bitmap_or(mask->bits,
331 power_domains->async_put_domains[0].bits,
332 power_domains->async_put_domains[1].bits,
333 POWER_DOMAIN_NUM);
334}
335
336#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
337
338static bool
339assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
340{
341 struct drm_i915_private *i915 = container_of(power_domains,
342 struct drm_i915_private,
343 display.power.domains);
344
345 return !drm_WARN_ON(&i915->drm,
346 bitmap_intersects(power_domains->async_put_domains[0].bits,
347 power_domains->async_put_domains[1].bits,
348 POWER_DOMAIN_NUM));
349}
350
351static bool
352__async_put_domains_state_ok(struct i915_power_domains *power_domains)
353{
354 struct drm_i915_private *i915 = container_of(power_domains,
355 struct drm_i915_private,
356 display.power.domains);
357 struct intel_power_domain_mask async_put_mask;
358 enum intel_display_power_domain domain;
359 bool err = false;
360
361 err |= !assert_async_put_domain_masks_disjoint(power_domains);
362 __async_put_domains_mask(power_domains, &async_put_mask);
363 err |= drm_WARN_ON(&i915->drm,
364 !!power_domains->async_put_wakeref !=
365 !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM));
366
367 for_each_power_domain(domain, &async_put_mask)
368 err |= drm_WARN_ON(&i915->drm,
369 power_domains->domain_use_count[domain] != 1);
370
371 return !err;
372}
373
374static void print_power_domains(struct i915_power_domains *power_domains,
375 const char *prefix, struct intel_power_domain_mask *mask)
376{
377 struct drm_i915_private *i915 = container_of(power_domains,
378 struct drm_i915_private,
379 display.power.domains);
380 enum intel_display_power_domain domain;
381
382 drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
383 for_each_power_domain(domain, mask)
384 drm_dbg(&i915->drm, "%s use_count %d\n",
385 intel_display_power_domain_str(domain),
386 power_domains->domain_use_count[domain]);
387}
388
389static void
390print_async_put_domains_state(struct i915_power_domains *power_domains)
391{
392 struct drm_i915_private *i915 = container_of(power_domains,
393 struct drm_i915_private,
394 display.power.domains);
395
396 drm_dbg(&i915->drm, "async_put_wakeref: %s\n",
397 str_yes_no(power_domains->async_put_wakeref));
398
399 print_power_domains(power_domains, "async_put_domains[0]",
400 &power_domains->async_put_domains[0]);
401 print_power_domains(power_domains, "async_put_domains[1]",
402 &power_domains->async_put_domains[1]);
403}
404
405static void
406verify_async_put_domains_state(struct i915_power_domains *power_domains)
407{
408 if (!__async_put_domains_state_ok(power_domains))
409 print_async_put_domains_state(power_domains);
410}
411
412#else
413
414static void
415assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
416{
417}
418
419static void
420verify_async_put_domains_state(struct i915_power_domains *power_domains)
421{
422}
423
424#endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */
425
426static void async_put_domains_mask(struct i915_power_domains *power_domains,
427 struct intel_power_domain_mask *mask)
428
429{
430 assert_async_put_domain_masks_disjoint(power_domains);
431
432 __async_put_domains_mask(power_domains, mask);
433}
434
435static void
436async_put_domains_clear_domain(struct i915_power_domains *power_domains,
437 enum intel_display_power_domain domain)
438{
439 assert_async_put_domain_masks_disjoint(power_domains);
440
441 clear_bit(domain, power_domains->async_put_domains[0].bits);
442 clear_bit(domain, power_domains->async_put_domains[1].bits);
443}
444
445static void
446cancel_async_put_work(struct i915_power_domains *power_domains, bool sync)
447{
448 if (sync)
449 cancel_delayed_work_sync(&power_domains->async_put_work);
450 else
451 cancel_delayed_work(&power_domains->async_put_work);
452
453 power_domains->async_put_next_delay = 0;
454}
455
456static bool
457intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
458 enum intel_display_power_domain domain)
459{
460 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
461 struct intel_power_domain_mask async_put_mask;
462 bool ret = false;
463
464 async_put_domains_mask(power_domains, &async_put_mask);
465 if (!test_bit(domain, async_put_mask.bits))
466 goto out_verify;
467
468 async_put_domains_clear_domain(power_domains, domain);
469
470 ret = true;
471
472 async_put_domains_mask(power_domains, &async_put_mask);
473 if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM))
474 goto out_verify;
475
476 cancel_async_put_work(power_domains, false);
477 intel_runtime_pm_put_raw(&dev_priv->runtime_pm,
478 fetch_and_zero(&power_domains->async_put_wakeref));
479out_verify:
480 verify_async_put_domains_state(power_domains);
481
482 return ret;
483}
484
485static void
486__intel_display_power_get_domain(struct drm_i915_private *dev_priv,
487 enum intel_display_power_domain domain)
488{
489 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
490 struct i915_power_well *power_well;
491
492 if (intel_display_power_grab_async_put_ref(dev_priv, domain))
493 return;
494
495 for_each_power_domain_well(dev_priv, power_well, domain)
496 intel_power_well_get(dev_priv, power_well);
497
498 power_domains->domain_use_count[domain]++;
499}
500
501/**
502 * intel_display_power_get - grab a power domain reference
503 * @dev_priv: i915 device instance
504 * @domain: power domain to reference
505 *
506 * This function grabs a power domain reference for @domain and ensures that the
507 * power domain and all its parents are powered up. Therefore users should only
508 * grab a reference to the innermost power domain they need.
509 *
510 * Any power domain reference obtained by this function must have a symmetric
511 * call to intel_display_power_put() to release the reference again.
512 */
513intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
514 enum intel_display_power_domain domain)
515{
516 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
517 intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
518
519 mutex_lock(&power_domains->lock);
520 __intel_display_power_get_domain(dev_priv, domain);
521 mutex_unlock(&power_domains->lock);
522
523 return wakeref;
524}
525
526/**
527 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
528 * @dev_priv: i915 device instance
529 * @domain: power domain to reference
530 *
531 * This function grabs a power domain reference for @domain and ensures that the
532 * power domain and all its parents are powered up. Therefore users should only
533 * grab a reference to the innermost power domain they need.
534 *
535 * Any power domain reference obtained by this function must have a symmetric
536 * call to intel_display_power_put() to release the reference again.
537 */
538intel_wakeref_t
539intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
540 enum intel_display_power_domain domain)
541{
542 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
543 intel_wakeref_t wakeref;
544 bool is_enabled;
545
546 wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm);
547 if (!wakeref)
548 return NULL;
549
550 mutex_lock(&power_domains->lock);
551
552 if (__intel_display_power_is_enabled(dev_priv, domain)) {
553 __intel_display_power_get_domain(dev_priv, domain);
554 is_enabled = true;
555 } else {
556 is_enabled = false;
557 }
558
559 mutex_unlock(&power_domains->lock);
560
561 if (!is_enabled) {
562 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
563 wakeref = NULL;
564 }
565
566 return wakeref;
567}
568
569static void
570__intel_display_power_put_domain(struct drm_i915_private *dev_priv,
571 enum intel_display_power_domain domain)
572{
573 struct i915_power_domains *power_domains;
574 struct i915_power_well *power_well;
575 const char *name = intel_display_power_domain_str(domain);
576 struct intel_power_domain_mask async_put_mask;
577
578 power_domains = &dev_priv->display.power.domains;
579
580 drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain],
581 "Use count on domain %s is already zero\n",
582 name);
583 async_put_domains_mask(power_domains, &async_put_mask);
584 drm_WARN(&dev_priv->drm,
585 test_bit(domain, async_put_mask.bits),
586 "Async disabling of domain %s is pending\n",
587 name);
588
589 power_domains->domain_use_count[domain]--;
590
591 for_each_power_domain_well_reverse(dev_priv, power_well, domain)
592 intel_power_well_put(dev_priv, power_well);
593}
594
595static void __intel_display_power_put(struct drm_i915_private *dev_priv,
596 enum intel_display_power_domain domain)
597{
598 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
599
600 mutex_lock(&power_domains->lock);
601 __intel_display_power_put_domain(dev_priv, domain);
602 mutex_unlock(&power_domains->lock);
603}
604
605static void
606queue_async_put_domains_work(struct i915_power_domains *power_domains,
607 intel_wakeref_t wakeref,
608 int delay_ms)
609{
610 struct drm_i915_private *i915 = container_of(power_domains,
611 struct drm_i915_private,
612 display.power.domains);
613 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
614 power_domains->async_put_wakeref = wakeref;
615 drm_WARN_ON(&i915->drm, !queue_delayed_work(system_unbound_wq,
616 &power_domains->async_put_work,
617 msecs_to_jiffies(delay_ms)));
618}
619
620static void
621release_async_put_domains(struct i915_power_domains *power_domains,
622 struct intel_power_domain_mask *mask)
623{
624 struct drm_i915_private *dev_priv =
625 container_of(power_domains, struct drm_i915_private,
626 display.power.domains);
627 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
628 enum intel_display_power_domain domain;
629 intel_wakeref_t wakeref;
630
631 wakeref = intel_runtime_pm_get_noresume(rpm);
632
633 for_each_power_domain(domain, mask) {
634 /* Clear before put, so put's sanity check is happy. */
635 async_put_domains_clear_domain(power_domains, domain);
636 __intel_display_power_put_domain(dev_priv, domain);
637 }
638
639 intel_runtime_pm_put(rpm, wakeref);
640}
641
642static void
643intel_display_power_put_async_work(struct work_struct *work)
644{
645 struct drm_i915_private *dev_priv =
646 container_of(work, struct drm_i915_private,
647 display.power.domains.async_put_work.work);
648 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
649 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
650 intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(rpm);
651 intel_wakeref_t old_work_wakeref = NULL;
652
653 mutex_lock(&power_domains->lock);
654
655 /*
656 * Bail out if all the domain refs pending to be released were grabbed
657 * by subsequent gets or a flush_work.
658 */
659 old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref);
660 if (!old_work_wakeref)
661 goto out_verify;
662
663 release_async_put_domains(power_domains,
664 &power_domains->async_put_domains[0]);
665
666 /*
667 * Cancel the work that got queued after this one got dequeued,
668 * since here we released the corresponding async-put reference.
669 */
670 cancel_async_put_work(power_domains, false);
671
672 /* Requeue the work if more domains were async put meanwhile. */
673 if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) {
674 bitmap_copy(power_domains->async_put_domains[0].bits,
675 power_domains->async_put_domains[1].bits,
676 POWER_DOMAIN_NUM);
677 bitmap_zero(power_domains->async_put_domains[1].bits,
678 POWER_DOMAIN_NUM);
679 queue_async_put_domains_work(power_domains,
680 fetch_and_zero(&new_work_wakeref),
681 power_domains->async_put_next_delay);
682 power_domains->async_put_next_delay = 0;
683 }
684
685out_verify:
686 verify_async_put_domains_state(power_domains);
687
688 mutex_unlock(&power_domains->lock);
689
690 if (old_work_wakeref)
691 intel_runtime_pm_put_raw(rpm, old_work_wakeref);
692 if (new_work_wakeref)
693 intel_runtime_pm_put_raw(rpm, new_work_wakeref);
694}
695
696/**
697 * __intel_display_power_put_async - release a power domain reference asynchronously
698 * @i915: i915 device instance
699 * @domain: power domain to reference
700 * @wakeref: wakeref acquired for the reference that is being released
701 * @delay_ms: delay of powering down the power domain
702 *
703 * This function drops the power domain reference obtained by
704 * intel_display_power_get*() and schedules a work to power down the
705 * corresponding hardware block if this is the last reference.
706 * The power down is delayed by @delay_ms if this is >= 0, or by a default
707 * 100 ms otherwise.
708 */
709void __intel_display_power_put_async(struct drm_i915_private *i915,
710 enum intel_display_power_domain domain,
711 intel_wakeref_t wakeref,
712 int delay_ms)
713{
714 struct i915_power_domains *power_domains = &i915->display.power.domains;
715 struct intel_runtime_pm *rpm = &i915->runtime_pm;
716 intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm);
717
718 delay_ms = delay_ms >= 0 ? delay_ms : 100;
719
720 mutex_lock(&power_domains->lock);
721
722 if (power_domains->domain_use_count[domain] > 1) {
723 __intel_display_power_put_domain(i915, domain);
724
725 goto out_verify;
726 }
727
728 drm_WARN_ON(&i915->drm, power_domains->domain_use_count[domain] != 1);
729
730 /* Let a pending work requeue itself or queue a new one. */
731 if (power_domains->async_put_wakeref) {
732 set_bit(domain, power_domains->async_put_domains[1].bits);
733 power_domains->async_put_next_delay = max(power_domains->async_put_next_delay,
734 delay_ms);
735 } else {
736 set_bit(domain, power_domains->async_put_domains[0].bits);
737 queue_async_put_domains_work(power_domains,
738 fetch_and_zero(&work_wakeref),
739 delay_ms);
740 }
741
742out_verify:
743 verify_async_put_domains_state(power_domains);
744
745 mutex_unlock(&power_domains->lock);
746
747 if (work_wakeref)
748 intel_runtime_pm_put_raw(rpm, work_wakeref);
749
750 intel_runtime_pm_put(rpm, wakeref);
751}
752
753/**
754 * intel_display_power_flush_work - flushes the async display power disabling work
755 * @i915: i915 device instance
756 *
757 * Flushes any pending work that was scheduled by a preceding
758 * intel_display_power_put_async() call, completing the disabling of the
759 * corresponding power domains.
760 *
761 * Note that the work handler function may still be running after this
762 * function returns; to ensure that the work handler isn't running use
763 * intel_display_power_flush_work_sync() instead.
764 */
765void intel_display_power_flush_work(struct drm_i915_private *i915)
766{
767 struct i915_power_domains *power_domains = &i915->display.power.domains;
768 struct intel_power_domain_mask async_put_mask;
769 intel_wakeref_t work_wakeref;
770
771 mutex_lock(&power_domains->lock);
772
773 work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref);
774 if (!work_wakeref)
775 goto out_verify;
776
777 async_put_domains_mask(power_domains, &async_put_mask);
778 release_async_put_domains(power_domains, &async_put_mask);
779 cancel_async_put_work(power_domains, false);
780
781out_verify:
782 verify_async_put_domains_state(power_domains);
783
784 mutex_unlock(&power_domains->lock);
785
786 if (work_wakeref)
787 intel_runtime_pm_put_raw(&i915->runtime_pm, work_wakeref);
788}
789
790/**
791 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work
792 * @i915: i915 device instance
793 *
794 * Like intel_display_power_flush_work(), but also ensure that the work
795 * handler function is not running any more when this function returns.
796 */
797static void
798intel_display_power_flush_work_sync(struct drm_i915_private *i915)
799{
800 struct i915_power_domains *power_domains = &i915->display.power.domains;
801
802 intel_display_power_flush_work(i915);
803 cancel_async_put_work(power_domains, true);
804
805 verify_async_put_domains_state(power_domains);
806
807 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
808}
809
810#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
811/**
812 * intel_display_power_put - release a power domain reference
813 * @dev_priv: i915 device instance
814 * @domain: power domain to reference
815 * @wakeref: wakeref acquired for the reference that is being released
816 *
817 * This function drops the power domain reference obtained by
818 * intel_display_power_get() and might power down the corresponding hardware
819 * block right away if this is the last reference.
820 */
821void intel_display_power_put(struct drm_i915_private *dev_priv,
822 enum intel_display_power_domain domain,
823 intel_wakeref_t wakeref)
824{
825 __intel_display_power_put(dev_priv, domain);
826 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
827}
828#else
829/**
830 * intel_display_power_put_unchecked - release an unchecked power domain reference
831 * @dev_priv: i915 device instance
832 * @domain: power domain to reference
833 *
834 * This function drops the power domain reference obtained by
835 * intel_display_power_get() and might power down the corresponding hardware
836 * block right away if this is the last reference.
837 *
838 * This function is only for the power domain code's internal use to suppress wakeref
839 * tracking when the correspondig debug kconfig option is disabled, should not
840 * be used otherwise.
841 */
842void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
843 enum intel_display_power_domain domain)
844{
845 __intel_display_power_put(dev_priv, domain);
846 intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm);
847}
848#endif
849
850void
851intel_display_power_get_in_set(struct drm_i915_private *i915,
852 struct intel_display_power_domain_set *power_domain_set,
853 enum intel_display_power_domain domain)
854{
855 intel_wakeref_t __maybe_unused wf;
856
857 drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
858
859 wf = intel_display_power_get(i915, domain);
860#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
861 power_domain_set->wakerefs[domain] = wf;
862#endif
863 set_bit(domain, power_domain_set->mask.bits);
864}
865
866bool
867intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
868 struct intel_display_power_domain_set *power_domain_set,
869 enum intel_display_power_domain domain)
870{
871 intel_wakeref_t wf;
872
873 drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
874
875 wf = intel_display_power_get_if_enabled(i915, domain);
876 if (!wf)
877 return false;
878
879#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
880 power_domain_set->wakerefs[domain] = wf;
881#endif
882 set_bit(domain, power_domain_set->mask.bits);
883
884 return true;
885}
886
887void
888intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
889 struct intel_display_power_domain_set *power_domain_set,
890 struct intel_power_domain_mask *mask)
891{
892 enum intel_display_power_domain domain;
893
894 drm_WARN_ON(&i915->drm,
895 !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
896
897 for_each_power_domain(domain, mask) {
898 intel_wakeref_t __maybe_unused wf = INTEL_WAKEREF_DEF;
899
900#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
901 wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
902#endif
903 intel_display_power_put(i915, domain, wf);
904 clear_bit(domain, power_domain_set->mask.bits);
905 }
906}
907
908static int
909sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
910 int disable_power_well)
911{
912 if (disable_power_well >= 0)
913 return !!disable_power_well;
914
915 return 1;
916}
917
918static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
919 int enable_dc)
920{
921 u32 mask;
922 int requested_dc;
923 int max_dc;
924
925 if (!HAS_DISPLAY(dev_priv))
926 return 0;
927
928 if (DISPLAY_VER(dev_priv) >= 20)
929 max_dc = 2;
930 else if (IS_DG2(dev_priv))
931 max_dc = 1;
932 else if (IS_DG1(dev_priv))
933 max_dc = 3;
934 else if (DISPLAY_VER(dev_priv) >= 12)
935 max_dc = 4;
936 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
937 max_dc = 1;
938 else if (DISPLAY_VER(dev_priv) >= 9)
939 max_dc = 2;
940 else
941 max_dc = 0;
942
943 /*
944 * DC9 has a separate HW flow from the rest of the DC states,
945 * not depending on the DMC firmware. It's needed by system
946 * suspend/resume, so allow it unconditionally.
947 */
948 mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
949 DISPLAY_VER(dev_priv) >= 11 ?
950 DC_STATE_EN_DC9 : 0;
951
952 if (!dev_priv->display.params.disable_power_well)
953 max_dc = 0;
954
955 if (enable_dc >= 0 && enable_dc <= max_dc) {
956 requested_dc = enable_dc;
957 } else if (enable_dc == -1) {
958 requested_dc = max_dc;
959 } else if (enable_dc > max_dc && enable_dc <= 4) {
960 drm_dbg_kms(&dev_priv->drm,
961 "Adjusting requested max DC state (%d->%d)\n",
962 enable_dc, max_dc);
963 requested_dc = max_dc;
964 } else {
965 drm_err(&dev_priv->drm,
966 "Unexpected value for enable_dc (%d)\n", enable_dc);
967 requested_dc = max_dc;
968 }
969
970 switch (requested_dc) {
971 case 4:
972 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
973 break;
974 case 3:
975 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
976 break;
977 case 2:
978 mask |= DC_STATE_EN_UPTO_DC6;
979 break;
980 case 1:
981 mask |= DC_STATE_EN_UPTO_DC5;
982 break;
983 }
984
985 drm_dbg_kms(&dev_priv->drm, "Allowed DC state mask %02x\n", mask);
986
987 return mask;
988}
989
990/**
991 * intel_power_domains_init - initializes the power domain structures
992 * @dev_priv: i915 device instance
993 *
994 * Initializes the power domain structures for @dev_priv depending upon the
995 * supported platform.
996 */
997int intel_power_domains_init(struct drm_i915_private *dev_priv)
998{
999 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1000
1001 dev_priv->display.params.disable_power_well =
1002 sanitize_disable_power_well_option(dev_priv,
1003 dev_priv->display.params.disable_power_well);
1004 power_domains->allowed_dc_mask =
1005 get_allowed_dc_mask(dev_priv, dev_priv->display.params.enable_dc);
1006
1007 power_domains->target_dc_state =
1008 sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
1009
1010 mutex_init(&power_domains->lock);
1011
1012 INIT_DELAYED_WORK(&power_domains->async_put_work,
1013 intel_display_power_put_async_work);
1014
1015 return intel_display_power_map_init(power_domains);
1016}
1017
1018/**
1019 * intel_power_domains_cleanup - clean up power domains resources
1020 * @dev_priv: i915 device instance
1021 *
1022 * Release any resources acquired by intel_power_domains_init()
1023 */
1024void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
1025{
1026 intel_display_power_map_cleanup(&dev_priv->display.power.domains);
1027}
1028
1029static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
1030{
1031 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1032 struct i915_power_well *power_well;
1033
1034 mutex_lock(&power_domains->lock);
1035 for_each_power_well(dev_priv, power_well)
1036 intel_power_well_sync_hw(dev_priv, power_well);
1037 mutex_unlock(&power_domains->lock);
1038}
1039
1040static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
1041 enum dbuf_slice slice, bool enable)
1042{
1043 i915_reg_t reg = DBUF_CTL_S(slice);
1044 bool state;
1045
1046 intel_de_rmw(dev_priv, reg, DBUF_POWER_REQUEST,
1047 enable ? DBUF_POWER_REQUEST : 0);
1048 intel_de_posting_read(dev_priv, reg);
1049 udelay(10);
1050
1051 state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE;
1052 drm_WARN(&dev_priv->drm, enable != state,
1053 "DBuf slice %d power %s timeout!\n",
1054 slice, str_enable_disable(enable));
1055}
1056
1057void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
1058 u8 req_slices)
1059{
1060 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1061 u8 slice_mask = DISPLAY_INFO(dev_priv)->dbuf.slice_mask;
1062 enum dbuf_slice slice;
1063
1064 drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
1065 "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n",
1066 req_slices, slice_mask);
1067
1068 drm_dbg_kms(&dev_priv->drm, "Updating dbuf slices to 0x%x\n",
1069 req_slices);
1070
1071 /*
1072 * Might be running this in parallel to gen9_dc_off_power_well_enable
1073 * being called from intel_dp_detect for instance,
1074 * which causes assertion triggered by race condition,
1075 * as gen9_assert_dbuf_enabled might preempt this when registers
1076 * were already updated, while dev_priv was not.
1077 */
1078 mutex_lock(&power_domains->lock);
1079
1080 for_each_dbuf_slice(dev_priv, slice)
1081 gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));
1082
1083 dev_priv->display.dbuf.enabled_slices = req_slices;
1084
1085 mutex_unlock(&power_domains->lock);
1086}
1087
1088static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
1089{
1090 u8 slices_mask;
1091
1092 dev_priv->display.dbuf.enabled_slices =
1093 intel_enabled_dbuf_slices_mask(dev_priv);
1094
1095 slices_mask = BIT(DBUF_S1) | dev_priv->display.dbuf.enabled_slices;
1096
1097 if (DISPLAY_VER(dev_priv) >= 14)
1098 intel_pmdemand_program_dbuf(dev_priv, slices_mask);
1099
1100 /*
1101 * Just power up at least 1 slice, we will
1102 * figure out later which slices we have and what we need.
1103 */
1104 gen9_dbuf_slices_update(dev_priv, slices_mask);
1105}
1106
1107static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
1108{
1109 gen9_dbuf_slices_update(dev_priv, 0);
1110
1111 if (DISPLAY_VER(dev_priv) >= 14)
1112 intel_pmdemand_program_dbuf(dev_priv, 0);
1113}
1114
1115static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
1116{
1117 enum dbuf_slice slice;
1118
1119 if (IS_ALDERLAKE_P(dev_priv))
1120 return;
1121
1122 for_each_dbuf_slice(dev_priv, slice)
1123 intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
1124 DBUF_TRACKER_STATE_SERVICE_MASK,
1125 DBUF_TRACKER_STATE_SERVICE(8));
1126}
1127
1128static void icl_mbus_init(struct drm_i915_private *dev_priv)
1129{
1130 unsigned long abox_regs = DISPLAY_INFO(dev_priv)->abox_mask;
1131 u32 mask, val, i;
1132
1133 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
1134 return;
1135
1136 mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
1137 MBUS_ABOX_BT_CREDIT_POOL2_MASK |
1138 MBUS_ABOX_B_CREDIT_MASK |
1139 MBUS_ABOX_BW_CREDIT_MASK;
1140 val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
1141 MBUS_ABOX_BT_CREDIT_POOL2(16) |
1142 MBUS_ABOX_B_CREDIT(1) |
1143 MBUS_ABOX_BW_CREDIT(1);
1144
1145 /*
1146 * gen12 platforms that use abox1 and abox2 for pixel data reads still
1147 * expect us to program the abox_ctl0 register as well, even though
1148 * we don't have to program other instance-0 registers like BW_BUDDY.
1149 */
1150 if (DISPLAY_VER(dev_priv) == 12)
1151 abox_regs |= BIT(0);
1152
1153 for_each_set_bit(i, &abox_regs, sizeof(abox_regs))
1154 intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val);
1155}
1156
1157static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
1158{
1159 u32 val = intel_de_read(dev_priv, LCPLL_CTL);
1160
1161 /*
1162 * The LCPLL register should be turned on by the BIOS. For now
1163 * let's just check its state and print errors in case
1164 * something is wrong. Don't even try to turn it on.
1165 */
1166
1167 if (val & LCPLL_CD_SOURCE_FCLK)
1168 drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n");
1169
1170 if (val & LCPLL_PLL_DISABLE)
1171 drm_err(&dev_priv->drm, "LCPLL is disabled\n");
1172
1173 if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC)
1174 drm_err(&dev_priv->drm, "LCPLL not using non-SSC reference\n");
1175}
1176
1177static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
1178{
1179 struct intel_display *display = &dev_priv->display;
1180 struct intel_crtc *crtc;
1181
1182 for_each_intel_crtc(display->drm, crtc)
1183 INTEL_DISPLAY_STATE_WARN(display, crtc->active,
1184 "CRTC for pipe %c enabled\n",
1185 pipe_name(crtc->pipe));
1186
1187 INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2),
1188 "Display power well on\n");
1189 INTEL_DISPLAY_STATE_WARN(display,
1190 intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE,
1191 "SPLL enabled\n");
1192 INTEL_DISPLAY_STATE_WARN(display,
1193 intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
1194 "WRPLL1 enabled\n");
1195 INTEL_DISPLAY_STATE_WARN(display,
1196 intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
1197 "WRPLL2 enabled\n");
1198 INTEL_DISPLAY_STATE_WARN(display,
1199 intel_de_read(display, PP_STATUS(display, 0)) & PP_ON,
1200 "Panel power on\n");
1201 INTEL_DISPLAY_STATE_WARN(display,
1202 intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
1203 "CPU PWM1 enabled\n");
1204 if (IS_HASWELL(dev_priv))
1205 INTEL_DISPLAY_STATE_WARN(display,
1206 intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
1207 "CPU PWM2 enabled\n");
1208 INTEL_DISPLAY_STATE_WARN(display,
1209 intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
1210 "PCH PWM1 enabled\n");
1211 INTEL_DISPLAY_STATE_WARN(display,
1212 (intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),
1213 "Utility pin enabled in PWM mode\n");
1214 INTEL_DISPLAY_STATE_WARN(display,
1215 intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE,
1216 "PCH GTC enabled\n");
1217
1218 /*
1219 * In theory we can still leave IRQs enabled, as long as only the HPD
1220 * interrupts remain enabled. We used to check for that, but since it's
1221 * gen-specific and since we only disable LCPLL after we fully disable
1222 * the interrupts, the check below should be enough.
1223 */
1224 INTEL_DISPLAY_STATE_WARN(display, intel_irqs_enabled(dev_priv),
1225 "IRQs enabled\n");
1226}
1227
1228static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
1229{
1230 if (IS_HASWELL(dev_priv))
1231 return intel_de_read(dev_priv, D_COMP_HSW);
1232 else
1233 return intel_de_read(dev_priv, D_COMP_BDW);
1234}
1235
1236static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
1237{
1238 if (IS_HASWELL(dev_priv)) {
1239 if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val))
1240 drm_dbg_kms(&dev_priv->drm,
1241 "Failed to write to D_COMP\n");
1242 } else {
1243 intel_de_write(dev_priv, D_COMP_BDW, val);
1244 intel_de_posting_read(dev_priv, D_COMP_BDW);
1245 }
1246}
1247
1248/*
1249 * This function implements pieces of two sequences from BSpec:
1250 * - Sequence for display software to disable LCPLL
1251 * - Sequence for display software to allow package C8+
1252 * The steps implemented here are just the steps that actually touch the LCPLL
1253 * register. Callers should take care of disabling all the display engine
1254 * functions, doing the mode unset, fixing interrupts, etc.
1255 */
1256static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
1257 bool switch_to_fclk, bool allow_power_down)
1258{
1259 u32 val;
1260
1261 assert_can_disable_lcpll(dev_priv);
1262
1263 val = intel_de_read(dev_priv, LCPLL_CTL);
1264
1265 if (switch_to_fclk) {
1266 val |= LCPLL_CD_SOURCE_FCLK;
1267 intel_de_write(dev_priv, LCPLL_CTL, val);
1268
1269 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
1270 LCPLL_CD_SOURCE_FCLK_DONE, 1))
1271 drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
1272
1273 val = intel_de_read(dev_priv, LCPLL_CTL);
1274 }
1275
1276 val |= LCPLL_PLL_DISABLE;
1277 intel_de_write(dev_priv, LCPLL_CTL, val);
1278 intel_de_posting_read(dev_priv, LCPLL_CTL);
1279
1280 if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
1281 drm_err(&dev_priv->drm, "LCPLL still locked\n");
1282
1283 val = hsw_read_dcomp(dev_priv);
1284 val |= D_COMP_COMP_DISABLE;
1285 hsw_write_dcomp(dev_priv, val);
1286 ndelay(100);
1287
1288 if (wait_for((hsw_read_dcomp(dev_priv) &
1289 D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
1290 drm_err(&dev_priv->drm, "D_COMP RCOMP still in progress\n");
1291
1292 if (allow_power_down) {
1293 intel_de_rmw(dev_priv, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW);
1294 intel_de_posting_read(dev_priv, LCPLL_CTL);
1295 }
1296}
1297
1298/*
1299 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
1300 * source.
1301 */
1302static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
1303{
1304 struct intel_display *display = &dev_priv->display;
1305 u32 val;
1306
1307 val = intel_de_read(dev_priv, LCPLL_CTL);
1308
1309 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
1310 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
1311 return;
1312
1313 /*
1314 * Make sure we're not on PC8 state before disabling PC8, otherwise
1315 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
1316 */
1317 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
1318
1319 if (val & LCPLL_POWER_DOWN_ALLOW) {
1320 val &= ~LCPLL_POWER_DOWN_ALLOW;
1321 intel_de_write(dev_priv, LCPLL_CTL, val);
1322 intel_de_posting_read(dev_priv, LCPLL_CTL);
1323 }
1324
1325 val = hsw_read_dcomp(dev_priv);
1326 val |= D_COMP_COMP_FORCE;
1327 val &= ~D_COMP_COMP_DISABLE;
1328 hsw_write_dcomp(dev_priv, val);
1329
1330 val = intel_de_read(dev_priv, LCPLL_CTL);
1331 val &= ~LCPLL_PLL_DISABLE;
1332 intel_de_write(dev_priv, LCPLL_CTL, val);
1333
1334 if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
1335 drm_err(&dev_priv->drm, "LCPLL not locked yet\n");
1336
1337 if (val & LCPLL_CD_SOURCE_FCLK) {
1338 intel_de_rmw(dev_priv, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0);
1339
1340 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
1341 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
1342 drm_err(&dev_priv->drm,
1343 "Switching back to LCPLL failed\n");
1344 }
1345
1346 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
1347
1348 intel_update_cdclk(display);
1349 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
1350}
1351
1352/*
1353 * Package states C8 and deeper are really deep PC states that can only be
1354 * reached when all the devices on the system allow it, so even if the graphics
1355 * device allows PC8+, it doesn't mean the system will actually get to these
1356 * states. Our driver only allows PC8+ when going into runtime PM.
1357 *
1358 * The requirements for PC8+ are that all the outputs are disabled, the power
1359 * well is disabled and most interrupts are disabled, and these are also
1360 * requirements for runtime PM. When these conditions are met, we manually do
1361 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
1362 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
1363 * hang the machine.
1364 *
1365 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1366 * the state of some registers, so when we come back from PC8+ we need to
1367 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1368 * need to take care of the registers kept by RC6. Notice that this happens even
1369 * if we don't put the device in PCI D3 state (which is what currently happens
1370 * because of the runtime PM support).
1371 *
1372 * For more, read "Display Sequences for Package C8" on the hardware
1373 * documentation.
1374 */
1375static void hsw_enable_pc8(struct drm_i915_private *dev_priv)
1376{
1377 drm_dbg_kms(&dev_priv->drm, "Enabling package C8+\n");
1378
1379 if (HAS_PCH_LPT_LP(dev_priv))
1380 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
1381 PCH_LP_PARTITION_LEVEL_DISABLE, 0);
1382
1383 lpt_disable_clkout_dp(dev_priv);
1384 hsw_disable_lcpll(dev_priv, true, true);
1385}
1386
1387static void hsw_disable_pc8(struct drm_i915_private *dev_priv)
1388{
1389 drm_dbg_kms(&dev_priv->drm, "Disabling package C8+\n");
1390
1391 hsw_restore_lcpll(dev_priv);
1392 intel_init_pch_refclk(dev_priv);
1393
1394 /* Many display registers don't survive PC8+ */
1395 intel_clock_gating_init(dev_priv);
1396}
1397
1398static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
1399 bool enable)
1400{
1401 i915_reg_t reg;
1402 u32 reset_bits;
1403
1404 if (IS_IVYBRIDGE(dev_priv)) {
1405 reg = GEN7_MSG_CTL;
1406 reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;
1407 } else {
1408 reg = HSW_NDE_RSTWRN_OPT;
1409 reset_bits = RESET_PCH_HANDSHAKE_ENABLE;
1410 }
1411
1412 if (DISPLAY_VER(dev_priv) >= 14)
1413 reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN;
1414
1415 intel_de_rmw(dev_priv, reg, reset_bits, enable ? reset_bits : 0);
1416}
1417
1418static void skl_display_core_init(struct drm_i915_private *dev_priv,
1419 bool resume)
1420{
1421 struct intel_display *display = &dev_priv->display;
1422 struct i915_power_domains *power_domains = &display->power.domains;
1423 struct i915_power_well *well;
1424
1425 gen9_set_dc_state(display, DC_STATE_DISABLE);
1426
1427 /* enable PCH reset handshake */
1428 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
1429
1430 if (!HAS_DISPLAY(dev_priv))
1431 return;
1432
1433 /* enable PG1 and Misc I/O */
1434 mutex_lock(&power_domains->lock);
1435
1436 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1437 intel_power_well_enable(dev_priv, well);
1438
1439 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1440 intel_power_well_enable(dev_priv, well);
1441
1442 mutex_unlock(&power_domains->lock);
1443
1444 intel_cdclk_init_hw(display);
1445
1446 gen9_dbuf_enable(dev_priv);
1447
1448 if (resume)
1449 intel_dmc_load_program(display);
1450}
1451
1452static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
1453{
1454 struct intel_display *display = &dev_priv->display;
1455 struct i915_power_domains *power_domains = &display->power.domains;
1456 struct i915_power_well *well;
1457
1458 if (!HAS_DISPLAY(dev_priv))
1459 return;
1460
1461 gen9_disable_dc_states(display);
1462 /* TODO: disable DMC program */
1463
1464 gen9_dbuf_disable(dev_priv);
1465
1466 intel_cdclk_uninit_hw(display);
1467
1468 /* The spec doesn't call for removing the reset handshake flag */
1469 /* disable PG1 and Misc I/O */
1470
1471 mutex_lock(&power_domains->lock);
1472
1473 /*
1474 * BSpec says to keep the MISC IO power well enabled here, only
1475 * remove our request for power well 1.
1476 * Note that even though the driver's request is removed power well 1
1477 * may stay enabled after this due to DMC's own request on it.
1478 */
1479 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1480 intel_power_well_disable(dev_priv, well);
1481
1482 mutex_unlock(&power_domains->lock);
1483
1484 usleep_range(10, 30); /* 10 us delay per Bspec */
1485}
1486
1487static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume)
1488{
1489 struct intel_display *display = &dev_priv->display;
1490 struct i915_power_domains *power_domains = &display->power.domains;
1491 struct i915_power_well *well;
1492
1493 gen9_set_dc_state(display, DC_STATE_DISABLE);
1494
1495 /*
1496 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
1497 * or else the reset will hang because there is no PCH to respond.
1498 * Move the handshake programming to initialization sequence.
1499 * Previously was left up to BIOS.
1500 */
1501 intel_pch_reset_handshake(dev_priv, false);
1502
1503 if (!HAS_DISPLAY(dev_priv))
1504 return;
1505
1506 /* Enable PG1 */
1507 mutex_lock(&power_domains->lock);
1508
1509 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1510 intel_power_well_enable(dev_priv, well);
1511
1512 mutex_unlock(&power_domains->lock);
1513
1514 intel_cdclk_init_hw(display);
1515
1516 gen9_dbuf_enable(dev_priv);
1517
1518 if (resume)
1519 intel_dmc_load_program(display);
1520}
1521
1522static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
1523{
1524 struct intel_display *display = &dev_priv->display;
1525 struct i915_power_domains *power_domains = &display->power.domains;
1526 struct i915_power_well *well;
1527
1528 if (!HAS_DISPLAY(dev_priv))
1529 return;
1530
1531 gen9_disable_dc_states(display);
1532 /* TODO: disable DMC program */
1533
1534 gen9_dbuf_disable(dev_priv);
1535
1536 intel_cdclk_uninit_hw(display);
1537
1538 /* The spec doesn't call for removing the reset handshake flag */
1539
1540 /*
1541 * Disable PW1 (PG1).
1542 * Note that even though the driver's request is removed power well 1
1543 * may stay enabled after this due to DMC's own request on it.
1544 */
1545 mutex_lock(&power_domains->lock);
1546
1547 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1548 intel_power_well_disable(dev_priv, well);
1549
1550 mutex_unlock(&power_domains->lock);
1551
1552 usleep_range(10, 30); /* 10 us delay per Bspec */
1553}
1554
1555struct buddy_page_mask {
1556 u32 page_mask;
1557 u8 type;
1558 u8 num_channels;
1559};
1560
1561static const struct buddy_page_mask tgl_buddy_page_masks[] = {
1562 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF },
1563 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0xF },
1564 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C },
1565 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1C },
1566 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F },
1567 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x1E },
1568 { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 },
1569 { .num_channels = 4, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x38 },
1570 {}
1571};
1572
1573static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = {
1574 { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 },
1575 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0x1 },
1576 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0x1 },
1577 { .num_channels = 1, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1 },
1578 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 },
1579 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x3 },
1580 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x3 },
1581 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x3 },
1582 {}
1583};
1584
1585static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
1586{
1587 enum intel_dram_type type = dev_priv->dram_info.type;
1588 u8 num_channels = dev_priv->dram_info.num_channels;
1589 const struct buddy_page_mask *table;
1590 unsigned long abox_mask = DISPLAY_INFO(dev_priv)->abox_mask;
1591 int config, i;
1592
1593 /* BW_BUDDY registers are not used on dgpu's beyond DG1 */
1594 if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv))
1595 return;
1596
1597 if (IS_ALDERLAKE_S(dev_priv) ||
1598 (IS_ROCKETLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)))
1599 /* Wa_1409767108 */
1600 table = wa_1409767108_buddy_page_masks;
1601 else
1602 table = tgl_buddy_page_masks;
1603
1604 for (config = 0; table[config].page_mask != 0; config++)
1605 if (table[config].num_channels == num_channels &&
1606 table[config].type == type)
1607 break;
1608
1609 if (table[config].page_mask == 0) {
1610 drm_dbg(&dev_priv->drm,
1611 "Unknown memory configuration; disabling address buddy logic.\n");
1612 for_each_set_bit(i, &abox_mask, sizeof(abox_mask))
1613 intel_de_write(dev_priv, BW_BUDDY_CTL(i),
1614 BW_BUDDY_DISABLE);
1615 } else {
1616 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) {
1617 intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
1618 table[config].page_mask);
1619
1620 /* Wa_22010178259:tgl,dg1,rkl,adl-s */
1621 if (DISPLAY_VER(dev_priv) == 12)
1622 intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
1623 BW_BUDDY_TLB_REQ_TIMER_MASK,
1624 BW_BUDDY_TLB_REQ_TIMER(0x8));
1625 }
1626 }
1627}
1628
1629static void icl_display_core_init(struct drm_i915_private *dev_priv,
1630 bool resume)
1631{
1632 struct intel_display *display = &dev_priv->display;
1633 struct i915_power_domains *power_domains = &display->power.domains;
1634 struct i915_power_well *well;
1635
1636 gen9_set_dc_state(display, DC_STATE_DISABLE);
1637
1638 /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
1639 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
1640 INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
1641 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
1642 PCH_DPMGUNIT_CLOCK_GATE_DISABLE);
1643
1644 /* 1. Enable PCH reset handshake. */
1645 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
1646
1647 if (!HAS_DISPLAY(dev_priv))
1648 return;
1649
1650 /* 2. Initialize all combo phys */
1651 intel_combo_phy_init(dev_priv);
1652
1653 /*
1654 * 3. Enable Power Well 1 (PG1).
1655 * The AUX IO power wells will be enabled on demand.
1656 */
1657 mutex_lock(&power_domains->lock);
1658 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1659 intel_power_well_enable(dev_priv, well);
1660 mutex_unlock(&power_domains->lock);
1661
1662 if (DISPLAY_VER(dev_priv) == 14)
1663 intel_de_rmw(dev_priv, DC_STATE_EN,
1664 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0);
1665
1666 /* 4. Enable CDCLK. */
1667 intel_cdclk_init_hw(display);
1668
1669 if (DISPLAY_VER(dev_priv) >= 12)
1670 gen12_dbuf_slices_config(dev_priv);
1671
1672 /* 5. Enable DBUF. */
1673 gen9_dbuf_enable(dev_priv);
1674
1675 /* 6. Setup MBUS. */
1676 icl_mbus_init(dev_priv);
1677
1678 /* 7. Program arbiter BW_BUDDY registers */
1679 if (DISPLAY_VER(dev_priv) >= 12)
1680 tgl_bw_buddy_init(dev_priv);
1681
1682 /* 8. Ensure PHYs have completed calibration and adaptation */
1683 if (IS_DG2(dev_priv))
1684 intel_snps_phy_wait_for_calibration(dev_priv);
1685
1686 /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */
1687 if (DISPLAY_VERx100(dev_priv) == 1401)
1688 intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1);
1689
1690 if (resume)
1691 intel_dmc_load_program(display);
1692
1693 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */
1694 if (IS_DISPLAY_VERx100(dev_priv, 1200, 1300))
1695 intel_de_rmw(dev_priv, GEN11_CHICKEN_DCPR_2, 0,
1696 DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
1697 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR);
1698
1699 /* Wa_14011503030:xelpd */
1700 if (DISPLAY_VER(dev_priv) == 13)
1701 intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
1702
1703 /* Wa_15013987218 */
1704 if (DISPLAY_VER(dev_priv) == 20) {
1705 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
1706 0, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE);
1707 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
1708 PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 0);
1709 }
1710}
1711
1712static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
1713{
1714 struct intel_display *display = &dev_priv->display;
1715 struct i915_power_domains *power_domains = &display->power.domains;
1716 struct i915_power_well *well;
1717
1718 if (!HAS_DISPLAY(dev_priv))
1719 return;
1720
1721 gen9_disable_dc_states(display);
1722 intel_dmc_disable_program(display);
1723
1724 /* 1. Disable all display engine functions -> aready done */
1725
1726 /* 2. Disable DBUF */
1727 gen9_dbuf_disable(dev_priv);
1728
1729 /* 3. Disable CD clock */
1730 intel_cdclk_uninit_hw(display);
1731
1732 if (DISPLAY_VER(dev_priv) == 14)
1733 intel_de_rmw(dev_priv, DC_STATE_EN, 0,
1734 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH);
1735
1736 /*
1737 * 4. Disable Power Well 1 (PG1).
1738 * The AUX IO power wells are toggled on demand, so they are already
1739 * disabled at this point.
1740 */
1741 mutex_lock(&power_domains->lock);
1742 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1743 intel_power_well_disable(dev_priv, well);
1744 mutex_unlock(&power_domains->lock);
1745
1746 /* 5. */
1747 intel_combo_phy_uninit(dev_priv);
1748}
1749
1750static void chv_phy_control_init(struct drm_i915_private *dev_priv)
1751{
1752 struct i915_power_well *cmn_bc =
1753 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1754 struct i915_power_well *cmn_d =
1755 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
1756
1757 /*
1758 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1759 * workaround never ever read DISPLAY_PHY_CONTROL, and
1760 * instead maintain a shadow copy ourselves. Use the actual
1761 * power well state and lane status to reconstruct the
1762 * expected initial value.
1763 */
1764 dev_priv->display.power.chv_phy_control =
1765 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
1766 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
1767 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
1768 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
1769 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
1770
1771 /*
1772 * If all lanes are disabled we leave the override disabled
1773 * with all power down bits cleared to match the state we
1774 * would use after disabling the port. Otherwise enable the
1775 * override and set the lane powerdown bits accding to the
1776 * current lane status.
1777 */
1778 if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
1779 u32 status = intel_de_read(dev_priv, DPLL(dev_priv, PIPE_A));
1780 unsigned int mask;
1781
1782 mask = status & DPLL_PORTB_READY_MASK;
1783 if (mask == 0xf)
1784 mask = 0x0;
1785 else
1786 dev_priv->display.power.chv_phy_control |=
1787 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
1788
1789 dev_priv->display.power.chv_phy_control |=
1790 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
1791
1792 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
1793 if (mask == 0xf)
1794 mask = 0x0;
1795 else
1796 dev_priv->display.power.chv_phy_control |=
1797 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
1798
1799 dev_priv->display.power.chv_phy_control |=
1800 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
1801
1802 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
1803
1804 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = false;
1805 } else {
1806 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true;
1807 }
1808
1809 if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
1810 u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS);
1811 unsigned int mask;
1812
1813 mask = status & DPLL_PORTD_READY_MASK;
1814
1815 if (mask == 0xf)
1816 mask = 0x0;
1817 else
1818 dev_priv->display.power.chv_phy_control |=
1819 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
1820
1821 dev_priv->display.power.chv_phy_control |=
1822 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
1823
1824 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
1825
1826 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = false;
1827 } else {
1828 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = true;
1829 }
1830
1831 drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n",
1832 dev_priv->display.power.chv_phy_control);
1833
1834 /* Defer application of initial phy_control to enabling the powerwell */
1835}
1836
1837static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1838{
1839 struct i915_power_well *cmn =
1840 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1841 struct i915_power_well *disp2d =
1842 lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);
1843
1844 /* If the display might be already active skip this */
1845 if (intel_power_well_is_enabled(dev_priv, cmn) &&
1846 intel_power_well_is_enabled(dev_priv, disp2d) &&
1847 intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST)
1848 return;
1849
1850 drm_dbg_kms(&dev_priv->drm, "toggling display PHY side reset\n");
1851
1852 /* cmnlane needs DPLL registers */
1853 intel_power_well_enable(dev_priv, disp2d);
1854
1855 /*
1856 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1857 * Need to assert and de-assert PHY SB reset by gating the
1858 * common lane power, then un-gating it.
1859 * Simply ungating isn't enough to reset the PHY enough to get
1860 * ports and lanes running.
1861 */
1862 intel_power_well_disable(dev_priv, cmn);
1863}
1864
1865static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0)
1866{
1867 bool ret;
1868
1869 vlv_punit_get(dev_priv);
1870 ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;
1871 vlv_punit_put(dev_priv);
1872
1873 return ret;
1874}
1875
1876static void assert_ved_power_gated(struct drm_i915_private *dev_priv)
1877{
1878 drm_WARN(&dev_priv->drm,
1879 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0),
1880 "VED not power gated\n");
1881}
1882
1883static void assert_isp_power_gated(struct drm_i915_private *dev_priv)
1884{
1885 static const struct pci_device_id isp_ids[] = {
1886 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)},
1887 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)},
1888 {}
1889 };
1890
1891 drm_WARN(&dev_priv->drm, !pci_dev_present(isp_ids) &&
1892 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0),
1893 "ISP not power gated\n");
1894}
1895
1896static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1897
1898/**
1899 * intel_power_domains_init_hw - initialize hardware power domain state
1900 * @i915: i915 device instance
1901 * @resume: Called from resume code paths or not
1902 *
1903 * This function initializes the hardware power domain state and enables all
1904 * power wells belonging to the INIT power domain. Power wells in other
1905 * domains (and not in the INIT domain) are referenced or disabled by
1906 * intel_modeset_readout_hw_state(). After that the reference count of each
1907 * power well must match its HW enabled state, see
1908 * intel_power_domains_verify_state().
1909 *
1910 * It will return with power domains disabled (to be enabled later by
1911 * intel_power_domains_enable()) and must be paired with
1912 * intel_power_domains_driver_remove().
1913 */
1914void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
1915{
1916 struct i915_power_domains *power_domains = &i915->display.power.domains;
1917
1918 power_domains->initializing = true;
1919
1920 if (DISPLAY_VER(i915) >= 11) {
1921 icl_display_core_init(i915, resume);
1922 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
1923 bxt_display_core_init(i915, resume);
1924 } else if (DISPLAY_VER(i915) == 9) {
1925 skl_display_core_init(i915, resume);
1926 } else if (IS_CHERRYVIEW(i915)) {
1927 mutex_lock(&power_domains->lock);
1928 chv_phy_control_init(i915);
1929 mutex_unlock(&power_domains->lock);
1930 assert_isp_power_gated(i915);
1931 } else if (IS_VALLEYVIEW(i915)) {
1932 mutex_lock(&power_domains->lock);
1933 vlv_cmnlane_wa(i915);
1934 mutex_unlock(&power_domains->lock);
1935 assert_ved_power_gated(i915);
1936 assert_isp_power_gated(i915);
1937 } else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) {
1938 hsw_assert_cdclk(i915);
1939 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
1940 } else if (IS_IVYBRIDGE(i915)) {
1941 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
1942 }
1943
1944 /*
1945 * Keep all power wells enabled for any dependent HW access during
1946 * initialization and to make sure we keep BIOS enabled display HW
1947 * resources powered until display HW readout is complete. We drop
1948 * this reference in intel_power_domains_enable().
1949 */
1950 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
1951 power_domains->init_wakeref =
1952 intel_display_power_get(i915, POWER_DOMAIN_INIT);
1953
1954 /* Disable power support if the user asked so. */
1955 if (!i915->display.params.disable_power_well) {
1956 drm_WARN_ON(&i915->drm, power_domains->disable_wakeref);
1957 i915->display.power.domains.disable_wakeref = intel_display_power_get(i915,
1958 POWER_DOMAIN_INIT);
1959 }
1960 intel_power_domains_sync_hw(i915);
1961
1962 power_domains->initializing = false;
1963}
1964
1965/**
1966 * intel_power_domains_driver_remove - deinitialize hw power domain state
1967 * @i915: i915 device instance
1968 *
1969 * De-initializes the display power domain HW state. It also ensures that the
1970 * device stays powered up so that the driver can be reloaded.
1971 *
1972 * It must be called with power domains already disabled (after a call to
1973 * intel_power_domains_disable()) and must be paired with
1974 * intel_power_domains_init_hw().
1975 */
1976void intel_power_domains_driver_remove(struct drm_i915_private *i915)
1977{
1978 intel_wakeref_t wakeref __maybe_unused =
1979 fetch_and_zero(&i915->display.power.domains.init_wakeref);
1980
1981 /* Remove the refcount we took to keep power well support disabled. */
1982 if (!i915->display.params.disable_power_well)
1983 intel_display_power_put(i915, POWER_DOMAIN_INIT,
1984 fetch_and_zero(&i915->display.power.domains.disable_wakeref));
1985
1986 intel_display_power_flush_work_sync(i915);
1987
1988 intel_power_domains_verify_state(i915);
1989
1990 /* Keep the power well enabled, but cancel its rpm wakeref. */
1991 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1992}
1993
1994/**
1995 * intel_power_domains_sanitize_state - sanitize power domains state
1996 * @i915: i915 device instance
1997 *
1998 * Sanitize the power domains state during driver loading and system resume.
1999 * The function will disable all display power wells that BIOS has enabled
2000 * without a user for it (any user for a power well has taken a reference
2001 * on it by the time this function is called, after the state of all the
2002 * pipe, encoder, etc. HW resources have been sanitized).
2003 */
2004void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
2005{
2006 struct i915_power_domains *power_domains = &i915->display.power.domains;
2007 struct i915_power_well *power_well;
2008
2009 mutex_lock(&power_domains->lock);
2010
2011 for_each_power_well_reverse(i915, power_well) {
2012 if (power_well->desc->always_on || power_well->count ||
2013 !intel_power_well_is_enabled(i915, power_well))
2014 continue;
2015
2016 drm_dbg_kms(&i915->drm,
2017 "BIOS left unused %s power well enabled, disabling it\n",
2018 intel_power_well_name(power_well));
2019 intel_power_well_disable(i915, power_well);
2020 }
2021
2022 mutex_unlock(&power_domains->lock);
2023}
2024
2025/**
2026 * intel_power_domains_enable - enable toggling of display power wells
2027 * @i915: i915 device instance
2028 *
2029 * Enable the ondemand enabling/disabling of the display power wells. Note that
2030 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled
2031 * only at specific points of the display modeset sequence, thus they are not
2032 * affected by the intel_power_domains_enable()/disable() calls. The purpose
2033 * of these function is to keep the rest of power wells enabled until the end
2034 * of display HW readout (which will acquire the power references reflecting
2035 * the current HW state).
2036 */
2037void intel_power_domains_enable(struct drm_i915_private *i915)
2038{
2039 intel_wakeref_t wakeref __maybe_unused =
2040 fetch_and_zero(&i915->display.power.domains.init_wakeref);
2041
2042 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
2043 intel_power_domains_verify_state(i915);
2044}
2045
2046/**
2047 * intel_power_domains_disable - disable toggling of display power wells
2048 * @i915: i915 device instance
2049 *
2050 * Disable the ondemand enabling/disabling of the display power wells. See
2051 * intel_power_domains_enable() for which power wells this call controls.
2052 */
2053void intel_power_domains_disable(struct drm_i915_private *i915)
2054{
2055 struct i915_power_domains *power_domains = &i915->display.power.domains;
2056
2057 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
2058 power_domains->init_wakeref =
2059 intel_display_power_get(i915, POWER_DOMAIN_INIT);
2060
2061 intel_power_domains_verify_state(i915);
2062}
2063
2064/**
2065 * intel_power_domains_suspend - suspend power domain state
2066 * @i915: i915 device instance
2067 * @s2idle: specifies whether we go to idle, or deeper sleep
2068 *
2069 * This function prepares the hardware power domain state before entering
2070 * system suspend.
2071 *
2072 * It must be called with power domains already disabled (after a call to
2073 * intel_power_domains_disable()) and paired with intel_power_domains_resume().
2074 */
2075void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle)
2076{
2077 struct intel_display *display = &i915->display;
2078 struct i915_power_domains *power_domains = &display->power.domains;
2079 intel_wakeref_t wakeref __maybe_unused =
2080 fetch_and_zero(&power_domains->init_wakeref);
2081
2082 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
2083
2084 /*
2085 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9
2086 * support don't manually deinit the power domains. This also means the
2087 * DMC firmware will stay active, it will power down any HW
2088 * resources as required and also enable deeper system power states
2089 * that would be blocked if the firmware was inactive.
2090 */
2091 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle &&
2092 intel_dmc_has_payload(display)) {
2093 intel_display_power_flush_work(i915);
2094 intel_power_domains_verify_state(i915);
2095 return;
2096 }
2097
2098 /*
2099 * Even if power well support was disabled we still want to disable
2100 * power wells if power domains must be deinitialized for suspend.
2101 */
2102 if (!i915->display.params.disable_power_well)
2103 intel_display_power_put(i915, POWER_DOMAIN_INIT,
2104 fetch_and_zero(&i915->display.power.domains.disable_wakeref));
2105
2106 intel_display_power_flush_work(i915);
2107 intel_power_domains_verify_state(i915);
2108
2109 if (DISPLAY_VER(i915) >= 11)
2110 icl_display_core_uninit(i915);
2111 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
2112 bxt_display_core_uninit(i915);
2113 else if (DISPLAY_VER(i915) == 9)
2114 skl_display_core_uninit(i915);
2115
2116 power_domains->display_core_suspended = true;
2117}
2118
2119/**
2120 * intel_power_domains_resume - resume power domain state
2121 * @i915: i915 device instance
2122 *
2123 * This function resume the hardware power domain state during system resume.
2124 *
2125 * It will return with power domain support disabled (to be enabled later by
2126 * intel_power_domains_enable()) and must be paired with
2127 * intel_power_domains_suspend().
2128 */
2129void intel_power_domains_resume(struct drm_i915_private *i915)
2130{
2131 struct i915_power_domains *power_domains = &i915->display.power.domains;
2132
2133 if (power_domains->display_core_suspended) {
2134 intel_power_domains_init_hw(i915, true);
2135 power_domains->display_core_suspended = false;
2136 } else {
2137 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
2138 power_domains->init_wakeref =
2139 intel_display_power_get(i915, POWER_DOMAIN_INIT);
2140 }
2141
2142 intel_power_domains_verify_state(i915);
2143}
2144
2145#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2146
2147static void intel_power_domains_dump_info(struct drm_i915_private *i915)
2148{
2149 struct i915_power_domains *power_domains = &i915->display.power.domains;
2150 struct i915_power_well *power_well;
2151
2152 for_each_power_well(i915, power_well) {
2153 enum intel_display_power_domain domain;
2154
2155 drm_dbg(&i915->drm, "%-25s %d\n",
2156 intel_power_well_name(power_well), intel_power_well_refcount(power_well));
2157
2158 for_each_power_domain(domain, intel_power_well_domains(power_well))
2159 drm_dbg(&i915->drm, " %-23s %d\n",
2160 intel_display_power_domain_str(domain),
2161 power_domains->domain_use_count[domain]);
2162 }
2163}
2164
2165/**
2166 * intel_power_domains_verify_state - verify the HW/SW state for all power wells
2167 * @i915: i915 device instance
2168 *
2169 * Verify if the reference count of each power well matches its HW enabled
2170 * state and the total refcount of the domains it belongs to. This must be
2171 * called after modeset HW state sanitization, which is responsible for
2172 * acquiring reference counts for any power wells in use and disabling the
2173 * ones left on by BIOS but not required by any active output.
2174 */
2175static void intel_power_domains_verify_state(struct drm_i915_private *i915)
2176{
2177 struct i915_power_domains *power_domains = &i915->display.power.domains;
2178 struct i915_power_well *power_well;
2179 bool dump_domain_info;
2180
2181 mutex_lock(&power_domains->lock);
2182
2183 verify_async_put_domains_state(power_domains);
2184
2185 dump_domain_info = false;
2186 for_each_power_well(i915, power_well) {
2187 enum intel_display_power_domain domain;
2188 int domains_count;
2189 bool enabled;
2190
2191 enabled = intel_power_well_is_enabled(i915, power_well);
2192 if ((intel_power_well_refcount(power_well) ||
2193 intel_power_well_is_always_on(power_well)) !=
2194 enabled)
2195 drm_err(&i915->drm,
2196 "power well %s state mismatch (refcount %d/enabled %d)",
2197 intel_power_well_name(power_well),
2198 intel_power_well_refcount(power_well), enabled);
2199
2200 domains_count = 0;
2201 for_each_power_domain(domain, intel_power_well_domains(power_well))
2202 domains_count += power_domains->domain_use_count[domain];
2203
2204 if (intel_power_well_refcount(power_well) != domains_count) {
2205 drm_err(&i915->drm,
2206 "power well %s refcount/domain refcount mismatch "
2207 "(refcount %d/domains refcount %d)\n",
2208 intel_power_well_name(power_well),
2209 intel_power_well_refcount(power_well),
2210 domains_count);
2211 dump_domain_info = true;
2212 }
2213 }
2214
2215 if (dump_domain_info) {
2216 static bool dumped;
2217
2218 if (!dumped) {
2219 intel_power_domains_dump_info(i915);
2220 dumped = true;
2221 }
2222 }
2223
2224 mutex_unlock(&power_domains->lock);
2225}
2226
2227#else
2228
2229static void intel_power_domains_verify_state(struct drm_i915_private *i915)
2230{
2231}
2232
2233#endif
2234
2235void intel_display_power_suspend_late(struct drm_i915_private *i915)
2236{
2237 struct intel_display *display = &i915->display;
2238
2239 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
2240 IS_BROXTON(i915)) {
2241 bxt_enable_dc9(display);
2242 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2243 hsw_enable_pc8(i915);
2244 }
2245
2246 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
2247 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
2248 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
2249}
2250
2251void intel_display_power_resume_early(struct drm_i915_private *i915)
2252{
2253 struct intel_display *display = &i915->display;
2254
2255 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
2256 IS_BROXTON(i915)) {
2257 gen9_sanitize_dc_state(display);
2258 bxt_disable_dc9(display);
2259 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2260 hsw_disable_pc8(i915);
2261 }
2262
2263 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
2264 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
2265 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
2266}
2267
2268void intel_display_power_suspend(struct drm_i915_private *i915)
2269{
2270 struct intel_display *display = &i915->display;
2271
2272 if (DISPLAY_VER(i915) >= 11) {
2273 icl_display_core_uninit(i915);
2274 bxt_enable_dc9(display);
2275 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
2276 bxt_display_core_uninit(i915);
2277 bxt_enable_dc9(display);
2278 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2279 hsw_enable_pc8(i915);
2280 }
2281}
2282
2283void intel_display_power_resume(struct drm_i915_private *i915)
2284{
2285 struct intel_display *display = &i915->display;
2286 struct i915_power_domains *power_domains = &display->power.domains;
2287
2288 if (DISPLAY_VER(i915) >= 11) {
2289 bxt_disable_dc9(display);
2290 icl_display_core_init(i915, true);
2291 if (intel_dmc_has_payload(display)) {
2292 if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
2293 skl_enable_dc6(display);
2294 else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
2295 gen9_enable_dc5(display);
2296 }
2297 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
2298 bxt_disable_dc9(display);
2299 bxt_display_core_init(i915, true);
2300 if (intel_dmc_has_payload(display) &&
2301 (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2302 gen9_enable_dc5(display);
2303 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2304 hsw_disable_pc8(i915);
2305 }
2306}
2307
2308void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m)
2309{
2310 struct i915_power_domains *power_domains = &i915->display.power.domains;
2311 int i;
2312
2313 mutex_lock(&power_domains->lock);
2314
2315 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2316 for (i = 0; i < power_domains->power_well_count; i++) {
2317 struct i915_power_well *power_well;
2318 enum intel_display_power_domain power_domain;
2319
2320 power_well = &power_domains->power_wells[i];
2321 seq_printf(m, "%-25s %d\n", intel_power_well_name(power_well),
2322 intel_power_well_refcount(power_well));
2323
2324 for_each_power_domain(power_domain, intel_power_well_domains(power_well))
2325 seq_printf(m, " %-23s %d\n",
2326 intel_display_power_domain_str(power_domain),
2327 power_domains->domain_use_count[power_domain]);
2328 }
2329
2330 mutex_unlock(&power_domains->lock);
2331}
2332
2333struct intel_ddi_port_domains {
2334 enum port port_start;
2335 enum port port_end;
2336 enum aux_ch aux_ch_start;
2337 enum aux_ch aux_ch_end;
2338
2339 enum intel_display_power_domain ddi_lanes;
2340 enum intel_display_power_domain ddi_io;
2341 enum intel_display_power_domain aux_io;
2342 enum intel_display_power_domain aux_legacy_usbc;
2343 enum intel_display_power_domain aux_tbt;
2344};
2345
2346static const struct intel_ddi_port_domains
2347i9xx_port_domains[] = {
2348 {
2349 .port_start = PORT_A,
2350 .port_end = PORT_F,
2351 .aux_ch_start = AUX_CH_A,
2352 .aux_ch_end = AUX_CH_F,
2353
2354 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2355 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2356 .aux_io = POWER_DOMAIN_AUX_IO_A,
2357 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2358 .aux_tbt = POWER_DOMAIN_INVALID,
2359 },
2360};
2361
2362static const struct intel_ddi_port_domains
2363d11_port_domains[] = {
2364 {
2365 .port_start = PORT_A,
2366 .port_end = PORT_B,
2367 .aux_ch_start = AUX_CH_A,
2368 .aux_ch_end = AUX_CH_B,
2369
2370 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2371 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2372 .aux_io = POWER_DOMAIN_AUX_IO_A,
2373 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2374 .aux_tbt = POWER_DOMAIN_INVALID,
2375 }, {
2376 .port_start = PORT_C,
2377 .port_end = PORT_F,
2378 .aux_ch_start = AUX_CH_C,
2379 .aux_ch_end = AUX_CH_F,
2380
2381 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
2382 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
2383 .aux_io = POWER_DOMAIN_AUX_IO_C,
2384 .aux_legacy_usbc = POWER_DOMAIN_AUX_C,
2385 .aux_tbt = POWER_DOMAIN_AUX_TBT1,
2386 },
2387};
2388
2389static const struct intel_ddi_port_domains
2390d12_port_domains[] = {
2391 {
2392 .port_start = PORT_A,
2393 .port_end = PORT_C,
2394 .aux_ch_start = AUX_CH_A,
2395 .aux_ch_end = AUX_CH_C,
2396
2397 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2398 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2399 .aux_io = POWER_DOMAIN_AUX_IO_A,
2400 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2401 .aux_tbt = POWER_DOMAIN_INVALID,
2402 }, {
2403 .port_start = PORT_TC1,
2404 .port_end = PORT_TC6,
2405 .aux_ch_start = AUX_CH_USBC1,
2406 .aux_ch_end = AUX_CH_USBC6,
2407
2408 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
2409 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
2410 .aux_io = POWER_DOMAIN_INVALID,
2411 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
2412 .aux_tbt = POWER_DOMAIN_AUX_TBT1,
2413 },
2414};
2415
2416static const struct intel_ddi_port_domains
2417d13_port_domains[] = {
2418 {
2419 .port_start = PORT_A,
2420 .port_end = PORT_C,
2421 .aux_ch_start = AUX_CH_A,
2422 .aux_ch_end = AUX_CH_C,
2423
2424 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2425 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2426 .aux_io = POWER_DOMAIN_AUX_IO_A,
2427 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2428 .aux_tbt = POWER_DOMAIN_INVALID,
2429 }, {
2430 .port_start = PORT_TC1,
2431 .port_end = PORT_TC4,
2432 .aux_ch_start = AUX_CH_USBC1,
2433 .aux_ch_end = AUX_CH_USBC4,
2434
2435 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
2436 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
2437 .aux_io = POWER_DOMAIN_INVALID,
2438 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
2439 .aux_tbt = POWER_DOMAIN_AUX_TBT1,
2440 }, {
2441 .port_start = PORT_D_XELPD,
2442 .port_end = PORT_E_XELPD,
2443 .aux_ch_start = AUX_CH_D_XELPD,
2444 .aux_ch_end = AUX_CH_E_XELPD,
2445
2446 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D,
2447 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D,
2448 .aux_io = POWER_DOMAIN_AUX_IO_D,
2449 .aux_legacy_usbc = POWER_DOMAIN_AUX_D,
2450 .aux_tbt = POWER_DOMAIN_INVALID,
2451 },
2452};
2453
2454static void
2455intel_port_domains_for_platform(struct drm_i915_private *i915,
2456 const struct intel_ddi_port_domains **domains,
2457 int *domains_size)
2458{
2459 if (DISPLAY_VER(i915) >= 13) {
2460 *domains = d13_port_domains;
2461 *domains_size = ARRAY_SIZE(d13_port_domains);
2462 } else if (DISPLAY_VER(i915) >= 12) {
2463 *domains = d12_port_domains;
2464 *domains_size = ARRAY_SIZE(d12_port_domains);
2465 } else if (DISPLAY_VER(i915) >= 11) {
2466 *domains = d11_port_domains;
2467 *domains_size = ARRAY_SIZE(d11_port_domains);
2468 } else {
2469 *domains = i9xx_port_domains;
2470 *domains_size = ARRAY_SIZE(i9xx_port_domains);
2471 }
2472}
2473
2474static const struct intel_ddi_port_domains *
2475intel_port_domains_for_port(struct drm_i915_private *i915, enum port port)
2476{
2477 const struct intel_ddi_port_domains *domains;
2478 int domains_size;
2479 int i;
2480
2481 intel_port_domains_for_platform(i915, &domains, &domains_size);
2482 for (i = 0; i < domains_size; i++)
2483 if (port >= domains[i].port_start && port <= domains[i].port_end)
2484 return &domains[i];
2485
2486 return NULL;
2487}
2488
2489enum intel_display_power_domain
2490intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port)
2491{
2492 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port);
2493
2494 if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID))
2495 return POWER_DOMAIN_PORT_DDI_IO_A;
2496
2497 return domains->ddi_io + (int)(port - domains->port_start);
2498}
2499
2500enum intel_display_power_domain
2501intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port)
2502{
2503 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port);
2504
2505 if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID))
2506 return POWER_DOMAIN_PORT_DDI_LANES_A;
2507
2508 return domains->ddi_lanes + (int)(port - domains->port_start);
2509}
2510
2511static const struct intel_ddi_port_domains *
2512intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch)
2513{
2514 const struct intel_ddi_port_domains *domains;
2515 int domains_size;
2516 int i;
2517
2518 intel_port_domains_for_platform(i915, &domains, &domains_size);
2519 for (i = 0; i < domains_size; i++)
2520 if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end)
2521 return &domains[i];
2522
2523 return NULL;
2524}
2525
2526enum intel_display_power_domain
2527intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
2528{
2529 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
2530
2531 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID))
2532 return POWER_DOMAIN_AUX_IO_A;
2533
2534 return domains->aux_io + (int)(aux_ch - domains->aux_ch_start);
2535}
2536
2537enum intel_display_power_domain
2538intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
2539{
2540 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
2541
2542 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID))
2543 return POWER_DOMAIN_AUX_A;
2544
2545 return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start);
2546}
2547
2548enum intel_display_power_domain
2549intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
2550{
2551 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
2552
2553 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID))
2554 return POWER_DOMAIN_AUX_TBT1;
2555
2556 return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start);
2557}
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#include <linux/string_helpers.h>
7
8#include "i915_drv.h"
9#include "i915_irq.h"
10#include "intel_backlight_regs.h"
11#include "intel_cdclk.h"
12#include "intel_combo_phy.h"
13#include "intel_de.h"
14#include "intel_display_power.h"
15#include "intel_display_power_map.h"
16#include "intel_display_power_well.h"
17#include "intel_display_types.h"
18#include "intel_dmc.h"
19#include "intel_mchbar_regs.h"
20#include "intel_pch_refclk.h"
21#include "intel_pcode.h"
22#include "intel_snps_phy.h"
23#include "skl_watermark.h"
24#include "vlv_sideband.h"
25
26#define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
27 for_each_power_well(__dev_priv, __power_well) \
28 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
29
30#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \
31 for_each_power_well_reverse(__dev_priv, __power_well) \
32 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
33
34const char *
35intel_display_power_domain_str(enum intel_display_power_domain domain)
36{
37 switch (domain) {
38 case POWER_DOMAIN_DISPLAY_CORE:
39 return "DISPLAY_CORE";
40 case POWER_DOMAIN_PIPE_A:
41 return "PIPE_A";
42 case POWER_DOMAIN_PIPE_B:
43 return "PIPE_B";
44 case POWER_DOMAIN_PIPE_C:
45 return "PIPE_C";
46 case POWER_DOMAIN_PIPE_D:
47 return "PIPE_D";
48 case POWER_DOMAIN_PIPE_PANEL_FITTER_A:
49 return "PIPE_PANEL_FITTER_A";
50 case POWER_DOMAIN_PIPE_PANEL_FITTER_B:
51 return "PIPE_PANEL_FITTER_B";
52 case POWER_DOMAIN_PIPE_PANEL_FITTER_C:
53 return "PIPE_PANEL_FITTER_C";
54 case POWER_DOMAIN_PIPE_PANEL_FITTER_D:
55 return "PIPE_PANEL_FITTER_D";
56 case POWER_DOMAIN_TRANSCODER_A:
57 return "TRANSCODER_A";
58 case POWER_DOMAIN_TRANSCODER_B:
59 return "TRANSCODER_B";
60 case POWER_DOMAIN_TRANSCODER_C:
61 return "TRANSCODER_C";
62 case POWER_DOMAIN_TRANSCODER_D:
63 return "TRANSCODER_D";
64 case POWER_DOMAIN_TRANSCODER_EDP:
65 return "TRANSCODER_EDP";
66 case POWER_DOMAIN_TRANSCODER_DSI_A:
67 return "TRANSCODER_DSI_A";
68 case POWER_DOMAIN_TRANSCODER_DSI_C:
69 return "TRANSCODER_DSI_C";
70 case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
71 return "TRANSCODER_VDSC_PW2";
72 case POWER_DOMAIN_PORT_DDI_LANES_A:
73 return "PORT_DDI_LANES_A";
74 case POWER_DOMAIN_PORT_DDI_LANES_B:
75 return "PORT_DDI_LANES_B";
76 case POWER_DOMAIN_PORT_DDI_LANES_C:
77 return "PORT_DDI_LANES_C";
78 case POWER_DOMAIN_PORT_DDI_LANES_D:
79 return "PORT_DDI_LANES_D";
80 case POWER_DOMAIN_PORT_DDI_LANES_E:
81 return "PORT_DDI_LANES_E";
82 case POWER_DOMAIN_PORT_DDI_LANES_F:
83 return "PORT_DDI_LANES_F";
84 case POWER_DOMAIN_PORT_DDI_LANES_TC1:
85 return "PORT_DDI_LANES_TC1";
86 case POWER_DOMAIN_PORT_DDI_LANES_TC2:
87 return "PORT_DDI_LANES_TC2";
88 case POWER_DOMAIN_PORT_DDI_LANES_TC3:
89 return "PORT_DDI_LANES_TC3";
90 case POWER_DOMAIN_PORT_DDI_LANES_TC4:
91 return "PORT_DDI_LANES_TC4";
92 case POWER_DOMAIN_PORT_DDI_LANES_TC5:
93 return "PORT_DDI_LANES_TC5";
94 case POWER_DOMAIN_PORT_DDI_LANES_TC6:
95 return "PORT_DDI_LANES_TC6";
96 case POWER_DOMAIN_PORT_DDI_IO_A:
97 return "PORT_DDI_IO_A";
98 case POWER_DOMAIN_PORT_DDI_IO_B:
99 return "PORT_DDI_IO_B";
100 case POWER_DOMAIN_PORT_DDI_IO_C:
101 return "PORT_DDI_IO_C";
102 case POWER_DOMAIN_PORT_DDI_IO_D:
103 return "PORT_DDI_IO_D";
104 case POWER_DOMAIN_PORT_DDI_IO_E:
105 return "PORT_DDI_IO_E";
106 case POWER_DOMAIN_PORT_DDI_IO_F:
107 return "PORT_DDI_IO_F";
108 case POWER_DOMAIN_PORT_DDI_IO_TC1:
109 return "PORT_DDI_IO_TC1";
110 case POWER_DOMAIN_PORT_DDI_IO_TC2:
111 return "PORT_DDI_IO_TC2";
112 case POWER_DOMAIN_PORT_DDI_IO_TC3:
113 return "PORT_DDI_IO_TC3";
114 case POWER_DOMAIN_PORT_DDI_IO_TC4:
115 return "PORT_DDI_IO_TC4";
116 case POWER_DOMAIN_PORT_DDI_IO_TC5:
117 return "PORT_DDI_IO_TC5";
118 case POWER_DOMAIN_PORT_DDI_IO_TC6:
119 return "PORT_DDI_IO_TC6";
120 case POWER_DOMAIN_PORT_DSI:
121 return "PORT_DSI";
122 case POWER_DOMAIN_PORT_CRT:
123 return "PORT_CRT";
124 case POWER_DOMAIN_PORT_OTHER:
125 return "PORT_OTHER";
126 case POWER_DOMAIN_VGA:
127 return "VGA";
128 case POWER_DOMAIN_AUDIO_MMIO:
129 return "AUDIO_MMIO";
130 case POWER_DOMAIN_AUDIO_PLAYBACK:
131 return "AUDIO_PLAYBACK";
132 case POWER_DOMAIN_AUX_IO_A:
133 return "AUX_IO_A";
134 case POWER_DOMAIN_AUX_IO_B:
135 return "AUX_IO_B";
136 case POWER_DOMAIN_AUX_IO_C:
137 return "AUX_IO_C";
138 case POWER_DOMAIN_AUX_IO_D:
139 return "AUX_IO_D";
140 case POWER_DOMAIN_AUX_IO_E:
141 return "AUX_IO_E";
142 case POWER_DOMAIN_AUX_IO_F:
143 return "AUX_IO_F";
144 case POWER_DOMAIN_AUX_A:
145 return "AUX_A";
146 case POWER_DOMAIN_AUX_B:
147 return "AUX_B";
148 case POWER_DOMAIN_AUX_C:
149 return "AUX_C";
150 case POWER_DOMAIN_AUX_D:
151 return "AUX_D";
152 case POWER_DOMAIN_AUX_E:
153 return "AUX_E";
154 case POWER_DOMAIN_AUX_F:
155 return "AUX_F";
156 case POWER_DOMAIN_AUX_USBC1:
157 return "AUX_USBC1";
158 case POWER_DOMAIN_AUX_USBC2:
159 return "AUX_USBC2";
160 case POWER_DOMAIN_AUX_USBC3:
161 return "AUX_USBC3";
162 case POWER_DOMAIN_AUX_USBC4:
163 return "AUX_USBC4";
164 case POWER_DOMAIN_AUX_USBC5:
165 return "AUX_USBC5";
166 case POWER_DOMAIN_AUX_USBC6:
167 return "AUX_USBC6";
168 case POWER_DOMAIN_AUX_TBT1:
169 return "AUX_TBT1";
170 case POWER_DOMAIN_AUX_TBT2:
171 return "AUX_TBT2";
172 case POWER_DOMAIN_AUX_TBT3:
173 return "AUX_TBT3";
174 case POWER_DOMAIN_AUX_TBT4:
175 return "AUX_TBT4";
176 case POWER_DOMAIN_AUX_TBT5:
177 return "AUX_TBT5";
178 case POWER_DOMAIN_AUX_TBT6:
179 return "AUX_TBT6";
180 case POWER_DOMAIN_GMBUS:
181 return "GMBUS";
182 case POWER_DOMAIN_INIT:
183 return "INIT";
184 case POWER_DOMAIN_MODESET:
185 return "MODESET";
186 case POWER_DOMAIN_GT_IRQ:
187 return "GT_IRQ";
188 case POWER_DOMAIN_DC_OFF:
189 return "DC_OFF";
190 case POWER_DOMAIN_TC_COLD_OFF:
191 return "TC_COLD_OFF";
192 default:
193 MISSING_CASE(domain);
194 return "?";
195 }
196}
197
198/**
199 * __intel_display_power_is_enabled - unlocked check for a power domain
200 * @dev_priv: i915 device instance
201 * @domain: power domain to check
202 *
203 * This is the unlocked version of intel_display_power_is_enabled() and should
204 * only be used from error capture and recovery code where deadlocks are
205 * possible.
206 *
207 * Returns:
208 * True when the power domain is enabled, false otherwise.
209 */
210bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
211 enum intel_display_power_domain domain)
212{
213 struct i915_power_well *power_well;
214 bool is_enabled;
215
216 if (dev_priv->runtime_pm.suspended)
217 return false;
218
219 is_enabled = true;
220
221 for_each_power_domain_well_reverse(dev_priv, power_well, domain) {
222 if (intel_power_well_is_always_on(power_well))
223 continue;
224
225 if (!intel_power_well_is_enabled_cached(power_well)) {
226 is_enabled = false;
227 break;
228 }
229 }
230
231 return is_enabled;
232}
233
234/**
235 * intel_display_power_is_enabled - check for a power domain
236 * @dev_priv: i915 device instance
237 * @domain: power domain to check
238 *
239 * This function can be used to check the hw power domain state. It is mostly
240 * used in hardware state readout functions. Everywhere else code should rely
241 * upon explicit power domain reference counting to ensure that the hardware
242 * block is powered up before accessing it.
243 *
244 * Callers must hold the relevant modesetting locks to ensure that concurrent
245 * threads can't disable the power well while the caller tries to read a few
246 * registers.
247 *
248 * Returns:
249 * True when the power domain is enabled, false otherwise.
250 */
251bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
252 enum intel_display_power_domain domain)
253{
254 struct i915_power_domains *power_domains;
255 bool ret;
256
257 power_domains = &dev_priv->display.power.domains;
258
259 mutex_lock(&power_domains->lock);
260 ret = __intel_display_power_is_enabled(dev_priv, domain);
261 mutex_unlock(&power_domains->lock);
262
263 return ret;
264}
265
266static u32
267sanitize_target_dc_state(struct drm_i915_private *dev_priv,
268 u32 target_dc_state)
269{
270 static const u32 states[] = {
271 DC_STATE_EN_UPTO_DC6,
272 DC_STATE_EN_UPTO_DC5,
273 DC_STATE_EN_DC3CO,
274 DC_STATE_DISABLE,
275 };
276 int i;
277
278 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
279 if (target_dc_state != states[i])
280 continue;
281
282 if (dev_priv->display.dmc.allowed_dc_mask & target_dc_state)
283 break;
284
285 target_dc_state = states[i + 1];
286 }
287
288 return target_dc_state;
289}
290
291/**
292 * intel_display_power_set_target_dc_state - Set target dc state.
293 * @dev_priv: i915 device
294 * @state: state which needs to be set as target_dc_state.
295 *
296 * This function set the "DC off" power well target_dc_state,
297 * based upon this target_dc_stste, "DC off" power well will
298 * enable desired DC state.
299 */
300void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
301 u32 state)
302{
303 struct i915_power_well *power_well;
304 bool dc_off_enabled;
305 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
306
307 mutex_lock(&power_domains->lock);
308 power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF);
309
310 if (drm_WARN_ON(&dev_priv->drm, !power_well))
311 goto unlock;
312
313 state = sanitize_target_dc_state(dev_priv, state);
314
315 if (state == dev_priv->display.dmc.target_dc_state)
316 goto unlock;
317
318 dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well);
319 /*
320 * If DC off power well is disabled, need to enable and disable the
321 * DC off power well to effect target DC state.
322 */
323 if (!dc_off_enabled)
324 intel_power_well_enable(dev_priv, power_well);
325
326 dev_priv->display.dmc.target_dc_state = state;
327
328 if (!dc_off_enabled)
329 intel_power_well_disable(dev_priv, power_well);
330
331unlock:
332 mutex_unlock(&power_domains->lock);
333}
334
335#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
336
337static void __async_put_domains_mask(struct i915_power_domains *power_domains,
338 struct intel_power_domain_mask *mask)
339{
340 bitmap_or(mask->bits,
341 power_domains->async_put_domains[0].bits,
342 power_domains->async_put_domains[1].bits,
343 POWER_DOMAIN_NUM);
344}
345
346#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
347
348static bool
349assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
350{
351 struct drm_i915_private *i915 = container_of(power_domains,
352 struct drm_i915_private,
353 display.power.domains);
354
355 return !drm_WARN_ON(&i915->drm,
356 bitmap_intersects(power_domains->async_put_domains[0].bits,
357 power_domains->async_put_domains[1].bits,
358 POWER_DOMAIN_NUM));
359}
360
361static bool
362__async_put_domains_state_ok(struct i915_power_domains *power_domains)
363{
364 struct drm_i915_private *i915 = container_of(power_domains,
365 struct drm_i915_private,
366 display.power.domains);
367 struct intel_power_domain_mask async_put_mask;
368 enum intel_display_power_domain domain;
369 bool err = false;
370
371 err |= !assert_async_put_domain_masks_disjoint(power_domains);
372 __async_put_domains_mask(power_domains, &async_put_mask);
373 err |= drm_WARN_ON(&i915->drm,
374 !!power_domains->async_put_wakeref !=
375 !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM));
376
377 for_each_power_domain(domain, &async_put_mask)
378 err |= drm_WARN_ON(&i915->drm,
379 power_domains->domain_use_count[domain] != 1);
380
381 return !err;
382}
383
384static void print_power_domains(struct i915_power_domains *power_domains,
385 const char *prefix, struct intel_power_domain_mask *mask)
386{
387 struct drm_i915_private *i915 = container_of(power_domains,
388 struct drm_i915_private,
389 display.power.domains);
390 enum intel_display_power_domain domain;
391
392 drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
393 for_each_power_domain(domain, mask)
394 drm_dbg(&i915->drm, "%s use_count %d\n",
395 intel_display_power_domain_str(domain),
396 power_domains->domain_use_count[domain]);
397}
398
399static void
400print_async_put_domains_state(struct i915_power_domains *power_domains)
401{
402 struct drm_i915_private *i915 = container_of(power_domains,
403 struct drm_i915_private,
404 display.power.domains);
405
406 drm_dbg(&i915->drm, "async_put_wakeref %u\n",
407 power_domains->async_put_wakeref);
408
409 print_power_domains(power_domains, "async_put_domains[0]",
410 &power_domains->async_put_domains[0]);
411 print_power_domains(power_domains, "async_put_domains[1]",
412 &power_domains->async_put_domains[1]);
413}
414
415static void
416verify_async_put_domains_state(struct i915_power_domains *power_domains)
417{
418 if (!__async_put_domains_state_ok(power_domains))
419 print_async_put_domains_state(power_domains);
420}
421
422#else
423
424static void
425assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
426{
427}
428
429static void
430verify_async_put_domains_state(struct i915_power_domains *power_domains)
431{
432}
433
434#endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */
435
436static void async_put_domains_mask(struct i915_power_domains *power_domains,
437 struct intel_power_domain_mask *mask)
438
439{
440 assert_async_put_domain_masks_disjoint(power_domains);
441
442 __async_put_domains_mask(power_domains, mask);
443}
444
445static void
446async_put_domains_clear_domain(struct i915_power_domains *power_domains,
447 enum intel_display_power_domain domain)
448{
449 assert_async_put_domain_masks_disjoint(power_domains);
450
451 clear_bit(domain, power_domains->async_put_domains[0].bits);
452 clear_bit(domain, power_domains->async_put_domains[1].bits);
453}
454
455static bool
456intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
457 enum intel_display_power_domain domain)
458{
459 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
460 struct intel_power_domain_mask async_put_mask;
461 bool ret = false;
462
463 async_put_domains_mask(power_domains, &async_put_mask);
464 if (!test_bit(domain, async_put_mask.bits))
465 goto out_verify;
466
467 async_put_domains_clear_domain(power_domains, domain);
468
469 ret = true;
470
471 async_put_domains_mask(power_domains, &async_put_mask);
472 if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM))
473 goto out_verify;
474
475 cancel_delayed_work(&power_domains->async_put_work);
476 intel_runtime_pm_put_raw(&dev_priv->runtime_pm,
477 fetch_and_zero(&power_domains->async_put_wakeref));
478out_verify:
479 verify_async_put_domains_state(power_domains);
480
481 return ret;
482}
483
484static void
485__intel_display_power_get_domain(struct drm_i915_private *dev_priv,
486 enum intel_display_power_domain domain)
487{
488 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
489 struct i915_power_well *power_well;
490
491 if (intel_display_power_grab_async_put_ref(dev_priv, domain))
492 return;
493
494 for_each_power_domain_well(dev_priv, power_well, domain)
495 intel_power_well_get(dev_priv, power_well);
496
497 power_domains->domain_use_count[domain]++;
498}
499
500/**
501 * intel_display_power_get - grab a power domain reference
502 * @dev_priv: i915 device instance
503 * @domain: power domain to reference
504 *
505 * This function grabs a power domain reference for @domain and ensures that the
506 * power domain and all its parents are powered up. Therefore users should only
507 * grab a reference to the innermost power domain they need.
508 *
509 * Any power domain reference obtained by this function must have a symmetric
510 * call to intel_display_power_put() to release the reference again.
511 */
512intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
513 enum intel_display_power_domain domain)
514{
515 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
516 intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
517
518 mutex_lock(&power_domains->lock);
519 __intel_display_power_get_domain(dev_priv, domain);
520 mutex_unlock(&power_domains->lock);
521
522 return wakeref;
523}
524
525/**
526 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
527 * @dev_priv: i915 device instance
528 * @domain: power domain to reference
529 *
530 * This function grabs a power domain reference for @domain and ensures that the
531 * power domain and all its parents are powered up. Therefore users should only
532 * grab a reference to the innermost power domain they need.
533 *
534 * Any power domain reference obtained by this function must have a symmetric
535 * call to intel_display_power_put() to release the reference again.
536 */
537intel_wakeref_t
538intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
539 enum intel_display_power_domain domain)
540{
541 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
542 intel_wakeref_t wakeref;
543 bool is_enabled;
544
545 wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm);
546 if (!wakeref)
547 return false;
548
549 mutex_lock(&power_domains->lock);
550
551 if (__intel_display_power_is_enabled(dev_priv, domain)) {
552 __intel_display_power_get_domain(dev_priv, domain);
553 is_enabled = true;
554 } else {
555 is_enabled = false;
556 }
557
558 mutex_unlock(&power_domains->lock);
559
560 if (!is_enabled) {
561 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
562 wakeref = 0;
563 }
564
565 return wakeref;
566}
567
568static void
569__intel_display_power_put_domain(struct drm_i915_private *dev_priv,
570 enum intel_display_power_domain domain)
571{
572 struct i915_power_domains *power_domains;
573 struct i915_power_well *power_well;
574 const char *name = intel_display_power_domain_str(domain);
575 struct intel_power_domain_mask async_put_mask;
576
577 power_domains = &dev_priv->display.power.domains;
578
579 drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain],
580 "Use count on domain %s is already zero\n",
581 name);
582 async_put_domains_mask(power_domains, &async_put_mask);
583 drm_WARN(&dev_priv->drm,
584 test_bit(domain, async_put_mask.bits),
585 "Async disabling of domain %s is pending\n",
586 name);
587
588 power_domains->domain_use_count[domain]--;
589
590 for_each_power_domain_well_reverse(dev_priv, power_well, domain)
591 intel_power_well_put(dev_priv, power_well);
592}
593
594static void __intel_display_power_put(struct drm_i915_private *dev_priv,
595 enum intel_display_power_domain domain)
596{
597 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
598
599 mutex_lock(&power_domains->lock);
600 __intel_display_power_put_domain(dev_priv, domain);
601 mutex_unlock(&power_domains->lock);
602}
603
604static void
605queue_async_put_domains_work(struct i915_power_domains *power_domains,
606 intel_wakeref_t wakeref)
607{
608 struct drm_i915_private *i915 = container_of(power_domains,
609 struct drm_i915_private,
610 display.power.domains);
611 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
612 power_domains->async_put_wakeref = wakeref;
613 drm_WARN_ON(&i915->drm, !queue_delayed_work(system_unbound_wq,
614 &power_domains->async_put_work,
615 msecs_to_jiffies(100)));
616}
617
618static void
619release_async_put_domains(struct i915_power_domains *power_domains,
620 struct intel_power_domain_mask *mask)
621{
622 struct drm_i915_private *dev_priv =
623 container_of(power_domains, struct drm_i915_private,
624 display.power.domains);
625 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
626 enum intel_display_power_domain domain;
627 intel_wakeref_t wakeref;
628
629 /*
630 * The caller must hold already raw wakeref, upgrade that to a proper
631 * wakeref to make the state checker happy about the HW access during
632 * power well disabling.
633 */
634 assert_rpm_raw_wakeref_held(rpm);
635 wakeref = intel_runtime_pm_get(rpm);
636
637 for_each_power_domain(domain, mask) {
638 /* Clear before put, so put's sanity check is happy. */
639 async_put_domains_clear_domain(power_domains, domain);
640 __intel_display_power_put_domain(dev_priv, domain);
641 }
642
643 intel_runtime_pm_put(rpm, wakeref);
644}
645
646static void
647intel_display_power_put_async_work(struct work_struct *work)
648{
649 struct drm_i915_private *dev_priv =
650 container_of(work, struct drm_i915_private,
651 display.power.domains.async_put_work.work);
652 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
653 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
654 intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(rpm);
655 intel_wakeref_t old_work_wakeref = 0;
656
657 mutex_lock(&power_domains->lock);
658
659 /*
660 * Bail out if all the domain refs pending to be released were grabbed
661 * by subsequent gets or a flush_work.
662 */
663 old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref);
664 if (!old_work_wakeref)
665 goto out_verify;
666
667 release_async_put_domains(power_domains,
668 &power_domains->async_put_domains[0]);
669
670 /* Requeue the work if more domains were async put meanwhile. */
671 if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) {
672 bitmap_copy(power_domains->async_put_domains[0].bits,
673 power_domains->async_put_domains[1].bits,
674 POWER_DOMAIN_NUM);
675 bitmap_zero(power_domains->async_put_domains[1].bits,
676 POWER_DOMAIN_NUM);
677 queue_async_put_domains_work(power_domains,
678 fetch_and_zero(&new_work_wakeref));
679 } else {
680 /*
681 * Cancel the work that got queued after this one got dequeued,
682 * since here we released the corresponding async-put reference.
683 */
684 cancel_delayed_work(&power_domains->async_put_work);
685 }
686
687out_verify:
688 verify_async_put_domains_state(power_domains);
689
690 mutex_unlock(&power_domains->lock);
691
692 if (old_work_wakeref)
693 intel_runtime_pm_put_raw(rpm, old_work_wakeref);
694 if (new_work_wakeref)
695 intel_runtime_pm_put_raw(rpm, new_work_wakeref);
696}
697
698/**
699 * intel_display_power_put_async - release a power domain reference asynchronously
700 * @i915: i915 device instance
701 * @domain: power domain to reference
702 * @wakeref: wakeref acquired for the reference that is being released
703 *
704 * This function drops the power domain reference obtained by
705 * intel_display_power_get*() and schedules a work to power down the
706 * corresponding hardware block if this is the last reference.
707 */
708void __intel_display_power_put_async(struct drm_i915_private *i915,
709 enum intel_display_power_domain domain,
710 intel_wakeref_t wakeref)
711{
712 struct i915_power_domains *power_domains = &i915->display.power.domains;
713 struct intel_runtime_pm *rpm = &i915->runtime_pm;
714 intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm);
715
716 mutex_lock(&power_domains->lock);
717
718 if (power_domains->domain_use_count[domain] > 1) {
719 __intel_display_power_put_domain(i915, domain);
720
721 goto out_verify;
722 }
723
724 drm_WARN_ON(&i915->drm, power_domains->domain_use_count[domain] != 1);
725
726 /* Let a pending work requeue itself or queue a new one. */
727 if (power_domains->async_put_wakeref) {
728 set_bit(domain, power_domains->async_put_domains[1].bits);
729 } else {
730 set_bit(domain, power_domains->async_put_domains[0].bits);
731 queue_async_put_domains_work(power_domains,
732 fetch_and_zero(&work_wakeref));
733 }
734
735out_verify:
736 verify_async_put_domains_state(power_domains);
737
738 mutex_unlock(&power_domains->lock);
739
740 if (work_wakeref)
741 intel_runtime_pm_put_raw(rpm, work_wakeref);
742
743 intel_runtime_pm_put(rpm, wakeref);
744}
745
746/**
747 * intel_display_power_flush_work - flushes the async display power disabling work
748 * @i915: i915 device instance
749 *
750 * Flushes any pending work that was scheduled by a preceding
751 * intel_display_power_put_async() call, completing the disabling of the
752 * corresponding power domains.
753 *
754 * Note that the work handler function may still be running after this
755 * function returns; to ensure that the work handler isn't running use
756 * intel_display_power_flush_work_sync() instead.
757 */
758void intel_display_power_flush_work(struct drm_i915_private *i915)
759{
760 struct i915_power_domains *power_domains = &i915->display.power.domains;
761 struct intel_power_domain_mask async_put_mask;
762 intel_wakeref_t work_wakeref;
763
764 mutex_lock(&power_domains->lock);
765
766 work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref);
767 if (!work_wakeref)
768 goto out_verify;
769
770 async_put_domains_mask(power_domains, &async_put_mask);
771 release_async_put_domains(power_domains, &async_put_mask);
772 cancel_delayed_work(&power_domains->async_put_work);
773
774out_verify:
775 verify_async_put_domains_state(power_domains);
776
777 mutex_unlock(&power_domains->lock);
778
779 if (work_wakeref)
780 intel_runtime_pm_put_raw(&i915->runtime_pm, work_wakeref);
781}
782
783/**
784 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work
785 * @i915: i915 device instance
786 *
787 * Like intel_display_power_flush_work(), but also ensure that the work
788 * handler function is not running any more when this function returns.
789 */
790static void
791intel_display_power_flush_work_sync(struct drm_i915_private *i915)
792{
793 struct i915_power_domains *power_domains = &i915->display.power.domains;
794
795 intel_display_power_flush_work(i915);
796 cancel_delayed_work_sync(&power_domains->async_put_work);
797
798 verify_async_put_domains_state(power_domains);
799
800 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
801}
802
803#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
804/**
805 * intel_display_power_put - release a power domain reference
806 * @dev_priv: i915 device instance
807 * @domain: power domain to reference
808 * @wakeref: wakeref acquired for the reference that is being released
809 *
810 * This function drops the power domain reference obtained by
811 * intel_display_power_get() and might power down the corresponding hardware
812 * block right away if this is the last reference.
813 */
814void intel_display_power_put(struct drm_i915_private *dev_priv,
815 enum intel_display_power_domain domain,
816 intel_wakeref_t wakeref)
817{
818 __intel_display_power_put(dev_priv, domain);
819 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
820}
821#else
822/**
823 * intel_display_power_put_unchecked - release an unchecked power domain reference
824 * @dev_priv: i915 device instance
825 * @domain: power domain to reference
826 *
827 * This function drops the power domain reference obtained by
828 * intel_display_power_get() and might power down the corresponding hardware
829 * block right away if this is the last reference.
830 *
831 * This function is only for the power domain code's internal use to suppress wakeref
832 * tracking when the correspondig debug kconfig option is disabled, should not
833 * be used otherwise.
834 */
835void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
836 enum intel_display_power_domain domain)
837{
838 __intel_display_power_put(dev_priv, domain);
839 intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm);
840}
841#endif
842
843void
844intel_display_power_get_in_set(struct drm_i915_private *i915,
845 struct intel_display_power_domain_set *power_domain_set,
846 enum intel_display_power_domain domain)
847{
848 intel_wakeref_t __maybe_unused wf;
849
850 drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
851
852 wf = intel_display_power_get(i915, domain);
853#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
854 power_domain_set->wakerefs[domain] = wf;
855#endif
856 set_bit(domain, power_domain_set->mask.bits);
857}
858
859bool
860intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
861 struct intel_display_power_domain_set *power_domain_set,
862 enum intel_display_power_domain domain)
863{
864 intel_wakeref_t wf;
865
866 drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
867
868 wf = intel_display_power_get_if_enabled(i915, domain);
869 if (!wf)
870 return false;
871
872#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
873 power_domain_set->wakerefs[domain] = wf;
874#endif
875 set_bit(domain, power_domain_set->mask.bits);
876
877 return true;
878}
879
880void
881intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
882 struct intel_display_power_domain_set *power_domain_set,
883 struct intel_power_domain_mask *mask)
884{
885 enum intel_display_power_domain domain;
886
887 drm_WARN_ON(&i915->drm,
888 !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
889
890 for_each_power_domain(domain, mask) {
891 intel_wakeref_t __maybe_unused wf = -1;
892
893#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
894 wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
895#endif
896 intel_display_power_put(i915, domain, wf);
897 clear_bit(domain, power_domain_set->mask.bits);
898 }
899}
900
901static int
902sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
903 int disable_power_well)
904{
905 if (disable_power_well >= 0)
906 return !!disable_power_well;
907
908 return 1;
909}
910
911static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
912 int enable_dc)
913{
914 u32 mask;
915 int requested_dc;
916 int max_dc;
917
918 if (!HAS_DISPLAY(dev_priv))
919 return 0;
920
921 if (IS_DG2(dev_priv))
922 max_dc = 1;
923 else if (IS_DG1(dev_priv))
924 max_dc = 3;
925 else if (DISPLAY_VER(dev_priv) >= 12)
926 max_dc = 4;
927 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
928 max_dc = 1;
929 else if (DISPLAY_VER(dev_priv) >= 9)
930 max_dc = 2;
931 else
932 max_dc = 0;
933
934 /*
935 * DC9 has a separate HW flow from the rest of the DC states,
936 * not depending on the DMC firmware. It's needed by system
937 * suspend/resume, so allow it unconditionally.
938 */
939 mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
940 DISPLAY_VER(dev_priv) >= 11 ?
941 DC_STATE_EN_DC9 : 0;
942
943 if (!dev_priv->params.disable_power_well)
944 max_dc = 0;
945
946 if (enable_dc >= 0 && enable_dc <= max_dc) {
947 requested_dc = enable_dc;
948 } else if (enable_dc == -1) {
949 requested_dc = max_dc;
950 } else if (enable_dc > max_dc && enable_dc <= 4) {
951 drm_dbg_kms(&dev_priv->drm,
952 "Adjusting requested max DC state (%d->%d)\n",
953 enable_dc, max_dc);
954 requested_dc = max_dc;
955 } else {
956 drm_err(&dev_priv->drm,
957 "Unexpected value for enable_dc (%d)\n", enable_dc);
958 requested_dc = max_dc;
959 }
960
961 switch (requested_dc) {
962 case 4:
963 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
964 break;
965 case 3:
966 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
967 break;
968 case 2:
969 mask |= DC_STATE_EN_UPTO_DC6;
970 break;
971 case 1:
972 mask |= DC_STATE_EN_UPTO_DC5;
973 break;
974 }
975
976 drm_dbg_kms(&dev_priv->drm, "Allowed DC state mask %02x\n", mask);
977
978 return mask;
979}
980
981/**
982 * intel_power_domains_init - initializes the power domain structures
983 * @dev_priv: i915 device instance
984 *
985 * Initializes the power domain structures for @dev_priv depending upon the
986 * supported platform.
987 */
988int intel_power_domains_init(struct drm_i915_private *dev_priv)
989{
990 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
991
992 dev_priv->params.disable_power_well =
993 sanitize_disable_power_well_option(dev_priv,
994 dev_priv->params.disable_power_well);
995 dev_priv->display.dmc.allowed_dc_mask =
996 get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
997
998 dev_priv->display.dmc.target_dc_state =
999 sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
1000
1001 mutex_init(&power_domains->lock);
1002
1003 INIT_DELAYED_WORK(&power_domains->async_put_work,
1004 intel_display_power_put_async_work);
1005
1006 return intel_display_power_map_init(power_domains);
1007}
1008
1009/**
1010 * intel_power_domains_cleanup - clean up power domains resources
1011 * @dev_priv: i915 device instance
1012 *
1013 * Release any resources acquired by intel_power_domains_init()
1014 */
1015void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
1016{
1017 intel_display_power_map_cleanup(&dev_priv->display.power.domains);
1018}
1019
1020static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
1021{
1022 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1023 struct i915_power_well *power_well;
1024
1025 mutex_lock(&power_domains->lock);
1026 for_each_power_well(dev_priv, power_well)
1027 intel_power_well_sync_hw(dev_priv, power_well);
1028 mutex_unlock(&power_domains->lock);
1029}
1030
1031static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
1032 enum dbuf_slice slice, bool enable)
1033{
1034 i915_reg_t reg = DBUF_CTL_S(slice);
1035 bool state;
1036
1037 intel_de_rmw(dev_priv, reg, DBUF_POWER_REQUEST,
1038 enable ? DBUF_POWER_REQUEST : 0);
1039 intel_de_posting_read(dev_priv, reg);
1040 udelay(10);
1041
1042 state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE;
1043 drm_WARN(&dev_priv->drm, enable != state,
1044 "DBuf slice %d power %s timeout!\n",
1045 slice, str_enable_disable(enable));
1046}
1047
1048void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
1049 u8 req_slices)
1050{
1051 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1052 u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask;
1053 enum dbuf_slice slice;
1054
1055 drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
1056 "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n",
1057 req_slices, slice_mask);
1058
1059 drm_dbg_kms(&dev_priv->drm, "Updating dbuf slices to 0x%x\n",
1060 req_slices);
1061
1062 /*
1063 * Might be running this in parallel to gen9_dc_off_power_well_enable
1064 * being called from intel_dp_detect for instance,
1065 * which causes assertion triggered by race condition,
1066 * as gen9_assert_dbuf_enabled might preempt this when registers
1067 * were already updated, while dev_priv was not.
1068 */
1069 mutex_lock(&power_domains->lock);
1070
1071 for_each_dbuf_slice(dev_priv, slice)
1072 gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));
1073
1074 dev_priv->display.dbuf.enabled_slices = req_slices;
1075
1076 mutex_unlock(&power_domains->lock);
1077}
1078
1079static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
1080{
1081 dev_priv->display.dbuf.enabled_slices =
1082 intel_enabled_dbuf_slices_mask(dev_priv);
1083
1084 /*
1085 * Just power up at least 1 slice, we will
1086 * figure out later which slices we have and what we need.
1087 */
1088 gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) |
1089 dev_priv->display.dbuf.enabled_slices);
1090}
1091
1092static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
1093{
1094 gen9_dbuf_slices_update(dev_priv, 0);
1095}
1096
1097static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
1098{
1099 enum dbuf_slice slice;
1100
1101 if (IS_ALDERLAKE_P(dev_priv))
1102 return;
1103
1104 for_each_dbuf_slice(dev_priv, slice)
1105 intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
1106 DBUF_TRACKER_STATE_SERVICE_MASK,
1107 DBUF_TRACKER_STATE_SERVICE(8));
1108}
1109
1110static void icl_mbus_init(struct drm_i915_private *dev_priv)
1111{
1112 unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask;
1113 u32 mask, val, i;
1114
1115 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
1116 return;
1117
1118 mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
1119 MBUS_ABOX_BT_CREDIT_POOL2_MASK |
1120 MBUS_ABOX_B_CREDIT_MASK |
1121 MBUS_ABOX_BW_CREDIT_MASK;
1122 val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
1123 MBUS_ABOX_BT_CREDIT_POOL2(16) |
1124 MBUS_ABOX_B_CREDIT(1) |
1125 MBUS_ABOX_BW_CREDIT(1);
1126
1127 /*
1128 * gen12 platforms that use abox1 and abox2 for pixel data reads still
1129 * expect us to program the abox_ctl0 register as well, even though
1130 * we don't have to program other instance-0 registers like BW_BUDDY.
1131 */
1132 if (DISPLAY_VER(dev_priv) == 12)
1133 abox_regs |= BIT(0);
1134
1135 for_each_set_bit(i, &abox_regs, sizeof(abox_regs))
1136 intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val);
1137}
1138
1139static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
1140{
1141 u32 val = intel_de_read(dev_priv, LCPLL_CTL);
1142
1143 /*
1144 * The LCPLL register should be turned on by the BIOS. For now
1145 * let's just check its state and print errors in case
1146 * something is wrong. Don't even try to turn it on.
1147 */
1148
1149 if (val & LCPLL_CD_SOURCE_FCLK)
1150 drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n");
1151
1152 if (val & LCPLL_PLL_DISABLE)
1153 drm_err(&dev_priv->drm, "LCPLL is disabled\n");
1154
1155 if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC)
1156 drm_err(&dev_priv->drm, "LCPLL not using non-SSC reference\n");
1157}
1158
1159static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
1160{
1161 struct intel_crtc *crtc;
1162
1163 for_each_intel_crtc(&dev_priv->drm, crtc)
1164 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
1165 pipe_name(crtc->pipe));
1166
1167 I915_STATE_WARN(intel_de_read(dev_priv, HSW_PWR_WELL_CTL2),
1168 "Display power well on\n");
1169 I915_STATE_WARN(intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE,
1170 "SPLL enabled\n");
1171 I915_STATE_WARN(intel_de_read(dev_priv, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
1172 "WRPLL1 enabled\n");
1173 I915_STATE_WARN(intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
1174 "WRPLL2 enabled\n");
1175 I915_STATE_WARN(intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON,
1176 "Panel power on\n");
1177 I915_STATE_WARN(intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
1178 "CPU PWM1 enabled\n");
1179 if (IS_HASWELL(dev_priv))
1180 I915_STATE_WARN(intel_de_read(dev_priv, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
1181 "CPU PWM2 enabled\n");
1182 I915_STATE_WARN(intel_de_read(dev_priv, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
1183 "PCH PWM1 enabled\n");
1184 I915_STATE_WARN(intel_de_read(dev_priv, UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
1185 "Utility pin enabled\n");
1186 I915_STATE_WARN(intel_de_read(dev_priv, PCH_GTC_CTL) & PCH_GTC_ENABLE,
1187 "PCH GTC enabled\n");
1188
1189 /*
1190 * In theory we can still leave IRQs enabled, as long as only the HPD
1191 * interrupts remain enabled. We used to check for that, but since it's
1192 * gen-specific and since we only disable LCPLL after we fully disable
1193 * the interrupts, the check below should be enough.
1194 */
1195 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
1196}
1197
1198static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
1199{
1200 if (IS_HASWELL(dev_priv))
1201 return intel_de_read(dev_priv, D_COMP_HSW);
1202 else
1203 return intel_de_read(dev_priv, D_COMP_BDW);
1204}
1205
1206static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
1207{
1208 if (IS_HASWELL(dev_priv)) {
1209 if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val))
1210 drm_dbg_kms(&dev_priv->drm,
1211 "Failed to write to D_COMP\n");
1212 } else {
1213 intel_de_write(dev_priv, D_COMP_BDW, val);
1214 intel_de_posting_read(dev_priv, D_COMP_BDW);
1215 }
1216}
1217
1218/*
1219 * This function implements pieces of two sequences from BSpec:
1220 * - Sequence for display software to disable LCPLL
1221 * - Sequence for display software to allow package C8+
1222 * The steps implemented here are just the steps that actually touch the LCPLL
1223 * register. Callers should take care of disabling all the display engine
1224 * functions, doing the mode unset, fixing interrupts, etc.
1225 */
1226static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
1227 bool switch_to_fclk, bool allow_power_down)
1228{
1229 u32 val;
1230
1231 assert_can_disable_lcpll(dev_priv);
1232
1233 val = intel_de_read(dev_priv, LCPLL_CTL);
1234
1235 if (switch_to_fclk) {
1236 val |= LCPLL_CD_SOURCE_FCLK;
1237 intel_de_write(dev_priv, LCPLL_CTL, val);
1238
1239 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
1240 LCPLL_CD_SOURCE_FCLK_DONE, 1))
1241 drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
1242
1243 val = intel_de_read(dev_priv, LCPLL_CTL);
1244 }
1245
1246 val |= LCPLL_PLL_DISABLE;
1247 intel_de_write(dev_priv, LCPLL_CTL, val);
1248 intel_de_posting_read(dev_priv, LCPLL_CTL);
1249
1250 if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
1251 drm_err(&dev_priv->drm, "LCPLL still locked\n");
1252
1253 val = hsw_read_dcomp(dev_priv);
1254 val |= D_COMP_COMP_DISABLE;
1255 hsw_write_dcomp(dev_priv, val);
1256 ndelay(100);
1257
1258 if (wait_for((hsw_read_dcomp(dev_priv) &
1259 D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
1260 drm_err(&dev_priv->drm, "D_COMP RCOMP still in progress\n");
1261
1262 if (allow_power_down) {
1263 val = intel_de_read(dev_priv, LCPLL_CTL);
1264 val |= LCPLL_POWER_DOWN_ALLOW;
1265 intel_de_write(dev_priv, LCPLL_CTL, val);
1266 intel_de_posting_read(dev_priv, LCPLL_CTL);
1267 }
1268}
1269
1270/*
1271 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
1272 * source.
1273 */
1274static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
1275{
1276 u32 val;
1277
1278 val = intel_de_read(dev_priv, LCPLL_CTL);
1279
1280 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
1281 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
1282 return;
1283
1284 /*
1285 * Make sure we're not on PC8 state before disabling PC8, otherwise
1286 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
1287 */
1288 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
1289
1290 if (val & LCPLL_POWER_DOWN_ALLOW) {
1291 val &= ~LCPLL_POWER_DOWN_ALLOW;
1292 intel_de_write(dev_priv, LCPLL_CTL, val);
1293 intel_de_posting_read(dev_priv, LCPLL_CTL);
1294 }
1295
1296 val = hsw_read_dcomp(dev_priv);
1297 val |= D_COMP_COMP_FORCE;
1298 val &= ~D_COMP_COMP_DISABLE;
1299 hsw_write_dcomp(dev_priv, val);
1300
1301 val = intel_de_read(dev_priv, LCPLL_CTL);
1302 val &= ~LCPLL_PLL_DISABLE;
1303 intel_de_write(dev_priv, LCPLL_CTL, val);
1304
1305 if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
1306 drm_err(&dev_priv->drm, "LCPLL not locked yet\n");
1307
1308 if (val & LCPLL_CD_SOURCE_FCLK) {
1309 val = intel_de_read(dev_priv, LCPLL_CTL);
1310 val &= ~LCPLL_CD_SOURCE_FCLK;
1311 intel_de_write(dev_priv, LCPLL_CTL, val);
1312
1313 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
1314 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
1315 drm_err(&dev_priv->drm,
1316 "Switching back to LCPLL failed\n");
1317 }
1318
1319 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
1320
1321 intel_update_cdclk(dev_priv);
1322 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
1323}
1324
1325/*
1326 * Package states C8 and deeper are really deep PC states that can only be
1327 * reached when all the devices on the system allow it, so even if the graphics
1328 * device allows PC8+, it doesn't mean the system will actually get to these
1329 * states. Our driver only allows PC8+ when going into runtime PM.
1330 *
1331 * The requirements for PC8+ are that all the outputs are disabled, the power
1332 * well is disabled and most interrupts are disabled, and these are also
1333 * requirements for runtime PM. When these conditions are met, we manually do
1334 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
1335 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
1336 * hang the machine.
1337 *
1338 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1339 * the state of some registers, so when we come back from PC8+ we need to
1340 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1341 * need to take care of the registers kept by RC6. Notice that this happens even
1342 * if we don't put the device in PCI D3 state (which is what currently happens
1343 * because of the runtime PM support).
1344 *
1345 * For more, read "Display Sequences for Package C8" on the hardware
1346 * documentation.
1347 */
1348static void hsw_enable_pc8(struct drm_i915_private *dev_priv)
1349{
1350 u32 val;
1351
1352 drm_dbg_kms(&dev_priv->drm, "Enabling package C8+\n");
1353
1354 if (HAS_PCH_LPT_LP(dev_priv)) {
1355 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
1356 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
1357 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
1358 }
1359
1360 lpt_disable_clkout_dp(dev_priv);
1361 hsw_disable_lcpll(dev_priv, true, true);
1362}
1363
1364static void hsw_disable_pc8(struct drm_i915_private *dev_priv)
1365{
1366 u32 val;
1367
1368 drm_dbg_kms(&dev_priv->drm, "Disabling package C8+\n");
1369
1370 hsw_restore_lcpll(dev_priv);
1371 intel_init_pch_refclk(dev_priv);
1372
1373 if (HAS_PCH_LPT_LP(dev_priv)) {
1374 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
1375 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
1376 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
1377 }
1378}
1379
1380static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
1381 bool enable)
1382{
1383 i915_reg_t reg;
1384 u32 reset_bits, val;
1385
1386 if (IS_IVYBRIDGE(dev_priv)) {
1387 reg = GEN7_MSG_CTL;
1388 reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;
1389 } else {
1390 reg = HSW_NDE_RSTWRN_OPT;
1391 reset_bits = RESET_PCH_HANDSHAKE_ENABLE;
1392 }
1393
1394 if (DISPLAY_VER(dev_priv) >= 14)
1395 reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN;
1396
1397 val = intel_de_read(dev_priv, reg);
1398
1399 if (enable)
1400 val |= reset_bits;
1401 else
1402 val &= ~reset_bits;
1403
1404 intel_de_write(dev_priv, reg, val);
1405}
1406
1407static void skl_display_core_init(struct drm_i915_private *dev_priv,
1408 bool resume)
1409{
1410 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1411 struct i915_power_well *well;
1412
1413 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1414
1415 /* enable PCH reset handshake */
1416 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
1417
1418 if (!HAS_DISPLAY(dev_priv))
1419 return;
1420
1421 /* enable PG1 and Misc I/O */
1422 mutex_lock(&power_domains->lock);
1423
1424 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1425 intel_power_well_enable(dev_priv, well);
1426
1427 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1428 intel_power_well_enable(dev_priv, well);
1429
1430 mutex_unlock(&power_domains->lock);
1431
1432 intel_cdclk_init_hw(dev_priv);
1433
1434 gen9_dbuf_enable(dev_priv);
1435
1436 if (resume)
1437 intel_dmc_load_program(dev_priv);
1438}
1439
1440static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
1441{
1442 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1443 struct i915_power_well *well;
1444
1445 if (!HAS_DISPLAY(dev_priv))
1446 return;
1447
1448 gen9_disable_dc_states(dev_priv);
1449 /* TODO: disable DMC program */
1450
1451 gen9_dbuf_disable(dev_priv);
1452
1453 intel_cdclk_uninit_hw(dev_priv);
1454
1455 /* The spec doesn't call for removing the reset handshake flag */
1456 /* disable PG1 and Misc I/O */
1457
1458 mutex_lock(&power_domains->lock);
1459
1460 /*
1461 * BSpec says to keep the MISC IO power well enabled here, only
1462 * remove our request for power well 1.
1463 * Note that even though the driver's request is removed power well 1
1464 * may stay enabled after this due to DMC's own request on it.
1465 */
1466 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1467 intel_power_well_disable(dev_priv, well);
1468
1469 mutex_unlock(&power_domains->lock);
1470
1471 usleep_range(10, 30); /* 10 us delay per Bspec */
1472}
1473
1474static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume)
1475{
1476 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1477 struct i915_power_well *well;
1478
1479 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1480
1481 /*
1482 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
1483 * or else the reset will hang because there is no PCH to respond.
1484 * Move the handshake programming to initialization sequence.
1485 * Previously was left up to BIOS.
1486 */
1487 intel_pch_reset_handshake(dev_priv, false);
1488
1489 if (!HAS_DISPLAY(dev_priv))
1490 return;
1491
1492 /* Enable PG1 */
1493 mutex_lock(&power_domains->lock);
1494
1495 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1496 intel_power_well_enable(dev_priv, well);
1497
1498 mutex_unlock(&power_domains->lock);
1499
1500 intel_cdclk_init_hw(dev_priv);
1501
1502 gen9_dbuf_enable(dev_priv);
1503
1504 if (resume)
1505 intel_dmc_load_program(dev_priv);
1506}
1507
1508static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
1509{
1510 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1511 struct i915_power_well *well;
1512
1513 if (!HAS_DISPLAY(dev_priv))
1514 return;
1515
1516 gen9_disable_dc_states(dev_priv);
1517 /* TODO: disable DMC program */
1518
1519 gen9_dbuf_disable(dev_priv);
1520
1521 intel_cdclk_uninit_hw(dev_priv);
1522
1523 /* The spec doesn't call for removing the reset handshake flag */
1524
1525 /*
1526 * Disable PW1 (PG1).
1527 * Note that even though the driver's request is removed power well 1
1528 * may stay enabled after this due to DMC's own request on it.
1529 */
1530 mutex_lock(&power_domains->lock);
1531
1532 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1533 intel_power_well_disable(dev_priv, well);
1534
1535 mutex_unlock(&power_domains->lock);
1536
1537 usleep_range(10, 30); /* 10 us delay per Bspec */
1538}
1539
1540struct buddy_page_mask {
1541 u32 page_mask;
1542 u8 type;
1543 u8 num_channels;
1544};
1545
1546static const struct buddy_page_mask tgl_buddy_page_masks[] = {
1547 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF },
1548 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0xF },
1549 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C },
1550 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1C },
1551 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F },
1552 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x1E },
1553 { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 },
1554 { .num_channels = 4, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x38 },
1555 {}
1556};
1557
1558static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = {
1559 { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 },
1560 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0x1 },
1561 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0x1 },
1562 { .num_channels = 1, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1 },
1563 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 },
1564 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x3 },
1565 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x3 },
1566 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x3 },
1567 {}
1568};
1569
1570static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
1571{
1572 enum intel_dram_type type = dev_priv->dram_info.type;
1573 u8 num_channels = dev_priv->dram_info.num_channels;
1574 const struct buddy_page_mask *table;
1575 unsigned long abox_mask = INTEL_INFO(dev_priv)->display.abox_mask;
1576 int config, i;
1577
1578 /* BW_BUDDY registers are not used on dgpu's beyond DG1 */
1579 if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv))
1580 return;
1581
1582 if (IS_ALDERLAKE_S(dev_priv) ||
1583 IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
1584 IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
1585 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
1586 /* Wa_1409767108:tgl,dg1,adl-s */
1587 table = wa_1409767108_buddy_page_masks;
1588 else
1589 table = tgl_buddy_page_masks;
1590
1591 for (config = 0; table[config].page_mask != 0; config++)
1592 if (table[config].num_channels == num_channels &&
1593 table[config].type == type)
1594 break;
1595
1596 if (table[config].page_mask == 0) {
1597 drm_dbg(&dev_priv->drm,
1598 "Unknown memory configuration; disabling address buddy logic.\n");
1599 for_each_set_bit(i, &abox_mask, sizeof(abox_mask))
1600 intel_de_write(dev_priv, BW_BUDDY_CTL(i),
1601 BW_BUDDY_DISABLE);
1602 } else {
1603 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) {
1604 intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
1605 table[config].page_mask);
1606
1607 /* Wa_22010178259:tgl,dg1,rkl,adl-s */
1608 if (DISPLAY_VER(dev_priv) == 12)
1609 intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
1610 BW_BUDDY_TLB_REQ_TIMER_MASK,
1611 BW_BUDDY_TLB_REQ_TIMER(0x8));
1612 }
1613 }
1614}
1615
1616static void icl_display_core_init(struct drm_i915_private *dev_priv,
1617 bool resume)
1618{
1619 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1620 struct i915_power_well *well;
1621 u32 val;
1622
1623 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1624
1625 /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
1626 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
1627 INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
1628 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
1629 PCH_DPMGUNIT_CLOCK_GATE_DISABLE);
1630
1631 /* 1. Enable PCH reset handshake. */
1632 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
1633
1634 if (!HAS_DISPLAY(dev_priv))
1635 return;
1636
1637 /* 2. Initialize all combo phys */
1638 intel_combo_phy_init(dev_priv);
1639
1640 /*
1641 * 3. Enable Power Well 1 (PG1).
1642 * The AUX IO power wells will be enabled on demand.
1643 */
1644 mutex_lock(&power_domains->lock);
1645 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1646 intel_power_well_enable(dev_priv, well);
1647 mutex_unlock(&power_domains->lock);
1648
1649 /* 4. Enable CDCLK. */
1650 intel_cdclk_init_hw(dev_priv);
1651
1652 if (DISPLAY_VER(dev_priv) >= 12)
1653 gen12_dbuf_slices_config(dev_priv);
1654
1655 /* 5. Enable DBUF. */
1656 gen9_dbuf_enable(dev_priv);
1657
1658 /* 6. Setup MBUS. */
1659 icl_mbus_init(dev_priv);
1660
1661 /* 7. Program arbiter BW_BUDDY registers */
1662 if (DISPLAY_VER(dev_priv) >= 12)
1663 tgl_bw_buddy_init(dev_priv);
1664
1665 /* 8. Ensure PHYs have completed calibration and adaptation */
1666 if (IS_DG2(dev_priv))
1667 intel_snps_phy_wait_for_calibration(dev_priv);
1668
1669 if (resume)
1670 intel_dmc_load_program(dev_priv);
1671
1672 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p */
1673 if (DISPLAY_VER(dev_priv) >= 12) {
1674 val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
1675 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
1676 intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val);
1677 }
1678
1679 /* Wa_14011503030:xelpd */
1680 if (DISPLAY_VER(dev_priv) >= 13)
1681 intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
1682}
1683
1684static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
1685{
1686 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1687 struct i915_power_well *well;
1688
1689 if (!HAS_DISPLAY(dev_priv))
1690 return;
1691
1692 gen9_disable_dc_states(dev_priv);
1693 intel_dmc_disable_program(dev_priv);
1694
1695 /* 1. Disable all display engine functions -> aready done */
1696
1697 /* 2. Disable DBUF */
1698 gen9_dbuf_disable(dev_priv);
1699
1700 /* 3. Disable CD clock */
1701 intel_cdclk_uninit_hw(dev_priv);
1702
1703 /*
1704 * 4. Disable Power Well 1 (PG1).
1705 * The AUX IO power wells are toggled on demand, so they are already
1706 * disabled at this point.
1707 */
1708 mutex_lock(&power_domains->lock);
1709 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1710 intel_power_well_disable(dev_priv, well);
1711 mutex_unlock(&power_domains->lock);
1712
1713 /* 5. */
1714 intel_combo_phy_uninit(dev_priv);
1715}
1716
1717static void chv_phy_control_init(struct drm_i915_private *dev_priv)
1718{
1719 struct i915_power_well *cmn_bc =
1720 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1721 struct i915_power_well *cmn_d =
1722 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
1723
1724 /*
1725 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1726 * workaround never ever read DISPLAY_PHY_CONTROL, and
1727 * instead maintain a shadow copy ourselves. Use the actual
1728 * power well state and lane status to reconstruct the
1729 * expected initial value.
1730 */
1731 dev_priv->display.power.chv_phy_control =
1732 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
1733 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
1734 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
1735 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
1736 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
1737
1738 /*
1739 * If all lanes are disabled we leave the override disabled
1740 * with all power down bits cleared to match the state we
1741 * would use after disabling the port. Otherwise enable the
1742 * override and set the lane powerdown bits accding to the
1743 * current lane status.
1744 */
1745 if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
1746 u32 status = intel_de_read(dev_priv, DPLL(PIPE_A));
1747 unsigned int mask;
1748
1749 mask = status & DPLL_PORTB_READY_MASK;
1750 if (mask == 0xf)
1751 mask = 0x0;
1752 else
1753 dev_priv->display.power.chv_phy_control |=
1754 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
1755
1756 dev_priv->display.power.chv_phy_control |=
1757 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
1758
1759 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
1760 if (mask == 0xf)
1761 mask = 0x0;
1762 else
1763 dev_priv->display.power.chv_phy_control |=
1764 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
1765
1766 dev_priv->display.power.chv_phy_control |=
1767 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
1768
1769 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
1770
1771 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = false;
1772 } else {
1773 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true;
1774 }
1775
1776 if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
1777 u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS);
1778 unsigned int mask;
1779
1780 mask = status & DPLL_PORTD_READY_MASK;
1781
1782 if (mask == 0xf)
1783 mask = 0x0;
1784 else
1785 dev_priv->display.power.chv_phy_control |=
1786 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
1787
1788 dev_priv->display.power.chv_phy_control |=
1789 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
1790
1791 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
1792
1793 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = false;
1794 } else {
1795 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = true;
1796 }
1797
1798 drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n",
1799 dev_priv->display.power.chv_phy_control);
1800
1801 /* Defer application of initial phy_control to enabling the powerwell */
1802}
1803
1804static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1805{
1806 struct i915_power_well *cmn =
1807 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1808 struct i915_power_well *disp2d =
1809 lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);
1810
1811 /* If the display might be already active skip this */
1812 if (intel_power_well_is_enabled(dev_priv, cmn) &&
1813 intel_power_well_is_enabled(dev_priv, disp2d) &&
1814 intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST)
1815 return;
1816
1817 drm_dbg_kms(&dev_priv->drm, "toggling display PHY side reset\n");
1818
1819 /* cmnlane needs DPLL registers */
1820 intel_power_well_enable(dev_priv, disp2d);
1821
1822 /*
1823 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1824 * Need to assert and de-assert PHY SB reset by gating the
1825 * common lane power, then un-gating it.
1826 * Simply ungating isn't enough to reset the PHY enough to get
1827 * ports and lanes running.
1828 */
1829 intel_power_well_disable(dev_priv, cmn);
1830}
1831
1832static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0)
1833{
1834 bool ret;
1835
1836 vlv_punit_get(dev_priv);
1837 ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;
1838 vlv_punit_put(dev_priv);
1839
1840 return ret;
1841}
1842
1843static void assert_ved_power_gated(struct drm_i915_private *dev_priv)
1844{
1845 drm_WARN(&dev_priv->drm,
1846 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0),
1847 "VED not power gated\n");
1848}
1849
1850static void assert_isp_power_gated(struct drm_i915_private *dev_priv)
1851{
1852 static const struct pci_device_id isp_ids[] = {
1853 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)},
1854 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)},
1855 {}
1856 };
1857
1858 drm_WARN(&dev_priv->drm, !pci_dev_present(isp_ids) &&
1859 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0),
1860 "ISP not power gated\n");
1861}
1862
1863static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1864
1865/**
1866 * intel_power_domains_init_hw - initialize hardware power domain state
1867 * @i915: i915 device instance
1868 * @resume: Called from resume code paths or not
1869 *
1870 * This function initializes the hardware power domain state and enables all
1871 * power wells belonging to the INIT power domain. Power wells in other
1872 * domains (and not in the INIT domain) are referenced or disabled by
1873 * intel_modeset_readout_hw_state(). After that the reference count of each
1874 * power well must match its HW enabled state, see
1875 * intel_power_domains_verify_state().
1876 *
1877 * It will return with power domains disabled (to be enabled later by
1878 * intel_power_domains_enable()) and must be paired with
1879 * intel_power_domains_driver_remove().
1880 */
1881void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
1882{
1883 struct i915_power_domains *power_domains = &i915->display.power.domains;
1884
1885 power_domains->initializing = true;
1886
1887 if (DISPLAY_VER(i915) >= 11) {
1888 icl_display_core_init(i915, resume);
1889 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
1890 bxt_display_core_init(i915, resume);
1891 } else if (DISPLAY_VER(i915) == 9) {
1892 skl_display_core_init(i915, resume);
1893 } else if (IS_CHERRYVIEW(i915)) {
1894 mutex_lock(&power_domains->lock);
1895 chv_phy_control_init(i915);
1896 mutex_unlock(&power_domains->lock);
1897 assert_isp_power_gated(i915);
1898 } else if (IS_VALLEYVIEW(i915)) {
1899 mutex_lock(&power_domains->lock);
1900 vlv_cmnlane_wa(i915);
1901 mutex_unlock(&power_domains->lock);
1902 assert_ved_power_gated(i915);
1903 assert_isp_power_gated(i915);
1904 } else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) {
1905 hsw_assert_cdclk(i915);
1906 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
1907 } else if (IS_IVYBRIDGE(i915)) {
1908 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
1909 }
1910
1911 /*
1912 * Keep all power wells enabled for any dependent HW access during
1913 * initialization and to make sure we keep BIOS enabled display HW
1914 * resources powered until display HW readout is complete. We drop
1915 * this reference in intel_power_domains_enable().
1916 */
1917 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
1918 power_domains->init_wakeref =
1919 intel_display_power_get(i915, POWER_DOMAIN_INIT);
1920
1921 /* Disable power support if the user asked so. */
1922 if (!i915->params.disable_power_well) {
1923 drm_WARN_ON(&i915->drm, power_domains->disable_wakeref);
1924 i915->display.power.domains.disable_wakeref = intel_display_power_get(i915,
1925 POWER_DOMAIN_INIT);
1926 }
1927 intel_power_domains_sync_hw(i915);
1928
1929 power_domains->initializing = false;
1930}
1931
1932/**
1933 * intel_power_domains_driver_remove - deinitialize hw power domain state
1934 * @i915: i915 device instance
1935 *
1936 * De-initializes the display power domain HW state. It also ensures that the
1937 * device stays powered up so that the driver can be reloaded.
1938 *
1939 * It must be called with power domains already disabled (after a call to
1940 * intel_power_domains_disable()) and must be paired with
1941 * intel_power_domains_init_hw().
1942 */
1943void intel_power_domains_driver_remove(struct drm_i915_private *i915)
1944{
1945 intel_wakeref_t wakeref __maybe_unused =
1946 fetch_and_zero(&i915->display.power.domains.init_wakeref);
1947
1948 /* Remove the refcount we took to keep power well support disabled. */
1949 if (!i915->params.disable_power_well)
1950 intel_display_power_put(i915, POWER_DOMAIN_INIT,
1951 fetch_and_zero(&i915->display.power.domains.disable_wakeref));
1952
1953 intel_display_power_flush_work_sync(i915);
1954
1955 intel_power_domains_verify_state(i915);
1956
1957 /* Keep the power well enabled, but cancel its rpm wakeref. */
1958 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1959}
1960
1961/**
1962 * intel_power_domains_sanitize_state - sanitize power domains state
1963 * @i915: i915 device instance
1964 *
1965 * Sanitize the power domains state during driver loading and system resume.
1966 * The function will disable all display power wells that BIOS has enabled
1967 * without a user for it (any user for a power well has taken a reference
1968 * on it by the time this function is called, after the state of all the
1969 * pipe, encoder, etc. HW resources have been sanitized).
1970 */
1971void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
1972{
1973 struct i915_power_domains *power_domains = &i915->display.power.domains;
1974 struct i915_power_well *power_well;
1975
1976 mutex_lock(&power_domains->lock);
1977
1978 for_each_power_well_reverse(i915, power_well) {
1979 if (power_well->desc->always_on || power_well->count ||
1980 !intel_power_well_is_enabled(i915, power_well))
1981 continue;
1982
1983 drm_dbg_kms(&i915->drm,
1984 "BIOS left unused %s power well enabled, disabling it\n",
1985 intel_power_well_name(power_well));
1986 intel_power_well_disable(i915, power_well);
1987 }
1988
1989 mutex_unlock(&power_domains->lock);
1990}
1991
1992/**
1993 * intel_power_domains_enable - enable toggling of display power wells
1994 * @i915: i915 device instance
1995 *
1996 * Enable the ondemand enabling/disabling of the display power wells. Note that
1997 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled
1998 * only at specific points of the display modeset sequence, thus they are not
1999 * affected by the intel_power_domains_enable()/disable() calls. The purpose
2000 * of these function is to keep the rest of power wells enabled until the end
2001 * of display HW readout (which will acquire the power references reflecting
2002 * the current HW state).
2003 */
2004void intel_power_domains_enable(struct drm_i915_private *i915)
2005{
2006 intel_wakeref_t wakeref __maybe_unused =
2007 fetch_and_zero(&i915->display.power.domains.init_wakeref);
2008
2009 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
2010 intel_power_domains_verify_state(i915);
2011}
2012
2013/**
2014 * intel_power_domains_disable - disable toggling of display power wells
2015 * @i915: i915 device instance
2016 *
2017 * Disable the ondemand enabling/disabling of the display power wells. See
2018 * intel_power_domains_enable() for which power wells this call controls.
2019 */
2020void intel_power_domains_disable(struct drm_i915_private *i915)
2021{
2022 struct i915_power_domains *power_domains = &i915->display.power.domains;
2023
2024 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
2025 power_domains->init_wakeref =
2026 intel_display_power_get(i915, POWER_DOMAIN_INIT);
2027
2028 intel_power_domains_verify_state(i915);
2029}
2030
2031/**
2032 * intel_power_domains_suspend - suspend power domain state
2033 * @i915: i915 device instance
2034 * @suspend_mode: specifies the target suspend state (idle, mem, hibernation)
2035 *
2036 * This function prepares the hardware power domain state before entering
2037 * system suspend.
2038 *
2039 * It must be called with power domains already disabled (after a call to
2040 * intel_power_domains_disable()) and paired with intel_power_domains_resume().
2041 */
2042void intel_power_domains_suspend(struct drm_i915_private *i915,
2043 enum i915_drm_suspend_mode suspend_mode)
2044{
2045 struct i915_power_domains *power_domains = &i915->display.power.domains;
2046 intel_wakeref_t wakeref __maybe_unused =
2047 fetch_and_zero(&power_domains->init_wakeref);
2048
2049 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
2050
2051 /*
2052 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9
2053 * support don't manually deinit the power domains. This also means the
2054 * DMC firmware will stay active, it will power down any HW
2055 * resources as required and also enable deeper system power states
2056 * that would be blocked if the firmware was inactive.
2057 */
2058 if (!(i915->display.dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
2059 suspend_mode == I915_DRM_SUSPEND_IDLE &&
2060 intel_dmc_has_payload(i915)) {
2061 intel_display_power_flush_work(i915);
2062 intel_power_domains_verify_state(i915);
2063 return;
2064 }
2065
2066 /*
2067 * Even if power well support was disabled we still want to disable
2068 * power wells if power domains must be deinitialized for suspend.
2069 */
2070 if (!i915->params.disable_power_well)
2071 intel_display_power_put(i915, POWER_DOMAIN_INIT,
2072 fetch_and_zero(&i915->display.power.domains.disable_wakeref));
2073
2074 intel_display_power_flush_work(i915);
2075 intel_power_domains_verify_state(i915);
2076
2077 if (DISPLAY_VER(i915) >= 11)
2078 icl_display_core_uninit(i915);
2079 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
2080 bxt_display_core_uninit(i915);
2081 else if (DISPLAY_VER(i915) == 9)
2082 skl_display_core_uninit(i915);
2083
2084 power_domains->display_core_suspended = true;
2085}
2086
2087/**
2088 * intel_power_domains_resume - resume power domain state
2089 * @i915: i915 device instance
2090 *
2091 * This function resume the hardware power domain state during system resume.
2092 *
2093 * It will return with power domain support disabled (to be enabled later by
2094 * intel_power_domains_enable()) and must be paired with
2095 * intel_power_domains_suspend().
2096 */
2097void intel_power_domains_resume(struct drm_i915_private *i915)
2098{
2099 struct i915_power_domains *power_domains = &i915->display.power.domains;
2100
2101 if (power_domains->display_core_suspended) {
2102 intel_power_domains_init_hw(i915, true);
2103 power_domains->display_core_suspended = false;
2104 } else {
2105 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
2106 power_domains->init_wakeref =
2107 intel_display_power_get(i915, POWER_DOMAIN_INIT);
2108 }
2109
2110 intel_power_domains_verify_state(i915);
2111}
2112
2113#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2114
2115static void intel_power_domains_dump_info(struct drm_i915_private *i915)
2116{
2117 struct i915_power_domains *power_domains = &i915->display.power.domains;
2118 struct i915_power_well *power_well;
2119
2120 for_each_power_well(i915, power_well) {
2121 enum intel_display_power_domain domain;
2122
2123 drm_dbg(&i915->drm, "%-25s %d\n",
2124 intel_power_well_name(power_well), intel_power_well_refcount(power_well));
2125
2126 for_each_power_domain(domain, intel_power_well_domains(power_well))
2127 drm_dbg(&i915->drm, " %-23s %d\n",
2128 intel_display_power_domain_str(domain),
2129 power_domains->domain_use_count[domain]);
2130 }
2131}
2132
2133/**
2134 * intel_power_domains_verify_state - verify the HW/SW state for all power wells
2135 * @i915: i915 device instance
2136 *
2137 * Verify if the reference count of each power well matches its HW enabled
2138 * state and the total refcount of the domains it belongs to. This must be
2139 * called after modeset HW state sanitization, which is responsible for
2140 * acquiring reference counts for any power wells in use and disabling the
2141 * ones left on by BIOS but not required by any active output.
2142 */
2143static void intel_power_domains_verify_state(struct drm_i915_private *i915)
2144{
2145 struct i915_power_domains *power_domains = &i915->display.power.domains;
2146 struct i915_power_well *power_well;
2147 bool dump_domain_info;
2148
2149 mutex_lock(&power_domains->lock);
2150
2151 verify_async_put_domains_state(power_domains);
2152
2153 dump_domain_info = false;
2154 for_each_power_well(i915, power_well) {
2155 enum intel_display_power_domain domain;
2156 int domains_count;
2157 bool enabled;
2158
2159 enabled = intel_power_well_is_enabled(i915, power_well);
2160 if ((intel_power_well_refcount(power_well) ||
2161 intel_power_well_is_always_on(power_well)) !=
2162 enabled)
2163 drm_err(&i915->drm,
2164 "power well %s state mismatch (refcount %d/enabled %d)",
2165 intel_power_well_name(power_well),
2166 intel_power_well_refcount(power_well), enabled);
2167
2168 domains_count = 0;
2169 for_each_power_domain(domain, intel_power_well_domains(power_well))
2170 domains_count += power_domains->domain_use_count[domain];
2171
2172 if (intel_power_well_refcount(power_well) != domains_count) {
2173 drm_err(&i915->drm,
2174 "power well %s refcount/domain refcount mismatch "
2175 "(refcount %d/domains refcount %d)\n",
2176 intel_power_well_name(power_well),
2177 intel_power_well_refcount(power_well),
2178 domains_count);
2179 dump_domain_info = true;
2180 }
2181 }
2182
2183 if (dump_domain_info) {
2184 static bool dumped;
2185
2186 if (!dumped) {
2187 intel_power_domains_dump_info(i915);
2188 dumped = true;
2189 }
2190 }
2191
2192 mutex_unlock(&power_domains->lock);
2193}
2194
2195#else
2196
2197static void intel_power_domains_verify_state(struct drm_i915_private *i915)
2198{
2199}
2200
2201#endif
2202
2203void intel_display_power_suspend_late(struct drm_i915_private *i915)
2204{
2205 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
2206 IS_BROXTON(i915)) {
2207 bxt_enable_dc9(i915);
2208 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2209 hsw_enable_pc8(i915);
2210 }
2211
2212 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
2213 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
2214 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
2215}
2216
2217void intel_display_power_resume_early(struct drm_i915_private *i915)
2218{
2219 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
2220 IS_BROXTON(i915)) {
2221 gen9_sanitize_dc_state(i915);
2222 bxt_disable_dc9(i915);
2223 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2224 hsw_disable_pc8(i915);
2225 }
2226
2227 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
2228 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
2229 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
2230}
2231
2232void intel_display_power_suspend(struct drm_i915_private *i915)
2233{
2234 if (DISPLAY_VER(i915) >= 11) {
2235 icl_display_core_uninit(i915);
2236 bxt_enable_dc9(i915);
2237 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
2238 bxt_display_core_uninit(i915);
2239 bxt_enable_dc9(i915);
2240 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2241 hsw_enable_pc8(i915);
2242 }
2243}
2244
2245void intel_display_power_resume(struct drm_i915_private *i915)
2246{
2247 if (DISPLAY_VER(i915) >= 11) {
2248 bxt_disable_dc9(i915);
2249 icl_display_core_init(i915, true);
2250 if (intel_dmc_has_payload(i915)) {
2251 if (i915->display.dmc.allowed_dc_mask &
2252 DC_STATE_EN_UPTO_DC6)
2253 skl_enable_dc6(i915);
2254 else if (i915->display.dmc.allowed_dc_mask &
2255 DC_STATE_EN_UPTO_DC5)
2256 gen9_enable_dc5(i915);
2257 }
2258 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
2259 bxt_disable_dc9(i915);
2260 bxt_display_core_init(i915, true);
2261 if (intel_dmc_has_payload(i915) &&
2262 (i915->display.dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2263 gen9_enable_dc5(i915);
2264 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2265 hsw_disable_pc8(i915);
2266 }
2267}
2268
2269void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m)
2270{
2271 struct i915_power_domains *power_domains = &i915->display.power.domains;
2272 int i;
2273
2274 mutex_lock(&power_domains->lock);
2275
2276 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2277 for (i = 0; i < power_domains->power_well_count; i++) {
2278 struct i915_power_well *power_well;
2279 enum intel_display_power_domain power_domain;
2280
2281 power_well = &power_domains->power_wells[i];
2282 seq_printf(m, "%-25s %d\n", intel_power_well_name(power_well),
2283 intel_power_well_refcount(power_well));
2284
2285 for_each_power_domain(power_domain, intel_power_well_domains(power_well))
2286 seq_printf(m, " %-23s %d\n",
2287 intel_display_power_domain_str(power_domain),
2288 power_domains->domain_use_count[power_domain]);
2289 }
2290
2291 mutex_unlock(&power_domains->lock);
2292}
2293
2294struct intel_ddi_port_domains {
2295 enum port port_start;
2296 enum port port_end;
2297 enum aux_ch aux_ch_start;
2298 enum aux_ch aux_ch_end;
2299
2300 enum intel_display_power_domain ddi_lanes;
2301 enum intel_display_power_domain ddi_io;
2302 enum intel_display_power_domain aux_io;
2303 enum intel_display_power_domain aux_legacy_usbc;
2304 enum intel_display_power_domain aux_tbt;
2305};
2306
2307static const struct intel_ddi_port_domains
2308i9xx_port_domains[] = {
2309 {
2310 .port_start = PORT_A,
2311 .port_end = PORT_F,
2312 .aux_ch_start = AUX_CH_A,
2313 .aux_ch_end = AUX_CH_F,
2314
2315 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2316 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2317 .aux_io = POWER_DOMAIN_AUX_IO_A,
2318 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2319 .aux_tbt = POWER_DOMAIN_INVALID,
2320 },
2321};
2322
2323static const struct intel_ddi_port_domains
2324d11_port_domains[] = {
2325 {
2326 .port_start = PORT_A,
2327 .port_end = PORT_B,
2328 .aux_ch_start = AUX_CH_A,
2329 .aux_ch_end = AUX_CH_B,
2330
2331 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2332 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2333 .aux_io = POWER_DOMAIN_AUX_IO_A,
2334 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2335 .aux_tbt = POWER_DOMAIN_INVALID,
2336 }, {
2337 .port_start = PORT_C,
2338 .port_end = PORT_F,
2339 .aux_ch_start = AUX_CH_C,
2340 .aux_ch_end = AUX_CH_F,
2341
2342 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
2343 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
2344 .aux_io = POWER_DOMAIN_AUX_IO_C,
2345 .aux_legacy_usbc = POWER_DOMAIN_AUX_C,
2346 .aux_tbt = POWER_DOMAIN_AUX_TBT1,
2347 },
2348};
2349
2350static const struct intel_ddi_port_domains
2351d12_port_domains[] = {
2352 {
2353 .port_start = PORT_A,
2354 .port_end = PORT_C,
2355 .aux_ch_start = AUX_CH_A,
2356 .aux_ch_end = AUX_CH_C,
2357
2358 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2359 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2360 .aux_io = POWER_DOMAIN_AUX_IO_A,
2361 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2362 .aux_tbt = POWER_DOMAIN_INVALID,
2363 }, {
2364 .port_start = PORT_TC1,
2365 .port_end = PORT_TC6,
2366 .aux_ch_start = AUX_CH_USBC1,
2367 .aux_ch_end = AUX_CH_USBC6,
2368
2369 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
2370 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
2371 .aux_io = POWER_DOMAIN_INVALID,
2372 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
2373 .aux_tbt = POWER_DOMAIN_AUX_TBT1,
2374 },
2375};
2376
2377static const struct intel_ddi_port_domains
2378d13_port_domains[] = {
2379 {
2380 .port_start = PORT_A,
2381 .port_end = PORT_C,
2382 .aux_ch_start = AUX_CH_A,
2383 .aux_ch_end = AUX_CH_C,
2384
2385 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2386 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2387 .aux_io = POWER_DOMAIN_AUX_IO_A,
2388 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2389 .aux_tbt = POWER_DOMAIN_INVALID,
2390 }, {
2391 .port_start = PORT_TC1,
2392 .port_end = PORT_TC4,
2393 .aux_ch_start = AUX_CH_USBC1,
2394 .aux_ch_end = AUX_CH_USBC4,
2395
2396 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
2397 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
2398 .aux_io = POWER_DOMAIN_INVALID,
2399 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
2400 .aux_tbt = POWER_DOMAIN_AUX_TBT1,
2401 }, {
2402 .port_start = PORT_D_XELPD,
2403 .port_end = PORT_E_XELPD,
2404 .aux_ch_start = AUX_CH_D_XELPD,
2405 .aux_ch_end = AUX_CH_E_XELPD,
2406
2407 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D,
2408 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D,
2409 .aux_io = POWER_DOMAIN_AUX_IO_D,
2410 .aux_legacy_usbc = POWER_DOMAIN_AUX_D,
2411 .aux_tbt = POWER_DOMAIN_INVALID,
2412 },
2413};
2414
2415static void
2416intel_port_domains_for_platform(struct drm_i915_private *i915,
2417 const struct intel_ddi_port_domains **domains,
2418 int *domains_size)
2419{
2420 if (DISPLAY_VER(i915) >= 13) {
2421 *domains = d13_port_domains;
2422 *domains_size = ARRAY_SIZE(d13_port_domains);
2423 } else if (DISPLAY_VER(i915) >= 12) {
2424 *domains = d12_port_domains;
2425 *domains_size = ARRAY_SIZE(d12_port_domains);
2426 } else if (DISPLAY_VER(i915) >= 11) {
2427 *domains = d11_port_domains;
2428 *domains_size = ARRAY_SIZE(d11_port_domains);
2429 } else {
2430 *domains = i9xx_port_domains;
2431 *domains_size = ARRAY_SIZE(i9xx_port_domains);
2432 }
2433}
2434
2435static const struct intel_ddi_port_domains *
2436intel_port_domains_for_port(struct drm_i915_private *i915, enum port port)
2437{
2438 const struct intel_ddi_port_domains *domains;
2439 int domains_size;
2440 int i;
2441
2442 intel_port_domains_for_platform(i915, &domains, &domains_size);
2443 for (i = 0; i < domains_size; i++)
2444 if (port >= domains[i].port_start && port <= domains[i].port_end)
2445 return &domains[i];
2446
2447 return NULL;
2448}
2449
2450enum intel_display_power_domain
2451intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port)
2452{
2453 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port);
2454
2455 if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID))
2456 return POWER_DOMAIN_PORT_DDI_IO_A;
2457
2458 return domains->ddi_io + (int)(port - domains->port_start);
2459}
2460
2461enum intel_display_power_domain
2462intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port)
2463{
2464 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port);
2465
2466 if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID))
2467 return POWER_DOMAIN_PORT_DDI_LANES_A;
2468
2469 return domains->ddi_lanes + (int)(port - domains->port_start);
2470}
2471
2472static const struct intel_ddi_port_domains *
2473intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch)
2474{
2475 const struct intel_ddi_port_domains *domains;
2476 int domains_size;
2477 int i;
2478
2479 intel_port_domains_for_platform(i915, &domains, &domains_size);
2480 for (i = 0; i < domains_size; i++)
2481 if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end)
2482 return &domains[i];
2483
2484 return NULL;
2485}
2486
2487enum intel_display_power_domain
2488intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
2489{
2490 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
2491
2492 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID))
2493 return POWER_DOMAIN_AUX_IO_A;
2494
2495 return domains->aux_io + (int)(aux_ch - domains->aux_ch_start);
2496}
2497
2498enum intel_display_power_domain
2499intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
2500{
2501 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
2502
2503 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID))
2504 return POWER_DOMAIN_AUX_A;
2505
2506 return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start);
2507}
2508
2509enum intel_display_power_domain
2510intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
2511{
2512 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
2513
2514 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID))
2515 return POWER_DOMAIN_AUX_TBT1;
2516
2517 return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start);
2518}