Loading...
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#include <drm/drm_atomic_state_helper.h>
7
8#include "i915_drv.h"
9#include "i915_reg.h"
10#include "i915_utils.h"
11#include "intel_atomic.h"
12#include "intel_bw.h"
13#include "intel_cdclk.h"
14#include "intel_display_core.h"
15#include "intel_display_types.h"
16#include "skl_watermark.h"
17#include "intel_mchbar_regs.h"
18#include "intel_pcode.h"
19
20/* Parameters for Qclk Geyserville (QGV) */
21struct intel_qgv_point {
22 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
23};
24
25#define DEPROGBWPCLIMIT 60
26
27struct intel_psf_gv_point {
28 u8 clk; /* clock in multiples of 16.6666 MHz */
29};
30
31struct intel_qgv_info {
32 struct intel_qgv_point points[I915_NUM_QGV_POINTS];
33 struct intel_psf_gv_point psf_points[I915_NUM_PSF_GV_POINTS];
34 u8 num_points;
35 u8 num_psf_points;
36 u8 t_bl;
37 u8 max_numchannels;
38 u8 channel_width;
39 u8 deinterleave;
40};
41
42static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
43 struct intel_qgv_point *sp,
44 int point)
45{
46 u32 dclk_ratio, dclk_reference;
47 u32 val;
48
49 val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
50 dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val);
51 if (val & DG1_QCLK_REFERENCE)
52 dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
53 else
54 dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
55 sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000);
56
57 val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
58 if (val & DG1_GEAR_TYPE)
59 sp->dclk *= 2;
60
61 if (sp->dclk == 0)
62 return -EINVAL;
63
64 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
65 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val);
66 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val);
67
68 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
69 sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val);
70 sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val);
71
72 sp->t_rc = sp->t_rp + sp->t_ras;
73
74 return 0;
75}
76
77static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
78 struct intel_qgv_point *sp,
79 int point)
80{
81 u32 val = 0, val2 = 0;
82 u16 dclk;
83 int ret;
84
85 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
86 ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
87 &val, &val2);
88 if (ret)
89 return ret;
90
91 dclk = val & 0xffff;
92 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ? 500 : 0),
93 1000);
94 sp->t_rp = (val & 0xff0000) >> 16;
95 sp->t_rcd = (val & 0xff000000) >> 24;
96
97 sp->t_rdpre = val2 & 0xff;
98 sp->t_ras = (val2 & 0xff00) >> 8;
99
100 sp->t_rc = sp->t_rp + sp->t_ras;
101
102 return 0;
103}
104
105static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
106 struct intel_psf_gv_point *points)
107{
108 u32 val = 0;
109 int ret;
110 int i;
111
112 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
113 ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
114 if (ret)
115 return ret;
116
117 for (i = 0; i < I915_NUM_PSF_GV_POINTS; i++) {
118 points[i].clk = val & 0xff;
119 val >>= 8;
120 }
121
122 return 0;
123}
124
125static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
126{
127 unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
128 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
129 u16 qgv_points = 0, psf_points = 0;
130
131 /*
132 * We can _not_ use the whole ADLS_QGV_PT_MASK here, as PCode rejects
133 * it with failure if we try masking any unadvertised points.
134 * So need to operate only with those returned from PCode.
135 */
136 if (num_qgv_points > 0)
137 qgv_points = GENMASK(num_qgv_points - 1, 0);
138
139 if (num_psf_gv_points > 0)
140 psf_points = GENMASK(num_psf_gv_points - 1, 0);
141
142 return ICL_PCODE_REQ_QGV_PT(qgv_points) | ADLS_PCODE_REQ_PSF_PT(psf_points);
143}
144
145static bool is_sagv_enabled(struct drm_i915_private *i915, u16 points_mask)
146{
147 return !is_power_of_2(~points_mask & icl_qgv_points_mask(i915) &
148 ICL_PCODE_REQ_QGV_PT_MASK);
149}
150
151int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
152 u32 points_mask)
153{
154 int ret;
155
156 if (DISPLAY_VER(dev_priv) >= 14)
157 return 0;
158
159 /* bspec says to keep retrying for at least 1 ms */
160 ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
161 points_mask,
162 ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
163 ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
164 1);
165
166 if (ret < 0) {
167 drm_err(&dev_priv->drm,
168 "Failed to disable qgv points (0x%x) points: 0x%x\n",
169 ret, points_mask);
170 return ret;
171 }
172
173 dev_priv->display.sagv.status = is_sagv_enabled(dev_priv, points_mask) ?
174 I915_SAGV_ENABLED : I915_SAGV_DISABLED;
175
176 return 0;
177}
178
179static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
180 struct intel_qgv_point *sp, int point)
181{
182 u32 val, val2;
183 u16 dclk;
184
185 val = intel_uncore_read(&dev_priv->uncore,
186 MTL_MEM_SS_INFO_QGV_POINT_LOW(point));
187 val2 = intel_uncore_read(&dev_priv->uncore,
188 MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
189 dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
190 sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000);
191 sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
192 sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
193
194 sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2);
195 sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2);
196
197 sp->t_rc = sp->t_rp + sp->t_ras;
198
199 return 0;
200}
201
202static int
203intel_read_qgv_point_info(struct drm_i915_private *dev_priv,
204 struct intel_qgv_point *sp,
205 int point)
206{
207 if (DISPLAY_VER(dev_priv) >= 14)
208 return mtl_read_qgv_point_info(dev_priv, sp, point);
209 else if (IS_DG1(dev_priv))
210 return dg1_mchbar_read_qgv_point_info(dev_priv, sp, point);
211 else
212 return icl_pcode_read_qgv_point_info(dev_priv, sp, point);
213}
214
215static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
216 struct intel_qgv_info *qi,
217 bool is_y_tile)
218{
219 const struct dram_info *dram_info = &dev_priv->dram_info;
220 int i, ret;
221
222 qi->num_points = dram_info->num_qgv_points;
223 qi->num_psf_points = dram_info->num_psf_gv_points;
224
225 if (DISPLAY_VER(dev_priv) >= 14) {
226 switch (dram_info->type) {
227 case INTEL_DRAM_DDR4:
228 qi->t_bl = 4;
229 qi->max_numchannels = 2;
230 qi->channel_width = 64;
231 qi->deinterleave = 2;
232 break;
233 case INTEL_DRAM_DDR5:
234 qi->t_bl = 8;
235 qi->max_numchannels = 4;
236 qi->channel_width = 32;
237 qi->deinterleave = 2;
238 break;
239 case INTEL_DRAM_LPDDR4:
240 case INTEL_DRAM_LPDDR5:
241 qi->t_bl = 16;
242 qi->max_numchannels = 8;
243 qi->channel_width = 16;
244 qi->deinterleave = 4;
245 break;
246 case INTEL_DRAM_GDDR:
247 qi->channel_width = 32;
248 break;
249 default:
250 MISSING_CASE(dram_info->type);
251 return -EINVAL;
252 }
253 } else if (DISPLAY_VER(dev_priv) >= 12) {
254 switch (dram_info->type) {
255 case INTEL_DRAM_DDR4:
256 qi->t_bl = is_y_tile ? 8 : 4;
257 qi->max_numchannels = 2;
258 qi->channel_width = 64;
259 qi->deinterleave = is_y_tile ? 1 : 2;
260 break;
261 case INTEL_DRAM_DDR5:
262 qi->t_bl = is_y_tile ? 16 : 8;
263 qi->max_numchannels = 4;
264 qi->channel_width = 32;
265 qi->deinterleave = is_y_tile ? 1 : 2;
266 break;
267 case INTEL_DRAM_LPDDR4:
268 if (IS_ROCKETLAKE(dev_priv)) {
269 qi->t_bl = 8;
270 qi->max_numchannels = 4;
271 qi->channel_width = 32;
272 qi->deinterleave = 2;
273 break;
274 }
275 fallthrough;
276 case INTEL_DRAM_LPDDR5:
277 qi->t_bl = 16;
278 qi->max_numchannels = 8;
279 qi->channel_width = 16;
280 qi->deinterleave = is_y_tile ? 2 : 4;
281 break;
282 default:
283 qi->t_bl = 16;
284 qi->max_numchannels = 1;
285 break;
286 }
287 } else if (DISPLAY_VER(dev_priv) == 11) {
288 qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
289 qi->max_numchannels = 1;
290 }
291
292 if (drm_WARN_ON(&dev_priv->drm,
293 qi->num_points > ARRAY_SIZE(qi->points)))
294 qi->num_points = ARRAY_SIZE(qi->points);
295
296 for (i = 0; i < qi->num_points; i++) {
297 struct intel_qgv_point *sp = &qi->points[i];
298
299 ret = intel_read_qgv_point_info(dev_priv, sp, i);
300 if (ret) {
301 drm_dbg_kms(&dev_priv->drm, "Could not read QGV %d info\n", i);
302 return ret;
303 }
304
305 drm_dbg_kms(&dev_priv->drm,
306 "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n",
307 i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras,
308 sp->t_rcd, sp->t_rc);
309 }
310
311 if (qi->num_psf_points > 0) {
312 ret = adls_pcode_read_psf_gv_point_info(dev_priv, qi->psf_points);
313 if (ret) {
314 drm_err(&dev_priv->drm, "Failed to read PSF point data; PSF points will not be considered in bandwidth calculations.\n");
315 qi->num_psf_points = 0;
316 }
317
318 for (i = 0; i < qi->num_psf_points; i++)
319 drm_dbg_kms(&dev_priv->drm,
320 "PSF GV %d: CLK=%d \n",
321 i, qi->psf_points[i].clk);
322 }
323
324 return 0;
325}
326
327static int adl_calc_psf_bw(int clk)
328{
329 /*
330 * clk is multiples of 16.666MHz (100/6)
331 * According to BSpec PSF GV bandwidth is
332 * calculated as BW = 64 * clk * 16.666Mhz
333 */
334 return DIV_ROUND_CLOSEST(64 * clk * 100, 6);
335}
336
337static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
338{
339 u16 dclk = 0;
340 int i;
341
342 for (i = 0; i < qi->num_points; i++)
343 dclk = max(dclk, qi->points[i].dclk);
344
345 return dclk;
346}
347
348struct intel_sa_info {
349 u16 displayrtids;
350 u8 deburst, deprogbwlimit, derating;
351};
352
353static const struct intel_sa_info icl_sa_info = {
354 .deburst = 8,
355 .deprogbwlimit = 25, /* GB/s */
356 .displayrtids = 128,
357 .derating = 10,
358};
359
360static const struct intel_sa_info tgl_sa_info = {
361 .deburst = 16,
362 .deprogbwlimit = 34, /* GB/s */
363 .displayrtids = 256,
364 .derating = 10,
365};
366
367static const struct intel_sa_info rkl_sa_info = {
368 .deburst = 8,
369 .deprogbwlimit = 20, /* GB/s */
370 .displayrtids = 128,
371 .derating = 10,
372};
373
374static const struct intel_sa_info adls_sa_info = {
375 .deburst = 16,
376 .deprogbwlimit = 38, /* GB/s */
377 .displayrtids = 256,
378 .derating = 10,
379};
380
381static const struct intel_sa_info adlp_sa_info = {
382 .deburst = 16,
383 .deprogbwlimit = 38, /* GB/s */
384 .displayrtids = 256,
385 .derating = 20,
386};
387
388static const struct intel_sa_info mtl_sa_info = {
389 .deburst = 32,
390 .deprogbwlimit = 38, /* GB/s */
391 .displayrtids = 256,
392 .derating = 10,
393};
394
395static const struct intel_sa_info xe2_hpd_sa_info = {
396 .derating = 30,
397 .deprogbwlimit = 53,
398 /* Other values not used by simplified algorithm */
399};
400
401static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
402{
403 struct intel_qgv_info qi = {};
404 bool is_y_tile = true; /* assume y tile may be used */
405 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
406 int ipqdepth, ipqdepthpch = 16;
407 int dclk_max;
408 int maxdebw;
409 int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
410 int i, ret;
411
412 ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
413 if (ret) {
414 drm_dbg_kms(&dev_priv->drm,
415 "Failed to get memory subsystem information, ignoring bandwidth limits");
416 return ret;
417 }
418
419 dclk_max = icl_sagv_max_dclk(&qi);
420 maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
421 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
422 qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
423
424 for (i = 0; i < num_groups; i++) {
425 struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
426 int clpchgroup;
427 int j;
428
429 clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
430 bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
431
432 bi->num_qgv_points = qi.num_points;
433 bi->num_psf_gv_points = qi.num_psf_points;
434
435 for (j = 0; j < qi.num_points; j++) {
436 const struct intel_qgv_point *sp = &qi.points[j];
437 int ct, bw;
438
439 /*
440 * Max row cycle time
441 *
442 * FIXME what is the logic behind the
443 * assumed burst length?
444 */
445 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
446 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
447 bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
448
449 bi->deratedbw[j] = min(maxdebw,
450 bw * (100 - sa->derating) / 100);
451
452 drm_dbg_kms(&dev_priv->drm,
453 "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
454 i, j, bi->num_planes, bi->deratedbw[j]);
455 }
456 }
457 /*
458 * In case if SAGV is disabled in BIOS, we always get 1
459 * SAGV point, but we can't send PCode commands to restrict it
460 * as it will fail and pointless anyway.
461 */
462 if (qi.num_points == 1)
463 dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
464 else
465 dev_priv->display.sagv.status = I915_SAGV_ENABLED;
466
467 return 0;
468}
469
470static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
471{
472 struct intel_qgv_info qi = {};
473 const struct dram_info *dram_info = &dev_priv->dram_info;
474 bool is_y_tile = true; /* assume y tile may be used */
475 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
476 int ipqdepth, ipqdepthpch = 16;
477 int dclk_max;
478 int maxdebw, peakbw;
479 int clperchgroup;
480 int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
481 int i, ret;
482
483 ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
484 if (ret) {
485 drm_dbg_kms(&dev_priv->drm,
486 "Failed to get memory subsystem information, ignoring bandwidth limits");
487 return ret;
488 }
489
490 if (DISPLAY_VER(dev_priv) < 14 &&
491 (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5))
492 num_channels *= 2;
493
494 qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
495
496 if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12)
497 qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1);
498
499 if (DISPLAY_VER(dev_priv) >= 12 && num_channels > qi.max_numchannels)
500 drm_warn(&dev_priv->drm, "Number of channels exceeds max number of channels.");
501 if (qi.max_numchannels != 0)
502 num_channels = min_t(u8, num_channels, qi.max_numchannels);
503
504 dclk_max = icl_sagv_max_dclk(&qi);
505
506 peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
507 maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
508
509 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
510 /*
511 * clperchgroup = 4kpagespermempage * clperchperblock,
512 * clperchperblock = 8 / num_channels * interleave
513 */
514 clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * qi.deinterleave;
515
516 for (i = 0; i < num_groups; i++) {
517 struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
518 struct intel_bw_info *bi_next;
519 int clpchgroup;
520 int j;
521
522 clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
523
524 if (i < num_groups - 1) {
525 bi_next = &dev_priv->display.bw.max[i + 1];
526
527 if (clpchgroup < clperchgroup)
528 bi_next->num_planes = (ipqdepth - clpchgroup) /
529 clpchgroup + 1;
530 else
531 bi_next->num_planes = 0;
532 }
533
534 bi->num_qgv_points = qi.num_points;
535 bi->num_psf_gv_points = qi.num_psf_points;
536
537 for (j = 0; j < qi.num_points; j++) {
538 const struct intel_qgv_point *sp = &qi.points[j];
539 int ct, bw;
540
541 /*
542 * Max row cycle time
543 *
544 * FIXME what is the logic behind the
545 * assumed burst length?
546 */
547 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
548 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
549 bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
550
551 bi->deratedbw[j] = min(maxdebw,
552 bw * (100 - sa->derating) / 100);
553 bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
554 num_channels *
555 qi.channel_width, 8);
556
557 drm_dbg_kms(&dev_priv->drm,
558 "BW%d / QGV %d: num_planes=%d deratedbw=%u peakbw: %u\n",
559 i, j, bi->num_planes, bi->deratedbw[j],
560 bi->peakbw[j]);
561 }
562
563 for (j = 0; j < qi.num_psf_points; j++) {
564 const struct intel_psf_gv_point *sp = &qi.psf_points[j];
565
566 bi->psf_bw[j] = adl_calc_psf_bw(sp->clk);
567
568 drm_dbg_kms(&dev_priv->drm,
569 "BW%d / PSF GV %d: num_planes=%d bw=%u\n",
570 i, j, bi->num_planes, bi->psf_bw[j]);
571 }
572 }
573
574 /*
575 * In case if SAGV is disabled in BIOS, we always get 1
576 * SAGV point, but we can't send PCode commands to restrict it
577 * as it will fail and pointless anyway.
578 */
579 if (qi.num_points == 1)
580 dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
581 else
582 dev_priv->display.sagv.status = I915_SAGV_ENABLED;
583
584 return 0;
585}
586
587static void dg2_get_bw_info(struct drm_i915_private *i915)
588{
589 unsigned int deratedbw = IS_DG2_G11(i915) ? 38000 : 50000;
590 int num_groups = ARRAY_SIZE(i915->display.bw.max);
591 int i;
592
593 /*
594 * DG2 doesn't have SAGV or QGV points, just a constant max bandwidth
595 * that doesn't depend on the number of planes enabled. So fill all the
596 * plane group with constant bw information for uniformity with other
597 * platforms. DG2-G10 platforms have a constant 50 GB/s bandwidth,
598 * whereas DG2-G11 platforms have 38 GB/s.
599 */
600 for (i = 0; i < num_groups; i++) {
601 struct intel_bw_info *bi = &i915->display.bw.max[i];
602
603 bi->num_planes = 1;
604 /* Need only one dummy QGV point per group */
605 bi->num_qgv_points = 1;
606 bi->deratedbw[0] = deratedbw;
607 }
608
609 i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
610}
611
612static int xe2_hpd_get_bw_info(struct drm_i915_private *i915,
613 const struct intel_sa_info *sa)
614{
615 struct intel_qgv_info qi = {};
616 int num_channels = i915->dram_info.num_channels;
617 int peakbw, maxdebw;
618 int ret, i;
619
620 ret = icl_get_qgv_points(i915, &qi, true);
621 if (ret) {
622 drm_dbg_kms(&i915->drm,
623 "Failed to get memory subsystem information, ignoring bandwidth limits");
624 return ret;
625 }
626
627 peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
628 maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
629
630 for (i = 0; i < qi.num_points; i++) {
631 const struct intel_qgv_point *point = &qi.points[i];
632 int bw = num_channels * (qi.channel_width / 8) * point->dclk;
633
634 i915->display.bw.max[0].deratedbw[i] =
635 min(maxdebw, (100 - sa->derating) * bw / 100);
636 i915->display.bw.max[0].peakbw[i] = bw;
637
638 drm_dbg_kms(&i915->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
639 i, i915->display.bw.max[0].deratedbw[i],
640 i915->display.bw.max[0].peakbw[i]);
641 }
642
643 /* Bandwidth does not depend on # of planes; set all groups the same */
644 i915->display.bw.max[0].num_planes = 1;
645 i915->display.bw.max[0].num_qgv_points = qi.num_points;
646 for (i = 1; i < ARRAY_SIZE(i915->display.bw.max); i++)
647 memcpy(&i915->display.bw.max[i], &i915->display.bw.max[0],
648 sizeof(i915->display.bw.max[0]));
649
650 /*
651 * Xe2_HPD should always have exactly two QGV points representing
652 * battery and plugged-in operation.
653 */
654 drm_WARN_ON(&i915->drm, qi.num_points != 2);
655 i915->display.sagv.status = I915_SAGV_ENABLED;
656
657 return 0;
658}
659
660static unsigned int icl_max_bw_index(struct drm_i915_private *dev_priv,
661 int num_planes, int qgv_point)
662{
663 int i;
664
665 /*
666 * Let's return max bw for 0 planes
667 */
668 num_planes = max(1, num_planes);
669
670 for (i = 0; i < ARRAY_SIZE(dev_priv->display.bw.max); i++) {
671 const struct intel_bw_info *bi =
672 &dev_priv->display.bw.max[i];
673
674 /*
675 * Pcode will not expose all QGV points when
676 * SAGV is forced to off/min/med/max.
677 */
678 if (qgv_point >= bi->num_qgv_points)
679 return UINT_MAX;
680
681 if (num_planes >= bi->num_planes)
682 return i;
683 }
684
685 return UINT_MAX;
686}
687
688static unsigned int tgl_max_bw_index(struct drm_i915_private *dev_priv,
689 int num_planes, int qgv_point)
690{
691 int i;
692
693 /*
694 * Let's return max bw for 0 planes
695 */
696 num_planes = max(1, num_planes);
697
698 for (i = ARRAY_SIZE(dev_priv->display.bw.max) - 1; i >= 0; i--) {
699 const struct intel_bw_info *bi =
700 &dev_priv->display.bw.max[i];
701
702 /*
703 * Pcode will not expose all QGV points when
704 * SAGV is forced to off/min/med/max.
705 */
706 if (qgv_point >= bi->num_qgv_points)
707 return UINT_MAX;
708
709 if (num_planes <= bi->num_planes)
710 return i;
711 }
712
713 return 0;
714}
715
716static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
717 int psf_gv_point)
718{
719 const struct intel_bw_info *bi =
720 &dev_priv->display.bw.max[0];
721
722 return bi->psf_bw[psf_gv_point];
723}
724
725static unsigned int icl_qgv_bw(struct drm_i915_private *i915,
726 int num_active_planes, int qgv_point)
727{
728 unsigned int idx;
729
730 if (DISPLAY_VER(i915) >= 12)
731 idx = tgl_max_bw_index(i915, num_active_planes, qgv_point);
732 else
733 idx = icl_max_bw_index(i915, num_active_planes, qgv_point);
734
735 if (idx >= ARRAY_SIZE(i915->display.bw.max))
736 return 0;
737
738 return i915->display.bw.max[idx].deratedbw[qgv_point];
739}
740
741void intel_bw_init_hw(struct drm_i915_private *dev_priv)
742{
743 if (!HAS_DISPLAY(dev_priv))
744 return;
745
746 if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv))
747 xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info);
748 else if (DISPLAY_VER(dev_priv) >= 14)
749 tgl_get_bw_info(dev_priv, &mtl_sa_info);
750 else if (IS_DG2(dev_priv))
751 dg2_get_bw_info(dev_priv);
752 else if (IS_ALDERLAKE_P(dev_priv))
753 tgl_get_bw_info(dev_priv, &adlp_sa_info);
754 else if (IS_ALDERLAKE_S(dev_priv))
755 tgl_get_bw_info(dev_priv, &adls_sa_info);
756 else if (IS_ROCKETLAKE(dev_priv))
757 tgl_get_bw_info(dev_priv, &rkl_sa_info);
758 else if (DISPLAY_VER(dev_priv) == 12)
759 tgl_get_bw_info(dev_priv, &tgl_sa_info);
760 else if (DISPLAY_VER(dev_priv) == 11)
761 icl_get_bw_info(dev_priv, &icl_sa_info);
762}
763
764static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
765{
766 /*
767 * We assume cursors are small enough
768 * to not not cause bandwidth problems.
769 */
770 return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
771}
772
773static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
774{
775 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
776 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
777 unsigned int data_rate = 0;
778 enum plane_id plane_id;
779
780 for_each_plane_id_on_crtc(crtc, plane_id) {
781 /*
782 * We assume cursors are small enough
783 * to not not cause bandwidth problems.
784 */
785 if (plane_id == PLANE_CURSOR)
786 continue;
787
788 data_rate += crtc_state->data_rate[plane_id];
789
790 if (DISPLAY_VER(i915) < 11)
791 data_rate += crtc_state->data_rate_y[plane_id];
792 }
793
794 return data_rate;
795}
796
797/* "Maximum Pipe Read Bandwidth" */
798static int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
799{
800 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
801 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
802
803 if (DISPLAY_VER(i915) < 12)
804 return 0;
805
806 return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);
807}
808
809void intel_bw_crtc_update(struct intel_bw_state *bw_state,
810 const struct intel_crtc_state *crtc_state)
811{
812 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
813 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
814
815 bw_state->data_rate[crtc->pipe] =
816 intel_bw_crtc_data_rate(crtc_state);
817 bw_state->num_active_planes[crtc->pipe] =
818 intel_bw_crtc_num_active_planes(crtc_state);
819 bw_state->force_check_qgv = true;
820
821 drm_dbg_kms(&i915->drm, "pipe %c data rate %u num active planes %u\n",
822 pipe_name(crtc->pipe),
823 bw_state->data_rate[crtc->pipe],
824 bw_state->num_active_planes[crtc->pipe]);
825}
826
827static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv,
828 const struct intel_bw_state *bw_state)
829{
830 unsigned int num_active_planes = 0;
831 enum pipe pipe;
832
833 for_each_pipe(dev_priv, pipe)
834 num_active_planes += bw_state->num_active_planes[pipe];
835
836 return num_active_planes;
837}
838
839static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
840 const struct intel_bw_state *bw_state)
841{
842 unsigned int data_rate = 0;
843 enum pipe pipe;
844
845 for_each_pipe(dev_priv, pipe)
846 data_rate += bw_state->data_rate[pipe];
847
848 if (DISPLAY_VER(dev_priv) >= 13 && i915_vtd_active(dev_priv))
849 data_rate = DIV_ROUND_UP(data_rate * 105, 100);
850
851 return data_rate;
852}
853
854struct intel_bw_state *
855intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
856{
857 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
858 struct intel_global_state *bw_state;
859
860 bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->display.bw.obj);
861
862 return to_intel_bw_state(bw_state);
863}
864
865struct intel_bw_state *
866intel_atomic_get_new_bw_state(struct intel_atomic_state *state)
867{
868 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
869 struct intel_global_state *bw_state;
870
871 bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->display.bw.obj);
872
873 return to_intel_bw_state(bw_state);
874}
875
876struct intel_bw_state *
877intel_atomic_get_bw_state(struct intel_atomic_state *state)
878{
879 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
880 struct intel_global_state *bw_state;
881
882 bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.bw.obj);
883 if (IS_ERR(bw_state))
884 return ERR_CAST(bw_state);
885
886 return to_intel_bw_state(bw_state);
887}
888
889static unsigned int icl_max_bw_qgv_point_mask(struct drm_i915_private *i915,
890 int num_active_planes)
891{
892 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
893 unsigned int max_bw_point = 0;
894 unsigned int max_bw = 0;
895 int i;
896
897 for (i = 0; i < num_qgv_points; i++) {
898 unsigned int max_data_rate =
899 icl_qgv_bw(i915, num_active_planes, i);
900
901 /*
902 * We need to know which qgv point gives us
903 * maximum bandwidth in order to disable SAGV
904 * if we find that we exceed SAGV block time
905 * with watermarks. By that moment we already
906 * have those, as it is calculated earlier in
907 * intel_atomic_check,
908 */
909 if (max_data_rate > max_bw) {
910 max_bw_point = BIT(i);
911 max_bw = max_data_rate;
912 }
913 }
914
915 return max_bw_point;
916}
917
918static u16 icl_prepare_qgv_points_mask(struct drm_i915_private *i915,
919 unsigned int qgv_points,
920 unsigned int psf_points)
921{
922 return ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
923 ADLS_PCODE_REQ_PSF_PT(psf_points)) & icl_qgv_points_mask(i915);
924}
925
926static unsigned int icl_max_bw_psf_gv_point_mask(struct drm_i915_private *i915)
927{
928 unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
929 unsigned int max_bw_point_mask = 0;
930 unsigned int max_bw = 0;
931 int i;
932
933 for (i = 0; i < num_psf_gv_points; i++) {
934 unsigned int max_data_rate = adl_psf_bw(i915, i);
935
936 if (max_data_rate > max_bw) {
937 max_bw_point_mask = BIT(i);
938 max_bw = max_data_rate;
939 } else if (max_data_rate == max_bw) {
940 max_bw_point_mask |= BIT(i);
941 }
942 }
943
944 return max_bw_point_mask;
945}
946
947static void icl_force_disable_sagv(struct drm_i915_private *i915,
948 struct intel_bw_state *bw_state)
949{
950 unsigned int qgv_points = icl_max_bw_qgv_point_mask(i915, 0);
951 unsigned int psf_points = icl_max_bw_psf_gv_point_mask(i915);
952
953 bw_state->qgv_points_mask = icl_prepare_qgv_points_mask(i915,
954 qgv_points,
955 psf_points);
956
957 drm_dbg_kms(&i915->drm, "Forcing SAGV disable: mask 0x%x\n",
958 bw_state->qgv_points_mask);
959
960 icl_pcode_restrict_qgv_points(i915, bw_state->qgv_points_mask);
961}
962
963static int mtl_find_qgv_points(struct drm_i915_private *i915,
964 unsigned int data_rate,
965 unsigned int num_active_planes,
966 struct intel_bw_state *new_bw_state)
967{
968 unsigned int best_rate = UINT_MAX;
969 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
970 unsigned int qgv_peak_bw = 0;
971 int i;
972 int ret;
973
974 ret = intel_atomic_lock_global_state(&new_bw_state->base);
975 if (ret)
976 return ret;
977
978 /*
979 * If SAGV cannot be enabled, disable the pcode SAGV by passing all 1's
980 * for qgv peak bw in PM Demand request. So assign UINT_MAX if SAGV is
981 * not enabled. PM Demand code will clamp the value for the register
982 */
983 if (!intel_can_enable_sagv(i915, new_bw_state)) {
984 new_bw_state->qgv_point_peakbw = U16_MAX;
985 drm_dbg_kms(&i915->drm, "No SAGV, use UINT_MAX as peak bw.");
986 return 0;
987 }
988
989 /*
990 * Find the best QGV point by comparing the data_rate with max data rate
991 * offered per plane group
992 */
993 for (i = 0; i < num_qgv_points; i++) {
994 unsigned int bw_index =
995 tgl_max_bw_index(i915, num_active_planes, i);
996 unsigned int max_data_rate;
997
998 if (bw_index >= ARRAY_SIZE(i915->display.bw.max))
999 continue;
1000
1001 max_data_rate = i915->display.bw.max[bw_index].deratedbw[i];
1002
1003 if (max_data_rate < data_rate)
1004 continue;
1005
1006 if (max_data_rate - data_rate < best_rate) {
1007 best_rate = max_data_rate - data_rate;
1008 qgv_peak_bw = i915->display.bw.max[bw_index].peakbw[i];
1009 }
1010
1011 drm_dbg_kms(&i915->drm, "QGV point %d: max bw %d required %d qgv_peak_bw: %d\n",
1012 i, max_data_rate, data_rate, qgv_peak_bw);
1013 }
1014
1015 drm_dbg_kms(&i915->drm, "Matching peaks QGV bw: %d for required data rate: %d\n",
1016 qgv_peak_bw, data_rate);
1017
1018 /*
1019 * The display configuration cannot be supported if no QGV point
1020 * satisfying the required data rate is found
1021 */
1022 if (qgv_peak_bw == 0) {
1023 drm_dbg_kms(&i915->drm, "No QGV points for bw %d for display configuration(%d active planes).\n",
1024 data_rate, num_active_planes);
1025 return -EINVAL;
1026 }
1027
1028 /* MTL PM DEMAND expects QGV BW parameter in multiples of 100 mbps */
1029 new_bw_state->qgv_point_peakbw = DIV_ROUND_CLOSEST(qgv_peak_bw, 100);
1030
1031 return 0;
1032}
1033
1034static int icl_find_qgv_points(struct drm_i915_private *i915,
1035 unsigned int data_rate,
1036 unsigned int num_active_planes,
1037 const struct intel_bw_state *old_bw_state,
1038 struct intel_bw_state *new_bw_state)
1039{
1040 unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
1041 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
1042 u16 psf_points = 0;
1043 u16 qgv_points = 0;
1044 int i;
1045 int ret;
1046
1047 ret = intel_atomic_lock_global_state(&new_bw_state->base);
1048 if (ret)
1049 return ret;
1050
1051 for (i = 0; i < num_qgv_points; i++) {
1052 unsigned int max_data_rate = icl_qgv_bw(i915,
1053 num_active_planes, i);
1054 if (max_data_rate >= data_rate)
1055 qgv_points |= BIT(i);
1056
1057 drm_dbg_kms(&i915->drm, "QGV point %d: max bw %d required %d\n",
1058 i, max_data_rate, data_rate);
1059 }
1060
1061 for (i = 0; i < num_psf_gv_points; i++) {
1062 unsigned int max_data_rate = adl_psf_bw(i915, i);
1063
1064 if (max_data_rate >= data_rate)
1065 psf_points |= BIT(i);
1066
1067 drm_dbg_kms(&i915->drm, "PSF GV point %d: max bw %d"
1068 " required %d\n",
1069 i, max_data_rate, data_rate);
1070 }
1071
1072 /*
1073 * BSpec states that we always should have at least one allowed point
1074 * left, so if we couldn't - simply reject the configuration for obvious
1075 * reasons.
1076 */
1077 if (qgv_points == 0) {
1078 drm_dbg_kms(&i915->drm, "No QGV points provide sufficient memory"
1079 " bandwidth %d for display configuration(%d active planes).\n",
1080 data_rate, num_active_planes);
1081 return -EINVAL;
1082 }
1083
1084 if (num_psf_gv_points > 0 && psf_points == 0) {
1085 drm_dbg_kms(&i915->drm, "No PSF GV points provide sufficient memory"
1086 " bandwidth %d for display configuration(%d active planes).\n",
1087 data_rate, num_active_planes);
1088 return -EINVAL;
1089 }
1090
1091 /*
1092 * Leave only single point with highest bandwidth, if
1093 * we can't enable SAGV due to the increased memory latency it may
1094 * cause.
1095 */
1096 if (!intel_can_enable_sagv(i915, new_bw_state)) {
1097 qgv_points = icl_max_bw_qgv_point_mask(i915, num_active_planes);
1098 drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point mask 0x%x\n",
1099 qgv_points);
1100 }
1101
1102 /*
1103 * We store the ones which need to be masked as that is what PCode
1104 * actually accepts as a parameter.
1105 */
1106 new_bw_state->qgv_points_mask = icl_prepare_qgv_points_mask(i915,
1107 qgv_points,
1108 psf_points);
1109 /*
1110 * If the actual mask had changed we need to make sure that
1111 * the commits are serialized(in case this is a nomodeset, nonblocking)
1112 */
1113 if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
1114 ret = intel_atomic_serialize_global_state(&new_bw_state->base);
1115 if (ret)
1116 return ret;
1117 }
1118
1119 return 0;
1120}
1121
1122static int intel_bw_check_qgv_points(struct drm_i915_private *i915,
1123 const struct intel_bw_state *old_bw_state,
1124 struct intel_bw_state *new_bw_state)
1125{
1126 unsigned int data_rate = intel_bw_data_rate(i915, new_bw_state);
1127 unsigned int num_active_planes =
1128 intel_bw_num_active_planes(i915, new_bw_state);
1129
1130 data_rate = DIV_ROUND_UP(data_rate, 1000);
1131
1132 if (DISPLAY_VER(i915) >= 14)
1133 return mtl_find_qgv_points(i915, data_rate, num_active_planes,
1134 new_bw_state);
1135 else
1136 return icl_find_qgv_points(i915, data_rate, num_active_planes,
1137 old_bw_state, new_bw_state);
1138}
1139
1140static bool intel_bw_state_changed(struct drm_i915_private *i915,
1141 const struct intel_bw_state *old_bw_state,
1142 const struct intel_bw_state *new_bw_state)
1143{
1144 enum pipe pipe;
1145
1146 for_each_pipe(i915, pipe) {
1147 const struct intel_dbuf_bw *old_crtc_bw =
1148 &old_bw_state->dbuf_bw[pipe];
1149 const struct intel_dbuf_bw *new_crtc_bw =
1150 &new_bw_state->dbuf_bw[pipe];
1151 enum dbuf_slice slice;
1152
1153 for_each_dbuf_slice(i915, slice) {
1154 if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
1155 old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
1156 return true;
1157 }
1158
1159 if (old_bw_state->min_cdclk[pipe] != new_bw_state->min_cdclk[pipe])
1160 return true;
1161 }
1162
1163 return false;
1164}
1165
1166static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
1167 struct intel_crtc *crtc,
1168 enum plane_id plane_id,
1169 const struct skl_ddb_entry *ddb,
1170 unsigned int data_rate)
1171{
1172 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1173 struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
1174 unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
1175 enum dbuf_slice slice;
1176
1177 /*
1178 * The arbiter can only really guarantee an
1179 * equal share of the total bw to each plane.
1180 */
1181 for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
1182 crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
1183 crtc_bw->active_planes[slice] |= BIT(plane_id);
1184 }
1185}
1186
1187static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
1188 const struct intel_crtc_state *crtc_state)
1189{
1190 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1191 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1192 struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
1193 enum plane_id plane_id;
1194
1195 memset(crtc_bw, 0, sizeof(*crtc_bw));
1196
1197 if (!crtc_state->hw.active)
1198 return;
1199
1200 for_each_plane_id_on_crtc(crtc, plane_id) {
1201 /*
1202 * We assume cursors are small enough
1203 * to not cause bandwidth problems.
1204 */
1205 if (plane_id == PLANE_CURSOR)
1206 continue;
1207
1208 skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
1209 &crtc_state->wm.skl.plane_ddb[plane_id],
1210 crtc_state->data_rate[plane_id]);
1211
1212 if (DISPLAY_VER(i915) < 11)
1213 skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
1214 &crtc_state->wm.skl.plane_ddb_y[plane_id],
1215 crtc_state->data_rate[plane_id]);
1216 }
1217}
1218
1219/* "Maximum Data Buffer Bandwidth" */
1220static int
1221intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
1222 const struct intel_bw_state *bw_state)
1223{
1224 unsigned int total_max_bw = 0;
1225 enum dbuf_slice slice;
1226
1227 for_each_dbuf_slice(i915, slice) {
1228 int num_active_planes = 0;
1229 unsigned int max_bw = 0;
1230 enum pipe pipe;
1231
1232 /*
1233 * The arbiter can only really guarantee an
1234 * equal share of the total bw to each plane.
1235 */
1236 for_each_pipe(i915, pipe) {
1237 const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe];
1238
1239 max_bw = max(crtc_bw->max_bw[slice], max_bw);
1240 num_active_planes += hweight8(crtc_bw->active_planes[slice]);
1241 }
1242 max_bw *= num_active_planes;
1243
1244 total_max_bw = max(total_max_bw, max_bw);
1245 }
1246
1247 return DIV_ROUND_UP(total_max_bw, 64);
1248}
1249
1250int intel_bw_min_cdclk(struct drm_i915_private *i915,
1251 const struct intel_bw_state *bw_state)
1252{
1253 enum pipe pipe;
1254 int min_cdclk;
1255
1256 min_cdclk = intel_bw_dbuf_min_cdclk(i915, bw_state);
1257
1258 for_each_pipe(i915, pipe)
1259 min_cdclk = max(bw_state->min_cdclk[pipe], min_cdclk);
1260
1261 return min_cdclk;
1262}
1263
1264int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
1265 bool *need_cdclk_calc)
1266{
1267 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1268 struct intel_bw_state *new_bw_state = NULL;
1269 const struct intel_bw_state *old_bw_state = NULL;
1270 const struct intel_cdclk_state *cdclk_state;
1271 const struct intel_crtc_state *crtc_state;
1272 int old_min_cdclk, new_min_cdclk;
1273 struct intel_crtc *crtc;
1274 int i;
1275
1276 if (DISPLAY_VER(dev_priv) < 9)
1277 return 0;
1278
1279 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
1280 new_bw_state = intel_atomic_get_bw_state(state);
1281 if (IS_ERR(new_bw_state))
1282 return PTR_ERR(new_bw_state);
1283
1284 old_bw_state = intel_atomic_get_old_bw_state(state);
1285
1286 skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);
1287
1288 new_bw_state->min_cdclk[crtc->pipe] =
1289 intel_bw_crtc_min_cdclk(crtc_state);
1290 }
1291
1292 if (!old_bw_state)
1293 return 0;
1294
1295 if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {
1296 int ret = intel_atomic_lock_global_state(&new_bw_state->base);
1297 if (ret)
1298 return ret;
1299 }
1300
1301 old_min_cdclk = intel_bw_min_cdclk(dev_priv, old_bw_state);
1302 new_min_cdclk = intel_bw_min_cdclk(dev_priv, new_bw_state);
1303
1304 /*
1305 * No need to check against the cdclk state if
1306 * the min cdclk doesn't increase.
1307 *
1308 * Ie. we only ever increase the cdclk due to bandwidth
1309 * requirements. This can reduce back and forth
1310 * display blinking due to constant cdclk changes.
1311 */
1312 if (new_min_cdclk <= old_min_cdclk)
1313 return 0;
1314
1315 cdclk_state = intel_atomic_get_cdclk_state(state);
1316 if (IS_ERR(cdclk_state))
1317 return PTR_ERR(cdclk_state);
1318
1319 /*
1320 * No need to recalculate the cdclk state if
1321 * the min cdclk doesn't increase.
1322 *
1323 * Ie. we only ever increase the cdclk due to bandwidth
1324 * requirements. This can reduce back and forth
1325 * display blinking due to constant cdclk changes.
1326 */
1327 if (new_min_cdclk <= cdclk_state->bw_min_cdclk)
1328 return 0;
1329
1330 drm_dbg_kms(&dev_priv->drm,
1331 "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n",
1332 new_min_cdclk, cdclk_state->bw_min_cdclk);
1333 *need_cdclk_calc = true;
1334
1335 return 0;
1336}
1337
1338static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *changed)
1339{
1340 struct drm_i915_private *i915 = to_i915(state->base.dev);
1341 const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1342 struct intel_crtc *crtc;
1343 int i;
1344
1345 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
1346 new_crtc_state, i) {
1347 unsigned int old_data_rate =
1348 intel_bw_crtc_data_rate(old_crtc_state);
1349 unsigned int new_data_rate =
1350 intel_bw_crtc_data_rate(new_crtc_state);
1351 unsigned int old_active_planes =
1352 intel_bw_crtc_num_active_planes(old_crtc_state);
1353 unsigned int new_active_planes =
1354 intel_bw_crtc_num_active_planes(new_crtc_state);
1355 struct intel_bw_state *new_bw_state;
1356
1357 /*
1358 * Avoid locking the bw state when
1359 * nothing significant has changed.
1360 */
1361 if (old_data_rate == new_data_rate &&
1362 old_active_planes == new_active_planes)
1363 continue;
1364
1365 new_bw_state = intel_atomic_get_bw_state(state);
1366 if (IS_ERR(new_bw_state))
1367 return PTR_ERR(new_bw_state);
1368
1369 new_bw_state->data_rate[crtc->pipe] = new_data_rate;
1370 new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
1371
1372 *changed = true;
1373
1374 drm_dbg_kms(&i915->drm,
1375 "[CRTC:%d:%s] data rate %u num active planes %u\n",
1376 crtc->base.base.id, crtc->base.name,
1377 new_bw_state->data_rate[crtc->pipe],
1378 new_bw_state->num_active_planes[crtc->pipe]);
1379 }
1380
1381 return 0;
1382}
1383
1384int intel_bw_atomic_check(struct intel_atomic_state *state)
1385{
1386 bool changed = false;
1387 struct drm_i915_private *i915 = to_i915(state->base.dev);
1388 struct intel_bw_state *new_bw_state;
1389 const struct intel_bw_state *old_bw_state;
1390 int ret;
1391
1392 /* FIXME earlier gens need some checks too */
1393 if (DISPLAY_VER(i915) < 11)
1394 return 0;
1395
1396 ret = intel_bw_check_data_rate(state, &changed);
1397 if (ret)
1398 return ret;
1399
1400 old_bw_state = intel_atomic_get_old_bw_state(state);
1401 new_bw_state = intel_atomic_get_new_bw_state(state);
1402
1403 if (new_bw_state &&
1404 (intel_can_enable_sagv(i915, old_bw_state) !=
1405 intel_can_enable_sagv(i915, new_bw_state) ||
1406 new_bw_state->force_check_qgv))
1407 changed = true;
1408
1409 /*
1410 * If none of our inputs (data rates, number of active
1411 * planes, SAGV yes/no) changed then nothing to do here.
1412 */
1413 if (!changed)
1414 return 0;
1415
1416 ret = intel_bw_check_qgv_points(i915, old_bw_state, new_bw_state);
1417 if (ret)
1418 return ret;
1419
1420 new_bw_state->force_check_qgv = false;
1421
1422 return 0;
1423}
1424
1425static struct intel_global_state *
1426intel_bw_duplicate_state(struct intel_global_obj *obj)
1427{
1428 struct intel_bw_state *state;
1429
1430 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
1431 if (!state)
1432 return NULL;
1433
1434 return &state->base;
1435}
1436
1437static void intel_bw_destroy_state(struct intel_global_obj *obj,
1438 struct intel_global_state *state)
1439{
1440 kfree(state);
1441}
1442
1443static const struct intel_global_state_funcs intel_bw_funcs = {
1444 .atomic_duplicate_state = intel_bw_duplicate_state,
1445 .atomic_destroy_state = intel_bw_destroy_state,
1446};
1447
1448int intel_bw_init(struct drm_i915_private *i915)
1449{
1450 struct intel_bw_state *state;
1451
1452 state = kzalloc(sizeof(*state), GFP_KERNEL);
1453 if (!state)
1454 return -ENOMEM;
1455
1456 intel_atomic_global_obj_init(i915, &i915->display.bw.obj,
1457 &state->base, &intel_bw_funcs);
1458
1459 /*
1460 * Limit this only if we have SAGV. And for Display version 14 onwards
1461 * sagv is handled though pmdemand requests
1462 */
1463 if (intel_has_sagv(i915) && IS_DISPLAY_VER(i915, 11, 13))
1464 icl_force_disable_sagv(i915, state);
1465
1466 return 0;
1467}
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#include <drm/drm_atomic_state_helper.h>
7
8#include "i915_drv.h"
9#include "i915_reg.h"
10#include "i915_utils.h"
11#include "intel_atomic.h"
12#include "intel_bw.h"
13#include "intel_cdclk.h"
14#include "intel_display_core.h"
15#include "intel_display_types.h"
16#include "skl_watermark.h"
17#include "intel_mchbar_regs.h"
18#include "intel_pcode.h"
19
20/* Parameters for Qclk Geyserville (QGV) */
21struct intel_qgv_point {
22 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
23};
24
25struct intel_psf_gv_point {
26 u8 clk; /* clock in multiples of 16.6666 MHz */
27};
28
29struct intel_qgv_info {
30 struct intel_qgv_point points[I915_NUM_QGV_POINTS];
31 struct intel_psf_gv_point psf_points[I915_NUM_PSF_GV_POINTS];
32 u8 num_points;
33 u8 num_psf_points;
34 u8 t_bl;
35 u8 max_numchannels;
36 u8 channel_width;
37 u8 deinterleave;
38};
39
40static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
41 struct intel_qgv_point *sp,
42 int point)
43{
44 u32 dclk_ratio, dclk_reference;
45 u32 val;
46
47 val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
48 dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val);
49 if (val & DG1_QCLK_REFERENCE)
50 dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
51 else
52 dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
53 sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000);
54
55 val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
56 if (val & DG1_GEAR_TYPE)
57 sp->dclk *= 2;
58
59 if (sp->dclk == 0)
60 return -EINVAL;
61
62 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
63 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val);
64 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val);
65
66 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
67 sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val);
68 sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val);
69
70 sp->t_rc = sp->t_rp + sp->t_ras;
71
72 return 0;
73}
74
75static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
76 struct intel_qgv_point *sp,
77 int point)
78{
79 u32 val = 0, val2 = 0;
80 u16 dclk;
81 int ret;
82
83 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
84 ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
85 &val, &val2);
86 if (ret)
87 return ret;
88
89 dclk = val & 0xffff;
90 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > 11 ? 500 : 0), 1000);
91 sp->t_rp = (val & 0xff0000) >> 16;
92 sp->t_rcd = (val & 0xff000000) >> 24;
93
94 sp->t_rdpre = val2 & 0xff;
95 sp->t_ras = (val2 & 0xff00) >> 8;
96
97 sp->t_rc = sp->t_rp + sp->t_ras;
98
99 return 0;
100}
101
102static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
103 struct intel_psf_gv_point *points)
104{
105 u32 val = 0;
106 int ret;
107 int i;
108
109 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
110 ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
111 if (ret)
112 return ret;
113
114 for (i = 0; i < I915_NUM_PSF_GV_POINTS; i++) {
115 points[i].clk = val & 0xff;
116 val >>= 8;
117 }
118
119 return 0;
120}
121
122int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
123 u32 points_mask)
124{
125 int ret;
126
127 /* bspec says to keep retrying for at least 1 ms */
128 ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
129 points_mask,
130 ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
131 ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
132 1);
133
134 if (ret < 0) {
135 drm_err(&dev_priv->drm, "Failed to disable qgv points (%d) points: 0x%x\n", ret, points_mask);
136 return ret;
137 }
138
139 return 0;
140}
141
142static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
143 struct intel_qgv_point *sp, int point)
144{
145 u32 val, val2;
146 u16 dclk;
147
148 val = intel_uncore_read(&dev_priv->uncore,
149 MTL_MEM_SS_INFO_QGV_POINT_LOW(point));
150 val2 = intel_uncore_read(&dev_priv->uncore,
151 MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
152 dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
153 sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000);
154 sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
155 sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
156
157 sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2);
158 sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2);
159
160 sp->t_rc = sp->t_rp + sp->t_ras;
161
162 return 0;
163}
164
165static int
166intel_read_qgv_point_info(struct drm_i915_private *dev_priv,
167 struct intel_qgv_point *sp,
168 int point)
169{
170 if (DISPLAY_VER(dev_priv) >= 14)
171 return mtl_read_qgv_point_info(dev_priv, sp, point);
172 else if (IS_DG1(dev_priv))
173 return dg1_mchbar_read_qgv_point_info(dev_priv, sp, point);
174 else
175 return icl_pcode_read_qgv_point_info(dev_priv, sp, point);
176}
177
178static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
179 struct intel_qgv_info *qi,
180 bool is_y_tile)
181{
182 const struct dram_info *dram_info = &dev_priv->dram_info;
183 int i, ret;
184
185 qi->num_points = dram_info->num_qgv_points;
186 qi->num_psf_points = dram_info->num_psf_gv_points;
187
188 if (DISPLAY_VER(dev_priv) >= 14) {
189 switch (dram_info->type) {
190 case INTEL_DRAM_DDR4:
191 qi->t_bl = 4;
192 qi->max_numchannels = 2;
193 qi->channel_width = 64;
194 qi->deinterleave = 2;
195 break;
196 case INTEL_DRAM_DDR5:
197 qi->t_bl = 8;
198 qi->max_numchannels = 4;
199 qi->channel_width = 32;
200 qi->deinterleave = 2;
201 break;
202 case INTEL_DRAM_LPDDR4:
203 case INTEL_DRAM_LPDDR5:
204 qi->t_bl = 16;
205 qi->max_numchannels = 8;
206 qi->channel_width = 16;
207 qi->deinterleave = 4;
208 break;
209 default:
210 MISSING_CASE(dram_info->type);
211 return -EINVAL;
212 }
213 } else if (DISPLAY_VER(dev_priv) >= 12) {
214 switch (dram_info->type) {
215 case INTEL_DRAM_DDR4:
216 qi->t_bl = is_y_tile ? 8 : 4;
217 qi->max_numchannels = 2;
218 qi->channel_width = 64;
219 qi->deinterleave = is_y_tile ? 1 : 2;
220 break;
221 case INTEL_DRAM_DDR5:
222 qi->t_bl = is_y_tile ? 16 : 8;
223 qi->max_numchannels = 4;
224 qi->channel_width = 32;
225 qi->deinterleave = is_y_tile ? 1 : 2;
226 break;
227 case INTEL_DRAM_LPDDR4:
228 if (IS_ROCKETLAKE(dev_priv)) {
229 qi->t_bl = 8;
230 qi->max_numchannels = 4;
231 qi->channel_width = 32;
232 qi->deinterleave = 2;
233 break;
234 }
235 fallthrough;
236 case INTEL_DRAM_LPDDR5:
237 qi->t_bl = 16;
238 qi->max_numchannels = 8;
239 qi->channel_width = 16;
240 qi->deinterleave = is_y_tile ? 2 : 4;
241 break;
242 default:
243 qi->t_bl = 16;
244 qi->max_numchannels = 1;
245 break;
246 }
247 } else if (DISPLAY_VER(dev_priv) == 11) {
248 qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
249 qi->max_numchannels = 1;
250 }
251
252 if (drm_WARN_ON(&dev_priv->drm,
253 qi->num_points > ARRAY_SIZE(qi->points)))
254 qi->num_points = ARRAY_SIZE(qi->points);
255
256 for (i = 0; i < qi->num_points; i++) {
257 struct intel_qgv_point *sp = &qi->points[i];
258
259 ret = intel_read_qgv_point_info(dev_priv, sp, i);
260 if (ret)
261 return ret;
262
263 drm_dbg_kms(&dev_priv->drm,
264 "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n",
265 i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras,
266 sp->t_rcd, sp->t_rc);
267 }
268
269 if (qi->num_psf_points > 0) {
270 ret = adls_pcode_read_psf_gv_point_info(dev_priv, qi->psf_points);
271 if (ret) {
272 drm_err(&dev_priv->drm, "Failed to read PSF point data; PSF points will not be considered in bandwidth calculations.\n");
273 qi->num_psf_points = 0;
274 }
275
276 for (i = 0; i < qi->num_psf_points; i++)
277 drm_dbg_kms(&dev_priv->drm,
278 "PSF GV %d: CLK=%d \n",
279 i, qi->psf_points[i].clk);
280 }
281
282 return 0;
283}
284
285static int adl_calc_psf_bw(int clk)
286{
287 /*
288 * clk is multiples of 16.666MHz (100/6)
289 * According to BSpec PSF GV bandwidth is
290 * calculated as BW = 64 * clk * 16.666Mhz
291 */
292 return DIV_ROUND_CLOSEST(64 * clk * 100, 6);
293}
294
295static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
296{
297 u16 dclk = 0;
298 int i;
299
300 for (i = 0; i < qi->num_points; i++)
301 dclk = max(dclk, qi->points[i].dclk);
302
303 return dclk;
304}
305
306struct intel_sa_info {
307 u16 displayrtids;
308 u8 deburst, deprogbwlimit, derating;
309};
310
311static const struct intel_sa_info icl_sa_info = {
312 .deburst = 8,
313 .deprogbwlimit = 25, /* GB/s */
314 .displayrtids = 128,
315 .derating = 10,
316};
317
318static const struct intel_sa_info tgl_sa_info = {
319 .deburst = 16,
320 .deprogbwlimit = 34, /* GB/s */
321 .displayrtids = 256,
322 .derating = 10,
323};
324
325static const struct intel_sa_info rkl_sa_info = {
326 .deburst = 8,
327 .deprogbwlimit = 20, /* GB/s */
328 .displayrtids = 128,
329 .derating = 10,
330};
331
332static const struct intel_sa_info adls_sa_info = {
333 .deburst = 16,
334 .deprogbwlimit = 38, /* GB/s */
335 .displayrtids = 256,
336 .derating = 10,
337};
338
339static const struct intel_sa_info adlp_sa_info = {
340 .deburst = 16,
341 .deprogbwlimit = 38, /* GB/s */
342 .displayrtids = 256,
343 .derating = 20,
344};
345
346static const struct intel_sa_info mtl_sa_info = {
347 .deburst = 32,
348 .deprogbwlimit = 38, /* GB/s */
349 .displayrtids = 256,
350 .derating = 20,
351};
352
353static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
354{
355 struct intel_qgv_info qi = {};
356 bool is_y_tile = true; /* assume y tile may be used */
357 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
358 int ipqdepth, ipqdepthpch = 16;
359 int dclk_max;
360 int maxdebw;
361 int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
362 int i, ret;
363
364 ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
365 if (ret) {
366 drm_dbg_kms(&dev_priv->drm,
367 "Failed to get memory subsystem information, ignoring bandwidth limits");
368 return ret;
369 }
370
371 dclk_max = icl_sagv_max_dclk(&qi);
372 maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
373 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
374 qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
375
376 for (i = 0; i < num_groups; i++) {
377 struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
378 int clpchgroup;
379 int j;
380
381 clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
382 bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
383
384 bi->num_qgv_points = qi.num_points;
385 bi->num_psf_gv_points = qi.num_psf_points;
386
387 for (j = 0; j < qi.num_points; j++) {
388 const struct intel_qgv_point *sp = &qi.points[j];
389 int ct, bw;
390
391 /*
392 * Max row cycle time
393 *
394 * FIXME what is the logic behind the
395 * assumed burst length?
396 */
397 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
398 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
399 bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
400
401 bi->deratedbw[j] = min(maxdebw,
402 bw * (100 - sa->derating) / 100);
403
404 drm_dbg_kms(&dev_priv->drm,
405 "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
406 i, j, bi->num_planes, bi->deratedbw[j]);
407 }
408 }
409 /*
410 * In case if SAGV is disabled in BIOS, we always get 1
411 * SAGV point, but we can't send PCode commands to restrict it
412 * as it will fail and pointless anyway.
413 */
414 if (qi.num_points == 1)
415 dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
416 else
417 dev_priv->display.sagv.status = I915_SAGV_ENABLED;
418
419 return 0;
420}
421
422static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
423{
424 struct intel_qgv_info qi = {};
425 const struct dram_info *dram_info = &dev_priv->dram_info;
426 bool is_y_tile = true; /* assume y tile may be used */
427 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
428 int ipqdepth, ipqdepthpch = 16;
429 int dclk_max;
430 int maxdebw, peakbw;
431 int clperchgroup;
432 int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
433 int i, ret;
434
435 ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
436 if (ret) {
437 drm_dbg_kms(&dev_priv->drm,
438 "Failed to get memory subsystem information, ignoring bandwidth limits");
439 return ret;
440 }
441
442 if (DISPLAY_VER(dev_priv) < 14 &&
443 (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5))
444 num_channels *= 2;
445
446 qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
447
448 if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12)
449 qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1);
450
451 if (DISPLAY_VER(dev_priv) > 11 && num_channels > qi.max_numchannels)
452 drm_warn(&dev_priv->drm, "Number of channels exceeds max number of channels.");
453 if (qi.max_numchannels != 0)
454 num_channels = min_t(u8, num_channels, qi.max_numchannels);
455
456 dclk_max = icl_sagv_max_dclk(&qi);
457
458 peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
459 maxdebw = min(sa->deprogbwlimit * 1000, peakbw * 6 / 10); /* 60% */
460
461 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
462 /*
463 * clperchgroup = 4kpagespermempage * clperchperblock,
464 * clperchperblock = 8 / num_channels * interleave
465 */
466 clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * qi.deinterleave;
467
468 for (i = 0; i < num_groups; i++) {
469 struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
470 struct intel_bw_info *bi_next;
471 int clpchgroup;
472 int j;
473
474 clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
475
476 if (i < num_groups - 1) {
477 bi_next = &dev_priv->display.bw.max[i + 1];
478
479 if (clpchgroup < clperchgroup)
480 bi_next->num_planes = (ipqdepth - clpchgroup) /
481 clpchgroup + 1;
482 else
483 bi_next->num_planes = 0;
484 }
485
486 bi->num_qgv_points = qi.num_points;
487 bi->num_psf_gv_points = qi.num_psf_points;
488
489 for (j = 0; j < qi.num_points; j++) {
490 const struct intel_qgv_point *sp = &qi.points[j];
491 int ct, bw;
492
493 /*
494 * Max row cycle time
495 *
496 * FIXME what is the logic behind the
497 * assumed burst length?
498 */
499 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
500 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
501 bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
502
503 bi->deratedbw[j] = min(maxdebw,
504 bw * (100 - sa->derating) / 100);
505
506 drm_dbg_kms(&dev_priv->drm,
507 "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
508 i, j, bi->num_planes, bi->deratedbw[j]);
509 }
510
511 for (j = 0; j < qi.num_psf_points; j++) {
512 const struct intel_psf_gv_point *sp = &qi.psf_points[j];
513
514 bi->psf_bw[j] = adl_calc_psf_bw(sp->clk);
515
516 drm_dbg_kms(&dev_priv->drm,
517 "BW%d / PSF GV %d: num_planes=%d bw=%u\n",
518 i, j, bi->num_planes, bi->psf_bw[j]);
519 }
520 }
521
522 /*
523 * In case if SAGV is disabled in BIOS, we always get 1
524 * SAGV point, but we can't send PCode commands to restrict it
525 * as it will fail and pointless anyway.
526 */
527 if (qi.num_points == 1)
528 dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
529 else
530 dev_priv->display.sagv.status = I915_SAGV_ENABLED;
531
532 return 0;
533}
534
535static void dg2_get_bw_info(struct drm_i915_private *i915)
536{
537 unsigned int deratedbw = IS_DG2_G11(i915) ? 38000 : 50000;
538 int num_groups = ARRAY_SIZE(i915->display.bw.max);
539 int i;
540
541 /*
542 * DG2 doesn't have SAGV or QGV points, just a constant max bandwidth
543 * that doesn't depend on the number of planes enabled. So fill all the
544 * plane group with constant bw information for uniformity with other
545 * platforms. DG2-G10 platforms have a constant 50 GB/s bandwidth,
546 * whereas DG2-G11 platforms have 38 GB/s.
547 */
548 for (i = 0; i < num_groups; i++) {
549 struct intel_bw_info *bi = &i915->display.bw.max[i];
550
551 bi->num_planes = 1;
552 /* Need only one dummy QGV point per group */
553 bi->num_qgv_points = 1;
554 bi->deratedbw[0] = deratedbw;
555 }
556
557 i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
558}
559
560static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
561 int num_planes, int qgv_point)
562{
563 int i;
564
565 /*
566 * Let's return max bw for 0 planes
567 */
568 num_planes = max(1, num_planes);
569
570 for (i = 0; i < ARRAY_SIZE(dev_priv->display.bw.max); i++) {
571 const struct intel_bw_info *bi =
572 &dev_priv->display.bw.max[i];
573
574 /*
575 * Pcode will not expose all QGV points when
576 * SAGV is forced to off/min/med/max.
577 */
578 if (qgv_point >= bi->num_qgv_points)
579 return UINT_MAX;
580
581 if (num_planes >= bi->num_planes)
582 return bi->deratedbw[qgv_point];
583 }
584
585 return 0;
586}
587
588static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
589 int num_planes, int qgv_point)
590{
591 int i;
592
593 /*
594 * Let's return max bw for 0 planes
595 */
596 num_planes = max(1, num_planes);
597
598 for (i = ARRAY_SIZE(dev_priv->display.bw.max) - 1; i >= 0; i--) {
599 const struct intel_bw_info *bi =
600 &dev_priv->display.bw.max[i];
601
602 /*
603 * Pcode will not expose all QGV points when
604 * SAGV is forced to off/min/med/max.
605 */
606 if (qgv_point >= bi->num_qgv_points)
607 return UINT_MAX;
608
609 if (num_planes <= bi->num_planes)
610 return bi->deratedbw[qgv_point];
611 }
612
613 return dev_priv->display.bw.max[0].deratedbw[qgv_point];
614}
615
616static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
617 int psf_gv_point)
618{
619 const struct intel_bw_info *bi =
620 &dev_priv->display.bw.max[0];
621
622 return bi->psf_bw[psf_gv_point];
623}
624
625void intel_bw_init_hw(struct drm_i915_private *dev_priv)
626{
627 if (!HAS_DISPLAY(dev_priv))
628 return;
629
630 if (DISPLAY_VER(dev_priv) >= 14)
631 tgl_get_bw_info(dev_priv, &mtl_sa_info);
632 else if (IS_DG2(dev_priv))
633 dg2_get_bw_info(dev_priv);
634 else if (IS_ALDERLAKE_P(dev_priv))
635 tgl_get_bw_info(dev_priv, &adlp_sa_info);
636 else if (IS_ALDERLAKE_S(dev_priv))
637 tgl_get_bw_info(dev_priv, &adls_sa_info);
638 else if (IS_ROCKETLAKE(dev_priv))
639 tgl_get_bw_info(dev_priv, &rkl_sa_info);
640 else if (DISPLAY_VER(dev_priv) == 12)
641 tgl_get_bw_info(dev_priv, &tgl_sa_info);
642 else if (DISPLAY_VER(dev_priv) == 11)
643 icl_get_bw_info(dev_priv, &icl_sa_info);
644}
645
646static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
647{
648 /*
649 * We assume cursors are small enough
650 * to not not cause bandwidth problems.
651 */
652 return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
653}
654
655static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
656{
657 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
658 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
659 unsigned int data_rate = 0;
660 enum plane_id plane_id;
661
662 for_each_plane_id_on_crtc(crtc, plane_id) {
663 /*
664 * We assume cursors are small enough
665 * to not not cause bandwidth problems.
666 */
667 if (plane_id == PLANE_CURSOR)
668 continue;
669
670 data_rate += crtc_state->data_rate[plane_id];
671
672 if (DISPLAY_VER(i915) < 11)
673 data_rate += crtc_state->data_rate_y[plane_id];
674 }
675
676 return data_rate;
677}
678
679/* "Maximum Pipe Read Bandwidth" */
680static int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
681{
682 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
683 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
684
685 if (DISPLAY_VER(i915) < 12)
686 return 0;
687
688 return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);
689}
690
691void intel_bw_crtc_update(struct intel_bw_state *bw_state,
692 const struct intel_crtc_state *crtc_state)
693{
694 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
695 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
696
697 bw_state->data_rate[crtc->pipe] =
698 intel_bw_crtc_data_rate(crtc_state);
699 bw_state->num_active_planes[crtc->pipe] =
700 intel_bw_crtc_num_active_planes(crtc_state);
701
702 drm_dbg_kms(&i915->drm, "pipe %c data rate %u num active planes %u\n",
703 pipe_name(crtc->pipe),
704 bw_state->data_rate[crtc->pipe],
705 bw_state->num_active_planes[crtc->pipe]);
706}
707
708static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv,
709 const struct intel_bw_state *bw_state)
710{
711 unsigned int num_active_planes = 0;
712 enum pipe pipe;
713
714 for_each_pipe(dev_priv, pipe)
715 num_active_planes += bw_state->num_active_planes[pipe];
716
717 return num_active_planes;
718}
719
720static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
721 const struct intel_bw_state *bw_state)
722{
723 unsigned int data_rate = 0;
724 enum pipe pipe;
725
726 for_each_pipe(dev_priv, pipe)
727 data_rate += bw_state->data_rate[pipe];
728
729 if (DISPLAY_VER(dev_priv) >= 13 && i915_vtd_active(dev_priv))
730 data_rate = DIV_ROUND_UP(data_rate * 105, 100);
731
732 return data_rate;
733}
734
735struct intel_bw_state *
736intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
737{
738 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
739 struct intel_global_state *bw_state;
740
741 bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->display.bw.obj);
742
743 return to_intel_bw_state(bw_state);
744}
745
746struct intel_bw_state *
747intel_atomic_get_new_bw_state(struct intel_atomic_state *state)
748{
749 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
750 struct intel_global_state *bw_state;
751
752 bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->display.bw.obj);
753
754 return to_intel_bw_state(bw_state);
755}
756
757struct intel_bw_state *
758intel_atomic_get_bw_state(struct intel_atomic_state *state)
759{
760 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
761 struct intel_global_state *bw_state;
762
763 bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.bw.obj);
764 if (IS_ERR(bw_state))
765 return ERR_CAST(bw_state);
766
767 return to_intel_bw_state(bw_state);
768}
769
770static bool intel_bw_state_changed(struct drm_i915_private *i915,
771 const struct intel_bw_state *old_bw_state,
772 const struct intel_bw_state *new_bw_state)
773{
774 enum pipe pipe;
775
776 for_each_pipe(i915, pipe) {
777 const struct intel_dbuf_bw *old_crtc_bw =
778 &old_bw_state->dbuf_bw[pipe];
779 const struct intel_dbuf_bw *new_crtc_bw =
780 &new_bw_state->dbuf_bw[pipe];
781 enum dbuf_slice slice;
782
783 for_each_dbuf_slice(i915, slice) {
784 if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
785 old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
786 return true;
787 }
788
789 if (old_bw_state->min_cdclk[pipe] != new_bw_state->min_cdclk[pipe])
790 return true;
791 }
792
793 return false;
794}
795
796static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
797 struct intel_crtc *crtc,
798 enum plane_id plane_id,
799 const struct skl_ddb_entry *ddb,
800 unsigned int data_rate)
801{
802 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
803 struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
804 unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
805 enum dbuf_slice slice;
806
807 /*
808 * The arbiter can only really guarantee an
809 * equal share of the total bw to each plane.
810 */
811 for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
812 crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
813 crtc_bw->active_planes[slice] |= BIT(plane_id);
814 }
815}
816
817static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
818 const struct intel_crtc_state *crtc_state)
819{
820 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
821 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
822 struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
823 enum plane_id plane_id;
824
825 memset(crtc_bw, 0, sizeof(*crtc_bw));
826
827 if (!crtc_state->hw.active)
828 return;
829
830 for_each_plane_id_on_crtc(crtc, plane_id) {
831 /*
832 * We assume cursors are small enough
833 * to not cause bandwidth problems.
834 */
835 if (plane_id == PLANE_CURSOR)
836 continue;
837
838 skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
839 &crtc_state->wm.skl.plane_ddb[plane_id],
840 crtc_state->data_rate[plane_id]);
841
842 if (DISPLAY_VER(i915) < 11)
843 skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
844 &crtc_state->wm.skl.plane_ddb_y[plane_id],
845 crtc_state->data_rate[plane_id]);
846 }
847}
848
849/* "Maximum Data Buffer Bandwidth" */
850static int
851intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
852 const struct intel_bw_state *bw_state)
853{
854 unsigned int total_max_bw = 0;
855 enum dbuf_slice slice;
856
857 for_each_dbuf_slice(i915, slice) {
858 int num_active_planes = 0;
859 unsigned int max_bw = 0;
860 enum pipe pipe;
861
862 /*
863 * The arbiter can only really guarantee an
864 * equal share of the total bw to each plane.
865 */
866 for_each_pipe(i915, pipe) {
867 const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe];
868
869 max_bw = max(crtc_bw->max_bw[slice], max_bw);
870 num_active_planes += hweight8(crtc_bw->active_planes[slice]);
871 }
872 max_bw *= num_active_planes;
873
874 total_max_bw = max(total_max_bw, max_bw);
875 }
876
877 return DIV_ROUND_UP(total_max_bw, 64);
878}
879
880int intel_bw_min_cdclk(struct drm_i915_private *i915,
881 const struct intel_bw_state *bw_state)
882{
883 enum pipe pipe;
884 int min_cdclk;
885
886 min_cdclk = intel_bw_dbuf_min_cdclk(i915, bw_state);
887
888 for_each_pipe(i915, pipe)
889 min_cdclk = max(bw_state->min_cdclk[pipe], min_cdclk);
890
891 return min_cdclk;
892}
893
894int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
895 bool *need_cdclk_calc)
896{
897 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
898 struct intel_bw_state *new_bw_state = NULL;
899 const struct intel_bw_state *old_bw_state = NULL;
900 const struct intel_cdclk_state *cdclk_state;
901 const struct intel_crtc_state *crtc_state;
902 int old_min_cdclk, new_min_cdclk;
903 struct intel_crtc *crtc;
904 int i;
905
906 if (DISPLAY_VER(dev_priv) < 9)
907 return 0;
908
909 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
910 new_bw_state = intel_atomic_get_bw_state(state);
911 if (IS_ERR(new_bw_state))
912 return PTR_ERR(new_bw_state);
913
914 old_bw_state = intel_atomic_get_old_bw_state(state);
915
916 skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);
917
918 new_bw_state->min_cdclk[crtc->pipe] =
919 intel_bw_crtc_min_cdclk(crtc_state);
920 }
921
922 if (!old_bw_state)
923 return 0;
924
925 if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {
926 int ret = intel_atomic_lock_global_state(&new_bw_state->base);
927 if (ret)
928 return ret;
929 }
930
931 old_min_cdclk = intel_bw_min_cdclk(dev_priv, old_bw_state);
932 new_min_cdclk = intel_bw_min_cdclk(dev_priv, new_bw_state);
933
934 /*
935 * No need to check against the cdclk state if
936 * the min cdclk doesn't increase.
937 *
938 * Ie. we only ever increase the cdclk due to bandwidth
939 * requirements. This can reduce back and forth
940 * display blinking due to constant cdclk changes.
941 */
942 if (new_min_cdclk <= old_min_cdclk)
943 return 0;
944
945 cdclk_state = intel_atomic_get_cdclk_state(state);
946 if (IS_ERR(cdclk_state))
947 return PTR_ERR(cdclk_state);
948
949 /*
950 * No need to recalculate the cdclk state if
951 * the min cdclk doesn't increase.
952 *
953 * Ie. we only ever increase the cdclk due to bandwidth
954 * requirements. This can reduce back and forth
955 * display blinking due to constant cdclk changes.
956 */
957 if (new_min_cdclk <= cdclk_state->bw_min_cdclk)
958 return 0;
959
960 drm_dbg_kms(&dev_priv->drm,
961 "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n",
962 new_min_cdclk, cdclk_state->bw_min_cdclk);
963 *need_cdclk_calc = true;
964
965 return 0;
966}
967
968static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
969{
970 unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
971 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
972 u16 qgv_points = 0, psf_points = 0;
973
974 /*
975 * We can _not_ use the whole ADLS_QGV_PT_MASK here, as PCode rejects
976 * it with failure if we try masking any unadvertised points.
977 * So need to operate only with those returned from PCode.
978 */
979 if (num_qgv_points > 0)
980 qgv_points = GENMASK(num_qgv_points - 1, 0);
981
982 if (num_psf_gv_points > 0)
983 psf_points = GENMASK(num_psf_gv_points - 1, 0);
984
985 return ICL_PCODE_REQ_QGV_PT(qgv_points) | ADLS_PCODE_REQ_PSF_PT(psf_points);
986}
987
988static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *changed)
989{
990 struct drm_i915_private *i915 = to_i915(state->base.dev);
991 const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
992 struct intel_crtc *crtc;
993 int i;
994
995 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
996 new_crtc_state, i) {
997 unsigned int old_data_rate =
998 intel_bw_crtc_data_rate(old_crtc_state);
999 unsigned int new_data_rate =
1000 intel_bw_crtc_data_rate(new_crtc_state);
1001 unsigned int old_active_planes =
1002 intel_bw_crtc_num_active_planes(old_crtc_state);
1003 unsigned int new_active_planes =
1004 intel_bw_crtc_num_active_planes(new_crtc_state);
1005 struct intel_bw_state *new_bw_state;
1006
1007 /*
1008 * Avoid locking the bw state when
1009 * nothing significant has changed.
1010 */
1011 if (old_data_rate == new_data_rate &&
1012 old_active_planes == new_active_planes)
1013 continue;
1014
1015 new_bw_state = intel_atomic_get_bw_state(state);
1016 if (IS_ERR(new_bw_state))
1017 return PTR_ERR(new_bw_state);
1018
1019 new_bw_state->data_rate[crtc->pipe] = new_data_rate;
1020 new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
1021
1022 *changed = true;
1023
1024 drm_dbg_kms(&i915->drm,
1025 "[CRTC:%d:%s] data rate %u num active planes %u\n",
1026 crtc->base.base.id, crtc->base.name,
1027 new_bw_state->data_rate[crtc->pipe],
1028 new_bw_state->num_active_planes[crtc->pipe]);
1029 }
1030
1031 return 0;
1032}
1033
1034int intel_bw_atomic_check(struct intel_atomic_state *state)
1035{
1036 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1037 const struct intel_bw_state *old_bw_state;
1038 struct intel_bw_state *new_bw_state;
1039 unsigned int data_rate;
1040 unsigned int num_active_planes;
1041 int i, ret;
1042 u16 qgv_points = 0, psf_points = 0;
1043 unsigned int max_bw_point = 0, max_bw = 0;
1044 unsigned int num_qgv_points = dev_priv->display.bw.max[0].num_qgv_points;
1045 unsigned int num_psf_gv_points = dev_priv->display.bw.max[0].num_psf_gv_points;
1046 bool changed = false;
1047
1048 /* FIXME earlier gens need some checks too */
1049 if (DISPLAY_VER(dev_priv) < 11)
1050 return 0;
1051
1052 ret = intel_bw_check_data_rate(state, &changed);
1053 if (ret)
1054 return ret;
1055
1056 old_bw_state = intel_atomic_get_old_bw_state(state);
1057 new_bw_state = intel_atomic_get_new_bw_state(state);
1058
1059 if (new_bw_state &&
1060 intel_can_enable_sagv(dev_priv, old_bw_state) !=
1061 intel_can_enable_sagv(dev_priv, new_bw_state))
1062 changed = true;
1063
1064 /*
1065 * If none of our inputs (data rates, number of active
1066 * planes, SAGV yes/no) changed then nothing to do here.
1067 */
1068 if (!changed)
1069 return 0;
1070
1071 ret = intel_atomic_lock_global_state(&new_bw_state->base);
1072 if (ret)
1073 return ret;
1074
1075 data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
1076 data_rate = DIV_ROUND_UP(data_rate, 1000);
1077
1078 num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
1079
1080 for (i = 0; i < num_qgv_points; i++) {
1081 unsigned int max_data_rate;
1082
1083 if (DISPLAY_VER(dev_priv) > 11)
1084 max_data_rate = tgl_max_bw(dev_priv, num_active_planes, i);
1085 else
1086 max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
1087 /*
1088 * We need to know which qgv point gives us
1089 * maximum bandwidth in order to disable SAGV
1090 * if we find that we exceed SAGV block time
1091 * with watermarks. By that moment we already
1092 * have those, as it is calculated earlier in
1093 * intel_atomic_check,
1094 */
1095 if (max_data_rate > max_bw) {
1096 max_bw_point = i;
1097 max_bw = max_data_rate;
1098 }
1099 if (max_data_rate >= data_rate)
1100 qgv_points |= BIT(i);
1101
1102 drm_dbg_kms(&dev_priv->drm, "QGV point %d: max bw %d required %d\n",
1103 i, max_data_rate, data_rate);
1104 }
1105
1106 for (i = 0; i < num_psf_gv_points; i++) {
1107 unsigned int max_data_rate = adl_psf_bw(dev_priv, i);
1108
1109 if (max_data_rate >= data_rate)
1110 psf_points |= BIT(i);
1111
1112 drm_dbg_kms(&dev_priv->drm, "PSF GV point %d: max bw %d"
1113 " required %d\n",
1114 i, max_data_rate, data_rate);
1115 }
1116
1117 /*
1118 * BSpec states that we always should have at least one allowed point
1119 * left, so if we couldn't - simply reject the configuration for obvious
1120 * reasons.
1121 */
1122 if (qgv_points == 0) {
1123 drm_dbg_kms(&dev_priv->drm, "No QGV points provide sufficient memory"
1124 " bandwidth %d for display configuration(%d active planes).\n",
1125 data_rate, num_active_planes);
1126 return -EINVAL;
1127 }
1128
1129 if (num_psf_gv_points > 0 && psf_points == 0) {
1130 drm_dbg_kms(&dev_priv->drm, "No PSF GV points provide sufficient memory"
1131 " bandwidth %d for display configuration(%d active planes).\n",
1132 data_rate, num_active_planes);
1133 return -EINVAL;
1134 }
1135
1136 /*
1137 * Leave only single point with highest bandwidth, if
1138 * we can't enable SAGV due to the increased memory latency it may
1139 * cause.
1140 */
1141 if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
1142 qgv_points = BIT(max_bw_point);
1143 drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n",
1144 max_bw_point);
1145 }
1146
1147 /*
1148 * We store the ones which need to be masked as that is what PCode
1149 * actually accepts as a parameter.
1150 */
1151 new_bw_state->qgv_points_mask =
1152 ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
1153 ADLS_PCODE_REQ_PSF_PT(psf_points)) &
1154 icl_qgv_points_mask(dev_priv);
1155
1156 /*
1157 * If the actual mask had changed we need to make sure that
1158 * the commits are serialized(in case this is a nomodeset, nonblocking)
1159 */
1160 if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
1161 ret = intel_atomic_serialize_global_state(&new_bw_state->base);
1162 if (ret)
1163 return ret;
1164 }
1165
1166 return 0;
1167}
1168
1169static struct intel_global_state *
1170intel_bw_duplicate_state(struct intel_global_obj *obj)
1171{
1172 struct intel_bw_state *state;
1173
1174 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
1175 if (!state)
1176 return NULL;
1177
1178 return &state->base;
1179}
1180
1181static void intel_bw_destroy_state(struct intel_global_obj *obj,
1182 struct intel_global_state *state)
1183{
1184 kfree(state);
1185}
1186
1187static const struct intel_global_state_funcs intel_bw_funcs = {
1188 .atomic_duplicate_state = intel_bw_duplicate_state,
1189 .atomic_destroy_state = intel_bw_destroy_state,
1190};
1191
1192int intel_bw_init(struct drm_i915_private *dev_priv)
1193{
1194 struct intel_bw_state *state;
1195
1196 state = kzalloc(sizeof(*state), GFP_KERNEL);
1197 if (!state)
1198 return -ENOMEM;
1199
1200 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.bw.obj,
1201 &state->base, &intel_bw_funcs);
1202
1203 return 0;
1204}