1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2015-2018 Etnaviv Project
   4 */
   5
   6#include <linux/clk.h>
   7#include <linux/component.h>
   8#include <linux/delay.h>
   9#include <linux/dma-fence.h>
  10#include <linux/dma-mapping.h>
  11#include <linux/mod_devicetable.h>
  12#include <linux/module.h>
 
  13#include <linux/platform_device.h>
  14#include <linux/pm_runtime.h>
  15#include <linux/regulator/consumer.h>
  16#include <linux/thermal.h>
  17
  18#include "etnaviv_cmdbuf.h"
  19#include "etnaviv_dump.h"
  20#include "etnaviv_gpu.h"
  21#include "etnaviv_gem.h"
  22#include "etnaviv_mmu.h"
  23#include "etnaviv_perfmon.h"
  24#include "etnaviv_sched.h"
  25#include "common.xml.h"
  26#include "state.xml.h"
  27#include "state_hi.xml.h"
  28#include "cmdstream.xml.h"
  29
  30static const struct platform_device_id gpu_ids[] = {
  31	{ .name = "etnaviv-gpu,2d" },
  32	{ },
  33};
  34
  35/*
  36 * Driver functions:
  37 */
  38
  39int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
  40{
  41	struct etnaviv_drm_private *priv = gpu->drm->dev_private;
  42
  43	switch (param) {
  44	case ETNAVIV_PARAM_GPU_MODEL:
  45		*value = gpu->identity.model;
  46		break;
  47
  48	case ETNAVIV_PARAM_GPU_REVISION:
  49		*value = gpu->identity.revision;
  50		break;
  51
  52	case ETNAVIV_PARAM_GPU_FEATURES_0:
  53		*value = gpu->identity.features;
  54		break;
  55
  56	case ETNAVIV_PARAM_GPU_FEATURES_1:
  57		*value = gpu->identity.minor_features0;
  58		break;
  59
  60	case ETNAVIV_PARAM_GPU_FEATURES_2:
  61		*value = gpu->identity.minor_features1;
  62		break;
  63
  64	case ETNAVIV_PARAM_GPU_FEATURES_3:
  65		*value = gpu->identity.minor_features2;
  66		break;
  67
  68	case ETNAVIV_PARAM_GPU_FEATURES_4:
  69		*value = gpu->identity.minor_features3;
  70		break;
  71
  72	case ETNAVIV_PARAM_GPU_FEATURES_5:
  73		*value = gpu->identity.minor_features4;
  74		break;
  75
  76	case ETNAVIV_PARAM_GPU_FEATURES_6:
  77		*value = gpu->identity.minor_features5;
  78		break;
  79
  80	case ETNAVIV_PARAM_GPU_FEATURES_7:
  81		*value = gpu->identity.minor_features6;
  82		break;
  83
  84	case ETNAVIV_PARAM_GPU_FEATURES_8:
  85		*value = gpu->identity.minor_features7;
  86		break;
  87
  88	case ETNAVIV_PARAM_GPU_FEATURES_9:
  89		*value = gpu->identity.minor_features8;
  90		break;
  91
  92	case ETNAVIV_PARAM_GPU_FEATURES_10:
  93		*value = gpu->identity.minor_features9;
  94		break;
  95
  96	case ETNAVIV_PARAM_GPU_FEATURES_11:
  97		*value = gpu->identity.minor_features10;
  98		break;
  99
 100	case ETNAVIV_PARAM_GPU_FEATURES_12:
 101		*value = gpu->identity.minor_features11;
 102		break;
 103
 104	case ETNAVIV_PARAM_GPU_STREAM_COUNT:
 105		*value = gpu->identity.stream_count;
 106		break;
 107
 108	case ETNAVIV_PARAM_GPU_REGISTER_MAX:
 109		*value = gpu->identity.register_max;
 110		break;
 111
 112	case ETNAVIV_PARAM_GPU_THREAD_COUNT:
 113		*value = gpu->identity.thread_count;
 114		break;
 115
 116	case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
 117		*value = gpu->identity.vertex_cache_size;
 118		break;
 119
 120	case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
 121		*value = gpu->identity.shader_core_count;
 122		break;
 123
 124	case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
 125		*value = gpu->identity.pixel_pipes;
 126		break;
 127
 128	case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
 129		*value = gpu->identity.vertex_output_buffer_size;
 130		break;
 131
 132	case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
 133		*value = gpu->identity.buffer_size;
 134		break;
 135
 136	case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
 137		*value = gpu->identity.instruction_count;
 138		break;
 139
 140	case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
 141		*value = gpu->identity.num_constants;
 142		break;
 143
 144	case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
 145		*value = gpu->identity.varyings_count;
 146		break;
 147
 148	case ETNAVIV_PARAM_SOFTPIN_START_ADDR:
 149		if (priv->mmu_global->version == ETNAVIV_IOMMU_V2)
 150			*value = ETNAVIV_SOFTPIN_START_ADDRESS;
 151		else
 152			*value = ~0ULL;
 153		break;
 154
 155	case ETNAVIV_PARAM_GPU_PRODUCT_ID:
 156		*value = gpu->identity.product_id;
 157		break;
 158
 159	case ETNAVIV_PARAM_GPU_CUSTOMER_ID:
 160		*value = gpu->identity.customer_id;
 161		break;
 162
 163	case ETNAVIV_PARAM_GPU_ECO_ID:
 164		*value = gpu->identity.eco_id;
 165		break;
 166
 167	default:
 168		DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
 169		return -EINVAL;
 170	}
 171
 172	return 0;
 173}
 174
 175static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision)
 176{
 177	return gpu->identity.model == model &&
 178	       gpu->identity.revision == revision;
 179}
 180
 
 
 
 181#define etnaviv_field(val, field) \
 182	(((val) & field##__MASK) >> field##__SHIFT)
 183
 184static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
 185{
 186	if (gpu->identity.minor_features0 &
 187	    chipMinorFeatures0_MORE_MINOR_FEATURES) {
 188		u32 specs[4];
 189		unsigned int streams;
 190
 191		specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
 192		specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
 193		specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
 194		specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
 195
 196		gpu->identity.stream_count = etnaviv_field(specs[0],
 197					VIVS_HI_CHIP_SPECS_STREAM_COUNT);
 198		gpu->identity.register_max = etnaviv_field(specs[0],
 199					VIVS_HI_CHIP_SPECS_REGISTER_MAX);
 200		gpu->identity.thread_count = etnaviv_field(specs[0],
 201					VIVS_HI_CHIP_SPECS_THREAD_COUNT);
 202		gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
 203					VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
 204		gpu->identity.shader_core_count = etnaviv_field(specs[0],
 205					VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
 206		gpu->identity.pixel_pipes = etnaviv_field(specs[0],
 207					VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
 208		gpu->identity.vertex_output_buffer_size =
 209			etnaviv_field(specs[0],
 210				VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
 211
 212		gpu->identity.buffer_size = etnaviv_field(specs[1],
 213					VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
 214		gpu->identity.instruction_count = etnaviv_field(specs[1],
 215					VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
 216		gpu->identity.num_constants = etnaviv_field(specs[1],
 217					VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
 218
 219		gpu->identity.varyings_count = etnaviv_field(specs[2],
 220					VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
 221
 222		/* This overrides the value from older register if non-zero */
 223		streams = etnaviv_field(specs[3],
 224					VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
 225		if (streams)
 226			gpu->identity.stream_count = streams;
 227	}
 228
 229	/* Fill in the stream count if not specified */
 230	if (gpu->identity.stream_count == 0) {
 231		if (gpu->identity.model >= 0x1000)
 232			gpu->identity.stream_count = 4;
 233		else
 234			gpu->identity.stream_count = 1;
 235	}
 236
 237	/* Convert the register max value */
 238	if (gpu->identity.register_max)
 239		gpu->identity.register_max = 1 << gpu->identity.register_max;
 240	else if (gpu->identity.model == chipModel_GC400)
 241		gpu->identity.register_max = 32;
 242	else
 243		gpu->identity.register_max = 64;
 244
 245	/* Convert thread count */
 246	if (gpu->identity.thread_count)
 247		gpu->identity.thread_count = 1 << gpu->identity.thread_count;
 248	else if (gpu->identity.model == chipModel_GC400)
 249		gpu->identity.thread_count = 64;
 250	else if (gpu->identity.model == chipModel_GC500 ||
 251		 gpu->identity.model == chipModel_GC530)
 252		gpu->identity.thread_count = 128;
 253	else
 254		gpu->identity.thread_count = 256;
 255
 256	if (gpu->identity.vertex_cache_size == 0)
 257		gpu->identity.vertex_cache_size = 8;
 258
 259	if (gpu->identity.shader_core_count == 0) {
 260		if (gpu->identity.model >= 0x1000)
 261			gpu->identity.shader_core_count = 2;
 262		else
 263			gpu->identity.shader_core_count = 1;
 264	}
 265
 266	if (gpu->identity.pixel_pipes == 0)
 267		gpu->identity.pixel_pipes = 1;
 268
 269	/* Convert virtex buffer size */
 270	if (gpu->identity.vertex_output_buffer_size) {
 271		gpu->identity.vertex_output_buffer_size =
 272			1 << gpu->identity.vertex_output_buffer_size;
 273	} else if (gpu->identity.model == chipModel_GC400) {
 274		if (gpu->identity.revision < 0x4000)
 275			gpu->identity.vertex_output_buffer_size = 512;
 276		else if (gpu->identity.revision < 0x4200)
 277			gpu->identity.vertex_output_buffer_size = 256;
 278		else
 279			gpu->identity.vertex_output_buffer_size = 128;
 280	} else {
 281		gpu->identity.vertex_output_buffer_size = 512;
 282	}
 283
 284	switch (gpu->identity.instruction_count) {
 285	case 0:
 286		if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
 287		    gpu->identity.model == chipModel_GC880)
 288			gpu->identity.instruction_count = 512;
 289		else
 290			gpu->identity.instruction_count = 256;
 291		break;
 292
 293	case 1:
 294		gpu->identity.instruction_count = 1024;
 295		break;
 296
 297	case 2:
 298		gpu->identity.instruction_count = 2048;
 299		break;
 300
 301	default:
 302		gpu->identity.instruction_count = 256;
 303		break;
 304	}
 305
 306	if (gpu->identity.num_constants == 0)
 307		gpu->identity.num_constants = 168;
 308
 309	if (gpu->identity.varyings_count == 0) {
 310		if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
 311			gpu->identity.varyings_count = 12;
 312		else
 313			gpu->identity.varyings_count = 8;
 314	}
 315
 316	/*
 317	 * For some cores, two varyings are consumed for position, so the
 318	 * maximum varying count needs to be reduced by one.
 319	 */
 320	if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) ||
 321	    etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
 322	    etnaviv_is_model_rev(gpu, 0x4000, 0x5245) ||
 323	    etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
 324	    etnaviv_is_model_rev(gpu, 0x3000, 0x5435) ||
 325	    etnaviv_is_model_rev(gpu, 0x2200, 0x5244) ||
 326	    etnaviv_is_model_rev(gpu, 0x2100, 0x5108) ||
 327	    etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
 328	    etnaviv_is_model_rev(gpu, 0x1500, 0x5246) ||
 329	    etnaviv_is_model_rev(gpu, 0x880, 0x5107) ||
 330	    etnaviv_is_model_rev(gpu, 0x880, 0x5106))
 331		gpu->identity.varyings_count -= 1;
 332}
 333
 334static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
 335{
 336	u32 chipIdentity;
 337
 338	chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
 339
 340	/* Special case for older graphic cores. */
 341	if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
 342		gpu->identity.model    = chipModel_GC500;
 343		gpu->identity.revision = etnaviv_field(chipIdentity,
 344					 VIVS_HI_CHIP_IDENTITY_REVISION);
 345	} else {
 346		u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
 347
 348		gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
 349		gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
 350		gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
 351
 352		/*
 353		 * Reading these two registers on GC600 rev 0x19 result in a
 354		 * unhandled fault: external abort on non-linefetch
 355		 */
 356		if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) {
 357			gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
 358			gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
 359		}
 360
 361		/*
 362		 * !!!! HACK ALERT !!!!
 363		 * Because people change device IDs without letting software
 364		 * know about it - here is the hack to make it all look the
 365		 * same.  Only for GC400 family.
 366		 */
 367		if ((gpu->identity.model & 0xff00) == 0x0400 &&
 368		    gpu->identity.model != chipModel_GC420) {
 369			gpu->identity.model = gpu->identity.model & 0x0400;
 370		}
 371
 372		/* Another special case */
 373		if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) {
 374			u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
 375
 376			if (chipDate == 0x20080814 && chipTime == 0x12051100) {
 377				/*
 378				 * This IP has an ECO; put the correct
 379				 * revision in it.
 380				 */
 381				gpu->identity.revision = 0x1051;
 382			}
 383		}
 384
 385		/*
 386		 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
 387		 * reality it's just a re-branded GC3000. We can identify this
 388		 * core by the upper half of the revision register being all 1.
 389		 * Fix model/rev here, so all other places can refer to this
 390		 * core by its real identity.
 391		 */
 392		if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) {
 393			gpu->identity.model = chipModel_GC3000;
 394			gpu->identity.revision &= 0xffff;
 395		}
 396
 397		if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617))
 398			gpu->identity.eco_id = 1;
 399
 400		if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511))
 401			gpu->identity.eco_id = 1;
 402	}
 403
 404	dev_info(gpu->dev, "model: GC%x, revision: %x\n",
 405		 gpu->identity.model, gpu->identity.revision);
 406
 407	gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
 408	/*
 409	 * If there is a match in the HWDB, we aren't interested in the
 410	 * remaining register values, as they might be wrong.
 411	 */
 412	if (etnaviv_fill_identity_from_hwdb(gpu))
 413		return;
 414
 415	gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
 416
 417	/* Disable fast clear on GC700. */
 418	if (gpu->identity.model == chipModel_GC700)
 419		gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 420
 421	/* These models/revisions don't have the 2D pipe bit */
 422	if ((gpu->identity.model == chipModel_GC500 &&
 423	     gpu->identity.revision <= 2) ||
 424	    gpu->identity.model == chipModel_GC300)
 425		gpu->identity.features |= chipFeatures_PIPE_2D;
 426
 427	if ((gpu->identity.model == chipModel_GC500 &&
 428	     gpu->identity.revision < 2) ||
 429	    (gpu->identity.model == chipModel_GC300 &&
 430	     gpu->identity.revision < 0x2000)) {
 431
 432		/*
 433		 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
 434		 * registers.
 435		 */
 436		gpu->identity.minor_features0 = 0;
 437		gpu->identity.minor_features1 = 0;
 438		gpu->identity.minor_features2 = 0;
 439		gpu->identity.minor_features3 = 0;
 440		gpu->identity.minor_features4 = 0;
 441		gpu->identity.minor_features5 = 0;
 442	} else
 443		gpu->identity.minor_features0 =
 444				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
 445
 446	if (gpu->identity.minor_features0 &
 447	    chipMinorFeatures0_MORE_MINOR_FEATURES) {
 448		gpu->identity.minor_features1 =
 449				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
 450		gpu->identity.minor_features2 =
 451				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
 452		gpu->identity.minor_features3 =
 453				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
 454		gpu->identity.minor_features4 =
 455				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
 456		gpu->identity.minor_features5 =
 457				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
 458	}
 459
 460	/* GC600/300 idle register reports zero bits where modules aren't present */
 461	if (gpu->identity.model == chipModel_GC600 ||
 462	    gpu->identity.model == chipModel_GC300)
 463		gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
 464				 VIVS_HI_IDLE_STATE_RA |
 465				 VIVS_HI_IDLE_STATE_SE |
 466				 VIVS_HI_IDLE_STATE_PA |
 467				 VIVS_HI_IDLE_STATE_SH |
 468				 VIVS_HI_IDLE_STATE_PE |
 469				 VIVS_HI_IDLE_STATE_DE |
 470				 VIVS_HI_IDLE_STATE_FE;
 471
 472	etnaviv_hw_specs(gpu);
 473}
 474
 475static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
 476{
 477	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
 478		  VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
 479	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
 480}
 481
 482static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
 483{
 484	if (gpu->identity.minor_features2 &
 485	    chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
 486		clk_set_rate(gpu->clk_core,
 487			     gpu->base_rate_core >> gpu->freq_scale);
 488		clk_set_rate(gpu->clk_shader,
 489			     gpu->base_rate_shader >> gpu->freq_scale);
 490	} else {
 491		unsigned int fscale = 1 << (6 - gpu->freq_scale);
 492		u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 493
 494		clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
 495		clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 496		etnaviv_gpu_load_clock(gpu, clock);
 497	}
 498
 499	/*
 500	 * Choose number of wait cycles to target a ~30us (1/32768) max latency
 501	 * until new work is picked up by the FE when it polls in the idle loop.
 502	 * If the GPU base frequency is unknown use 200 wait cycles.
 503	 */
 504	gpu->fe_waitcycles = clamp(gpu->base_rate_core >> (15 - gpu->freq_scale),
 505				   200UL, 0xffffUL);
 506}
 507
 508static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
 509{
 510	u32 control, idle;
 511	unsigned long timeout;
 512	bool failed = true;
 513
 514	/* We hope that the GPU resets in under one second */
 515	timeout = jiffies + msecs_to_jiffies(1000);
 516
 517	while (time_is_after_jiffies(timeout)) {
 518		unsigned int fscale = 1 << (6 - gpu->freq_scale);
 519		u32 pulse_eater = 0x01590880;
 520
 521		/* disable clock gating */
 522		gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, 0x0);
 523
 524		/* disable pulse eater */
 525		pulse_eater |= BIT(17);
 526		gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
 527		pulse_eater |= BIT(0);
 528		gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
 529
 530		/* enable clock */
 
 531		control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 532		etnaviv_gpu_load_clock(gpu, control);
 533
 534		/* isolate the GPU. */
 535		control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 536		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 537
 538		if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 539			gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
 540			          VIVS_MMUv2_AHB_CONTROL_RESET);
 541		} else {
 542			/* set soft reset. */
 543			control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 544			gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 545		}
 546
 547		/* wait for reset. */
 548		usleep_range(10, 20);
 549
 550		/* reset soft reset bit. */
 551		control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 552		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 553
 554		/* reset GPU isolation. */
 555		control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 556		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 557
 558		/* read idle register. */
 559		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 560
 561		/* try resetting again if FE is not idle */
 562		if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
 563			dev_dbg(gpu->dev, "FE is not idle\n");
 564			continue;
 565		}
 566
 567		/* read reset register. */
 568		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 569
 570		/* is the GPU idle? */
 571		if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
 572		    ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
 573			dev_dbg(gpu->dev, "GPU is not idle\n");
 574			continue;
 575		}
 576
 577		/* enable debug register access */
 578		control &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
 579		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 580
 581		failed = false;
 582		break;
 583	}
 584
 585	if (failed) {
 586		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 587		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 588
 589		dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
 590			idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
 591			control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
 592			control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
 593
 594		return -EBUSY;
 595	}
 596
 597	/* We rely on the GPU running, so program the clock */
 598	etnaviv_gpu_update_clock(gpu);
 599
 600	gpu->state = ETNA_GPU_STATE_RESET;
 601	gpu->exec_state = -1;
 602	if (gpu->mmu_context)
 603		etnaviv_iommu_context_put(gpu->mmu_context);
 604	gpu->mmu_context = NULL;
 605
 606	return 0;
 607}
 608
 609static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
 610{
 611	u32 pmc, ppc;
 612
 613	/* enable clock gating */
 614	ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
 615	ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
 616
 617	/* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
 618	if (gpu->identity.revision == 0x4301 ||
 619	    gpu->identity.revision == 0x4302)
 620		ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
 621
 622	gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc);
 623
 624	pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS);
 625
 626	/* Disable PA clock gating for GC400+ without bugfix except for GC420 */
 627	if (gpu->identity.model >= chipModel_GC400 &&
 628	    gpu->identity.model != chipModel_GC420 &&
 629	    !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
 630		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
 631
 632	/*
 633	 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
 634	 * present without a bug fix.
 635	 */
 636	if (gpu->identity.revision < 0x5000 &&
 637	    gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
 638	    !(gpu->identity.minor_features1 &
 639	      chipMinorFeatures1_DISABLE_PE_GATING))
 640		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
 641
 642	if (gpu->identity.revision < 0x5422)
 643		pmc |= BIT(15); /* Unknown bit */
 644
 645	/* Disable TX clock gating on affected core revisions. */
 646	if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
 647	    etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
 648	    etnaviv_is_model_rev(gpu, 0x7000, 0x6202) ||
 649	    etnaviv_is_model_rev(gpu, 0x7000, 0x6203))
 650		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
 651
 652	/* Disable SE and RA clock gating on affected core revisions. */
 653	if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202))
 654		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
 655		       VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
 656
 657	/* Disable SH_EU clock gating on affected core revisions. */
 658	if (etnaviv_is_model_rev(gpu, 0x8000, 0x7200) ||
 659	    etnaviv_is_model_rev(gpu, 0x8000, 0x8002) ||
 660	    etnaviv_is_model_rev(gpu, 0x9200, 0x6304))
 661		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU;
 662
 663	pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
 664	pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
 665
 666	gpu_write_power(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
 667}
 668
 669void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
 670{
 671	gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
 672	gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
 673		  VIVS_FE_COMMAND_CONTROL_ENABLE |
 674		  VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
 675
 676	if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 677		gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
 678			  VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
 679			  VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
 680	}
 
 
 681}
 682
 683static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu,
 684					  struct etnaviv_iommu_context *context)
 685{
 686	u16 prefetch;
 687	u32 address;
 688
 689	WARN_ON(gpu->state != ETNA_GPU_STATE_INITIALIZED);
 690
 691	/* setup the MMU */
 692	etnaviv_iommu_restore(gpu, context);
 693
 694	/* Start command processor */
 695	prefetch = etnaviv_buffer_init(gpu);
 696	address = etnaviv_cmdbuf_get_va(&gpu->buffer,
 697					&gpu->mmu_context->cmdbuf_mapping);
 698
 699	etnaviv_gpu_start_fe(gpu, address, prefetch);
 700
 701	gpu->state = ETNA_GPU_STATE_RUNNING;
 702}
 703
 704static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
 705{
 706	/*
 707	 * Base value for VIVS_PM_PULSE_EATER register on models where it
 708	 * cannot be read, extracted from vivante kernel driver.
 709	 */
 710	u32 pulse_eater = 0x01590880;
 711
 712	if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
 713	    etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) {
 714		pulse_eater |= BIT(23);
 715
 716	}
 717
 718	if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) ||
 719	    etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) {
 720		pulse_eater &= ~BIT(16);
 721		pulse_eater |= BIT(17);
 722	}
 723
 724	if ((gpu->identity.revision > 0x5420) &&
 725	    (gpu->identity.features & chipFeatures_PIPE_3D))
 726	{
 727		/* Performance fix: disable internal DFS */
 728		pulse_eater = gpu_read_power(gpu, VIVS_PM_PULSE_EATER);
 729		pulse_eater |= BIT(18);
 730	}
 731
 732	gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
 733}
 734
 735static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
 736{
 737	WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED ||
 738		  gpu->state == ETNA_GPU_STATE_RESET));
 739
 740	if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) ||
 741	     etnaviv_is_model_rev(gpu, 0x320, 0x5220)) &&
 742	    gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
 743		u32 mc_memory_debug;
 744
 745		mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
 746
 747		if (gpu->identity.revision == 0x5007)
 748			mc_memory_debug |= 0x0c;
 749		else
 750			mc_memory_debug |= 0x08;
 751
 752		gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
 753	}
 754
 755	/* enable module-level clock gating */
 756	etnaviv_gpu_enable_mlcg(gpu);
 757
 758	/*
 759	 * Update GPU AXI cache atttribute to "cacheable, no allocate".
 760	 * This is necessary to prevent the iMX6 SoC locking up.
 761	 */
 762	gpu_write(gpu, VIVS_HI_AXI_CONFIG,
 763		  VIVS_HI_AXI_CONFIG_AWCACHE(2) |
 764		  VIVS_HI_AXI_CONFIG_ARCACHE(2));
 765
 766	/* GC2000 rev 5108 needs a special bus config */
 767	if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) {
 768		u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
 769		bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
 770				VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
 771		bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
 772			      VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
 773		gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
 774	}
 775
 776	if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 777		u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
 778		val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
 779		gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
 780	}
 781
 782	/* setup the pulse eater */
 783	etnaviv_gpu_setup_pulse_eater(gpu);
 784
 785	gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
 786
 787	gpu->state = ETNA_GPU_STATE_INITIALIZED;
 788}
 789
 790int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
 791{
 792	struct etnaviv_drm_private *priv = gpu->drm->dev_private;
 793	dma_addr_t cmdbuf_paddr;
 794	int ret, i;
 795
 796	ret = pm_runtime_get_sync(gpu->dev);
 797	if (ret < 0) {
 798		dev_err(gpu->dev, "Failed to enable GPU power domain\n");
 799		goto pm_put;
 800	}
 801
 802	etnaviv_hw_identify(gpu);
 803
 804	if (gpu->identity.model == 0) {
 805		dev_err(gpu->dev, "Unknown GPU model\n");
 806		ret = -ENXIO;
 807		goto fail;
 808	}
 809
 810	if (gpu->identity.nn_core_count > 0)
 811		dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, "
 812                                   "for which the UAPI is still experimental\n");
 813
 814	/* Exclude VG cores with FE2.0 */
 815	if (gpu->identity.features & chipFeatures_PIPE_VG &&
 816	    gpu->identity.features & chipFeatures_FE20) {
 817		dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
 818		ret = -ENXIO;
 819		goto fail;
 820	}
 821
 822	/*
 823	 * On cores with security features supported, we claim control over the
 824	 * security states.
 825	 */
 826	if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
 827	    (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
 828		gpu->sec_mode = ETNA_SEC_KERNEL;
 829
 830	gpu->state = ETNA_GPU_STATE_IDENTIFIED;
 831
 832	ret = etnaviv_hw_reset(gpu);
 833	if (ret) {
 834		dev_err(gpu->dev, "GPU reset failed\n");
 835		goto fail;
 836	}
 837
 838	ret = etnaviv_iommu_global_init(gpu);
 839	if (ret)
 840		goto fail;
 841
 
 
 
 
 
 
 
 
 842	/* Create buffer: */
 843	ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, SZ_4K);
 
 844	if (ret) {
 845		dev_err(gpu->dev, "could not create command buffer\n");
 846		goto fail;
 847	}
 848
 849	/*
 850	 * Set the GPU linear window to cover the cmdbuf region, as the GPU
 851	 * won't be able to start execution otherwise. The alignment to 128M is
 852	 * chosen arbitrarily but helps in debugging, as the MMU offset
 853	 * calculations are much more straight forward this way.
 854	 *
 855	 * On MC1.0 cores the linear window offset is ignored by the TS engine,
 856	 * leading to inconsistent memory views. Avoid using the offset on those
 857	 * cores if possible, otherwise disable the TS feature. MMUv2 doesn't
 858	 * expose this issue, as all TS accesses are MMU translated, so the
 859	 * linear window offset won't be used.
 860	 */
 861	cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M);
 862
 863	if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
 864	    (gpu->identity.minor_features0 & chipMinorFeatures0_MC20) ||
 865	    (gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION)) {
 866		if (cmdbuf_paddr >= SZ_2G)
 867			priv->mmu_global->memory_base = SZ_2G;
 868		else
 869			priv->mmu_global->memory_base = cmdbuf_paddr;
 870	} else if (cmdbuf_paddr + SZ_128M >= SZ_2G) {
 871		dev_info(gpu->dev,
 872			 "Need to move linear window on MC1.0, disabling TS\n");
 873		gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 874		priv->mmu_global->memory_base = SZ_2G;
 875	}
 876
 877	/* Setup event management */
 878	spin_lock_init(&gpu->event_spinlock);
 879	init_completion(&gpu->event_free);
 880	bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
 881	for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
 882		complete(&gpu->event_free);
 883
 884	/* Now program the hardware */
 885	mutex_lock(&gpu->lock);
 886	etnaviv_gpu_hw_init(gpu);
 887	mutex_unlock(&gpu->lock);
 888
 889	pm_runtime_mark_last_busy(gpu->dev);
 890	pm_runtime_put_autosuspend(gpu->dev);
 891
 
 
 892	return 0;
 893
 894fail:
 895	pm_runtime_mark_last_busy(gpu->dev);
 896pm_put:
 897	pm_runtime_put_autosuspend(gpu->dev);
 898
 899	return ret;
 900}
 901
 902#ifdef CONFIG_DEBUG_FS
 903struct dma_debug {
 904	u32 address[2];
 905	u32 state[2];
 906};
 907
 908static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
 909{
 910	u32 i;
 911
 912	debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 913	debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 914
 915	for (i = 0; i < 500; i++) {
 916		debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 917		debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 918
 919		if (debug->address[0] != debug->address[1])
 920			break;
 921
 922		if (debug->state[0] != debug->state[1])
 923			break;
 924	}
 925}
 926
 927int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
 928{
 929	struct dma_debug debug;
 930	u32 dma_lo, dma_hi, axi, idle;
 931	int ret;
 932
 933	seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
 934
 935	ret = pm_runtime_get_sync(gpu->dev);
 936	if (ret < 0)
 937		goto pm_put;
 938
 939	dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
 940	dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
 941	axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
 942	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 943
 944	verify_dma(gpu, &debug);
 945
 946	seq_puts(m, "\tidentity\n");
 947	seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);
 948	seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);
 949	seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);
 950	seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);
 951	seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);
 952
 953	seq_puts(m, "\tfeatures\n");
 954	seq_printf(m, "\t major_features: 0x%08x\n",
 955		   gpu->identity.features);
 956	seq_printf(m, "\t minor_features0: 0x%08x\n",
 957		   gpu->identity.minor_features0);
 958	seq_printf(m, "\t minor_features1: 0x%08x\n",
 959		   gpu->identity.minor_features1);
 960	seq_printf(m, "\t minor_features2: 0x%08x\n",
 961		   gpu->identity.minor_features2);
 962	seq_printf(m, "\t minor_features3: 0x%08x\n",
 963		   gpu->identity.minor_features3);
 964	seq_printf(m, "\t minor_features4: 0x%08x\n",
 965		   gpu->identity.minor_features4);
 966	seq_printf(m, "\t minor_features5: 0x%08x\n",
 967		   gpu->identity.minor_features5);
 968	seq_printf(m, "\t minor_features6: 0x%08x\n",
 969		   gpu->identity.minor_features6);
 970	seq_printf(m, "\t minor_features7: 0x%08x\n",
 971		   gpu->identity.minor_features7);
 972	seq_printf(m, "\t minor_features8: 0x%08x\n",
 973		   gpu->identity.minor_features8);
 974	seq_printf(m, "\t minor_features9: 0x%08x\n",
 975		   gpu->identity.minor_features9);
 976	seq_printf(m, "\t minor_features10: 0x%08x\n",
 977		   gpu->identity.minor_features10);
 978	seq_printf(m, "\t minor_features11: 0x%08x\n",
 979		   gpu->identity.minor_features11);
 980
 981	seq_puts(m, "\tspecs\n");
 982	seq_printf(m, "\t stream_count:  %d\n",
 983			gpu->identity.stream_count);
 984	seq_printf(m, "\t register_max: %d\n",
 985			gpu->identity.register_max);
 986	seq_printf(m, "\t thread_count: %d\n",
 987			gpu->identity.thread_count);
 988	seq_printf(m, "\t vertex_cache_size: %d\n",
 989			gpu->identity.vertex_cache_size);
 990	seq_printf(m, "\t shader_core_count: %d\n",
 991			gpu->identity.shader_core_count);
 992	seq_printf(m, "\t nn_core_count: %d\n",
 993			gpu->identity.nn_core_count);
 994	seq_printf(m, "\t pixel_pipes: %d\n",
 995			gpu->identity.pixel_pipes);
 996	seq_printf(m, "\t vertex_output_buffer_size: %d\n",
 997			gpu->identity.vertex_output_buffer_size);
 998	seq_printf(m, "\t buffer_size: %d\n",
 999			gpu->identity.buffer_size);
1000	seq_printf(m, "\t instruction_count: %d\n",
1001			gpu->identity.instruction_count);
1002	seq_printf(m, "\t num_constants: %d\n",
1003			gpu->identity.num_constants);
1004	seq_printf(m, "\t varyings_count: %d\n",
1005			gpu->identity.varyings_count);
1006
1007	seq_printf(m, "\taxi: 0x%08x\n", axi);
1008	seq_printf(m, "\tidle: 0x%08x\n", idle);
1009	idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
1010	if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
1011		seq_puts(m, "\t FE is not idle\n");
1012	if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
1013		seq_puts(m, "\t DE is not idle\n");
1014	if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
1015		seq_puts(m, "\t PE is not idle\n");
1016	if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
1017		seq_puts(m, "\t SH is not idle\n");
1018	if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
1019		seq_puts(m, "\t PA is not idle\n");
1020	if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
1021		seq_puts(m, "\t SE is not idle\n");
1022	if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
1023		seq_puts(m, "\t RA is not idle\n");
1024	if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
1025		seq_puts(m, "\t TX is not idle\n");
1026	if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
1027		seq_puts(m, "\t VG is not idle\n");
1028	if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
1029		seq_puts(m, "\t IM is not idle\n");
1030	if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
1031		seq_puts(m, "\t FP is not idle\n");
1032	if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
1033		seq_puts(m, "\t TS is not idle\n");
1034	if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)
1035		seq_puts(m, "\t BL is not idle\n");
1036	if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)
1037		seq_puts(m, "\t ASYNCFE is not idle\n");
1038	if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)
1039		seq_puts(m, "\t MC is not idle\n");
1040	if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)
1041		seq_puts(m, "\t PPA is not idle\n");
1042	if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)
1043		seq_puts(m, "\t WD is not idle\n");
1044	if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)
1045		seq_puts(m, "\t NN is not idle\n");
1046	if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)
1047		seq_puts(m, "\t TP is not idle\n");
1048	if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
1049		seq_puts(m, "\t AXI low power mode\n");
1050
1051	if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
1052		u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
1053		u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
1054		u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
1055
1056		seq_puts(m, "\tMC\n");
1057		seq_printf(m, "\t read0: 0x%08x\n", read0);
1058		seq_printf(m, "\t read1: 0x%08x\n", read1);
1059		seq_printf(m, "\t write: 0x%08x\n", write);
1060	}
1061
1062	seq_puts(m, "\tDMA ");
1063
1064	if (debug.address[0] == debug.address[1] &&
1065	    debug.state[0] == debug.state[1]) {
1066		seq_puts(m, "seems to be stuck\n");
1067	} else if (debug.address[0] == debug.address[1]) {
1068		seq_puts(m, "address is constant\n");
1069	} else {
1070		seq_puts(m, "is running\n");
1071	}
1072
1073	seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
1074	seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
1075	seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
1076	seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
1077	seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
1078		   dma_lo, dma_hi);
1079
1080	ret = 0;
1081
1082	pm_runtime_mark_last_busy(gpu->dev);
1083pm_put:
1084	pm_runtime_put_autosuspend(gpu->dev);
1085
1086	return ret;
1087}
1088#endif
1089
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1090/* fence object management */
1091struct etnaviv_fence {
1092	struct etnaviv_gpu *gpu;
1093	struct dma_fence base;
1094};
1095
1096static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1097{
1098	return container_of(fence, struct etnaviv_fence, base);
1099}
1100
1101static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1102{
1103	return "etnaviv";
1104}
1105
1106static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1107{
1108	struct etnaviv_fence *f = to_etnaviv_fence(fence);
1109
1110	return dev_name(f->gpu->dev);
1111}
1112
1113static bool etnaviv_fence_signaled(struct dma_fence *fence)
1114{
1115	struct etnaviv_fence *f = to_etnaviv_fence(fence);
1116
1117	return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1118}
1119
1120static void etnaviv_fence_release(struct dma_fence *fence)
1121{
1122	struct etnaviv_fence *f = to_etnaviv_fence(fence);
1123
1124	kfree_rcu(f, base.rcu);
1125}
1126
1127static const struct dma_fence_ops etnaviv_fence_ops = {
1128	.get_driver_name = etnaviv_fence_get_driver_name,
1129	.get_timeline_name = etnaviv_fence_get_timeline_name,
1130	.signaled = etnaviv_fence_signaled,
1131	.release = etnaviv_fence_release,
1132};
1133
1134static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1135{
1136	struct etnaviv_fence *f;
1137
1138	/*
1139	 * GPU lock must already be held, otherwise fence completion order might
1140	 * not match the seqno order assigned here.
1141	 */
1142	lockdep_assert_held(&gpu->lock);
1143
1144	f = kzalloc(sizeof(*f), GFP_KERNEL);
1145	if (!f)
1146		return NULL;
1147
1148	f->gpu = gpu;
1149
1150	dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1151		       gpu->fence_context, ++gpu->next_fence);
1152
1153	return &f->base;
1154}
1155
1156/* returns true if fence a comes after fence b */
1157static inline bool fence_after(u32 a, u32 b)
1158{
1159	return (s32)(a - b) > 0;
1160}
1161
1162/*
1163 * event management:
1164 */
1165
1166static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1167	unsigned int *events)
1168{
1169	unsigned long timeout = msecs_to_jiffies(10 * 10000);
1170	unsigned i, acquired = 0, rpm_count = 0;
1171	int ret;
1172
1173	for (i = 0; i < nr_events; i++) {
1174		unsigned long remaining;
1175
1176		remaining = wait_for_completion_timeout(&gpu->event_free, timeout);
1177
1178		if (!remaining) {
1179			dev_err(gpu->dev, "wait_for_completion_timeout failed");
1180			ret = -EBUSY;
1181			goto out;
1182		}
1183
1184		acquired++;
1185		timeout = remaining;
1186	}
1187
1188	spin_lock(&gpu->event_spinlock);
1189
1190	for (i = 0; i < nr_events; i++) {
1191		int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1192
1193		events[i] = event;
1194		memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1195		set_bit(event, gpu->event_bitmap);
1196	}
1197
1198	spin_unlock(&gpu->event_spinlock);
1199
1200	for (i = 0; i < nr_events; i++) {
1201		ret = pm_runtime_resume_and_get(gpu->dev);
1202		if (ret)
1203			goto out_rpm;
1204		rpm_count++;
1205	}
1206
1207	return 0;
1208
1209out_rpm:
1210	for (i = 0; i < rpm_count; i++)
1211		pm_runtime_put_autosuspend(gpu->dev);
1212out:
1213	for (i = 0; i < acquired; i++)
1214		complete(&gpu->event_free);
1215
1216	return ret;
1217}
1218
1219static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1220{
1221	if (!test_bit(event, gpu->event_bitmap)) {
1222		dev_warn(gpu->dev, "event %u is already marked as free",
1223			 event);
1224	} else {
1225		clear_bit(event, gpu->event_bitmap);
1226		complete(&gpu->event_free);
1227	}
1228
1229	pm_runtime_put_autosuspend(gpu->dev);
1230}
1231
1232/*
1233 * Cmdstream submission/retirement:
1234 */
1235int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1236	u32 id, struct drm_etnaviv_timespec *timeout)
1237{
1238	struct dma_fence *fence;
1239	int ret;
1240
1241	/*
1242	 * Look up the fence and take a reference. We might still find a fence
1243	 * whose refcount has already dropped to zero. dma_fence_get_rcu
1244	 * pretends we didn't find a fence in that case.
1245	 */
1246	rcu_read_lock();
1247	fence = xa_load(&gpu->user_fences, id);
1248	if (fence)
1249		fence = dma_fence_get_rcu(fence);
1250	rcu_read_unlock();
1251
1252	if (!fence)
1253		return 0;
1254
1255	if (!timeout) {
1256		/* No timeout was requested: just test for completion */
1257		ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1258	} else {
1259		unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1260
1261		ret = dma_fence_wait_timeout(fence, true, remaining);
1262		if (ret == 0)
1263			ret = -ETIMEDOUT;
1264		else if (ret != -ERESTARTSYS)
1265			ret = 0;
1266
1267	}
1268
1269	dma_fence_put(fence);
1270	return ret;
1271}
1272
1273/*
1274 * Wait for an object to become inactive.  This, on it's own, is not race
1275 * free: the object is moved by the scheduler off the active list, and
1276 * then the iova is put.  Moreover, the object could be re-submitted just
1277 * after we notice that it's become inactive.
1278 *
1279 * Although the retirement happens under the gpu lock, we don't want to hold
1280 * that lock in this function while waiting.
1281 */
1282int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1283	struct etnaviv_gem_object *etnaviv_obj,
1284	struct drm_etnaviv_timespec *timeout)
1285{
1286	unsigned long remaining;
1287	long ret;
1288
1289	if (!timeout)
1290		return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1291
1292	remaining = etnaviv_timeout_to_jiffies(timeout);
1293
1294	ret = wait_event_interruptible_timeout(gpu->fence_event,
1295					       !is_active(etnaviv_obj),
1296					       remaining);
1297	if (ret > 0)
1298		return 0;
1299	else if (ret == -ERESTARTSYS)
1300		return -ERESTARTSYS;
1301	else
1302		return -ETIMEDOUT;
1303}
1304
1305static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1306	struct etnaviv_event *event, unsigned int flags)
1307{
1308	const struct etnaviv_gem_submit *submit = event->submit;
1309	unsigned int i;
1310
1311	for (i = 0; i < submit->nr_pmrs; i++) {
1312		const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1313
1314		if (pmr->flags == flags)
1315			etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1316	}
1317}
1318
1319static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1320	struct etnaviv_event *event)
1321{
1322	u32 val;
1323
1324	mutex_lock(&gpu->lock);
1325
1326	/* disable clock gating */
1327	val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
1328	val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1329	gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
1330
1331	sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
 
 
 
1332
1333	mutex_unlock(&gpu->lock);
1334}
1335
1336static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1337	struct etnaviv_event *event)
1338{
1339	const struct etnaviv_gem_submit *submit = event->submit;
1340	unsigned int i;
1341	u32 val;
1342
1343	mutex_lock(&gpu->lock);
1344
1345	sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1346
1347	/* enable clock gating */
1348	val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
1349	val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1350	gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
1351
1352	mutex_unlock(&gpu->lock);
1353
1354	for (i = 0; i < submit->nr_pmrs; i++) {
1355		const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1356
1357		*pmr->bo_vma = pmr->sequence;
1358	}
 
 
 
 
 
 
 
 
 
 
1359}
1360
1361
1362/* add bo's to gpu's ring, and kick gpu: */
1363struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1364{
1365	struct etnaviv_gpu *gpu = submit->gpu;
1366	struct dma_fence *gpu_fence;
1367	unsigned int i, nr_events = 1, event[3];
1368	int ret;
1369
 
 
 
 
 
 
 
 
 
1370	/*
1371	 * if there are performance monitor requests we need to have
1372	 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1373	 *   requests.
1374	 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1375	 *   and update the sequence number for userspace.
1376	 */
1377	if (submit->nr_pmrs)
1378		nr_events = 3;
1379
1380	ret = event_alloc(gpu, nr_events, event);
1381	if (ret) {
1382		DRM_ERROR("no free events\n");
1383		pm_runtime_put_noidle(gpu->dev);
1384		return NULL;
1385	}
1386
1387	mutex_lock(&gpu->lock);
1388
1389	gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1390	if (!gpu_fence) {
1391		for (i = 0; i < nr_events; i++)
1392			event_free(gpu, event[i]);
1393
1394		goto out_unlock;
1395	}
1396
1397	if (gpu->state == ETNA_GPU_STATE_INITIALIZED)
1398		etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context);
1399
1400	if (submit->prev_mmu_context)
1401		etnaviv_iommu_context_put(submit->prev_mmu_context);
1402	submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context);
1403
1404	if (submit->nr_pmrs) {
1405		gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1406		kref_get(&submit->refcount);
1407		gpu->event[event[1]].submit = submit;
1408		etnaviv_sync_point_queue(gpu, event[1]);
1409	}
1410
1411	gpu->event[event[0]].fence = gpu_fence;
1412	submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1413	etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
1414			     event[0], &submit->cmdbuf);
1415
1416	if (submit->nr_pmrs) {
1417		gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1418		kref_get(&submit->refcount);
1419		gpu->event[event[2]].submit = submit;
1420		etnaviv_sync_point_queue(gpu, event[2]);
1421	}
1422
1423out_unlock:
1424	mutex_unlock(&gpu->lock);
1425
1426	return gpu_fence;
1427}
1428
1429static void sync_point_worker(struct work_struct *work)
1430{
1431	struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1432					       sync_point_work);
1433	struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1434	u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1435
1436	event->sync_point(gpu, event);
1437	etnaviv_submit_put(event->submit);
1438	event_free(gpu, gpu->sync_point_event);
1439
1440	/* restart FE last to avoid GPU and IRQ racing against this worker */
1441	etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1442}
1443
1444void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit)
1445{
1446	struct etnaviv_gpu *gpu = submit->gpu;
1447	char *comm = NULL, *cmd = NULL;
1448	struct task_struct *task;
1449	unsigned int i;
1450
1451	dev_err(gpu->dev, "recover hung GPU!\n");
1452
1453	task = get_pid_task(submit->pid, PIDTYPE_PID);
1454	if (task) {
1455		comm = kstrdup(task->comm, GFP_KERNEL);
1456		cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
1457		put_task_struct(task);
1458	}
1459
1460	if (comm && cmd)
1461		dev_err(gpu->dev, "offending task: %s (%s)\n", comm, cmd);
1462
1463	kfree(cmd);
1464	kfree(comm);
1465
1466	if (pm_runtime_get_sync(gpu->dev) < 0)
1467		goto pm_put;
1468
1469	mutex_lock(&gpu->lock);
1470
1471	etnaviv_hw_reset(gpu);
1472
1473	/* complete all events, the GPU won't do it after the reset */
1474	spin_lock(&gpu->event_spinlock);
1475	for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS)
1476		event_free(gpu, i);
1477	spin_unlock(&gpu->event_spinlock);
1478
1479	etnaviv_gpu_hw_init(gpu);
1480
1481	mutex_unlock(&gpu->lock);
1482	pm_runtime_mark_last_busy(gpu->dev);
1483pm_put:
1484	pm_runtime_put_autosuspend(gpu->dev);
1485}
1486
1487static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1488{
1489	static const char *fault_reasons[] = {
1490		"slave not present",
1491		"page not present",
1492		"write violation",
1493		"out of bounds",
1494		"read security violation",
1495		"write security violation",
1496	};
1497
1498	u32 status_reg, status;
1499	int i;
1500
1501	if (gpu->sec_mode == ETNA_SEC_NONE)
1502		status_reg = VIVS_MMUv2_STATUS;
1503	else
1504		status_reg = VIVS_MMUv2_SEC_STATUS;
1505
1506	status = gpu_read(gpu, status_reg);
1507	dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1508
1509	for (i = 0; i < 4; i++) {
1510		const char *reason = "unknown";
1511		u32 address_reg;
1512		u32 mmu_status;
1513
1514		mmu_status = (status >> (i * 4)) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK;
1515		if (!mmu_status)
1516			continue;
1517
1518		if ((mmu_status - 1) < ARRAY_SIZE(fault_reasons))
1519			reason = fault_reasons[mmu_status - 1];
1520
1521		if (gpu->sec_mode == ETNA_SEC_NONE)
1522			address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1523		else
1524			address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1525
1526		dev_err_ratelimited(gpu->dev,
1527				    "MMU %d fault (%s) addr 0x%08x\n",
1528				    i, reason, gpu_read(gpu, address_reg));
1529	}
1530}
1531
1532static irqreturn_t irq_handler(int irq, void *data)
1533{
1534	struct etnaviv_gpu *gpu = data;
1535	irqreturn_t ret = IRQ_NONE;
1536
1537	u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1538
1539	if (intr != 0) {
1540		ktime_t now = ktime_get();
1541		int event;
1542
1543		pm_runtime_mark_last_busy(gpu->dev);
1544
1545		dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1546
1547		if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1548			dev_err(gpu->dev, "AXI bus error\n");
1549			intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1550		}
1551
1552		if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1553			dump_mmu_fault(gpu);
1554			gpu->state = ETNA_GPU_STATE_FAULT;
1555			drm_sched_fault(&gpu->sched);
1556			intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1557		}
1558
1559		while ((event = ffs(intr)) != 0) {
1560			struct dma_fence *fence;
1561
1562			event -= 1;
1563
1564			intr &= ~(1 << event);
1565
1566			dev_dbg(gpu->dev, "event %u\n", event);
1567
1568			if (gpu->event[event].sync_point) {
1569				gpu->sync_point_event = event;
1570				queue_work(gpu->wq, &gpu->sync_point_work);
1571			}
1572
1573			fence = gpu->event[event].fence;
1574			if (!fence)
1575				continue;
1576
1577			gpu->event[event].fence = NULL;
1578
1579			/*
1580			 * Events can be processed out of order.  Eg,
1581			 * - allocate and queue event 0
1582			 * - allocate event 1
1583			 * - event 0 completes, we process it
1584			 * - allocate and queue event 0
1585			 * - event 1 and event 0 complete
1586			 * we can end up processing event 0 first, then 1.
1587			 */
1588			if (fence_after(fence->seqno, gpu->completed_fence))
1589				gpu->completed_fence = fence->seqno;
1590			dma_fence_signal_timestamp(fence, now);
1591
1592			event_free(gpu, event);
1593		}
1594
1595		ret = IRQ_HANDLED;
1596	}
1597
1598	return ret;
1599}
1600
1601static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1602{
1603	int ret;
1604
1605	ret = clk_prepare_enable(gpu->clk_reg);
1606	if (ret)
1607		return ret;
1608
1609	ret = clk_prepare_enable(gpu->clk_bus);
1610	if (ret)
1611		goto disable_clk_reg;
1612
1613	ret = clk_prepare_enable(gpu->clk_core);
1614	if (ret)
1615		goto disable_clk_bus;
1616
1617	ret = clk_prepare_enable(gpu->clk_shader);
1618	if (ret)
1619		goto disable_clk_core;
1620
1621	return 0;
1622
1623disable_clk_core:
1624	clk_disable_unprepare(gpu->clk_core);
1625disable_clk_bus:
1626	clk_disable_unprepare(gpu->clk_bus);
1627disable_clk_reg:
1628	clk_disable_unprepare(gpu->clk_reg);
1629
1630	return ret;
1631}
1632
1633static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1634{
1635	clk_disable_unprepare(gpu->clk_shader);
1636	clk_disable_unprepare(gpu->clk_core);
1637	clk_disable_unprepare(gpu->clk_bus);
1638	clk_disable_unprepare(gpu->clk_reg);
1639
1640	return 0;
1641}
1642
1643int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1644{
1645	unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1646
1647	do {
1648		u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1649
1650		if ((idle & gpu->idle_mask) == gpu->idle_mask)
1651			return 0;
1652
1653		if (time_is_before_jiffies(timeout)) {
1654			dev_warn(gpu->dev,
1655				 "timed out waiting for idle: idle=0x%x\n",
1656				 idle);
1657			return -ETIMEDOUT;
1658		}
1659
1660		udelay(5);
1661	} while (1);
1662}
1663
1664static void etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1665{
1666	if (gpu->state == ETNA_GPU_STATE_RUNNING) {
1667		/* Replace the last WAIT with END */
1668		mutex_lock(&gpu->lock);
1669		etnaviv_buffer_end(gpu);
1670		mutex_unlock(&gpu->lock);
1671
1672		/*
1673		 * We know that only the FE is busy here, this should
1674		 * happen quickly (as the WAIT is only 200 cycles).  If
1675		 * we fail, just warn and continue.
1676		 */
1677		etnaviv_gpu_wait_idle(gpu, 100);
1678
1679		gpu->state = ETNA_GPU_STATE_INITIALIZED;
1680	}
1681
1682	gpu->exec_state = -1;
 
 
1683}
1684
 
1685static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1686{
1687	int ret;
1688
1689	ret = mutex_lock_killable(&gpu->lock);
1690	if (ret)
1691		return ret;
1692
1693	etnaviv_gpu_update_clock(gpu);
1694	etnaviv_gpu_hw_init(gpu);
1695
1696	mutex_unlock(&gpu->lock);
1697
1698	return 0;
1699}
 
1700
1701static int
1702etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1703				  unsigned long *state)
1704{
1705	*state = 6;
1706
1707	return 0;
1708}
1709
1710static int
1711etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1712				  unsigned long *state)
1713{
1714	struct etnaviv_gpu *gpu = cdev->devdata;
1715
1716	*state = gpu->freq_scale;
1717
1718	return 0;
1719}
1720
1721static int
1722etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1723				  unsigned long state)
1724{
1725	struct etnaviv_gpu *gpu = cdev->devdata;
1726
1727	mutex_lock(&gpu->lock);
1728	gpu->freq_scale = state;
1729	if (!pm_runtime_suspended(gpu->dev))
1730		etnaviv_gpu_update_clock(gpu);
1731	mutex_unlock(&gpu->lock);
1732
1733	return 0;
1734}
1735
1736static const struct thermal_cooling_device_ops cooling_ops = {
1737	.get_max_state = etnaviv_gpu_cooling_get_max_state,
1738	.get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1739	.set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1740};
1741
1742static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1743	void *data)
1744{
1745	struct drm_device *drm = data;
1746	struct etnaviv_drm_private *priv = drm->dev_private;
1747	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1748	int ret;
1749
1750	if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1751		gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1752				(char *)dev_name(dev), gpu, &cooling_ops);
1753		if (IS_ERR(gpu->cooling))
1754			return PTR_ERR(gpu->cooling);
1755	}
1756
1757	gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1758	if (!gpu->wq) {
1759		ret = -ENOMEM;
1760		goto out_thermal;
1761	}
1762
1763	ret = etnaviv_sched_init(gpu);
1764	if (ret)
1765		goto out_workqueue;
1766
1767	if (!IS_ENABLED(CONFIG_PM)) {
1768		ret = etnaviv_gpu_clk_enable(gpu);
1769		if (ret < 0)
1770			goto out_sched;
1771	}
 
 
 
1772
1773	gpu->drm = drm;
1774	gpu->fence_context = dma_fence_context_alloc(1);
1775	xa_init_flags(&gpu->user_fences, XA_FLAGS_ALLOC);
1776	spin_lock_init(&gpu->fence_spinlock);
1777
1778	INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1779	init_waitqueue_head(&gpu->fence_event);
1780
1781	priv->gpu[priv->num_gpus++] = gpu;
1782
 
 
 
1783	return 0;
1784
1785out_sched:
1786	etnaviv_sched_fini(gpu);
1787
1788out_workqueue:
1789	destroy_workqueue(gpu->wq);
1790
1791out_thermal:
1792	if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1793		thermal_cooling_device_unregister(gpu->cooling);
1794
1795	return ret;
1796}
1797
1798static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1799	void *data)
1800{
1801	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1802
1803	DBG("%s", dev_name(gpu->dev));
1804
1805	destroy_workqueue(gpu->wq);
1806
1807	etnaviv_sched_fini(gpu);
1808
1809	if (IS_ENABLED(CONFIG_PM)) {
1810		pm_runtime_get_sync(gpu->dev);
1811		pm_runtime_put_sync_suspend(gpu->dev);
1812	} else {
1813		etnaviv_gpu_hw_suspend(gpu);
1814		etnaviv_gpu_clk_disable(gpu);
1815	}
1816
1817	if (gpu->mmu_context)
1818		etnaviv_iommu_context_put(gpu->mmu_context);
1819
1820	etnaviv_cmdbuf_free(&gpu->buffer);
1821	etnaviv_iommu_global_fini(gpu);
 
 
 
1822
1823	gpu->drm = NULL;
1824	xa_destroy(&gpu->user_fences);
1825
1826	if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1827		thermal_cooling_device_unregister(gpu->cooling);
1828	gpu->cooling = NULL;
1829}
1830
1831static const struct component_ops gpu_ops = {
1832	.bind = etnaviv_gpu_bind,
1833	.unbind = etnaviv_gpu_unbind,
1834};
1835
1836static const struct of_device_id etnaviv_gpu_match[] = {
1837	{
1838		.compatible = "vivante,gc"
1839	},
1840	{ /* sentinel */ }
1841};
1842MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1843
1844static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1845{
1846	struct device *dev = &pdev->dev;
1847	struct etnaviv_gpu *gpu;
1848	int err;
1849
1850	gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1851	if (!gpu)
1852		return -ENOMEM;
1853
1854	gpu->dev = dev;
1855	mutex_init(&gpu->lock);
1856	mutex_init(&gpu->sched_lock);
1857
1858	/* Map registers: */
1859	gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
1860	if (IS_ERR(gpu->mmio))
1861		return PTR_ERR(gpu->mmio);
1862
1863	/* Get Interrupt: */
1864	gpu->irq = platform_get_irq(pdev, 0);
1865	if (gpu->irq < 0)
1866		return gpu->irq;
1867
1868	err = devm_request_irq(dev, gpu->irq, irq_handler, 0,
1869			       dev_name(dev), gpu);
1870	if (err) {
1871		dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1872		return err;
1873	}
1874
1875	/* Get Clocks: */
1876	gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg");
1877	DBG("clk_reg: %p", gpu->clk_reg);
1878	if (IS_ERR(gpu->clk_reg))
1879		return PTR_ERR(gpu->clk_reg);
1880
1881	gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus");
1882	DBG("clk_bus: %p", gpu->clk_bus);
1883	if (IS_ERR(gpu->clk_bus))
1884		return PTR_ERR(gpu->clk_bus);
1885
1886	gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1887	DBG("clk_core: %p", gpu->clk_core);
1888	if (IS_ERR(gpu->clk_core))
1889		return PTR_ERR(gpu->clk_core);
1890	gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1891
1892	gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader");
1893	DBG("clk_shader: %p", gpu->clk_shader);
1894	if (IS_ERR(gpu->clk_shader))
1895		return PTR_ERR(gpu->clk_shader);
1896	gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1897
1898	/* TODO: figure out max mapped size */
1899	dev_set_drvdata(dev, gpu);
1900
1901	/*
1902	 * We treat the device as initially suspended.  The runtime PM
1903	 * autosuspend delay is rather arbitary: no measurements have
1904	 * yet been performed to determine an appropriate value.
1905	 */
1906	pm_runtime_use_autosuspend(dev);
1907	pm_runtime_set_autosuspend_delay(dev, 200);
1908	pm_runtime_enable(dev);
1909
1910	err = component_add(dev, &gpu_ops);
1911	if (err < 0) {
1912		dev_err(dev, "failed to register component: %d\n", err);
1913		return err;
1914	}
1915
1916	return 0;
1917}
1918
1919static void etnaviv_gpu_platform_remove(struct platform_device *pdev)
1920{
1921	struct etnaviv_gpu *gpu = dev_get_drvdata(&pdev->dev);
1922
1923	component_del(&pdev->dev, &gpu_ops);
1924	pm_runtime_disable(&pdev->dev);
1925
1926	mutex_destroy(&gpu->lock);
1927	mutex_destroy(&gpu->sched_lock);
1928}
1929
 
1930static int etnaviv_gpu_rpm_suspend(struct device *dev)
1931{
1932	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1933	u32 idle, mask;
1934
1935	/* If there are any jobs in the HW queue, we're not idle */
1936	if (atomic_read(&gpu->sched.credit_count))
1937		return -EBUSY;
1938
1939	/* Check whether the hardware (except FE and MC) is idle */
1940	mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE |
1941				  VIVS_HI_IDLE_STATE_MC);
1942	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1943	if (idle != mask) {
1944		dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n",
1945				     idle);
1946		return -EBUSY;
1947	}
1948
1949	etnaviv_gpu_hw_suspend(gpu);
1950
1951	gpu->state = ETNA_GPU_STATE_IDENTIFIED;
1952
1953	return etnaviv_gpu_clk_disable(gpu);
1954}
1955
1956static int etnaviv_gpu_rpm_resume(struct device *dev)
1957{
1958	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1959	int ret;
1960
1961	ret = etnaviv_gpu_clk_enable(gpu);
1962	if (ret)
1963		return ret;
1964
1965	/* Re-initialise the basic hardware state */
1966	if (gpu->state == ETNA_GPU_STATE_IDENTIFIED) {
1967		ret = etnaviv_gpu_hw_resume(gpu);
1968		if (ret) {
1969			etnaviv_gpu_clk_disable(gpu);
1970			return ret;
1971		}
1972	}
1973
1974	return 0;
1975}
 
1976
1977static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1978	RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, NULL)
 
1979};
1980
1981struct platform_driver etnaviv_gpu_driver = {
1982	.driver = {
1983		.name = "etnaviv-gpu",
1984		.pm = pm_ptr(&etnaviv_gpu_pm_ops),
 
1985		.of_match_table = etnaviv_gpu_match,
1986	},
1987	.probe = etnaviv_gpu_platform_probe,
1988	.remove = etnaviv_gpu_platform_remove,
1989	.id_table = gpu_ids,
1990};