1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * MIPI Display Bus Interface (DBI) LCD controller support
   4 *
   5 * Copyright 2016 Noralf Trønnes
   6 */
   7
   8#include <linux/backlight.h>
   9#include <linux/debugfs.h>
  10#include <linux/delay.h>
  11#include <linux/gpio/consumer.h>
  12#include <linux/module.h>
  13#include <linux/regulator/consumer.h>
  14#include <linux/spi/spi.h>
  15
  16#include <drm/drm_connector.h>
  17#include <drm/drm_damage_helper.h>
  18#include <drm/drm_drv.h>
  19#include <drm/drm_file.h>
  20#include <drm/drm_format_helper.h>
  21#include <drm/drm_fourcc.h>
  22#include <drm/drm_framebuffer.h>
  23#include <drm/drm_gem.h>
  24#include <drm/drm_gem_atomic_helper.h>
  25#include <drm/drm_gem_framebuffer_helper.h>
  26#include <drm/drm_mipi_dbi.h>
  27#include <drm/drm_modes.h>
  28#include <drm/drm_probe_helper.h>
  29#include <drm/drm_rect.h>
  30#include <video/mipi_display.h>
  31
  32#define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */
  33
  34#define DCS_POWER_MODE_DISPLAY			BIT(2)
  35#define DCS_POWER_MODE_DISPLAY_NORMAL_MODE	BIT(3)
  36#define DCS_POWER_MODE_SLEEP_MODE		BIT(4)
  37#define DCS_POWER_MODE_PARTIAL_MODE		BIT(5)
  38#define DCS_POWER_MODE_IDLE_MODE		BIT(6)
  39#define DCS_POWER_MODE_RESERVED_MASK		(BIT(0) | BIT(1) | BIT(7))
  40
  41/**
  42 * DOC: overview
  43 *
  44 * This library provides helpers for MIPI Display Bus Interface (DBI)
  45 * compatible display controllers.
  46 *
  47 * Many controllers for tiny lcd displays are MIPI compliant and can use this
  48 * library. If a controller uses registers 0x2A and 0x2B to set the area to
  49 * update and uses register 0x2C to write to frame memory, it is most likely
  50 * MIPI compliant.
  51 *
  52 * Only MIPI Type 1 displays are supported since a full frame memory is needed.
  53 *
  54 * There are 3 MIPI DBI implementation types:
  55 *
  56 * A. Motorola 6800 type parallel bus
  57 *
  58 * B. Intel 8080 type parallel bus
  59 *
  60 * C. SPI type with 3 options:
  61 *
  62 *    1. 9-bit with the Data/Command signal as the ninth bit
  63 *    2. Same as above except it's sent as 16 bits
  64 *    3. 8-bit with the Data/Command signal as a separate D/CX pin
  65 *
  66 * Currently mipi_dbi only supports Type C options 1 and 3 with
  67 * mipi_dbi_spi_init().
  68 */
  69
  70#define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
  71({ \
  72	if (!len) \
  73		DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
  74	else if (len <= 32) \
  75		DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\
  76	else \
  77		DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
  78})
  79
  80static const u8 mipi_dbi_dcs_read_commands[] = {
  81	MIPI_DCS_GET_DISPLAY_ID,
  82	MIPI_DCS_GET_RED_CHANNEL,
  83	MIPI_DCS_GET_GREEN_CHANNEL,
  84	MIPI_DCS_GET_BLUE_CHANNEL,
  85	MIPI_DCS_GET_DISPLAY_STATUS,
  86	MIPI_DCS_GET_POWER_MODE,
  87	MIPI_DCS_GET_ADDRESS_MODE,
  88	MIPI_DCS_GET_PIXEL_FORMAT,
  89	MIPI_DCS_GET_DISPLAY_MODE,
  90	MIPI_DCS_GET_SIGNAL_MODE,
  91	MIPI_DCS_GET_DIAGNOSTIC_RESULT,
  92	MIPI_DCS_READ_MEMORY_START,
  93	MIPI_DCS_READ_MEMORY_CONTINUE,
  94	MIPI_DCS_GET_SCANLINE,
  95	MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
  96	MIPI_DCS_GET_CONTROL_DISPLAY,
  97	MIPI_DCS_GET_POWER_SAVE,
  98	MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
  99	MIPI_DCS_READ_DDB_START,
 100	MIPI_DCS_READ_DDB_CONTINUE,
 101	0, /* sentinel */
 102};
 103
 104static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd)
 105{
 106	unsigned int i;
 107
 108	if (!dbi->read_commands)
 109		return false;
 110
 111	for (i = 0; i < 0xff; i++) {
 112		if (!dbi->read_commands[i])
 113			return false;
 114		if (cmd == dbi->read_commands[i])
 115			return true;
 116	}
 117
 118	return false;
 119}
 120
 121/**
 122 * mipi_dbi_command_read - MIPI DCS read command
 123 * @dbi: MIPI DBI structure
 124 * @cmd: Command
 125 * @val: Value read
 126 *
 127 * Send MIPI DCS read command to the controller.
 128 *
 129 * Returns:
 130 * Zero on success, negative error code on failure.
 131 */
 132int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val)
 133{
 134	if (!dbi->read_commands)
 135		return -EACCES;
 136
 137	if (!mipi_dbi_command_is_read(dbi, cmd))
 138		return -EINVAL;
 139
 140	return mipi_dbi_command_buf(dbi, cmd, val, 1);
 141}
 142EXPORT_SYMBOL(mipi_dbi_command_read);
 143
 144/**
 145 * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array
 146 * @dbi: MIPI DBI structure
 147 * @cmd: Command
 148 * @data: Parameter buffer
 149 * @len: Buffer length
 150 *
 151 * Returns:
 152 * Zero on success, negative error code on failure.
 153 */
 154int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
 155{
 156	u8 *cmdbuf;
 157	int ret;
 158
 159	/* SPI requires dma-safe buffers */
 160	cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL);
 161	if (!cmdbuf)
 162		return -ENOMEM;
 163
 164	mutex_lock(&dbi->cmdlock);
 165	ret = dbi->command(dbi, cmdbuf, data, len);
 166	mutex_unlock(&dbi->cmdlock);
 167
 168	kfree(cmdbuf);
 169
 170	return ret;
 171}
 172EXPORT_SYMBOL(mipi_dbi_command_buf);
 173
 174/* This should only be used by mipi_dbi_command() */
 175int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data,
 176			      size_t len)
 177{
 178	u8 *buf;
 179	int ret;
 180
 181	buf = kmemdup(data, len, GFP_KERNEL);
 182	if (!buf)
 183		return -ENOMEM;
 184
 185	ret = mipi_dbi_command_buf(dbi, cmd, buf, len);
 186
 187	kfree(buf);
 188
 189	return ret;
 190}
 191EXPORT_SYMBOL(mipi_dbi_command_stackbuf);
 192
 193/**
 194 * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary
 195 * @dst: The destination buffer
 196 * @src: The source buffer
 197 * @fb: The source framebuffer
 198 * @clip: Clipping rectangle of the area to be copied
 199 * @swap: When true, swap MSB/LSB of 16-bit values
 200 * @fmtcnv_state: Format-conversion state
 201 *
 202 * Returns:
 203 * Zero on success, negative error code on failure.
 204 */
 205int mipi_dbi_buf_copy(void *dst, struct iosys_map *src, struct drm_framebuffer *fb,
 206		      struct drm_rect *clip, bool swap,
 207		      struct drm_format_conv_state *fmtcnv_state)
 208{
 209	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
 210	struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
 
 
 211	struct iosys_map dst_map = IOSYS_MAP_INIT_VADDR(dst);
 212	int ret;
 213
 214	ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
 215	if (ret)
 216		return ret;
 217
 
 
 
 
 218	switch (fb->format->format) {
 219	case DRM_FORMAT_RGB565:
 220		if (swap)
 221			drm_fb_swab(&dst_map, NULL, src, fb, clip, !gem->import_attach,
 222				    fmtcnv_state);
 223		else
 224			drm_fb_memcpy(&dst_map, NULL, src, fb, clip);
 225		break;
 226	case DRM_FORMAT_RGB888:
 227		drm_fb_memcpy(&dst_map, NULL, src, fb, clip);
 228		break;
 229	case DRM_FORMAT_XRGB8888:
 230		switch (dbidev->pixel_format) {
 231		case DRM_FORMAT_RGB565:
 232			drm_fb_xrgb8888_to_rgb565(&dst_map, NULL, src, fb, clip, fmtcnv_state, swap);
 233			break;
 234		case DRM_FORMAT_RGB888:
 235			drm_fb_xrgb8888_to_rgb888(&dst_map, NULL, src, fb, clip, fmtcnv_state);
 236			break;
 237		}
 238		break;
 239	default:
 240		drm_err_once(fb->dev, "Format is not supported: %p4cc\n",
 241			     &fb->format->format);
 242		ret = -EINVAL;
 243	}
 244
 
 
 245	drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
 246
 247	return ret;
 248}
 249EXPORT_SYMBOL(mipi_dbi_buf_copy);
 250
 251static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev,
 252					unsigned int xs, unsigned int xe,
 253					unsigned int ys, unsigned int ye)
 254{
 255	struct mipi_dbi *dbi = &dbidev->dbi;
 256
 257	xs += dbidev->left_offset;
 258	xe += dbidev->left_offset;
 259	ys += dbidev->top_offset;
 260	ye += dbidev->top_offset;
 261
 262	mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff,
 263			 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff);
 264	mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff,
 265			 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff);
 266}
 267
 268static void mipi_dbi_fb_dirty(struct iosys_map *src, struct drm_framebuffer *fb,
 269			      struct drm_rect *rect, struct drm_format_conv_state *fmtcnv_state)
 270{
 
 
 271	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
 272	unsigned int height = rect->y2 - rect->y1;
 273	unsigned int width = rect->x2 - rect->x1;
 274	const struct drm_format_info *dst_format;
 275	struct mipi_dbi *dbi = &dbidev->dbi;
 276	bool swap = dbi->swap_bytes;
 277	int ret = 0;
 278	size_t len;
 279	bool full;
 280	void *tr;
 281
 
 
 
 
 
 
 
 
 
 
 282	full = width == fb->width && height == fb->height;
 283
 284	DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
 285
 286	if (!dbi->dc || !full || swap ||
 287	    fb->format->format == DRM_FORMAT_XRGB8888) {
 288		tr = dbidev->tx_buf;
 289		ret = mipi_dbi_buf_copy(tr, src, fb, rect, swap, fmtcnv_state);
 290		if (ret)
 291			goto err_msg;
 292	} else {
 293		tr = src->vaddr; /* TODO: Use mapping abstraction properly */
 294	}
 295
 296	mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1,
 297				    rect->y2 - 1);
 298
 299	if (fb->format->format == DRM_FORMAT_XRGB8888)
 300		dst_format = drm_format_info(dbidev->pixel_format);
 301	else
 302		dst_format = fb->format;
 303	len = drm_format_info_min_pitch(dst_format, 0, width) * height;
 304
 305	ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, len);
 306err_msg:
 307	if (ret)
 308		drm_err_once(fb->dev, "Failed to update display %d\n", ret);
 
 
 
 
 
 309}
 310
 311/**
 312 * mipi_dbi_pipe_mode_valid - MIPI DBI mode-valid helper
 313 * @pipe: Simple display pipe
 314 * @mode: The mode to test
 315 *
 316 * This function validates a given display mode against the MIPI DBI's hardware
 317 * display. Drivers can use this as their &drm_simple_display_pipe_funcs->mode_valid
 318 * callback.
 319 */
 320enum drm_mode_status mipi_dbi_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
 321					      const struct drm_display_mode *mode)
 322{
 323	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
 324
 325	return drm_crtc_helper_mode_valid_fixed(&pipe->crtc, mode, &dbidev->mode);
 326}
 327EXPORT_SYMBOL(mipi_dbi_pipe_mode_valid);
 328
 329/**
 330 * mipi_dbi_pipe_update - Display pipe update helper
 331 * @pipe: Simple display pipe
 332 * @old_state: Old plane state
 333 *
 334 * This function handles framebuffer flushing and vblank events. Drivers can use
 335 * this as their &drm_simple_display_pipe_funcs->update callback.
 336 */
 337void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
 338			  struct drm_plane_state *old_state)
 339{
 340	struct drm_plane_state *state = pipe->plane.state;
 341	struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state);
 342	struct drm_framebuffer *fb = state->fb;
 343	struct drm_rect rect;
 344	int idx;
 345
 346	if (!pipe->crtc.state->active)
 347		return;
 348
 349	if (WARN_ON(!fb))
 350		return;
 351
 352	if (!drm_dev_enter(fb->dev, &idx))
 353		return;
 354
 355	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
 356		mipi_dbi_fb_dirty(&shadow_plane_state->data[0], fb, &rect,
 357				  &shadow_plane_state->fmtcnv_state);
 358
 359	drm_dev_exit(idx);
 360}
 361EXPORT_SYMBOL(mipi_dbi_pipe_update);
 362
 363/**
 364 * mipi_dbi_enable_flush - MIPI DBI enable helper
 365 * @dbidev: MIPI DBI device structure
 366 * @crtc_state: CRTC state
 367 * @plane_state: Plane state
 368 *
 369 * Flushes the whole framebuffer and enables the backlight. Drivers can use this
 370 * in their &drm_simple_display_pipe_funcs->enable callback.
 371 *
 372 * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom
 373 * framebuffer flushing, can't use this function since they both use the same
 374 * flushing code.
 375 */
 376void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
 377			   struct drm_crtc_state *crtc_state,
 378			   struct drm_plane_state *plane_state)
 379{
 380	struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
 381	struct drm_framebuffer *fb = plane_state->fb;
 382	struct drm_rect rect = {
 383		.x1 = 0,
 384		.x2 = fb->width,
 385		.y1 = 0,
 386		.y2 = fb->height,
 387	};
 388	int idx;
 389
 390	if (!drm_dev_enter(&dbidev->drm, &idx))
 391		return;
 392
 393	mipi_dbi_fb_dirty(&shadow_plane_state->data[0], fb, &rect,
 394			  &shadow_plane_state->fmtcnv_state);
 395	backlight_enable(dbidev->backlight);
 396
 397	drm_dev_exit(idx);
 398}
 399EXPORT_SYMBOL(mipi_dbi_enable_flush);
 400
 401static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev)
 402{
 403	struct drm_device *drm = &dbidev->drm;
 404	u16 height = drm->mode_config.min_height;
 405	u16 width = drm->mode_config.min_width;
 406	struct mipi_dbi *dbi = &dbidev->dbi;
 407	size_t len = width * height * 2;
 408	int idx;
 409
 410	if (!drm_dev_enter(drm, &idx))
 411		return;
 412
 413	memset(dbidev->tx_buf, 0, len);
 414
 415	mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1);
 416	mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
 417			     (u8 *)dbidev->tx_buf, len);
 418
 419	drm_dev_exit(idx);
 420}
 421
 422/**
 423 * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper
 424 * @pipe: Display pipe
 425 *
 426 * This function disables backlight if present, if not the display memory is
 427 * blanked. The regulator is disabled if in use. Drivers can use this as their
 428 * &drm_simple_display_pipe_funcs->disable callback.
 429 */
 430void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
 431{
 432	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
 433
 434	DRM_DEBUG_KMS("\n");
 435
 436	if (dbidev->backlight)
 437		backlight_disable(dbidev->backlight);
 438	else
 439		mipi_dbi_blank(dbidev);
 440
 441	if (dbidev->regulator)
 442		regulator_disable(dbidev->regulator);
 443	if (dbidev->io_regulator)
 444		regulator_disable(dbidev->io_regulator);
 445}
 446EXPORT_SYMBOL(mipi_dbi_pipe_disable);
 447
 448/**
 449 * mipi_dbi_pipe_begin_fb_access - MIPI DBI pipe begin-access helper
 450 * @pipe: Display pipe
 451 * @plane_state: Plane state
 452 *
 453 * This function implements struct &drm_simple_display_funcs.begin_fb_access.
 454 *
 455 * See drm_gem_begin_shadow_fb_access() for details and mipi_dbi_pipe_cleanup_fb()
 456 * for cleanup.
 457 *
 458 * Returns:
 459 * 0 on success, or a negative errno code otherwise.
 460 */
 461int mipi_dbi_pipe_begin_fb_access(struct drm_simple_display_pipe *pipe,
 462				  struct drm_plane_state *plane_state)
 463{
 464	return drm_gem_begin_shadow_fb_access(&pipe->plane, plane_state);
 465}
 466EXPORT_SYMBOL(mipi_dbi_pipe_begin_fb_access);
 467
 468/**
 469 * mipi_dbi_pipe_end_fb_access - MIPI DBI pipe end-access helper
 470 * @pipe: Display pipe
 471 * @plane_state: Plane state
 472 *
 473 * This function implements struct &drm_simple_display_funcs.end_fb_access.
 474 *
 475 * See mipi_dbi_pipe_begin_fb_access().
 476 */
 477void mipi_dbi_pipe_end_fb_access(struct drm_simple_display_pipe *pipe,
 478				 struct drm_plane_state *plane_state)
 479{
 480	drm_gem_end_shadow_fb_access(&pipe->plane, plane_state);
 481}
 482EXPORT_SYMBOL(mipi_dbi_pipe_end_fb_access);
 483
 484/**
 485 * mipi_dbi_pipe_reset_plane - MIPI DBI plane-reset helper
 486 * @pipe: Display pipe
 487 *
 488 * This function implements struct &drm_simple_display_funcs.reset_plane
 489 * for MIPI DBI planes.
 490 */
 491void mipi_dbi_pipe_reset_plane(struct drm_simple_display_pipe *pipe)
 492{
 493	drm_gem_reset_shadow_plane(&pipe->plane);
 494}
 495EXPORT_SYMBOL(mipi_dbi_pipe_reset_plane);
 496
 497/**
 498 * mipi_dbi_pipe_duplicate_plane_state - duplicates MIPI DBI plane state
 499 * @pipe: Display pipe
 500 *
 501 * This function implements struct &drm_simple_display_funcs.duplicate_plane_state
 502 * for MIPI DBI planes.
 503 *
 504 * See drm_gem_duplicate_shadow_plane_state() for additional details.
 505 *
 506 * Returns:
 507 * A pointer to a new plane state on success, or NULL otherwise.
 508 */
 509struct drm_plane_state *mipi_dbi_pipe_duplicate_plane_state(struct drm_simple_display_pipe *pipe)
 510{
 511	return drm_gem_duplicate_shadow_plane_state(&pipe->plane);
 512}
 513EXPORT_SYMBOL(mipi_dbi_pipe_duplicate_plane_state);
 514
 515/**
 516 * mipi_dbi_pipe_destroy_plane_state - cleans up MIPI DBI plane state
 517 * @pipe: Display pipe
 518 * @plane_state: Plane state
 519 *
 520 * This function implements struct drm_simple_display_funcs.destroy_plane_state
 521 * for MIPI DBI planes.
 522 *
 523 * See drm_gem_destroy_shadow_plane_state() for additional details.
 524 */
 525void mipi_dbi_pipe_destroy_plane_state(struct drm_simple_display_pipe *pipe,
 526				       struct drm_plane_state *plane_state)
 527{
 528	drm_gem_destroy_shadow_plane_state(&pipe->plane, plane_state);
 529}
 530EXPORT_SYMBOL(mipi_dbi_pipe_destroy_plane_state);
 531
 532static int mipi_dbi_connector_get_modes(struct drm_connector *connector)
 533{
 534	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev);
 535
 536	return drm_connector_helper_get_modes_fixed(connector, &dbidev->mode);
 537}
 538
 539static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = {
 540	.get_modes = mipi_dbi_connector_get_modes,
 541};
 542
 543static const struct drm_connector_funcs mipi_dbi_connector_funcs = {
 544	.reset = drm_atomic_helper_connector_reset,
 545	.fill_modes = drm_helper_probe_single_connector_modes,
 546	.destroy = drm_connector_cleanup,
 547	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 548	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 549};
 550
 551static int mipi_dbi_rotate_mode(struct drm_display_mode *mode,
 552				unsigned int rotation)
 553{
 554	if (rotation == 0 || rotation == 180) {
 555		return 0;
 556	} else if (rotation == 90 || rotation == 270) {
 557		swap(mode->hdisplay, mode->vdisplay);
 558		swap(mode->hsync_start, mode->vsync_start);
 559		swap(mode->hsync_end, mode->vsync_end);
 560		swap(mode->htotal, mode->vtotal);
 561		swap(mode->width_mm, mode->height_mm);
 562		return 0;
 563	} else {
 564		return -EINVAL;
 565	}
 566}
 567
 568static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = {
 569	.fb_create = drm_gem_fb_create_with_dirty,
 570	.atomic_check = drm_atomic_helper_check,
 571	.atomic_commit = drm_atomic_helper_commit,
 572};
 573
 574static const uint32_t mipi_dbi_formats[] = {
 575	DRM_FORMAT_RGB565,
 576	DRM_FORMAT_XRGB8888,
 577};
 578
 579/**
 580 * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats
 581 * @dbidev: MIPI DBI device structure to initialize
 582 * @funcs: Display pipe functions
 583 * @formats: Array of supported formats (DRM_FORMAT\_\*).
 584 * @format_count: Number of elements in @formats
 585 * @mode: Display mode
 586 * @rotation: Initial rotation in degrees Counter Clock Wise
 587 * @tx_buf_size: Allocate a transmit buffer of this size.
 588 *
 589 * This function sets up a &drm_simple_display_pipe with a &drm_connector that
 590 * has one fixed &drm_display_mode which is rotated according to @rotation.
 591 * This mode is used to set the mode config min/max width/height properties.
 592 *
 593 * Use mipi_dbi_dev_init() if you want native RGB565 and emulated XRGB8888 format.
 594 *
 595 * Note:
 596 * Some of the helper functions expects RGB565 to be the default format and the
 597 * transmit buffer sized to fit that.
 598 *
 599 * Returns:
 600 * Zero on success, negative error code on failure.
 601 */
 602int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
 603				   const struct drm_simple_display_pipe_funcs *funcs,
 604				   const uint32_t *formats, unsigned int format_count,
 605				   const struct drm_display_mode *mode,
 606				   unsigned int rotation, size_t tx_buf_size)
 607{
 608	static const uint64_t modifiers[] = {
 609		DRM_FORMAT_MOD_LINEAR,
 610		DRM_FORMAT_MOD_INVALID
 611	};
 612	struct drm_device *drm = &dbidev->drm;
 613	int ret;
 614
 615	if (!dbidev->dbi.command)
 616		return -EINVAL;
 617
 618	ret = drmm_mode_config_init(drm);
 619	if (ret)
 620		return ret;
 621
 622	dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL);
 623	if (!dbidev->tx_buf)
 624		return -ENOMEM;
 625
 626	drm_mode_copy(&dbidev->mode, mode);
 627	ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation);
 628	if (ret) {
 629		DRM_ERROR("Illegal rotation value %u\n", rotation);
 630		return -EINVAL;
 631	}
 632
 633	drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs);
 634	ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs,
 635				 DRM_MODE_CONNECTOR_SPI);
 636	if (ret)
 637		return ret;
 638
 639	ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count,
 640					   modifiers, &dbidev->connector);
 641	if (ret)
 642		return ret;
 643
 644	drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane);
 645
 646	drm->mode_config.funcs = &mipi_dbi_mode_config_funcs;
 647	drm->mode_config.min_width = dbidev->mode.hdisplay;
 648	drm->mode_config.max_width = dbidev->mode.hdisplay;
 649	drm->mode_config.min_height = dbidev->mode.vdisplay;
 650	drm->mode_config.max_height = dbidev->mode.vdisplay;
 651	dbidev->rotation = rotation;
 652	dbidev->pixel_format = formats[0];
 653	if (formats[0] == DRM_FORMAT_RGB888)
 654		dbidev->dbi.write_memory_bpw = 8;
 655
 656	DRM_DEBUG_KMS("rotation = %u\n", rotation);
 657
 658	return 0;
 659}
 660EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats);
 661
 662/**
 663 * mipi_dbi_dev_init - MIPI DBI device initialization
 664 * @dbidev: MIPI DBI device structure to initialize
 665 * @funcs: Display pipe functions
 666 * @mode: Display mode
 667 * @rotation: Initial rotation in degrees Counter Clock Wise
 668 *
 669 * This function sets up a &drm_simple_display_pipe with a &drm_connector that
 670 * has one fixed &drm_display_mode which is rotated according to @rotation.
 671 * This mode is used to set the mode config min/max width/height properties.
 672 * Additionally &mipi_dbi.tx_buf is allocated.
 673 *
 674 * Supported formats: Native RGB565 and emulated XRGB8888.
 675 *
 676 * Returns:
 677 * Zero on success, negative error code on failure.
 678 */
 679int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
 680		      const struct drm_simple_display_pipe_funcs *funcs,
 681		      const struct drm_display_mode *mode, unsigned int rotation)
 682{
 683	size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16);
 684
 685	dbidev->drm.mode_config.preferred_depth = 16;
 686
 687	return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats,
 688					      ARRAY_SIZE(mipi_dbi_formats), mode,
 689					      rotation, bufsize);
 690}
 691EXPORT_SYMBOL(mipi_dbi_dev_init);
 692
 693/**
 694 * mipi_dbi_hw_reset - Hardware reset of controller
 695 * @dbi: MIPI DBI structure
 696 *
 697 * Reset controller if the &mipi_dbi->reset gpio is set.
 698 */
 699void mipi_dbi_hw_reset(struct mipi_dbi *dbi)
 700{
 701	if (!dbi->reset)
 702		return;
 703
 704	gpiod_set_value_cansleep(dbi->reset, 0);
 705	usleep_range(20, 1000);
 706	gpiod_set_value_cansleep(dbi->reset, 1);
 707	msleep(120);
 708}
 709EXPORT_SYMBOL(mipi_dbi_hw_reset);
 710
 711/**
 712 * mipi_dbi_display_is_on - Check if display is on
 713 * @dbi: MIPI DBI structure
 714 *
 715 * This function checks the Power Mode register (if readable) to see if
 716 * display output is turned on. This can be used to see if the bootloader
 717 * has already turned on the display avoiding flicker when the pipeline is
 718 * enabled.
 719 *
 720 * Returns:
 721 * true if the display can be verified to be on, false otherwise.
 722 */
 723bool mipi_dbi_display_is_on(struct mipi_dbi *dbi)
 724{
 725	u8 val;
 726
 727	if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val))
 728		return false;
 729
 730	val &= ~DCS_POWER_MODE_RESERVED_MASK;
 731
 732	/* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */
 733	if (val != (DCS_POWER_MODE_DISPLAY |
 734	    DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
 735		return false;
 736
 737	DRM_DEBUG_DRIVER("Display is ON\n");
 738
 739	return true;
 740}
 741EXPORT_SYMBOL(mipi_dbi_display_is_on);
 742
 743static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond)
 744{
 745	struct device *dev = dbidev->drm.dev;
 746	struct mipi_dbi *dbi = &dbidev->dbi;
 747	int ret;
 748
 749	if (dbidev->regulator) {
 750		ret = regulator_enable(dbidev->regulator);
 751		if (ret) {
 752			DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret);
 753			return ret;
 754		}
 755	}
 756
 757	if (dbidev->io_regulator) {
 758		ret = regulator_enable(dbidev->io_regulator);
 759		if (ret) {
 760			DRM_DEV_ERROR(dev, "Failed to enable I/O regulator (%d)\n", ret);
 761			if (dbidev->regulator)
 762				regulator_disable(dbidev->regulator);
 763			return ret;
 764		}
 765	}
 766
 767	if (cond && mipi_dbi_display_is_on(dbi))
 768		return 1;
 769
 770	mipi_dbi_hw_reset(dbi);
 771	ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET);
 772	if (ret) {
 773		DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret);
 774		if (dbidev->regulator)
 775			regulator_disable(dbidev->regulator);
 776		if (dbidev->io_regulator)
 777			regulator_disable(dbidev->io_regulator);
 778		return ret;
 779	}
 780
 781	/*
 782	 * If we did a hw reset, we know the controller is in Sleep mode and
 783	 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't,
 784	 * we assume worst case and wait 120ms.
 785	 */
 786	if (dbi->reset)
 787		usleep_range(5000, 20000);
 788	else
 789		msleep(120);
 790
 791	return 0;
 792}
 793
 794/**
 795 * mipi_dbi_poweron_reset - MIPI DBI poweron and reset
 796 * @dbidev: MIPI DBI device structure
 797 *
 798 * This function enables the regulator if used and does a hardware and software
 799 * reset.
 800 *
 801 * Returns:
 802 * Zero on success, or a negative error code.
 803 */
 804int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev)
 805{
 806	return mipi_dbi_poweron_reset_conditional(dbidev, false);
 807}
 808EXPORT_SYMBOL(mipi_dbi_poweron_reset);
 809
 810/**
 811 * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset
 812 * @dbidev: MIPI DBI device structure
 813 *
 814 * This function enables the regulator if used and if the display is off, it
 815 * does a hardware and software reset. If mipi_dbi_display_is_on() determines
 816 * that the display is on, no reset is performed.
 817 *
 818 * Returns:
 819 * Zero if the controller was reset, 1 if the display was already on, or a
 820 * negative error code.
 821 */
 822int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev)
 823{
 824	return mipi_dbi_poweron_reset_conditional(dbidev, true);
 825}
 826EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset);
 827
 828#if IS_ENABLED(CONFIG_SPI)
 829
 830/**
 831 * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed
 832 * @spi: SPI device
 833 * @len: The transfer buffer length.
 834 *
 835 * Many controllers have a max speed of 10MHz, but can be pushed way beyond
 836 * that. Increase reliability by running pixel data at max speed and the rest
 837 * at 10MHz, preventing transfer glitches from messing up the init settings.
 838 */
 839u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
 840{
 841	if (len > 64)
 842		return 0; /* use default */
 843
 844	return min_t(u32, 10000000, spi->max_speed_hz);
 845}
 846EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
 847
 
 
 
 
 
 
 
 
 
 848/*
 849 * MIPI DBI Type C Option 1
 850 *
 851 * If the SPI controller doesn't have 9 bits per word support,
 852 * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer.
 853 * Pad partial blocks with MIPI_DCS_NOP (zero).
 854 * This is how the D/C bit (x) is added:
 855 *     x7654321
 856 *     0x765432
 857 *     10x76543
 858 *     210x7654
 859 *     3210x765
 860 *     43210x76
 861 *     543210x7
 862 *     6543210x
 863 *     76543210
 864 */
 865
 866static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,
 867				   const void *buf, size_t len,
 868				   unsigned int bpw)
 869{
 870	bool swap_bytes = (bpw == 16);
 871	size_t chunk, max_chunk = dbi->tx_buf9_len;
 872	struct spi_device *spi = dbi->spi;
 873	struct spi_transfer tr = {
 874		.tx_buf = dbi->tx_buf9,
 875		.bits_per_word = 8,
 876	};
 877	struct spi_message m;
 878	const u8 *src = buf;
 879	int i, ret;
 880	u8 *dst;
 881
 882	if (drm_debug_enabled(DRM_UT_DRIVER))
 883		pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
 884			 __func__, dc, max_chunk);
 885
 886	tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
 887	spi_message_init_with_transfers(&m, &tr, 1);
 888
 889	if (!dc) {
 890		if (WARN_ON_ONCE(len != 1))
 891			return -EINVAL;
 892
 893		/* Command: pad no-op's (zeroes) at beginning of block */
 894		dst = dbi->tx_buf9;
 895		memset(dst, 0, 9);
 896		dst[8] = *src;
 897		tr.len = 9;
 898
 899		return spi_sync(spi, &m);
 900	}
 901
 902	/* max with room for adding one bit per byte */
 903	max_chunk = max_chunk / 9 * 8;
 904	/* but no bigger than len */
 905	max_chunk = min(max_chunk, len);
 906	/* 8 byte blocks */
 907	max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
 908
 909	while (len) {
 910		size_t added = 0;
 911
 912		chunk = min(len, max_chunk);
 913		len -= chunk;
 914		dst = dbi->tx_buf9;
 915
 916		if (chunk < 8) {
 917			u8 val, carry = 0;
 918
 919			/* Data: pad no-op's (zeroes) at end of block */
 920			memset(dst, 0, 9);
 921
 922			if (swap_bytes) {
 923				for (i = 1; i < (chunk + 1); i++) {
 924					val = src[1];
 925					*dst++ = carry | BIT(8 - i) | (val >> i);
 926					carry = val << (8 - i);
 927					i++;
 928					val = src[0];
 929					*dst++ = carry | BIT(8 - i) | (val >> i);
 930					carry = val << (8 - i);
 931					src += 2;
 932				}
 933				*dst++ = carry;
 934			} else {
 935				for (i = 1; i < (chunk + 1); i++) {
 936					val = *src++;
 937					*dst++ = carry | BIT(8 - i) | (val >> i);
 938					carry = val << (8 - i);
 939				}
 940				*dst++ = carry;
 941			}
 942
 943			chunk = 8;
 944			added = 1;
 945		} else {
 946			for (i = 0; i < chunk; i += 8) {
 947				if (swap_bytes) {
 948					*dst++ =                 BIT(7) | (src[1] >> 1);
 949					*dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
 950					*dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
 951					*dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
 952					*dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
 953					*dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
 954					*dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
 955					*dst++ = (src[7] << 1) | BIT(0);
 956					*dst++ = src[6];
 957				} else {
 958					*dst++ =                 BIT(7) | (src[0] >> 1);
 959					*dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
 960					*dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
 961					*dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
 962					*dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
 963					*dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
 964					*dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
 965					*dst++ = (src[6] << 1) | BIT(0);
 966					*dst++ = src[7];
 967				}
 968
 969				src += 8;
 970				added++;
 971			}
 972		}
 973
 974		tr.len = chunk + added;
 975
 976		ret = spi_sync(spi, &m);
 977		if (ret)
 978			return ret;
 979	}
 980
 981	return 0;
 982}
 983
 984static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,
 985				  const void *buf, size_t len,
 986				  unsigned int bpw)
 987{
 988	struct spi_device *spi = dbi->spi;
 989	struct spi_transfer tr = {
 990		.bits_per_word = 9,
 991	};
 992	const u16 *src16 = buf;
 993	const u8 *src8 = buf;
 994	struct spi_message m;
 995	size_t max_chunk;
 996	u16 *dst16;
 997	int ret;
 998
 999	if (!spi_is_bpw_supported(spi, 9))
1000		return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);
1001
1002	tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
1003	max_chunk = dbi->tx_buf9_len;
1004	dst16 = dbi->tx_buf9;
1005
1006	if (drm_debug_enabled(DRM_UT_DRIVER))
1007		pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
1008			 __func__, dc, max_chunk);
1009
1010	max_chunk = min(max_chunk / 2, len);
1011
1012	spi_message_init_with_transfers(&m, &tr, 1);
1013	tr.tx_buf = dst16;
1014
1015	while (len) {
1016		size_t chunk = min(len, max_chunk);
1017		unsigned int i;
1018
1019		if (bpw == 16) {
1020			for (i = 0; i < (chunk * 2); i += 2) {
1021				dst16[i]     = *src16 >> 8;
1022				dst16[i + 1] = *src16++ & 0xFF;
1023				if (dc) {
1024					dst16[i]     |= 0x0100;
1025					dst16[i + 1] |= 0x0100;
1026				}
1027			}
1028		} else {
1029			for (i = 0; i < chunk; i++) {
1030				dst16[i] = *src8++;
1031				if (dc)
1032					dst16[i] |= 0x0100;
1033			}
1034		}
1035
1036		tr.len = chunk * 2;
1037		len -= chunk;
1038
1039		ret = spi_sync(spi, &m);
1040		if (ret)
1041			return ret;
1042	}
1043
1044	return 0;
1045}
1046
1047static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd,
1048					u8 *data, size_t len)
1049{
1050	struct spi_device *spi = dbi->spi;
1051	u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
1052			     spi->max_speed_hz / 2);
1053	struct spi_transfer tr[2] = {
1054		{
1055			.speed_hz = speed_hz,
1056			.bits_per_word = 9,
1057			.tx_buf = dbi->tx_buf9,
1058			.len = 2,
1059		}, {
1060			.speed_hz = speed_hz,
1061			.bits_per_word = 8,
1062			.len = len,
1063			.rx_buf = data,
1064		},
1065	};
1066	struct spi_message m;
1067	u16 *dst16;
1068	int ret;
1069
1070	if (!len)
1071		return -EINVAL;
1072
1073	if (!spi_is_bpw_supported(spi, 9)) {
1074		/*
1075		 * FIXME: implement something like mipi_dbi_spi1e_transfer() but
1076		 * for reads using emulation.
1077		 */
1078		dev_err(&spi->dev,
1079			"reading on host not supporting 9 bpw not yet implemented\n");
1080		return -EOPNOTSUPP;
1081	}
1082
1083	/*
1084	 * Turn the 8bit command into a 16bit version of the command in the
1085	 * buffer. Only 9 bits of this will be used when executing the actual
1086	 * transfer.
1087	 */
1088	dst16 = dbi->tx_buf9;
1089	dst16[0] = *cmd;
1090
1091	spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
1092	ret = spi_sync(spi, &m);
1093
1094	if (!ret)
1095		MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
1096
1097	return ret;
1098}
1099
1100static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,
1101				   u8 *parameters, size_t num)
1102{
1103	unsigned int bpw = 8;
1104	int ret;
1105
1106	if (mipi_dbi_command_is_read(dbi, *cmd))
1107		return mipi_dbi_typec1_command_read(dbi, cmd, parameters, num);
1108
1109	MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num);
1110
1111	ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8);
1112	if (ret || !num)
1113		return ret;
1114
1115	if (*cmd == MIPI_DCS_WRITE_MEMORY_START)
1116		bpw = dbi->write_memory_bpw;
1117
1118	return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);
1119}
1120
1121/* MIPI DBI Type C Option 3 */
1122
1123static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd,
1124					u8 *data, size_t len)
1125{
1126	struct spi_device *spi = dbi->spi;
1127	u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
1128			     spi->max_speed_hz / 2);
1129	struct spi_transfer tr[2] = {
1130		{
1131			.speed_hz = speed_hz,
1132			.tx_buf = cmd,
1133			.len = 1,
1134		}, {
1135			.speed_hz = speed_hz,
1136			.len = len,
1137		},
1138	};
1139	struct spi_message m;
1140	u8 *buf;
1141	int ret;
1142
1143	if (!len)
1144		return -EINVAL;
1145
1146	/*
1147	 * Support non-standard 24-bit and 32-bit Nokia read commands which
1148	 * start with a dummy clock, so we need to read an extra byte.
1149	 */
1150	if (*cmd == MIPI_DCS_GET_DISPLAY_ID ||
1151	    *cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
1152		if (!(len == 3 || len == 4))
1153			return -EINVAL;
1154
1155		tr[1].len = len + 1;
1156	}
1157
1158	buf = kmalloc(tr[1].len, GFP_KERNEL);
1159	if (!buf)
1160		return -ENOMEM;
1161
1162	tr[1].rx_buf = buf;
1163
1164	spi_bus_lock(spi->controller);
1165	gpiod_set_value_cansleep(dbi->dc, 0);
1166
1167	spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
1168	ret = spi_sync_locked(spi, &m);
1169	spi_bus_unlock(spi->controller);
1170	if (ret)
1171		goto err_free;
1172
1173	if (tr[1].len == len) {
1174		memcpy(data, buf, len);
1175	} else {
1176		unsigned int i;
1177
1178		for (i = 0; i < len; i++)
1179			data[i] = (buf[i] << 1) | (buf[i + 1] >> 7);
1180	}
1181
1182	MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
1183
1184err_free:
1185	kfree(buf);
1186
1187	return ret;
1188}
1189
1190static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd,
1191				   u8 *par, size_t num)
1192{
1193	struct spi_device *spi = dbi->spi;
1194	unsigned int bpw = 8;
1195	u32 speed_hz;
1196	int ret;
1197
1198	if (mipi_dbi_command_is_read(dbi, *cmd))
1199		return mipi_dbi_typec3_command_read(dbi, cmd, par, num);
1200
1201	MIPI_DBI_DEBUG_COMMAND(*cmd, par, num);
1202
1203	spi_bus_lock(spi->controller);
1204	gpiod_set_value_cansleep(dbi->dc, 0);
1205	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
1206	ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1);
1207	spi_bus_unlock(spi->controller);
1208	if (ret || !num)
1209		return ret;
1210
1211	if (*cmd == MIPI_DCS_WRITE_MEMORY_START)
1212		bpw = dbi->write_memory_bpw;
1213
1214	spi_bus_lock(spi->controller);
1215	gpiod_set_value_cansleep(dbi->dc, 1);
1216	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
1217	ret = mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num);
1218	spi_bus_unlock(spi->controller);
1219
1220	return ret;
1221}
1222
1223/**
1224 * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface
1225 * @spi: SPI device
1226 * @dbi: MIPI DBI structure to initialize
1227 * @dc: D/C gpio (optional)
1228 *
1229 * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the
1230 * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or
1231 * a driver-specific init.
1232 *
1233 * If @dc is set, a Type C Option 3 interface is assumed, if not
1234 * Type C Option 1.
1235 *
1236 * If the command is %MIPI_DCS_WRITE_MEMORY_START and the pixel format is RGB565, endianness has
1237 * to be taken into account. The MIPI DBI serial interface is big endian and framebuffers are
1238 * assumed stored in memory as little endian (%DRM_FORMAT_BIG_ENDIAN is not supported).
1239 *
1240 * This is how endianness is handled:
1241 *
1242 * Option 1 (D/C as a bit): The buffer is sent on the wire byte by byte so the 16-bit buffer is
1243 *                          byteswapped before transfer.
1244 *
1245 * Option 3 (D/C as a gpio): If the SPI controller supports 16 bits per word the buffer can be
1246 *                           sent as-is. If not the caller is responsible for swapping the bytes
1247 *                           before calling mipi_dbi_command_buf() and the buffer is sent 8 bpw.
1248 *
1249 * This handling is optimised for %DRM_FORMAT_RGB565 framebuffers.
1250 *
1251 * If the interface is Option 1 and the SPI controller doesn't support 9 bits per word,
1252 * the buffer is sent as 9x 8-bit words, padded with MIPI DCS no-op commands if necessary.
1253 *
1254 * Returns:
1255 * Zero on success, negative error code on failure.
1256 */
1257int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
1258		      struct gpio_desc *dc)
1259{
1260	struct device *dev = &spi->dev;
1261	int ret;
1262
1263	/*
1264	 * Even though it's not the SPI device that does DMA (the master does),
1265	 * the dma mask is necessary for the dma_alloc_wc() in the GEM code
1266	 * (e.g., drm_gem_dma_create()). The dma_addr returned will be a physical
1267	 * address which might be different from the bus address, but this is
1268	 * not a problem since the address will not be used.
1269	 * The virtual address is used in the transfer and the SPI core
1270	 * re-maps it on the SPI master device using the DMA streaming API
1271	 * (spi_map_buf()).
1272	 */
1273	if (!dev->coherent_dma_mask) {
1274		ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
1275		if (ret) {
1276			dev_warn(dev, "Failed to set dma mask %d\n", ret);
1277			return ret;
1278		}
1279	}
1280
1281	dbi->spi = spi;
1282	dbi->read_commands = mipi_dbi_dcs_read_commands;
1283	dbi->write_memory_bpw = 16;
1284
1285	if (dc) {
1286		dbi->command = mipi_dbi_typec3_command;
1287		dbi->dc = dc;
1288		if (!spi_is_bpw_supported(spi, 16)) {
1289			dbi->write_memory_bpw = 8;
1290			dbi->swap_bytes = true;
1291		}
1292	} else {
1293		dbi->command = mipi_dbi_typec1_command;
1294		dbi->tx_buf9_len = SZ_16K;
1295		dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL);
1296		if (!dbi->tx_buf9)
1297			return -ENOMEM;
1298	}
1299
1300	mutex_init(&dbi->cmdlock);
1301
1302	DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
1303
1304	return 0;
1305}
1306EXPORT_SYMBOL(mipi_dbi_spi_init);
1307
1308/**
1309 * mipi_dbi_spi_transfer - SPI transfer helper
1310 * @spi: SPI device
1311 * @speed_hz: Override speed (optional)
1312 * @bpw: Bits per word
1313 * @buf: Buffer to transfer
1314 * @len: Buffer length
1315 *
1316 * This SPI transfer helper breaks up the transfer of @buf into chunks which
1317 * the SPI controller driver can handle. The SPI bus must be locked when
1318 * calling this.
1319 *
1320 * Returns:
1321 * Zero on success, negative error code on failure.
1322 */
1323int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
1324			  u8 bpw, const void *buf, size_t len)
1325{
1326	size_t max_chunk = spi_max_transfer_size(spi);
1327	struct spi_transfer tr = {
1328		.bits_per_word = bpw,
1329		.speed_hz = speed_hz,
1330	};
1331	struct spi_message m;
1332	size_t chunk;
1333	int ret;
1334
1335	/* In __spi_validate, there's a validation that no partial transfers
1336	 * are accepted (xfer->len % w_size must be zero).
1337	 * Here we align max_chunk to multiple of 2 (16bits),
1338	 * to prevent transfers from being rejected.
1339	 */
1340	max_chunk = ALIGN_DOWN(max_chunk, 2);
1341
1342	spi_message_init_with_transfers(&m, &tr, 1);
1343
1344	while (len) {
1345		chunk = min(len, max_chunk);
1346
1347		tr.tx_buf = buf;
1348		tr.len = chunk;
1349		buf += chunk;
1350		len -= chunk;
1351
1352		ret = spi_sync_locked(spi, &m);
1353		if (ret)
1354			return ret;
1355	}
1356
1357	return 0;
1358}
1359EXPORT_SYMBOL(mipi_dbi_spi_transfer);
1360
1361#endif /* CONFIG_SPI */
1362
1363#ifdef CONFIG_DEBUG_FS
1364
1365static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
1366					      const char __user *ubuf,
1367					      size_t count, loff_t *ppos)
1368{
1369	struct seq_file *m = file->private_data;
1370	struct mipi_dbi_dev *dbidev = m->private;
1371	u8 val, cmd = 0, parameters[64];
1372	char *buf, *pos, *token;
1373	int i, ret, idx;
1374
1375	if (!drm_dev_enter(&dbidev->drm, &idx))
1376		return -ENODEV;
1377
1378	buf = memdup_user_nul(ubuf, count);
1379	if (IS_ERR(buf)) {
1380		ret = PTR_ERR(buf);
1381		goto err_exit;
1382	}
1383
1384	/* strip trailing whitespace */
1385	for (i = count - 1; i > 0; i--)
1386		if (isspace(buf[i]))
1387			buf[i] = '\0';
1388		else
1389			break;
1390	i = 0;
1391	pos = buf;
1392	while (pos) {
1393		token = strsep(&pos, " ");
1394		if (!token) {
1395			ret = -EINVAL;
1396			goto err_free;
1397		}
1398
1399		ret = kstrtou8(token, 16, &val);
1400		if (ret < 0)
1401			goto err_free;
1402
1403		if (token == buf)
1404			cmd = val;
1405		else
1406			parameters[i++] = val;
1407
1408		if (i == 64) {
1409			ret = -E2BIG;
1410			goto err_free;
1411		}
1412	}
1413
1414	ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i);
1415
1416err_free:
1417	kfree(buf);
1418err_exit:
1419	drm_dev_exit(idx);
1420
1421	return ret < 0 ? ret : count;
1422}
1423
1424static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
1425{
1426	struct mipi_dbi_dev *dbidev = m->private;
1427	struct mipi_dbi *dbi = &dbidev->dbi;
1428	u8 cmd, val[4];
1429	int ret, idx;
1430	size_t len;
1431
1432	if (!drm_dev_enter(&dbidev->drm, &idx))
1433		return -ENODEV;
1434
1435	for (cmd = 0; cmd < 255; cmd++) {
1436		if (!mipi_dbi_command_is_read(dbi, cmd))
1437			continue;
1438
1439		switch (cmd) {
1440		case MIPI_DCS_READ_MEMORY_START:
1441		case MIPI_DCS_READ_MEMORY_CONTINUE:
1442			len = 2;
1443			break;
1444		case MIPI_DCS_GET_DISPLAY_ID:
1445			len = 3;
1446			break;
1447		case MIPI_DCS_GET_DISPLAY_STATUS:
1448			len = 4;
1449			break;
1450		default:
1451			len = 1;
1452			break;
1453		}
1454
1455		seq_printf(m, "%02x: ", cmd);
1456		ret = mipi_dbi_command_buf(dbi, cmd, val, len);
1457		if (ret) {
1458			seq_puts(m, "XX\n");
1459			continue;
1460		}
1461		seq_printf(m, "%*phN\n", (int)len, val);
1462	}
1463
1464	drm_dev_exit(idx);
1465
1466	return 0;
1467}
1468
1469static int mipi_dbi_debugfs_command_open(struct inode *inode,
1470					 struct file *file)
1471{
1472	return single_open(file, mipi_dbi_debugfs_command_show,
1473			   inode->i_private);
1474}
1475
1476static const struct file_operations mipi_dbi_debugfs_command_fops = {
1477	.owner = THIS_MODULE,
1478	.open = mipi_dbi_debugfs_command_open,
1479	.read = seq_read,
1480	.llseek = seq_lseek,
1481	.release = single_release,
1482	.write = mipi_dbi_debugfs_command_write,
1483};
1484
1485/**
1486 * mipi_dbi_debugfs_init - Create debugfs entries
1487 * @minor: DRM minor
1488 *
1489 * This function creates a 'command' debugfs file for sending commands to the
1490 * controller or getting the read command values.
1491 * Drivers can use this as their &drm_driver->debugfs_init callback.
1492 *
1493 */
1494void mipi_dbi_debugfs_init(struct drm_minor *minor)
1495{
1496	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev);
1497	umode_t mode = S_IFREG | S_IWUSR;
1498
1499	if (dbidev->dbi.read_commands)
1500		mode |= S_IRUGO;
1501	debugfs_create_file("command", mode, minor->debugfs_root, dbidev,
1502			    &mipi_dbi_debugfs_command_fops);
1503}
1504EXPORT_SYMBOL(mipi_dbi_debugfs_init);
1505
1506#endif
1507
1508MODULE_DESCRIPTION("MIPI Display Bus Interface (DBI) LCD controller support");
1509MODULE_LICENSE("GPL");