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1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#include "dm_services.h"
28#include "dc.h"
29
30#include "dcn30_init.h"
31
32#include "resource.h"
33#include "include/irq_service_interface.h"
34#include "dcn20/dcn20_resource.h"
35
36#include "dcn30_resource.h"
37
38#include "dcn10/dcn10_ipp.h"
39#include "dcn30/dcn30_hubbub.h"
40#include "dcn30/dcn30_mpc.h"
41#include "dcn30/dcn30_hubp.h"
42#include "irq/dcn30/irq_service_dcn30.h"
43#include "dcn30/dcn30_dpp.h"
44#include "dcn30/dcn30_optc.h"
45#include "dcn20/dcn20_hwseq.h"
46#include "dcn30/dcn30_hwseq.h"
47#include "dce110/dce110_hw_sequencer.h"
48#include "dcn30/dcn30_opp.h"
49#include "dcn20/dcn20_dsc.h"
50#include "dcn30/dcn30_vpg.h"
51#include "dcn30/dcn30_afmt.h"
52#include "dcn30/dcn30_dio_stream_encoder.h"
53#include "dcn30/dcn30_dio_link_encoder.h"
54#include "dce/dce_clock_source.h"
55#include "dce/dce_audio.h"
56#include "dce/dce_hwseq.h"
57#include "clk_mgr.h"
58#include "virtual/virtual_stream_encoder.h"
59#include "dce110/dce110_resource.h"
60#include "dml/display_mode_vba.h"
61#include "dcn30/dcn30_dccg.h"
62#include "dcn10/dcn10_resource.h"
63#include "dc_link_ddc.h"
64#include "dce/dce_panel_cntl.h"
65
66#include "dcn30/dcn30_dwb.h"
67#include "dcn30/dcn30_mmhubbub.h"
68
69#include "sienna_cichlid_ip_offset.h"
70#include "dcn/dcn_3_0_0_offset.h"
71#include "dcn/dcn_3_0_0_sh_mask.h"
72
73#include "nbio/nbio_7_4_offset.h"
74
75#include "dpcs/dpcs_3_0_0_offset.h"
76#include "dpcs/dpcs_3_0_0_sh_mask.h"
77
78#include "mmhub/mmhub_2_0_0_offset.h"
79#include "mmhub/mmhub_2_0_0_sh_mask.h"
80
81#include "reg_helper.h"
82#include "dce/dmub_abm.h"
83#include "dce/dmub_psr.h"
84#include "dce/dce_aux.h"
85#include "dce/dce_i2c.h"
86
87#include "dml/dcn30/dcn30_fpu.h"
88#include "dml/dcn30/display_mode_vba_30.h"
89#include "vm_helper.h"
90#include "dcn20/dcn20_vmid.h"
91#include "amdgpu_socbb.h"
92#include "dc_dmub_srv.h"
93
94#define DC_LOGGER_INIT(logger)
95
96enum dcn30_clk_src_array_id {
97 DCN30_CLK_SRC_PLL0,
98 DCN30_CLK_SRC_PLL1,
99 DCN30_CLK_SRC_PLL2,
100 DCN30_CLK_SRC_PLL3,
101 DCN30_CLK_SRC_PLL4,
102 DCN30_CLK_SRC_PLL5,
103 DCN30_CLK_SRC_TOTAL
104};
105
106/* begin *********************
107 * macros to expend register list macro defined in HW object header file
108 */
109
110/* DCN */
111#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
112
113#define BASE(seg) BASE_INNER(seg)
114
115#define SR(reg_name)\
116 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
117 mm ## reg_name
118
119#define SRI(reg_name, block, id)\
120 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
121 mm ## block ## id ## _ ## reg_name
122
123#define SRI2(reg_name, block, id)\
124 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
125 mm ## reg_name
126
127#define SRIR(var_name, reg_name, block, id)\
128 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
129 mm ## block ## id ## _ ## reg_name
130
131#define SRII(reg_name, block, id)\
132 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
133 mm ## block ## id ## _ ## reg_name
134
135#define SRII_MPC_RMU(reg_name, block, id)\
136 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 mm ## block ## id ## _ ## reg_name
138
139#define SRII_DWB(reg_name, temp_name, block, id)\
140 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
141 mm ## block ## id ## _ ## temp_name
142
143#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
144 .field_name = reg_name ## __ ## field_name ## post_fix
145
146#define DCCG_SRII(reg_name, block, id)\
147 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
148 mm ## block ## id ## _ ## reg_name
149
150#define VUPDATE_SRII(reg_name, block, id)\
151 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
152 mm ## reg_name ## _ ## block ## id
153
154/* NBIO */
155#define NBIO_BASE_INNER(seg) \
156 NBIO_BASE__INST0_SEG ## seg
157
158#define NBIO_BASE(seg) \
159 NBIO_BASE_INNER(seg)
160
161#define NBIO_SR(reg_name)\
162 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
163 mm ## reg_name
164
165/* MMHUB */
166#define MMHUB_BASE_INNER(seg) \
167 MMHUB_BASE__INST0_SEG ## seg
168
169#define MMHUB_BASE(seg) \
170 MMHUB_BASE_INNER(seg)
171
172#define MMHUB_SR(reg_name)\
173 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
174 mmMM ## reg_name
175
176/* CLOCK */
177#define CLK_BASE_INNER(seg) \
178 CLK_BASE__INST0_SEG ## seg
179
180#define CLK_BASE(seg) \
181 CLK_BASE_INNER(seg)
182
183#define CLK_SRI(reg_name, block, inst)\
184 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
185 mm ## block ## _ ## inst ## _ ## reg_name
186
187
188static const struct bios_registers bios_regs = {
189 NBIO_SR(BIOS_SCRATCH_3),
190 NBIO_SR(BIOS_SCRATCH_6)
191};
192
193#define clk_src_regs(index, pllid)\
194[index] = {\
195 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
196}
197
198static const struct dce110_clk_src_regs clk_src_regs[] = {
199 clk_src_regs(0, A),
200 clk_src_regs(1, B),
201 clk_src_regs(2, C),
202 clk_src_regs(3, D),
203 clk_src_regs(4, E),
204 clk_src_regs(5, F)
205};
206
207static const struct dce110_clk_src_shift cs_shift = {
208 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
209};
210
211static const struct dce110_clk_src_mask cs_mask = {
212 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
213};
214
215#define abm_regs(id)\
216[id] = {\
217 ABM_DCN30_REG_LIST(id)\
218}
219
220static const struct dce_abm_registers abm_regs[] = {
221 abm_regs(0),
222 abm_regs(1),
223 abm_regs(2),
224 abm_regs(3),
225 abm_regs(4),
226 abm_regs(5),
227};
228
229static const struct dce_abm_shift abm_shift = {
230 ABM_MASK_SH_LIST_DCN30(__SHIFT)
231};
232
233static const struct dce_abm_mask abm_mask = {
234 ABM_MASK_SH_LIST_DCN30(_MASK)
235};
236
237
238
239#define audio_regs(id)\
240[id] = {\
241 AUD_COMMON_REG_LIST(id)\
242}
243
244static const struct dce_audio_registers audio_regs[] = {
245 audio_regs(0),
246 audio_regs(1),
247 audio_regs(2),
248 audio_regs(3),
249 audio_regs(4),
250 audio_regs(5),
251 audio_regs(6)
252};
253
254#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
255 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
256 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
257 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
258
259static const struct dce_audio_shift audio_shift = {
260 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
261};
262
263static const struct dce_audio_mask audio_mask = {
264 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
265};
266
267#define vpg_regs(id)\
268[id] = {\
269 VPG_DCN3_REG_LIST(id)\
270}
271
272static const struct dcn30_vpg_registers vpg_regs[] = {
273 vpg_regs(0),
274 vpg_regs(1),
275 vpg_regs(2),
276 vpg_regs(3),
277 vpg_regs(4),
278 vpg_regs(5),
279 vpg_regs(6),
280};
281
282static const struct dcn30_vpg_shift vpg_shift = {
283 DCN3_VPG_MASK_SH_LIST(__SHIFT)
284};
285
286static const struct dcn30_vpg_mask vpg_mask = {
287 DCN3_VPG_MASK_SH_LIST(_MASK)
288};
289
290#define afmt_regs(id)\
291[id] = {\
292 AFMT_DCN3_REG_LIST(id)\
293}
294
295static const struct dcn30_afmt_registers afmt_regs[] = {
296 afmt_regs(0),
297 afmt_regs(1),
298 afmt_regs(2),
299 afmt_regs(3),
300 afmt_regs(4),
301 afmt_regs(5),
302 afmt_regs(6),
303};
304
305static const struct dcn30_afmt_shift afmt_shift = {
306 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
307};
308
309static const struct dcn30_afmt_mask afmt_mask = {
310 DCN3_AFMT_MASK_SH_LIST(_MASK)
311};
312
313#define stream_enc_regs(id)\
314[id] = {\
315 SE_DCN3_REG_LIST(id)\
316}
317
318static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
319 stream_enc_regs(0),
320 stream_enc_regs(1),
321 stream_enc_regs(2),
322 stream_enc_regs(3),
323 stream_enc_regs(4),
324 stream_enc_regs(5)
325};
326
327static const struct dcn10_stream_encoder_shift se_shift = {
328 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
329};
330
331static const struct dcn10_stream_encoder_mask se_mask = {
332 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
333};
334
335
336#define aux_regs(id)\
337[id] = {\
338 DCN2_AUX_REG_LIST(id)\
339}
340
341static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
342 aux_regs(0),
343 aux_regs(1),
344 aux_regs(2),
345 aux_regs(3),
346 aux_regs(4),
347 aux_regs(5)
348};
349
350#define hpd_regs(id)\
351[id] = {\
352 HPD_REG_LIST(id)\
353}
354
355static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
356 hpd_regs(0),
357 hpd_regs(1),
358 hpd_regs(2),
359 hpd_regs(3),
360 hpd_regs(4),
361 hpd_regs(5)
362};
363
364#define link_regs(id, phyid)\
365[id] = {\
366 LE_DCN3_REG_LIST(id), \
367 UNIPHY_DCN2_REG_LIST(phyid), \
368 DPCS_DCN2_REG_LIST(id), \
369 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
370}
371
372static const struct dce110_aux_registers_shift aux_shift = {
373 DCN_AUX_MASK_SH_LIST(__SHIFT)
374};
375
376static const struct dce110_aux_registers_mask aux_mask = {
377 DCN_AUX_MASK_SH_LIST(_MASK)
378};
379
380static const struct dcn10_link_enc_registers link_enc_regs[] = {
381 link_regs(0, A),
382 link_regs(1, B),
383 link_regs(2, C),
384 link_regs(3, D),
385 link_regs(4, E),
386 link_regs(5, F)
387};
388
389static const struct dcn10_link_enc_shift le_shift = {
390 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\
391 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
392};
393
394static const struct dcn10_link_enc_mask le_mask = {
395 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\
396 DPCS_DCN2_MASK_SH_LIST(_MASK)
397};
398
399
400static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
401 { DCN_PANEL_CNTL_REG_LIST() }
402};
403
404static const struct dce_panel_cntl_shift panel_cntl_shift = {
405 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
406};
407
408static const struct dce_panel_cntl_mask panel_cntl_mask = {
409 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
410};
411
412#define dpp_regs(id)\
413[id] = {\
414 DPP_REG_LIST_DCN30(id),\
415}
416
417static const struct dcn3_dpp_registers dpp_regs[] = {
418 dpp_regs(0),
419 dpp_regs(1),
420 dpp_regs(2),
421 dpp_regs(3),
422 dpp_regs(4),
423 dpp_regs(5),
424};
425
426static const struct dcn3_dpp_shift tf_shift = {
427 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
428};
429
430static const struct dcn3_dpp_mask tf_mask = {
431 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
432};
433
434#define opp_regs(id)\
435[id] = {\
436 OPP_REG_LIST_DCN30(id),\
437}
438
439static const struct dcn20_opp_registers opp_regs[] = {
440 opp_regs(0),
441 opp_regs(1),
442 opp_regs(2),
443 opp_regs(3),
444 opp_regs(4),
445 opp_regs(5)
446};
447
448static const struct dcn20_opp_shift opp_shift = {
449 OPP_MASK_SH_LIST_DCN20(__SHIFT)
450};
451
452static const struct dcn20_opp_mask opp_mask = {
453 OPP_MASK_SH_LIST_DCN20(_MASK)
454};
455
456#define aux_engine_regs(id)\
457[id] = {\
458 AUX_COMMON_REG_LIST0(id), \
459 .AUXN_IMPCAL = 0, \
460 .AUXP_IMPCAL = 0, \
461 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
462}
463
464static const struct dce110_aux_registers aux_engine_regs[] = {
465 aux_engine_regs(0),
466 aux_engine_regs(1),
467 aux_engine_regs(2),
468 aux_engine_regs(3),
469 aux_engine_regs(4),
470 aux_engine_regs(5)
471};
472
473#define dwbc_regs_dcn3(id)\
474[id] = {\
475 DWBC_COMMON_REG_LIST_DCN30(id),\
476}
477
478static const struct dcn30_dwbc_registers dwbc30_regs[] = {
479 dwbc_regs_dcn3(0),
480};
481
482static const struct dcn30_dwbc_shift dwbc30_shift = {
483 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
484};
485
486static const struct dcn30_dwbc_mask dwbc30_mask = {
487 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
488};
489
490#define mcif_wb_regs_dcn3(id)\
491[id] = {\
492 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
493}
494
495static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
496 mcif_wb_regs_dcn3(0)
497};
498
499static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
500 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
501};
502
503static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
504 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
505};
506
507#define dsc_regsDCN20(id)\
508[id] = {\
509 DSC_REG_LIST_DCN20(id)\
510}
511
512static const struct dcn20_dsc_registers dsc_regs[] = {
513 dsc_regsDCN20(0),
514 dsc_regsDCN20(1),
515 dsc_regsDCN20(2),
516 dsc_regsDCN20(3),
517 dsc_regsDCN20(4),
518 dsc_regsDCN20(5)
519};
520
521static const struct dcn20_dsc_shift dsc_shift = {
522 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
523};
524
525static const struct dcn20_dsc_mask dsc_mask = {
526 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
527};
528
529static const struct dcn30_mpc_registers mpc_regs = {
530 MPC_REG_LIST_DCN3_0(0),
531 MPC_REG_LIST_DCN3_0(1),
532 MPC_REG_LIST_DCN3_0(2),
533 MPC_REG_LIST_DCN3_0(3),
534 MPC_REG_LIST_DCN3_0(4),
535 MPC_REG_LIST_DCN3_0(5),
536 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
537 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
538 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
539 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
540 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
541 MPC_OUT_MUX_REG_LIST_DCN3_0(5),
542 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
543 MPC_RMU_REG_LIST_DCN3AG(0),
544 MPC_RMU_REG_LIST_DCN3AG(1),
545 MPC_RMU_REG_LIST_DCN3AG(2),
546 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
547};
548
549static const struct dcn30_mpc_shift mpc_shift = {
550 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
551};
552
553static const struct dcn30_mpc_mask mpc_mask = {
554 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
555};
556
557#define optc_regs(id)\
558[id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
559
560
561static const struct dcn_optc_registers optc_regs[] = {
562 optc_regs(0),
563 optc_regs(1),
564 optc_regs(2),
565 optc_regs(3),
566 optc_regs(4),
567 optc_regs(5)
568};
569
570static const struct dcn_optc_shift optc_shift = {
571 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
572};
573
574static const struct dcn_optc_mask optc_mask = {
575 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
576};
577
578#define hubp_regs(id)\
579[id] = {\
580 HUBP_REG_LIST_DCN30(id)\
581}
582
583static const struct dcn_hubp2_registers hubp_regs[] = {
584 hubp_regs(0),
585 hubp_regs(1),
586 hubp_regs(2),
587 hubp_regs(3),
588 hubp_regs(4),
589 hubp_regs(5)
590};
591
592static const struct dcn_hubp2_shift hubp_shift = {
593 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
594};
595
596static const struct dcn_hubp2_mask hubp_mask = {
597 HUBP_MASK_SH_LIST_DCN30(_MASK)
598};
599
600static const struct dcn_hubbub_registers hubbub_reg = {
601 HUBBUB_REG_LIST_DCN30(0)
602};
603
604static const struct dcn_hubbub_shift hubbub_shift = {
605 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
606};
607
608static const struct dcn_hubbub_mask hubbub_mask = {
609 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
610};
611
612static const struct dccg_registers dccg_regs = {
613 DCCG_REG_LIST_DCN30()
614};
615
616static const struct dccg_shift dccg_shift = {
617 DCCG_MASK_SH_LIST_DCN3(__SHIFT)
618};
619
620static const struct dccg_mask dccg_mask = {
621 DCCG_MASK_SH_LIST_DCN3(_MASK)
622};
623
624static const struct dce_hwseq_registers hwseq_reg = {
625 HWSEQ_DCN30_REG_LIST()
626};
627
628static const struct dce_hwseq_shift hwseq_shift = {
629 HWSEQ_DCN30_MASK_SH_LIST(__SHIFT)
630};
631
632static const struct dce_hwseq_mask hwseq_mask = {
633 HWSEQ_DCN30_MASK_SH_LIST(_MASK)
634};
635#define vmid_regs(id)\
636[id] = {\
637 DCN20_VMID_REG_LIST(id)\
638}
639
640static const struct dcn_vmid_registers vmid_regs[] = {
641 vmid_regs(0),
642 vmid_regs(1),
643 vmid_regs(2),
644 vmid_regs(3),
645 vmid_regs(4),
646 vmid_regs(5),
647 vmid_regs(6),
648 vmid_regs(7),
649 vmid_regs(8),
650 vmid_regs(9),
651 vmid_regs(10),
652 vmid_regs(11),
653 vmid_regs(12),
654 vmid_regs(13),
655 vmid_regs(14),
656 vmid_regs(15)
657};
658
659static const struct dcn20_vmid_shift vmid_shifts = {
660 DCN20_VMID_MASK_SH_LIST(__SHIFT)
661};
662
663static const struct dcn20_vmid_mask vmid_masks = {
664 DCN20_VMID_MASK_SH_LIST(_MASK)
665};
666
667static const struct resource_caps res_cap_dcn3 = {
668 .num_timing_generator = 6,
669 .num_opp = 6,
670 .num_video_plane = 6,
671 .num_audio = 6,
672 .num_stream_encoder = 6,
673 .num_pll = 6,
674 .num_dwb = 1,
675 .num_ddc = 6,
676 .num_vmid = 16,
677 .num_mpc_3dlut = 3,
678 .num_dsc = 6,
679};
680
681static const struct dc_plane_cap plane_cap = {
682 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
683 .blends_with_above = true,
684 .blends_with_below = true,
685 .per_pixel_alpha = true,
686
687 .pixel_format_support = {
688 .argb8888 = true,
689 .nv12 = true,
690 .fp16 = true,
691 .p010 = true,
692 .ayuv = false,
693 },
694
695 .max_upscale_factor = {
696 .argb8888 = 16000,
697 .nv12 = 16000,
698 .fp16 = 16000
699 },
700
701 /* 6:1 downscaling ratio: 1000/6 = 166.666 */
702 .max_downscale_factor = {
703 .argb8888 = 167,
704 .nv12 = 167,
705 .fp16 = 167
706 }
707};
708
709static const struct dc_debug_options debug_defaults_drv = {
710 .disable_dmcu = true, //No DMCU on DCN30
711 .force_abm_enable = false,
712 .timing_trace = false,
713 .clock_trace = true,
714 .disable_pplib_clock_request = true,
715 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
716 .force_single_disp_pipe_split = false,
717 .disable_dcc = DCC_ENABLE,
718 .vsr_support = true,
719 .performance_trace = false,
720 .max_downscale_src_width = 7680,/*upto 8K*/
721 .disable_pplib_wm_range = false,
722 .scl_reset_length10 = true,
723 .sanity_checks = false,
724 .underflow_assert_delay_us = 0xFFFFFFFF,
725 .dwb_fi_phase = -1, // -1 = disable,
726 .dmub_command_table = true,
727 .use_max_lb = true,
728 .exit_idle_opt_for_cursor_updates = true
729};
730
731static const struct dc_debug_options debug_defaults_diags = {
732 .disable_dmcu = true, //No dmcu on DCN30
733 .force_abm_enable = false,
734 .timing_trace = true,
735 .clock_trace = true,
736 .disable_dpp_power_gate = true,
737 .disable_hubp_power_gate = true,
738 .disable_clock_gate = true,
739 .disable_pplib_clock_request = true,
740 .disable_pplib_wm_range = true,
741 .disable_stutter = false,
742 .scl_reset_length10 = true,
743 .dwb_fi_phase = -1, // -1 = disable
744 .dmub_command_table = true,
745 .enable_tri_buf = true,
746 .use_max_lb = true
747};
748
749static const struct dc_panel_config panel_config_defaults = {
750 .psr = {
751 .disable_psr = false,
752 .disallow_psrsu = false,
753 },
754};
755
756static void dcn30_dpp_destroy(struct dpp **dpp)
757{
758 kfree(TO_DCN20_DPP(*dpp));
759 *dpp = NULL;
760}
761
762static struct dpp *dcn30_dpp_create(
763 struct dc_context *ctx,
764 uint32_t inst)
765{
766 struct dcn3_dpp *dpp =
767 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
768
769 if (!dpp)
770 return NULL;
771
772 if (dpp3_construct(dpp, ctx, inst,
773 &dpp_regs[inst], &tf_shift, &tf_mask))
774 return &dpp->base;
775
776 BREAK_TO_DEBUGGER();
777 kfree(dpp);
778 return NULL;
779}
780
781static struct output_pixel_processor *dcn30_opp_create(
782 struct dc_context *ctx, uint32_t inst)
783{
784 struct dcn20_opp *opp =
785 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
786
787 if (!opp) {
788 BREAK_TO_DEBUGGER();
789 return NULL;
790 }
791
792 dcn20_opp_construct(opp, ctx, inst,
793 &opp_regs[inst], &opp_shift, &opp_mask);
794 return &opp->base;
795}
796
797static struct dce_aux *dcn30_aux_engine_create(
798 struct dc_context *ctx,
799 uint32_t inst)
800{
801 struct aux_engine_dce110 *aux_engine =
802 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
803
804 if (!aux_engine)
805 return NULL;
806
807 dce110_aux_engine_construct(aux_engine, ctx, inst,
808 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
809 &aux_engine_regs[inst],
810 &aux_mask,
811 &aux_shift,
812 ctx->dc->caps.extended_aux_timeout_support);
813
814 return &aux_engine->base;
815}
816
817#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
818
819static const struct dce_i2c_registers i2c_hw_regs[] = {
820 i2c_inst_regs(1),
821 i2c_inst_regs(2),
822 i2c_inst_regs(3),
823 i2c_inst_regs(4),
824 i2c_inst_regs(5),
825 i2c_inst_regs(6),
826};
827
828static const struct dce_i2c_shift i2c_shifts = {
829 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
830};
831
832static const struct dce_i2c_mask i2c_masks = {
833 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
834};
835
836static struct dce_i2c_hw *dcn30_i2c_hw_create(
837 struct dc_context *ctx,
838 uint32_t inst)
839{
840 struct dce_i2c_hw *dce_i2c_hw =
841 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
842
843 if (!dce_i2c_hw)
844 return NULL;
845
846 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
847 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
848
849 return dce_i2c_hw;
850}
851
852static struct mpc *dcn30_mpc_create(
853 struct dc_context *ctx,
854 int num_mpcc,
855 int num_rmu)
856{
857 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
858 GFP_KERNEL);
859
860 if (!mpc30)
861 return NULL;
862
863 dcn30_mpc_construct(mpc30, ctx,
864 &mpc_regs,
865 &mpc_shift,
866 &mpc_mask,
867 num_mpcc,
868 num_rmu);
869
870 return &mpc30->base;
871}
872
873static struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
874{
875 int i;
876
877 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
878 GFP_KERNEL);
879
880 if (!hubbub3)
881 return NULL;
882
883 hubbub3_construct(hubbub3, ctx,
884 &hubbub_reg,
885 &hubbub_shift,
886 &hubbub_mask);
887
888
889 for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
890 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
891
892 vmid->ctx = ctx;
893
894 vmid->regs = &vmid_regs[i];
895 vmid->shifts = &vmid_shifts;
896 vmid->masks = &vmid_masks;
897 }
898
899 return &hubbub3->base;
900}
901
902static struct timing_generator *dcn30_timing_generator_create(
903 struct dc_context *ctx,
904 uint32_t instance)
905{
906 struct optc *tgn10 =
907 kzalloc(sizeof(struct optc), GFP_KERNEL);
908
909 if (!tgn10)
910 return NULL;
911
912 tgn10->base.inst = instance;
913 tgn10->base.ctx = ctx;
914
915 tgn10->tg_regs = &optc_regs[instance];
916 tgn10->tg_shift = &optc_shift;
917 tgn10->tg_mask = &optc_mask;
918
919 dcn30_timing_generator_init(tgn10);
920
921 return &tgn10->base;
922}
923
924static const struct encoder_feature_support link_enc_feature = {
925 .max_hdmi_deep_color = COLOR_DEPTH_121212,
926 .max_hdmi_pixel_clock = 600000,
927 .hdmi_ycbcr420_supported = true,
928 .dp_ycbcr420_supported = true,
929 .fec_supported = true,
930 .flags.bits.IS_HBR2_CAPABLE = true,
931 .flags.bits.IS_HBR3_CAPABLE = true,
932 .flags.bits.IS_TPS3_CAPABLE = true,
933 .flags.bits.IS_TPS4_CAPABLE = true
934};
935
936static struct link_encoder *dcn30_link_encoder_create(
937 struct dc_context *ctx,
938 const struct encoder_init_data *enc_init_data)
939{
940 struct dcn20_link_encoder *enc20 =
941 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
942
943 if (!enc20)
944 return NULL;
945
946 dcn30_link_encoder_construct(enc20,
947 enc_init_data,
948 &link_enc_feature,
949 &link_enc_regs[enc_init_data->transmitter],
950 &link_enc_aux_regs[enc_init_data->channel - 1],
951 &link_enc_hpd_regs[enc_init_data->hpd_source],
952 &le_shift,
953 &le_mask);
954
955 return &enc20->enc10.base;
956}
957
958static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
959{
960 struct dce_panel_cntl *panel_cntl =
961 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
962
963 if (!panel_cntl)
964 return NULL;
965
966 dce_panel_cntl_construct(panel_cntl,
967 init_data,
968 &panel_cntl_regs[init_data->inst],
969 &panel_cntl_shift,
970 &panel_cntl_mask);
971
972 return &panel_cntl->base;
973}
974
975static void read_dce_straps(
976 struct dc_context *ctx,
977 struct resource_straps *straps)
978{
979 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
980 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
981
982}
983
984static struct audio *dcn30_create_audio(
985 struct dc_context *ctx, unsigned int inst)
986{
987 return dce_audio_create(ctx, inst,
988 &audio_regs[inst], &audio_shift, &audio_mask);
989}
990
991static struct vpg *dcn30_vpg_create(
992 struct dc_context *ctx,
993 uint32_t inst)
994{
995 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
996
997 if (!vpg3)
998 return NULL;
999
1000 vpg3_construct(vpg3, ctx, inst,
1001 &vpg_regs[inst],
1002 &vpg_shift,
1003 &vpg_mask);
1004
1005 return &vpg3->base;
1006}
1007
1008static struct afmt *dcn30_afmt_create(
1009 struct dc_context *ctx,
1010 uint32_t inst)
1011{
1012 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1013
1014 if (!afmt3)
1015 return NULL;
1016
1017 afmt3_construct(afmt3, ctx, inst,
1018 &afmt_regs[inst],
1019 &afmt_shift,
1020 &afmt_mask);
1021
1022 return &afmt3->base;
1023}
1024
1025static struct stream_encoder *dcn30_stream_encoder_create(enum engine_id eng_id,
1026 struct dc_context *ctx)
1027{
1028 struct dcn10_stream_encoder *enc1;
1029 struct vpg *vpg;
1030 struct afmt *afmt;
1031 int vpg_inst;
1032 int afmt_inst;
1033
1034 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1035 if (eng_id <= ENGINE_ID_DIGF) {
1036 vpg_inst = eng_id;
1037 afmt_inst = eng_id;
1038 } else
1039 return NULL;
1040
1041 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1042 vpg = dcn30_vpg_create(ctx, vpg_inst);
1043 afmt = dcn30_afmt_create(ctx, afmt_inst);
1044
1045 if (!enc1 || !vpg || !afmt) {
1046 kfree(enc1);
1047 kfree(vpg);
1048 kfree(afmt);
1049 return NULL;
1050 }
1051
1052 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1053 eng_id, vpg, afmt,
1054 &stream_enc_regs[eng_id],
1055 &se_shift, &se_mask);
1056
1057 return &enc1->base;
1058}
1059
1060static struct dce_hwseq *dcn30_hwseq_create(struct dc_context *ctx)
1061{
1062 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1063
1064 if (hws) {
1065 hws->ctx = ctx;
1066 hws->regs = &hwseq_reg;
1067 hws->shifts = &hwseq_shift;
1068 hws->masks = &hwseq_mask;
1069 }
1070 return hws;
1071}
1072static const struct resource_create_funcs res_create_funcs = {
1073 .read_dce_straps = read_dce_straps,
1074 .create_audio = dcn30_create_audio,
1075 .create_stream_encoder = dcn30_stream_encoder_create,
1076 .create_hwseq = dcn30_hwseq_create,
1077};
1078
1079static const struct resource_create_funcs res_create_maximus_funcs = {
1080 .read_dce_straps = NULL,
1081 .create_audio = NULL,
1082 .create_stream_encoder = NULL,
1083 .create_hwseq = dcn30_hwseq_create,
1084};
1085
1086static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1087{
1088 unsigned int i;
1089
1090 for (i = 0; i < pool->base.stream_enc_count; i++) {
1091 if (pool->base.stream_enc[i] != NULL) {
1092 if (pool->base.stream_enc[i]->vpg != NULL) {
1093 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1094 pool->base.stream_enc[i]->vpg = NULL;
1095 }
1096 if (pool->base.stream_enc[i]->afmt != NULL) {
1097 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1098 pool->base.stream_enc[i]->afmt = NULL;
1099 }
1100 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1101 pool->base.stream_enc[i] = NULL;
1102 }
1103 }
1104
1105 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1106 if (pool->base.dscs[i] != NULL)
1107 dcn20_dsc_destroy(&pool->base.dscs[i]);
1108 }
1109
1110 if (pool->base.mpc != NULL) {
1111 kfree(TO_DCN20_MPC(pool->base.mpc));
1112 pool->base.mpc = NULL;
1113 }
1114 if (pool->base.hubbub != NULL) {
1115 kfree(pool->base.hubbub);
1116 pool->base.hubbub = NULL;
1117 }
1118 for (i = 0; i < pool->base.pipe_count; i++) {
1119 if (pool->base.dpps[i] != NULL)
1120 dcn30_dpp_destroy(&pool->base.dpps[i]);
1121
1122 if (pool->base.ipps[i] != NULL)
1123 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1124
1125 if (pool->base.hubps[i] != NULL) {
1126 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1127 pool->base.hubps[i] = NULL;
1128 }
1129
1130 if (pool->base.irqs != NULL) {
1131 dal_irq_service_destroy(&pool->base.irqs);
1132 }
1133 }
1134
1135 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1136 if (pool->base.engines[i] != NULL)
1137 dce110_engine_destroy(&pool->base.engines[i]);
1138 if (pool->base.hw_i2cs[i] != NULL) {
1139 kfree(pool->base.hw_i2cs[i]);
1140 pool->base.hw_i2cs[i] = NULL;
1141 }
1142 if (pool->base.sw_i2cs[i] != NULL) {
1143 kfree(pool->base.sw_i2cs[i]);
1144 pool->base.sw_i2cs[i] = NULL;
1145 }
1146 }
1147
1148 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1149 if (pool->base.opps[i] != NULL)
1150 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1151 }
1152
1153 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1154 if (pool->base.timing_generators[i] != NULL) {
1155 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1156 pool->base.timing_generators[i] = NULL;
1157 }
1158 }
1159
1160 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1161 if (pool->base.dwbc[i] != NULL) {
1162 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1163 pool->base.dwbc[i] = NULL;
1164 }
1165 if (pool->base.mcif_wb[i] != NULL) {
1166 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1167 pool->base.mcif_wb[i] = NULL;
1168 }
1169 }
1170
1171 for (i = 0; i < pool->base.audio_count; i++) {
1172 if (pool->base.audios[i])
1173 dce_aud_destroy(&pool->base.audios[i]);
1174 }
1175
1176 for (i = 0; i < pool->base.clk_src_count; i++) {
1177 if (pool->base.clock_sources[i] != NULL) {
1178 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1179 pool->base.clock_sources[i] = NULL;
1180 }
1181 }
1182
1183 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1184 if (pool->base.mpc_lut[i] != NULL) {
1185 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1186 pool->base.mpc_lut[i] = NULL;
1187 }
1188 if (pool->base.mpc_shaper[i] != NULL) {
1189 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1190 pool->base.mpc_shaper[i] = NULL;
1191 }
1192 }
1193
1194 if (pool->base.dp_clock_source != NULL) {
1195 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1196 pool->base.dp_clock_source = NULL;
1197 }
1198
1199 for (i = 0; i < pool->base.pipe_count; i++) {
1200 if (pool->base.multiple_abms[i] != NULL)
1201 dce_abm_destroy(&pool->base.multiple_abms[i]);
1202 }
1203
1204 if (pool->base.psr != NULL)
1205 dmub_psr_destroy(&pool->base.psr);
1206
1207 if (pool->base.dccg != NULL)
1208 dcn_dccg_destroy(&pool->base.dccg);
1209
1210 if (pool->base.oem_device != NULL)
1211 dal_ddc_service_destroy(&pool->base.oem_device);
1212}
1213
1214static struct hubp *dcn30_hubp_create(
1215 struct dc_context *ctx,
1216 uint32_t inst)
1217{
1218 struct dcn20_hubp *hubp2 =
1219 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1220
1221 if (!hubp2)
1222 return NULL;
1223
1224 if (hubp3_construct(hubp2, ctx, inst,
1225 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1226 return &hubp2->base;
1227
1228 BREAK_TO_DEBUGGER();
1229 kfree(hubp2);
1230 return NULL;
1231}
1232
1233static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1234{
1235 int i;
1236 uint32_t pipe_count = pool->res_cap->num_dwb;
1237
1238 for (i = 0; i < pipe_count; i++) {
1239 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1240 GFP_KERNEL);
1241
1242 if (!dwbc30) {
1243 dm_error("DC: failed to create dwbc30!\n");
1244 return false;
1245 }
1246
1247 dcn30_dwbc_construct(dwbc30, ctx,
1248 &dwbc30_regs[i],
1249 &dwbc30_shift,
1250 &dwbc30_mask,
1251 i);
1252
1253 pool->dwbc[i] = &dwbc30->base;
1254 }
1255 return true;
1256}
1257
1258static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1259{
1260 int i;
1261 uint32_t pipe_count = pool->res_cap->num_dwb;
1262
1263 for (i = 0; i < pipe_count; i++) {
1264 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1265 GFP_KERNEL);
1266
1267 if (!mcif_wb30) {
1268 dm_error("DC: failed to create mcif_wb30!\n");
1269 return false;
1270 }
1271
1272 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1273 &mcif_wb30_regs[i],
1274 &mcif_wb30_shift,
1275 &mcif_wb30_mask,
1276 i);
1277
1278 pool->mcif_wb[i] = &mcif_wb30->base;
1279 }
1280 return true;
1281}
1282
1283static struct display_stream_compressor *dcn30_dsc_create(
1284 struct dc_context *ctx, uint32_t inst)
1285{
1286 struct dcn20_dsc *dsc =
1287 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1288
1289 if (!dsc) {
1290 BREAK_TO_DEBUGGER();
1291 return NULL;
1292 }
1293
1294 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1295 return &dsc->base;
1296}
1297
1298enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1299{
1300
1301 return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1302}
1303
1304static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1305{
1306 struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);
1307
1308 dcn30_resource_destruct(dcn30_pool);
1309 kfree(dcn30_pool);
1310 *pool = NULL;
1311}
1312
1313static struct clock_source *dcn30_clock_source_create(
1314 struct dc_context *ctx,
1315 struct dc_bios *bios,
1316 enum clock_source_id id,
1317 const struct dce110_clk_src_regs *regs,
1318 bool dp_clk_src)
1319{
1320 struct dce110_clk_src *clk_src =
1321 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1322
1323 if (!clk_src)
1324 return NULL;
1325
1326 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1327 regs, &cs_shift, &cs_mask)) {
1328 clk_src->base.dp_clk_src = dp_clk_src;
1329 return &clk_src->base;
1330 }
1331
1332 kfree(clk_src);
1333 BREAK_TO_DEBUGGER();
1334 return NULL;
1335}
1336
1337int dcn30_populate_dml_pipes_from_context(
1338 struct dc *dc, struct dc_state *context,
1339 display_e2e_pipe_params_st *pipes,
1340 bool fast_validate)
1341{
1342 int i, pipe_cnt;
1343 struct resource_context *res_ctx = &context->res_ctx;
1344
1345 DC_FP_START();
1346 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1347 DC_FP_END();
1348
1349 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1350 if (!res_ctx->pipe_ctx[i].stream)
1351 continue;
1352
1353 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1354 dm_lb_16;
1355 }
1356
1357 return pipe_cnt;
1358}
1359
1360void dcn30_populate_dml_writeback_from_context(
1361 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1362{
1363 DC_FP_START();
1364 dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1365 DC_FP_END();
1366}
1367
1368unsigned int dcn30_calc_max_scaled_time(
1369 unsigned int time_per_pixel,
1370 enum mmhubbub_wbif_mode mode,
1371 unsigned int urgent_watermark)
1372{
1373 unsigned int time_per_byte = 0;
1374 unsigned int total_free_entry = 0xb40;
1375 unsigned int buf_lh_capability;
1376 unsigned int max_scaled_time;
1377
1378 if (mode == PACKED_444) /* packed mode 32 bpp */
1379 time_per_byte = time_per_pixel/4;
1380 else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
1381 time_per_byte = time_per_pixel/8;
1382
1383 if (time_per_byte == 0)
1384 time_per_byte = 1;
1385
1386 buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
1387 max_scaled_time = buf_lh_capability - urgent_watermark;
1388 return max_scaled_time;
1389}
1390
1391void dcn30_set_mcif_arb_params(
1392 struct dc *dc,
1393 struct dc_state *context,
1394 display_e2e_pipe_params_st *pipes,
1395 int pipe_cnt)
1396{
1397 enum mmhubbub_wbif_mode wbif_mode;
1398 struct display_mode_lib *dml = &context->bw_ctx.dml;
1399 struct mcif_arb_params *wb_arb_params;
1400 int i, j, dwb_pipe;
1401
1402 /* Writeback MCIF_WB arbitration parameters */
1403 dwb_pipe = 0;
1404 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1405
1406 if (!context->res_ctx.pipe_ctx[i].stream)
1407 continue;
1408
1409 for (j = 0; j < MAX_DWB_PIPES; j++) {
1410 struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1411
1412 if (writeback_info->wb_enabled == false)
1413 continue;
1414
1415 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1416 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1417
1418 if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1419 writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1420 wbif_mode = PACKED_444_FP16;
1421 else
1422 wbif_mode = PACKED_444;
1423
1424 DC_FP_START();
1425 dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j);
1426 DC_FP_END();
1427 wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
1428 wb_arb_params->slice_lines = 32;
1429 wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
1430 wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1431 wbif_mode,
1432 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1433
1434 dwb_pipe++;
1435
1436 if (dwb_pipe >= MAX_DWB_PIPES)
1437 return;
1438 }
1439 if (dwb_pipe >= MAX_DWB_PIPES)
1440 return;
1441 }
1442
1443}
1444
1445static struct dc_cap_funcs cap_funcs = {
1446 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1447};
1448
1449bool dcn30_acquire_post_bldn_3dlut(
1450 struct resource_context *res_ctx,
1451 const struct resource_pool *pool,
1452 int mpcc_id,
1453 struct dc_3dlut **lut,
1454 struct dc_transfer_func **shaper)
1455{
1456 int i;
1457 bool ret = false;
1458 union dc_3dlut_state *state;
1459
1460 ASSERT(*lut == NULL && *shaper == NULL);
1461 *lut = NULL;
1462 *shaper = NULL;
1463
1464 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1465 if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1466 *lut = pool->mpc_lut[i];
1467 *shaper = pool->mpc_shaper[i];
1468 state = &pool->mpc_lut[i]->state;
1469 res_ctx->is_mpc_3dlut_acquired[i] = true;
1470 state->bits.rmu_idx_valid = 1;
1471 state->bits.rmu_mux_num = i;
1472 if (state->bits.rmu_mux_num == 0)
1473 state->bits.mpc_rmu0_mux = mpcc_id;
1474 else if (state->bits.rmu_mux_num == 1)
1475 state->bits.mpc_rmu1_mux = mpcc_id;
1476 else if (state->bits.rmu_mux_num == 2)
1477 state->bits.mpc_rmu2_mux = mpcc_id;
1478 ret = true;
1479 break;
1480 }
1481 }
1482 return ret;
1483}
1484
1485bool dcn30_release_post_bldn_3dlut(
1486 struct resource_context *res_ctx,
1487 const struct resource_pool *pool,
1488 struct dc_3dlut **lut,
1489 struct dc_transfer_func **shaper)
1490{
1491 int i;
1492 bool ret = false;
1493
1494 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1495 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1496 res_ctx->is_mpc_3dlut_acquired[i] = false;
1497 pool->mpc_lut[i]->state.raw = 0;
1498 *lut = NULL;
1499 *shaper = NULL;
1500 ret = true;
1501 break;
1502 }
1503 }
1504 return ret;
1505}
1506
1507static bool is_soc_bounding_box_valid(struct dc *dc)
1508{
1509 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1510
1511 if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev))
1512 return true;
1513
1514 return false;
1515}
1516
1517static bool init_soc_bounding_box(struct dc *dc,
1518 struct dcn30_resource_pool *pool)
1519{
1520 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1521 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1522
1523 DC_LOGGER_INIT(dc->ctx->logger);
1524
1525 if (!is_soc_bounding_box_valid(dc)) {
1526 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1527 return false;
1528 }
1529
1530 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1531 loaded_ip->max_num_dpp = pool->base.pipe_count;
1532 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1533 dcn20_patch_bounding_box(dc, loaded_bb);
1534 DC_FP_START();
1535 patch_dcn30_soc_bounding_box(dc, &dcn3_0_soc);
1536 DC_FP_END();
1537
1538 return true;
1539}
1540
1541static bool dcn30_split_stream_for_mpc_or_odm(
1542 const struct dc *dc,
1543 struct resource_context *res_ctx,
1544 struct pipe_ctx *pri_pipe,
1545 struct pipe_ctx *sec_pipe,
1546 bool odm)
1547{
1548 int pipe_idx = sec_pipe->pipe_idx;
1549 const struct resource_pool *pool = dc->res_pool;
1550
1551 *sec_pipe = *pri_pipe;
1552
1553 sec_pipe->pipe_idx = pipe_idx;
1554 sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1555 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1556 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1557 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1558 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1559 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1560 sec_pipe->stream_res.dsc = NULL;
1561 if (odm) {
1562 if (pri_pipe->next_odm_pipe) {
1563 ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1564 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1565 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1566 }
1567 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1568 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1569 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1570 }
1571 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1572 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1573 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1574 }
1575 pri_pipe->next_odm_pipe = sec_pipe;
1576 sec_pipe->prev_odm_pipe = pri_pipe;
1577
1578 if (!sec_pipe->top_pipe)
1579 sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1580 else
1581 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1582 if (sec_pipe->stream->timing.flags.DSC == 1) {
1583 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1584 ASSERT(sec_pipe->stream_res.dsc);
1585 if (sec_pipe->stream_res.dsc == NULL)
1586 return false;
1587 }
1588 } else {
1589 if (pri_pipe->bottom_pipe) {
1590 ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1591 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1592 sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1593 }
1594 pri_pipe->bottom_pipe = sec_pipe;
1595 sec_pipe->top_pipe = pri_pipe;
1596
1597 ASSERT(pri_pipe->plane_state);
1598 }
1599
1600 return true;
1601}
1602
1603static struct pipe_ctx *dcn30_find_split_pipe(
1604 struct dc *dc,
1605 struct dc_state *context,
1606 int old_index)
1607{
1608 struct pipe_ctx *pipe = NULL;
1609 int i;
1610
1611 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1612 pipe = &context->res_ctx.pipe_ctx[old_index];
1613 pipe->pipe_idx = old_index;
1614 }
1615
1616 if (!pipe)
1617 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1618 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1619 && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1620 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1621 pipe = &context->res_ctx.pipe_ctx[i];
1622 pipe->pipe_idx = i;
1623 break;
1624 }
1625 }
1626 }
1627
1628 /*
1629 * May need to fix pipes getting tossed from 1 opp to another on flip
1630 * Add for debugging transient underflow during topology updates:
1631 * ASSERT(pipe);
1632 */
1633 if (!pipe)
1634 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1635 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1636 pipe = &context->res_ctx.pipe_ctx[i];
1637 pipe->pipe_idx = i;
1638 break;
1639 }
1640 }
1641
1642 return pipe;
1643}
1644
1645noinline bool dcn30_internal_validate_bw(
1646 struct dc *dc,
1647 struct dc_state *context,
1648 display_e2e_pipe_params_st *pipes,
1649 int *pipe_cnt_out,
1650 int *vlevel_out,
1651 bool fast_validate)
1652{
1653 bool out = false;
1654 bool repopulate_pipes = false;
1655 int split[MAX_PIPES] = { 0 };
1656 bool merge[MAX_PIPES] = { false };
1657 bool newly_split[MAX_PIPES] = { false };
1658 int pipe_cnt, i, pipe_idx, vlevel;
1659 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1660
1661 ASSERT(pipes);
1662 if (!pipes)
1663 return false;
1664
1665 context->bw_ctx.dml.vba.maxMpcComb = 0;
1666 context->bw_ctx.dml.vba.VoltageLevel = 0;
1667 context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
1668 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1669 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1670
1671 if (!pipe_cnt) {
1672 out = true;
1673 goto validate_out;
1674 }
1675
1676 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1677
1678 if (!fast_validate) {
1679 /*
1680 * DML favors voltage over p-state, but we're more interested in
1681 * supporting p-state over voltage. We can't support p-state in
1682 * prefetch mode > 0 so try capping the prefetch mode to start.
1683 */
1684 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1685 dm_allow_self_refresh_and_mclk_switch;
1686 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1687 /* This may adjust vlevel and maxMpcComb */
1688 if (vlevel < context->bw_ctx.dml.soc.num_states)
1689 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1690 }
1691 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1692 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
1693 /*
1694 * If mode is unsupported or there's still no p-state support then
1695 * fall back to favoring voltage.
1696 *
1697 * We don't actually support prefetch mode 2, so require that we
1698 * at least support prefetch mode 1.
1699 */
1700 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1701 dm_allow_self_refresh;
1702
1703 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1704 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1705 memset(split, 0, sizeof(split));
1706 memset(merge, 0, sizeof(merge));
1707 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1708 }
1709 }
1710
1711 dml_log_mode_support_params(&context->bw_ctx.dml);
1712
1713 if (vlevel == context->bw_ctx.dml.soc.num_states)
1714 goto validate_fail;
1715
1716 if (!dc->config.enable_windowed_mpo_odm) {
1717 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1718 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1719 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1720
1721 if (!pipe->stream)
1722 continue;
1723
1724 /* We only support full screen mpo with ODM */
1725 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1726 && pipe->plane_state && mpo_pipe
1727 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
1728 &pipe->plane_res.scl_data.recout,
1729 sizeof(struct rect)) != 0) {
1730 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1731 goto validate_fail;
1732 }
1733 pipe_idx++;
1734 }
1735 }
1736
1737 /* merge pipes if necessary */
1738 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1739 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1740
1741 /*skip pipes that don't need merging*/
1742 if (!merge[i])
1743 continue;
1744
1745 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1746 if (pipe->prev_odm_pipe) {
1747 /*split off odm pipe*/
1748 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1749 if (pipe->next_odm_pipe)
1750 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1751
1752 pipe->bottom_pipe = NULL;
1753 pipe->next_odm_pipe = NULL;
1754 pipe->plane_state = NULL;
1755 pipe->stream = NULL;
1756 pipe->top_pipe = NULL;
1757 pipe->prev_odm_pipe = NULL;
1758 if (pipe->stream_res.dsc)
1759 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1760 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1761 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1762 repopulate_pipes = true;
1763 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1764 struct pipe_ctx *top_pipe = pipe->top_pipe;
1765 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1766
1767 top_pipe->bottom_pipe = bottom_pipe;
1768 if (bottom_pipe)
1769 bottom_pipe->top_pipe = top_pipe;
1770
1771 pipe->top_pipe = NULL;
1772 pipe->bottom_pipe = NULL;
1773 pipe->plane_state = NULL;
1774 pipe->stream = NULL;
1775 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1776 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1777 repopulate_pipes = true;
1778 } else
1779 ASSERT(0); /* Should never try to merge master pipe */
1780
1781 }
1782
1783 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1784 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1785 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1786 struct pipe_ctx *hsplit_pipe = NULL;
1787 bool odm;
1788 int old_index = -1;
1789
1790 if (!pipe->stream || newly_split[i])
1791 continue;
1792
1793 pipe_idx++;
1794 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
1795
1796 if (!pipe->plane_state && !odm)
1797 continue;
1798
1799 if (split[i]) {
1800 if (odm) {
1801 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
1802 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1803 else if (old_pipe->next_odm_pipe)
1804 old_index = old_pipe->next_odm_pipe->pipe_idx;
1805 } else {
1806 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1807 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1808 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1809 else if (old_pipe->bottom_pipe &&
1810 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1811 old_index = old_pipe->bottom_pipe->pipe_idx;
1812 }
1813 hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
1814 ASSERT(hsplit_pipe);
1815 if (!hsplit_pipe)
1816 goto validate_fail;
1817
1818 if (!dcn30_split_stream_for_mpc_or_odm(
1819 dc, &context->res_ctx,
1820 pipe, hsplit_pipe, odm))
1821 goto validate_fail;
1822
1823 newly_split[hsplit_pipe->pipe_idx] = true;
1824 repopulate_pipes = true;
1825 }
1826 if (split[i] == 4) {
1827 struct pipe_ctx *pipe_4to1;
1828
1829 if (odm && old_pipe->next_odm_pipe)
1830 old_index = old_pipe->next_odm_pipe->pipe_idx;
1831 else if (!odm && old_pipe->bottom_pipe &&
1832 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1833 old_index = old_pipe->bottom_pipe->pipe_idx;
1834 else
1835 old_index = -1;
1836 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1837 ASSERT(pipe_4to1);
1838 if (!pipe_4to1)
1839 goto validate_fail;
1840 if (!dcn30_split_stream_for_mpc_or_odm(
1841 dc, &context->res_ctx,
1842 pipe, pipe_4to1, odm))
1843 goto validate_fail;
1844 newly_split[pipe_4to1->pipe_idx] = true;
1845
1846 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
1847 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
1848 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1849 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1850 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
1851 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1852 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1853 else
1854 old_index = -1;
1855 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1856 ASSERT(pipe_4to1);
1857 if (!pipe_4to1)
1858 goto validate_fail;
1859 if (!dcn30_split_stream_for_mpc_or_odm(
1860 dc, &context->res_ctx,
1861 hsplit_pipe, pipe_4to1, odm))
1862 goto validate_fail;
1863 newly_split[pipe_4to1->pipe_idx] = true;
1864 }
1865 if (odm)
1866 dcn20_build_mapped_resource(dc, context, pipe->stream);
1867 }
1868
1869 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1870 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1871
1872 if (pipe->plane_state) {
1873 if (!resource_build_scaling_params(pipe))
1874 goto validate_fail;
1875 }
1876 }
1877
1878 /* Actual dsc count per stream dsc validation*/
1879 if (!dcn20_validate_dsc(dc, context)) {
1880 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
1881 goto validate_fail;
1882 }
1883
1884 if (repopulate_pipes)
1885 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1886 context->bw_ctx.dml.vba.VoltageLevel = vlevel;
1887 *vlevel_out = vlevel;
1888 *pipe_cnt_out = pipe_cnt;
1889
1890 out = true;
1891 goto validate_out;
1892
1893validate_fail:
1894 out = false;
1895
1896validate_out:
1897 return out;
1898}
1899
1900static int get_refresh_rate(struct dc_state *context)
1901{
1902 int refresh_rate = 0;
1903 int h_v_total = 0;
1904 struct dc_crtc_timing *timing = NULL;
1905
1906 if (context == NULL || context->streams[0] == NULL)
1907 return 0;
1908
1909 /* check if refresh rate at least 120hz */
1910 timing = &context->streams[0]->timing;
1911 if (timing == NULL)
1912 return 0;
1913
1914 h_v_total = timing->h_total * timing->v_total;
1915 if (h_v_total == 0)
1916 return 0;
1917
1918 refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;
1919 return refresh_rate;
1920}
1921
1922#define MAX_STRETCHED_V_BLANK 500 // in micro-seconds
1923/*
1924 * Scaling factor for v_blank stretch calculations considering timing in
1925 * micro-seconds and pixel clock in 100hz.
1926 * Note: the parenthesis are necessary to ensure the correct order of
1927 * operation where V_SCALE is used.
1928 */
1929#define V_SCALE (10000 / MAX_STRETCHED_V_BLANK)
1930
1931static int get_frame_rate_at_max_stretch_100hz(struct dc_state *context)
1932{
1933 struct dc_crtc_timing *timing = NULL;
1934 uint32_t sec_per_100_lines;
1935 uint32_t max_v_blank;
1936 uint32_t curr_v_blank;
1937 uint32_t v_stretch_max;
1938 uint32_t stretched_frame_pix_cnt;
1939 uint32_t scaled_stretched_frame_pix_cnt;
1940 uint32_t scaled_refresh_rate;
1941
1942 if (context == NULL || context->streams[0] == NULL)
1943 return 0;
1944
1945 /* check if refresh rate at least 120hz */
1946 timing = &context->streams[0]->timing;
1947 if (timing == NULL)
1948 return 0;
1949
1950 sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;
1951 max_v_blank = sec_per_100_lines / V_SCALE + 1;
1952 curr_v_blank = timing->v_total - timing->v_addressable;
1953 v_stretch_max = (max_v_blank > curr_v_blank) ? (max_v_blank - curr_v_blank) : (0);
1954 stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;
1955 scaled_stretched_frame_pix_cnt = stretched_frame_pix_cnt / 10000;
1956 scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;
1957
1958 return scaled_refresh_rate;
1959}
1960
1961static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct dc_state *context)
1962{
1963 int refresh_rate_max_stretch_100hz;
1964 int min_refresh_100hz;
1965
1966 if (context == NULL || context->streams[0] == NULL)
1967 return false;
1968
1969 refresh_rate_max_stretch_100hz = get_frame_rate_at_max_stretch_100hz(context);
1970 min_refresh_100hz = context->streams[0]->timing.min_refresh_in_uhz / 10000;
1971
1972 if (refresh_rate_max_stretch_100hz < min_refresh_100hz)
1973 return false;
1974
1975 return true;
1976}
1977
1978bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
1979{
1980 int refresh_rate = 0;
1981 const int minimum_refreshrate_supported = 120;
1982
1983 if (context == NULL || context->streams[0] == NULL)
1984 return false;
1985
1986 if (context->streams[0]->sink->edid_caps.panel_patch.disable_fams)
1987 return false;
1988
1989 if (dc->debug.disable_fams)
1990 return false;
1991
1992 if (!dc->caps.dmub_caps.mclk_sw)
1993 return false;
1994
1995 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)
1996 return false;
1997
1998 /* more then 1 monitor connected */
1999 if (context->stream_count != 1)
2000 return false;
2001
2002 refresh_rate = get_refresh_rate(context);
2003 if (refresh_rate < minimum_refreshrate_supported)
2004 return false;
2005
2006 if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(context))
2007 return false;
2008
2009 // check if freesync enabled
2010 if (!context->streams[0]->allow_freesync)
2011 return false;
2012
2013 if (context->streams[0]->vrr_active_variable)
2014 return false;
2015
2016 return true;
2017}
2018
2019/*
2020 * set up FPO watermarks, pstate, dram latency
2021 */
2022void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
2023{
2024 ASSERT(dc != NULL && context != NULL);
2025 if (dc == NULL || context == NULL)
2026 return;
2027
2028 /* Set wm_a.pstate so high natural MCLK switches are impossible: 4 seconds */
2029 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2030}
2031
2032void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
2033{
2034 DC_FP_START();
2035 dcn30_fpu_update_soc_for_wm_a(dc, context);
2036 DC_FP_END();
2037}
2038
2039void dcn30_calculate_wm_and_dlg(
2040 struct dc *dc, struct dc_state *context,
2041 display_e2e_pipe_params_st *pipes,
2042 int pipe_cnt,
2043 int vlevel)
2044{
2045 DC_FP_START();
2046 dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2047 DC_FP_END();
2048}
2049
2050bool dcn30_validate_bandwidth(struct dc *dc,
2051 struct dc_state *context,
2052 bool fast_validate)
2053{
2054 bool out = false;
2055
2056 BW_VAL_TRACE_SETUP();
2057
2058 int vlevel = 0;
2059 int pipe_cnt = 0;
2060 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2061 DC_LOGGER_INIT(dc->ctx->logger);
2062
2063 BW_VAL_TRACE_COUNT();
2064
2065 DC_FP_START();
2066 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2067 DC_FP_END();
2068
2069 if (pipe_cnt == 0)
2070 goto validate_out;
2071
2072 if (!out)
2073 goto validate_fail;
2074
2075 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2076
2077 if (fast_validate) {
2078 BW_VAL_TRACE_SKIP(fast);
2079 goto validate_out;
2080 }
2081
2082 DC_FP_START();
2083 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2084 DC_FP_END();
2085
2086 BW_VAL_TRACE_END_WATERMARKS();
2087
2088 goto validate_out;
2089
2090validate_fail:
2091 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2092 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2093
2094 BW_VAL_TRACE_SKIP(fail);
2095 out = false;
2096
2097validate_out:
2098 kfree(pipes);
2099
2100 BW_VAL_TRACE_FINISH();
2101
2102 return out;
2103}
2104
2105void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2106{
2107 unsigned int i, j;
2108 unsigned int num_states = 0;
2109
2110 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2111 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2112 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2113 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2114
2115 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
2116 unsigned int num_dcfclk_sta_targets = 4;
2117 unsigned int num_uclk_states;
2118
2119 struct dc_bounding_box_max_clk dcn30_bb_max_clk;
2120
2121 memset(&dcn30_bb_max_clk, 0, sizeof(dcn30_bb_max_clk));
2122
2123 if (dc->ctx->dc_bios->vram_info.num_chans)
2124 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2125
2126 DC_FP_START();
2127 dcn30_fpu_update_dram_channel_width_bytes(dc);
2128 DC_FP_END();
2129
2130 if (bw_params->clk_table.entries[0].memclk_mhz) {
2131
2132 for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2133 if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz)
2134 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2135 if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz)
2136 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2137 if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz)
2138 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2139 if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz)
2140 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2141 }
2142
2143 DC_FP_START();
2144 dcn30_fpu_update_max_clk(&dcn30_bb_max_clk);
2145 DC_FP_END();
2146
2147 if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2148 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2149 dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz;
2150 num_dcfclk_sta_targets++;
2151 } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2152 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2153 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2154 if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) {
2155 dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz;
2156 break;
2157 }
2158 }
2159 // Update size of array since we "removed" duplicates
2160 num_dcfclk_sta_targets = i + 1;
2161 }
2162
2163 num_uclk_states = bw_params->clk_table.num_entries;
2164
2165 // Calculate optimal dcfclk for each uclk
2166 for (i = 0; i < num_uclk_states; i++) {
2167 DC_FP_START();
2168 dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2169 &optimal_dcfclk_for_uclk[i], NULL);
2170 DC_FP_END();
2171 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2172 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2173 }
2174 }
2175
2176 // Calculate optimal uclk for each dcfclk sta target
2177 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2178 for (j = 0; j < num_uclk_states; j++) {
2179 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2180 optimal_uclk_for_dcfclk_sta_targets[i] =
2181 bw_params->clk_table.entries[j].memclk_mhz * 16;
2182 break;
2183 }
2184 }
2185 }
2186
2187 i = 0;
2188 j = 0;
2189 // create the final dcfclk and uclk table
2190 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2191 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2192 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2193 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2194 } else {
2195 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2196 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2197 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2198 } else {
2199 j = num_uclk_states;
2200 }
2201 }
2202 }
2203
2204 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2205 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2206 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2207 }
2208
2209 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2210 optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2211 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2212 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2213 }
2214
2215 dcn3_0_soc.num_states = num_states;
2216 DC_FP_START();
2217 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts);
2218 DC_FP_END();
2219 }
2220}
2221
2222static void dcn30_get_panel_config_defaults(struct dc_panel_config *panel_config)
2223{
2224 *panel_config = panel_config_defaults;
2225}
2226
2227static const struct resource_funcs dcn30_res_pool_funcs = {
2228 .destroy = dcn30_destroy_resource_pool,
2229 .link_enc_create = dcn30_link_encoder_create,
2230 .panel_cntl_create = dcn30_panel_cntl_create,
2231 .validate_bandwidth = dcn30_validate_bandwidth,
2232 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2233 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2234 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2235 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2236 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2237 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2238 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2239 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2240 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2241 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2242 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2243 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2244 .update_bw_bounding_box = dcn30_update_bw_bounding_box,
2245 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2246 .get_panel_config_defaults = dcn30_get_panel_config_defaults,
2247};
2248
2249#define CTX ctx
2250
2251#define REG(reg_name) \
2252 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
2253
2254static uint32_t read_pipe_fuses(struct dc_context *ctx)
2255{
2256 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2257 /* Support for max 6 pipes */
2258 value = value & 0x3f;
2259 return value;
2260}
2261
2262static bool dcn30_resource_construct(
2263 uint8_t num_virtual_links,
2264 struct dc *dc,
2265 struct dcn30_resource_pool *pool)
2266{
2267 int i;
2268 struct dc_context *ctx = dc->ctx;
2269 struct irq_service_init_data init_data;
2270 struct ddc_service_init_data ddc_init_data = {0};
2271 uint32_t pipe_fuses = read_pipe_fuses(ctx);
2272 uint32_t num_pipes = 0;
2273
2274 if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) {
2275 BREAK_TO_DEBUGGER();
2276 dm_error("DC: Unexpected fuse recipe for navi2x !\n");
2277 /* fault to single pipe */
2278 pipe_fuses = 0x3e;
2279 }
2280
2281 DC_FP_START();
2282
2283 ctx->dc_bios->regs = &bios_regs;
2284
2285 pool->base.res_cap = &res_cap_dcn3;
2286
2287 pool->base.funcs = &dcn30_res_pool_funcs;
2288
2289 /*************************************************
2290 * Resource + asic cap harcoding *
2291 *************************************************/
2292 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2293 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2294 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2295 dc->caps.max_downscale_ratio = 600;
2296 dc->caps.i2c_speed_in_khz = 100;
2297 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2298 dc->caps.max_cursor_size = 256;
2299 dc->caps.min_horizontal_blanking_period = 80;
2300 dc->caps.dmdata_alloc_size = 2048;
2301 dc->caps.mall_size_per_mem_channel = 8;
2302 /* total size = mall per channel * num channels * 1024 * 1024 */
2303 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2304 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2305
2306 dc->caps.max_slave_planes = 2;
2307 dc->caps.max_slave_yuv_planes = 2;
2308 dc->caps.max_slave_rgb_planes = 2;
2309 dc->caps.post_blend_color_processing = true;
2310 dc->caps.force_dp_tps4_for_cp2520 = true;
2311 dc->caps.extended_aux_timeout_support = true;
2312 dc->caps.dmcub_support = true;
2313
2314 /* Color pipeline capabilities */
2315 dc->caps.color.dpp.dcn_arch = 1;
2316 dc->caps.color.dpp.input_lut_shared = 0;
2317 dc->caps.color.dpp.icsc = 1;
2318 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2319 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2320 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2321 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2322 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2323 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2324 dc->caps.color.dpp.post_csc = 1;
2325 dc->caps.color.dpp.gamma_corr = 1;
2326 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2327
2328 dc->caps.color.dpp.hw_3d_lut = 1;
2329 dc->caps.color.dpp.ogam_ram = 1;
2330 // no OGAM ROM on DCN3
2331 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2332 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2333 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2334 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2335 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2336 dc->caps.color.dpp.ocsc = 0;
2337
2338 dc->caps.color.mpc.gamut_remap = 1;
2339 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
2340 dc->caps.color.mpc.ogam_ram = 1;
2341 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2342 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2343 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2344 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2345 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2346 dc->caps.color.mpc.ocsc = 1;
2347
2348 dc->caps.dp_hdmi21_pcon_support = true;
2349
2350 /* read VBIOS LTTPR caps */
2351 {
2352 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2353 enum bp_result bp_query_result;
2354 uint8_t is_vbios_lttpr_enable = 0;
2355
2356 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2357 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2358 }
2359
2360 if (ctx->dc_bios->funcs->get_lttpr_interop) {
2361 enum bp_result bp_query_result;
2362 uint8_t is_vbios_interop_enabled = 0;
2363
2364 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
2365 &is_vbios_interop_enabled);
2366 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
2367 }
2368 }
2369
2370 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2371 dc->debug = debug_defaults_drv;
2372 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2373 dc->debug = debug_defaults_diags;
2374 } else
2375 dc->debug = debug_defaults_diags;
2376 // Init the vm_helper
2377 if (dc->vm_helper)
2378 vm_helper_init(dc->vm_helper, 16);
2379
2380 /*************************************************
2381 * Create resources *
2382 *************************************************/
2383
2384 /* Clock Sources for Pixel Clock*/
2385 pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2386 dcn30_clock_source_create(ctx, ctx->dc_bios,
2387 CLOCK_SOURCE_COMBO_PHY_PLL0,
2388 &clk_src_regs[0], false);
2389 pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2390 dcn30_clock_source_create(ctx, ctx->dc_bios,
2391 CLOCK_SOURCE_COMBO_PHY_PLL1,
2392 &clk_src_regs[1], false);
2393 pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2394 dcn30_clock_source_create(ctx, ctx->dc_bios,
2395 CLOCK_SOURCE_COMBO_PHY_PLL2,
2396 &clk_src_regs[2], false);
2397 pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2398 dcn30_clock_source_create(ctx, ctx->dc_bios,
2399 CLOCK_SOURCE_COMBO_PHY_PLL3,
2400 &clk_src_regs[3], false);
2401 pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2402 dcn30_clock_source_create(ctx, ctx->dc_bios,
2403 CLOCK_SOURCE_COMBO_PHY_PLL4,
2404 &clk_src_regs[4], false);
2405 pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2406 dcn30_clock_source_create(ctx, ctx->dc_bios,
2407 CLOCK_SOURCE_COMBO_PHY_PLL5,
2408 &clk_src_regs[5], false);
2409
2410 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2411
2412 /* todo: not reuse phy_pll registers */
2413 pool->base.dp_clock_source =
2414 dcn30_clock_source_create(ctx, ctx->dc_bios,
2415 CLOCK_SOURCE_ID_DP_DTO,
2416 &clk_src_regs[0], true);
2417
2418 for (i = 0; i < pool->base.clk_src_count; i++) {
2419 if (pool->base.clock_sources[i] == NULL) {
2420 dm_error("DC: failed to create clock sources!\n");
2421 BREAK_TO_DEBUGGER();
2422 goto create_fail;
2423 }
2424 }
2425
2426 /* DCCG */
2427 pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2428 if (pool->base.dccg == NULL) {
2429 dm_error("DC: failed to create dccg!\n");
2430 BREAK_TO_DEBUGGER();
2431 goto create_fail;
2432 }
2433
2434 /* PP Lib and SMU interfaces */
2435 init_soc_bounding_box(dc, pool);
2436
2437 num_pipes = dcn3_0_ip.max_num_dpp;
2438
2439 for (i = 0; i < dcn3_0_ip.max_num_dpp; i++)
2440 if (pipe_fuses & 1 << i)
2441 num_pipes--;
2442
2443 dcn3_0_ip.max_num_dpp = num_pipes;
2444 dcn3_0_ip.max_num_otg = num_pipes;
2445
2446 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2447
2448 /* IRQ */
2449 init_data.ctx = dc->ctx;
2450 pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
2451 if (!pool->base.irqs)
2452 goto create_fail;
2453
2454 /* HUBBUB */
2455 pool->base.hubbub = dcn30_hubbub_create(ctx);
2456 if (pool->base.hubbub == NULL) {
2457 BREAK_TO_DEBUGGER();
2458 dm_error("DC: failed to create hubbub!\n");
2459 goto create_fail;
2460 }
2461
2462 /* HUBPs, DPPs, OPPs and TGs */
2463 for (i = 0; i < pool->base.pipe_count; i++) {
2464 pool->base.hubps[i] = dcn30_hubp_create(ctx, i);
2465 if (pool->base.hubps[i] == NULL) {
2466 BREAK_TO_DEBUGGER();
2467 dm_error(
2468 "DC: failed to create hubps!\n");
2469 goto create_fail;
2470 }
2471
2472 pool->base.dpps[i] = dcn30_dpp_create(ctx, i);
2473 if (pool->base.dpps[i] == NULL) {
2474 BREAK_TO_DEBUGGER();
2475 dm_error(
2476 "DC: failed to create dpps!\n");
2477 goto create_fail;
2478 }
2479 }
2480
2481 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2482 pool->base.opps[i] = dcn30_opp_create(ctx, i);
2483 if (pool->base.opps[i] == NULL) {
2484 BREAK_TO_DEBUGGER();
2485 dm_error(
2486 "DC: failed to create output pixel processor!\n");
2487 goto create_fail;
2488 }
2489 }
2490
2491 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2492 pool->base.timing_generators[i] = dcn30_timing_generator_create(
2493 ctx, i);
2494 if (pool->base.timing_generators[i] == NULL) {
2495 BREAK_TO_DEBUGGER();
2496 dm_error("DC: failed to create tg!\n");
2497 goto create_fail;
2498 }
2499 }
2500 pool->base.timing_generator_count = i;
2501 /* PSR */
2502 pool->base.psr = dmub_psr_create(ctx);
2503
2504 if (pool->base.psr == NULL) {
2505 dm_error("DC: failed to create PSR obj!\n");
2506 BREAK_TO_DEBUGGER();
2507 goto create_fail;
2508 }
2509
2510 /* ABM */
2511 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2512 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2513 &abm_regs[i],
2514 &abm_shift,
2515 &abm_mask);
2516 if (pool->base.multiple_abms[i] == NULL) {
2517 dm_error("DC: failed to create abm for pipe %d!\n", i);
2518 BREAK_TO_DEBUGGER();
2519 goto create_fail;
2520 }
2521 }
2522 /* MPC and DSC */
2523 pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2524 if (pool->base.mpc == NULL) {
2525 BREAK_TO_DEBUGGER();
2526 dm_error("DC: failed to create mpc!\n");
2527 goto create_fail;
2528 }
2529
2530 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2531 pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
2532 if (pool->base.dscs[i] == NULL) {
2533 BREAK_TO_DEBUGGER();
2534 dm_error("DC: failed to create display stream compressor %d!\n", i);
2535 goto create_fail;
2536 }
2537 }
2538
2539 /* DWB and MMHUBBUB */
2540 if (!dcn30_dwbc_create(ctx, &pool->base)) {
2541 BREAK_TO_DEBUGGER();
2542 dm_error("DC: failed to create dwbc!\n");
2543 goto create_fail;
2544 }
2545
2546 if (!dcn30_mmhubbub_create(ctx, &pool->base)) {
2547 BREAK_TO_DEBUGGER();
2548 dm_error("DC: failed to create mcif_wb!\n");
2549 goto create_fail;
2550 }
2551
2552 /* AUX and I2C */
2553 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2554 pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
2555 if (pool->base.engines[i] == NULL) {
2556 BREAK_TO_DEBUGGER();
2557 dm_error(
2558 "DC:failed to create aux engine!!\n");
2559 goto create_fail;
2560 }
2561 pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);
2562 if (pool->base.hw_i2cs[i] == NULL) {
2563 BREAK_TO_DEBUGGER();
2564 dm_error(
2565 "DC:failed to create hw i2c!!\n");
2566 goto create_fail;
2567 }
2568 pool->base.sw_i2cs[i] = NULL;
2569 }
2570
2571 /* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */
2572 if (!resource_construct(num_virtual_links, dc, &pool->base,
2573 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2574 &res_create_funcs : &res_create_maximus_funcs)))
2575 goto create_fail;
2576
2577 /* HW Sequencer and Plane caps */
2578 dcn30_hw_sequencer_construct(dc);
2579
2580 dc->caps.max_planes = pool->base.pipe_count;
2581
2582 for (i = 0; i < dc->caps.max_planes; ++i)
2583 dc->caps.planes[i] = plane_cap;
2584
2585 dc->cap_funcs = cap_funcs;
2586
2587 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2588 ddc_init_data.ctx = dc->ctx;
2589 ddc_init_data.link = NULL;
2590 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2591 ddc_init_data.id.enum_id = 0;
2592 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2593 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
2594 } else {
2595 pool->base.oem_device = NULL;
2596 }
2597
2598 DC_FP_END();
2599
2600 return true;
2601
2602create_fail:
2603
2604 DC_FP_END();
2605 dcn30_resource_destruct(pool);
2606
2607 return false;
2608}
2609
2610struct resource_pool *dcn30_create_resource_pool(
2611 const struct dc_init_data *init_data,
2612 struct dc *dc)
2613{
2614 struct dcn30_resource_pool *pool =
2615 kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL);
2616
2617 if (!pool)
2618 return NULL;
2619
2620 if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
2621 return &pool->base;
2622
2623 BREAK_TO_DEBUGGER();
2624 kfree(pool);
2625 return NULL;
2626}