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1#
2# EDAC Kconfig
3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4# Licensed and distributed under the GPL
5
6config EDAC_ATOMIC_SCRUB
7 bool
8
9config EDAC_SUPPORT
10 bool
11
12menuconfig EDAC
13 tristate "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
15 help
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
18 in the CPU or supporting chipset or other subsystems:
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
21
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
23
24if EDAC
25
26config EDAC_LEGACY_SYSFS
27 bool "EDAC legacy sysfs"
28 default y
29 help
30 Enable the compatibility sysfs nodes.
31 Use 'Y' if your edac utilities aren't ported to work with the newer
32 structures.
33
34config EDAC_DEBUG
35 bool "Debugging"
36 select DEBUG_FS
37 help
38 This turns on debugging information for the entire EDAC subsystem.
39 You do so by inserting edac_module with "edac_debug_level=x." Valid
40 levels are 0-4 (from low to high) and by default it is set to 2.
41 Usually you should select 'N' here.
42
43config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
45 depends on CPU_SUP_AMD && X86_MCE_AMD
46 default y
47 help
48 Enable this option if you want to decode Machine Check Exceptions
49 occurring on your machine in human-readable form.
50
51 You should definitely say Y here in case you want to decode MCEs
52 which occur really early upon boot, before the module infrastructure
53 has been initialized.
54
55config EDAC_GHES
56 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC"
57 depends on ACPI_APEI_GHES
58 select UEFI_CPER
59 help
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
62 APEI/GHES driver. By enabling this option, the error reports provided
63 by GHES are sent to userspace via the EDAC API.
64
65 When this option is enabled, it will disable the hardware-driven
66 mechanisms, if a GHES BIOS is detected, entering into the
67 "Firmware First" mode.
68
69 It should be noticed that keeping both GHES and a hardware-driven
70 error mechanism won't work well, as BIOS will race with OS, while
71 reading the error registers. So, if you want to not use "Firmware
72 first" GHES error mechanism, you should disable GHES either at
73 compilation time or by passing "ghes.disable=1" Kernel parameter
74 at boot time.
75
76 In doubt, say 'Y'.
77
78config EDAC_AMD64
79 tristate "AMD64 (Opteron, Athlon64)"
80 depends on AMD_NB && EDAC_DECODE_MCE
81 imply AMD_ATL
82 help
83 Support for error detection and correction of DRAM ECC errors on
84 the AMD64 families (>= K8) of memory controllers.
85
86 When EDAC_DEBUG is enabled, hardware error injection facilities
87 through sysfs are available:
88
89 AMD CPUs up to and excluding family 0x17 provide for Memory
90 Error Injection into the ECC detection circuits. The amd64_edac
91 module allows the operator/user to inject Uncorrectable and
92 Correctable errors into DRAM.
93
94 When enabled, in each of the respective memory controller directories
95 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
96
97 - inject_section (0..3, 16-byte section of 64-byte cacheline),
98 - inject_word (0..8, 16-bit word of 16-byte section),
99 - inject_ecc_vector (hex ecc vector: select bits of inject word)
100
101 In addition, there are two control files, inject_read and inject_write,
102 which trigger the DRAM ECC Read and Write respectively.
103
104config EDAC_AL_MC
105 tristate "Amazon's Annapurna Lab Memory Controller"
106 depends on (ARCH_ALPINE || COMPILE_TEST)
107 help
108 Support for error detection and correction for Amazon's Annapurna
109 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
110
111config EDAC_AMD76X
112 tristate "AMD 76x (760, 762, 768)"
113 depends on PCI && X86_32
114 help
115 Support for error detection and correction on the AMD 76x
116 series of chipsets used with the Athlon processor.
117
118config EDAC_E7XXX
119 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
120 depends on PCI && X86_32
121 help
122 Support for error detection and correction on the Intel
123 E7205, E7500, E7501 and E7505 server chipsets.
124
125config EDAC_E752X
126 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
127 depends on PCI && X86
128 help
129 Support for error detection and correction on the Intel
130 E7520, E7525, E7320 server chipsets.
131
132config EDAC_I82443BXGX
133 tristate "Intel 82443BX/GX (440BX/GX)"
134 depends on PCI && X86_32
135 depends on BROKEN
136 help
137 Support for error detection and correction on the Intel
138 82443BX/GX memory controllers (440BX/GX chipsets).
139
140config EDAC_I82875P
141 tristate "Intel 82875p (D82875P, E7210)"
142 depends on PCI && X86_32
143 help
144 Support for error detection and correction on the Intel
145 DP82785P and E7210 server chipsets.
146
147config EDAC_I82975X
148 tristate "Intel 82975x (D82975x)"
149 depends on PCI && X86
150 help
151 Support for error detection and correction on the Intel
152 DP82975x server chipsets.
153
154config EDAC_I3000
155 tristate "Intel 3000/3010"
156 depends on PCI && X86
157 help
158 Support for error detection and correction on the Intel
159 3000 and 3010 server chipsets.
160
161config EDAC_I3200
162 tristate "Intel 3200"
163 depends on PCI && X86
164 help
165 Support for error detection and correction on the Intel
166 3200 and 3210 server chipsets.
167
168config EDAC_IE31200
169 tristate "Intel e312xx"
170 depends on PCI && X86
171 help
172 Support for error detection and correction on the Intel
173 E3-1200 based DRAM controllers.
174
175config EDAC_X38
176 tristate "Intel X38"
177 depends on PCI && X86
178 help
179 Support for error detection and correction on the Intel
180 X38 server chipsets.
181
182config EDAC_I5400
183 tristate "Intel 5400 (Seaburg) chipsets"
184 depends on PCI && X86
185 help
186 Support for error detection and correction the Intel
187 i5400 MCH chipset (Seaburg).
188
189config EDAC_I7CORE
190 tristate "Intel i7 Core (Nehalem) processors"
191 depends on PCI && X86 && X86_MCE_INTEL
192 help
193 Support for error detection and correction the Intel
194 i7 Core (Nehalem) Integrated Memory Controller that exists on
195 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
196 and Xeon 55xx processors.
197
198config EDAC_I82860
199 tristate "Intel 82860"
200 depends on PCI && X86_32
201 help
202 Support for error detection and correction on the Intel
203 82860 chipset.
204
205config EDAC_R82600
206 tristate "Radisys 82600 embedded chipset"
207 depends on PCI && X86_32
208 help
209 Support for error detection and correction on the Radisys
210 82600 embedded chipset.
211
212config EDAC_I5000
213 tristate "Intel Greencreek/Blackford chipset"
214 depends on X86 && PCI
215 depends on BROKEN
216 help
217 Support for error detection and correction the Intel
218 Greekcreek/Blackford chipsets.
219
220config EDAC_I5100
221 tristate "Intel San Clemente MCH"
222 depends on X86 && PCI
223 help
224 Support for error detection and correction the Intel
225 San Clemente MCH.
226
227config EDAC_I7300
228 tristate "Intel Clarksboro MCH"
229 depends on X86 && PCI
230 help
231 Support for error detection and correction the Intel
232 Clarksboro MCH (Intel 7300 chipset).
233
234config EDAC_SBRIDGE
235 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
236 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
237 help
238 Support for error detection and correction the Intel
239 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
240
241config EDAC_SKX
242 tristate "Intel Skylake server Integrated MC"
243 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
244 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
245 select DMI
246 select ACPI_ADXL
247 help
248 Support for error detection and correction the Intel
249 Skylake server Integrated Memory Controllers. If your
250 system has non-volatile DIMMs you should also manually
251 select CONFIG_ACPI_NFIT.
252
253config EDAC_I10NM
254 tristate "Intel 10nm server Integrated MC"
255 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
256 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
257 select DMI
258 select ACPI_ADXL
259 help
260 Support for error detection and correction the Intel
261 10nm server Integrated Memory Controllers. If your
262 system has non-volatile DIMMs you should also manually
263 select CONFIG_ACPI_NFIT.
264
265config EDAC_PND2
266 tristate "Intel Pondicherry2"
267 depends on PCI && X86_64 && X86_MCE_INTEL
268 select P2SB if X86
269 help
270 Support for error detection and correction on the Intel
271 Pondicherry2 Integrated Memory Controller. This SoC IP is
272 first used on the Apollo Lake platform and Denverton
273 micro-server but may appear on others in the future.
274
275config EDAC_IGEN6
276 tristate "Intel client SoC Integrated MC"
277 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
278 depends on X86_64 && X86_MCE_INTEL
279 help
280 Support for error detection and correction on the Intel
281 client SoC Integrated Memory Controller using In-Band ECC IP.
282 This In-Band ECC is first used on the Elkhart Lake SoC but
283 may appear on others in the future.
284
285config EDAC_MPC85XX
286 bool "Freescale MPC83xx / MPC85xx"
287 depends on FSL_SOC && EDAC=y
288 help
289 Support for error detection and correction on the Freescale
290 MPC8349, MPC8560, MPC8540, MPC8548, T4240
291
292config EDAC_LAYERSCAPE
293 tristate "Freescale Layerscape DDR"
294 depends on ARCH_LAYERSCAPE || SOC_LS1021A
295 help
296 Support for error detection and correction on Freescale memory
297 controllers on Layerscape SoCs.
298
299config EDAC_PASEMI
300 tristate "PA Semi PWRficient"
301 depends on PPC_PASEMI && PCI
302 help
303 Support for error detection and correction on PA Semi
304 PWRficient.
305
306config EDAC_CELL
307 tristate "Cell Broadband Engine memory controller"
308 depends on PPC_CELL_COMMON
309 help
310 Support for error detection and correction on the
311 Cell Broadband Engine internal memory controller
312 on platform without a hypervisor
313
314config EDAC_CPC925
315 tristate "IBM CPC925 Memory Controller (PPC970FX)"
316 depends on PPC64
317 help
318 Support for error detection and correction on the
319 IBM CPC925 Bridge and Memory Controller, which is
320 a companion chip to the PowerPC 970 family of
321 processors.
322
323config EDAC_HIGHBANK_MC
324 tristate "Highbank Memory Controller"
325 depends on ARCH_HIGHBANK
326 help
327 Support for error detection and correction on the
328 Calxeda Highbank memory controller.
329
330config EDAC_HIGHBANK_L2
331 tristate "Highbank L2 Cache"
332 depends on ARCH_HIGHBANK
333 help
334 Support for error detection and correction on the
335 Calxeda Highbank memory controller.
336
337config EDAC_OCTEON_PC
338 tristate "Cavium Octeon Primary Caches"
339 depends on CPU_CAVIUM_OCTEON
340 help
341 Support for error detection and correction on the primary caches of
342 the cnMIPS cores of Cavium Octeon family SOCs.
343
344config EDAC_OCTEON_L2C
345 tristate "Cavium Octeon Secondary Caches (L2C)"
346 depends on CAVIUM_OCTEON_SOC
347 help
348 Support for error detection and correction on the
349 Cavium Octeon family of SOCs.
350
351config EDAC_OCTEON_LMC
352 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
353 depends on CAVIUM_OCTEON_SOC
354 help
355 Support for error detection and correction on the
356 Cavium Octeon family of SOCs.
357
358config EDAC_OCTEON_PCI
359 tristate "Cavium Octeon PCI Controller"
360 depends on PCI && CAVIUM_OCTEON_SOC
361 help
362 Support for error detection and correction on the
363 Cavium Octeon family of SOCs.
364
365config EDAC_THUNDERX
366 tristate "Cavium ThunderX EDAC"
367 depends on ARM64
368 depends on PCI
369 help
370 Support for error detection and correction on the
371 Cavium ThunderX memory controllers (LMC), Cache
372 Coherent Processor Interconnect (CCPI) and L2 cache
373 blocks (TAD, CBC, MCI).
374
375config EDAC_ALTERA
376 bool "Altera SOCFPGA ECC"
377 depends on EDAC=y && ARCH_INTEL_SOCFPGA
378 help
379 Support for error detection and correction on the
380 Altera SOCs. This is the global enable for the
381 various Altera peripherals.
382
383config EDAC_ALTERA_SDRAM
384 bool "Altera SDRAM ECC"
385 depends on EDAC_ALTERA=y
386 help
387 Support for error detection and correction on the
388 Altera SDRAM Memory for Altera SoCs. Note that the
389 preloader must initialize the SDRAM before loading
390 the kernel.
391
392config EDAC_ALTERA_L2C
393 bool "Altera L2 Cache ECC"
394 depends on EDAC_ALTERA=y && CACHE_L2X0
395 help
396 Support for error detection and correction on the
397 Altera L2 cache Memory for Altera SoCs. This option
398 requires L2 cache.
399
400config EDAC_ALTERA_OCRAM
401 bool "Altera On-Chip RAM ECC"
402 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
403 help
404 Support for error detection and correction on the
405 Altera On-Chip RAM Memory for Altera SoCs.
406
407config EDAC_ALTERA_ETHERNET
408 bool "Altera Ethernet FIFO ECC"
409 depends on EDAC_ALTERA=y
410 help
411 Support for error detection and correction on the
412 Altera Ethernet FIFO Memory for Altera SoCs.
413
414config EDAC_ALTERA_NAND
415 bool "Altera NAND FIFO ECC"
416 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
417 help
418 Support for error detection and correction on the
419 Altera NAND FIFO Memory for Altera SoCs.
420
421config EDAC_ALTERA_DMA
422 bool "Altera DMA FIFO ECC"
423 depends on EDAC_ALTERA=y && PL330_DMA=y
424 help
425 Support for error detection and correction on the
426 Altera DMA FIFO Memory for Altera SoCs.
427
428config EDAC_ALTERA_USB
429 bool "Altera USB FIFO ECC"
430 depends on EDAC_ALTERA=y && USB_DWC2
431 help
432 Support for error detection and correction on the
433 Altera USB FIFO Memory for Altera SoCs.
434
435config EDAC_ALTERA_QSPI
436 bool "Altera QSPI FIFO ECC"
437 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
438 help
439 Support for error detection and correction on the
440 Altera QSPI FIFO Memory for Altera SoCs.
441
442config EDAC_ALTERA_SDMMC
443 bool "Altera SDMMC FIFO ECC"
444 depends on EDAC_ALTERA=y && MMC_DW
445 help
446 Support for error detection and correction on the
447 Altera SDMMC FIFO Memory for Altera SoCs.
448
449config EDAC_SIFIVE
450 bool "Sifive platform EDAC driver"
451 depends on EDAC=y && SIFIVE_CCACHE
452 help
453 Support for error detection and correction on the SiFive SoCs.
454
455config EDAC_ARMADA_XP
456 bool "Marvell Armada XP DDR and L2 Cache ECC"
457 depends on MACH_MVEBU_V7
458 help
459 Support for error correction and detection on the Marvell Aramada XP
460 DDR RAM and L2 cache controllers.
461
462config EDAC_SYNOPSYS
463 tristate "Synopsys DDR Memory Controller"
464 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC
465 help
466 Support for error detection and correction on the Synopsys DDR
467 memory controller.
468
469config EDAC_XGENE
470 tristate "APM X-Gene SoC"
471 depends on (ARM64 || COMPILE_TEST)
472 help
473 Support for error detection and correction on the
474 APM X-Gene family of SOCs.
475
476config EDAC_TI
477 tristate "Texas Instruments DDR3 ECC Controller"
478 depends on ARCH_KEYSTONE || SOC_DRA7XX
479 help
480 Support for error detection and correction on the TI SoCs.
481
482config EDAC_QCOM
483 tristate "QCOM EDAC Controller"
484 depends on ARCH_QCOM && QCOM_LLCC
485 help
486 Support for error detection and correction on the
487 Qualcomm Technologies, Inc. SoCs.
488
489 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
490 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
491 of Tag RAM and Data RAM.
492
493 For debugging issues having to do with stability and overall system
494 health, you should probably say 'Y' here.
495
496config EDAC_ASPEED
497 tristate "Aspeed AST BMC SoC"
498 depends on ARCH_ASPEED
499 help
500 Support for error detection and correction on the Aspeed AST BMC SoC.
501
502 First, ECC must be configured in the bootloader. Then, this driver
503 will expose error counters via the EDAC kernel framework.
504
505config EDAC_BLUEFIELD
506 tristate "Mellanox BlueField Memory ECC"
507 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
508 help
509 Support for error detection and correction on the
510 Mellanox BlueField SoCs.
511
512config EDAC_DMC520
513 tristate "ARM DMC-520 ECC"
514 depends on ARM64
515 help
516 Support for error detection and correction on the
517 SoCs with ARM DMC-520 DRAM controller.
518
519config EDAC_ZYNQMP
520 tristate "Xilinx ZynqMP OCM Controller"
521 depends on ARCH_ZYNQMP || COMPILE_TEST
522 help
523 This driver supports error detection and correction for the
524 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be
525 built as a module. In that case it will be called zynqmp_edac.
526
527config EDAC_NPCM
528 tristate "Nuvoton NPCM DDR Memory Controller"
529 depends on (ARCH_NPCM || COMPILE_TEST)
530 help
531 Support for error detection and correction on the Nuvoton NPCM DDR
532 memory controller.
533
534 The memory controller supports single bit error correction, double bit
535 error detection (in-line ECC in which a section 1/8th of the memory
536 device used to store data is used for ECC storage).
537
538config EDAC_VERSAL
539 tristate "Xilinx Versal DDR Memory Controller"
540 depends on ARCH_ZYNQMP || COMPILE_TEST
541 help
542 Support for error detection and correction on the Xilinx Versal DDR
543 memory controller.
544
545 Report both single bit errors (CE) and double bit errors (UE).
546 Support injecting both correctable and uncorrectable errors
547 for debugging purposes.
548
549
550endif # EDAC
1#
2# EDAC Kconfig
3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4# Licensed and distributed under the GPL
5
6config EDAC_ATOMIC_SCRUB
7 bool
8
9config EDAC_SUPPORT
10 bool
11
12menuconfig EDAC
13 tristate "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
15 help
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
18 in the CPU or supporting chipset or other subsystems:
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
21
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
23
24if EDAC
25
26config EDAC_LEGACY_SYSFS
27 bool "EDAC legacy sysfs"
28 default y
29 help
30 Enable the compatibility sysfs nodes.
31 Use 'Y' if your edac utilities aren't ported to work with the newer
32 structures.
33
34config EDAC_DEBUG
35 bool "Debugging"
36 select DEBUG_FS
37 help
38 This turns on debugging information for the entire EDAC subsystem.
39 You do so by inserting edac_module with "edac_debug_level=x." Valid
40 levels are 0-4 (from low to high) and by default it is set to 2.
41 Usually you should select 'N' here.
42
43config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
45 depends on CPU_SUP_AMD && X86_MCE_AMD
46 default y
47 help
48 Enable this option if you want to decode Machine Check Exceptions
49 occurring on your machine in human-readable form.
50
51 You should definitely say Y here in case you want to decode MCEs
52 which occur really early upon boot, before the module infrastructure
53 has been initialized.
54
55config EDAC_GHES
56 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC"
57 depends on ACPI_APEI_GHES
58 select UEFI_CPER
59 help
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
62 APEI/GHES driver. By enabling this option, the error reports provided
63 by GHES are sent to userspace via the EDAC API.
64
65 When this option is enabled, it will disable the hardware-driven
66 mechanisms, if a GHES BIOS is detected, entering into the
67 "Firmware First" mode.
68
69 It should be noticed that keeping both GHES and a hardware-driven
70 error mechanism won't work well, as BIOS will race with OS, while
71 reading the error registers. So, if you want to not use "Firmware
72 first" GHES error mechanism, you should disable GHES either at
73 compilation time or by passing "ghes.disable=1" Kernel parameter
74 at boot time.
75
76 In doubt, say 'Y'.
77
78config EDAC_AMD64
79 tristate "AMD64 (Opteron, Athlon64)"
80 depends on AMD_NB && EDAC_DECODE_MCE
81 help
82 Support for error detection and correction of DRAM ECC errors on
83 the AMD64 families (>= K8) of memory controllers.
84
85 When EDAC_DEBUG is enabled, hardware error injection facilities
86 through sysfs are available:
87
88 AMD CPUs up to and excluding family 0x17 provide for Memory
89 Error Injection into the ECC detection circuits. The amd64_edac
90 module allows the operator/user to inject Uncorrectable and
91 Correctable errors into DRAM.
92
93 When enabled, in each of the respective memory controller directories
94 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
95
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
99
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
102
103config EDAC_AL_MC
104 tristate "Amazon's Annapurna Lab Memory Controller"
105 depends on (ARCH_ALPINE || COMPILE_TEST)
106 help
107 Support for error detection and correction for Amazon's Annapurna
108 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
109
110config EDAC_AMD76X
111 tristate "AMD 76x (760, 762, 768)"
112 depends on PCI && X86_32
113 help
114 Support for error detection and correction on the AMD 76x
115 series of chipsets used with the Athlon processor.
116
117config EDAC_E7XXX
118 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
119 depends on PCI && X86_32
120 help
121 Support for error detection and correction on the Intel
122 E7205, E7500, E7501 and E7505 server chipsets.
123
124config EDAC_E752X
125 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
126 depends on PCI && X86
127 help
128 Support for error detection and correction on the Intel
129 E7520, E7525, E7320 server chipsets.
130
131config EDAC_I82443BXGX
132 tristate "Intel 82443BX/GX (440BX/GX)"
133 depends on PCI && X86_32
134 depends on BROKEN
135 help
136 Support for error detection and correction on the Intel
137 82443BX/GX memory controllers (440BX/GX chipsets).
138
139config EDAC_I82875P
140 tristate "Intel 82875p (D82875P, E7210)"
141 depends on PCI && X86_32
142 help
143 Support for error detection and correction on the Intel
144 DP82785P and E7210 server chipsets.
145
146config EDAC_I82975X
147 tristate "Intel 82975x (D82975x)"
148 depends on PCI && X86
149 help
150 Support for error detection and correction on the Intel
151 DP82975x server chipsets.
152
153config EDAC_I3000
154 tristate "Intel 3000/3010"
155 depends on PCI && X86
156 help
157 Support for error detection and correction on the Intel
158 3000 and 3010 server chipsets.
159
160config EDAC_I3200
161 tristate "Intel 3200"
162 depends on PCI && X86
163 help
164 Support for error detection and correction on the Intel
165 3200 and 3210 server chipsets.
166
167config EDAC_IE31200
168 tristate "Intel e312xx"
169 depends on PCI && X86
170 help
171 Support for error detection and correction on the Intel
172 E3-1200 based DRAM controllers.
173
174config EDAC_X38
175 tristate "Intel X38"
176 depends on PCI && X86
177 help
178 Support for error detection and correction on the Intel
179 X38 server chipsets.
180
181config EDAC_I5400
182 tristate "Intel 5400 (Seaburg) chipsets"
183 depends on PCI && X86
184 help
185 Support for error detection and correction the Intel
186 i5400 MCH chipset (Seaburg).
187
188config EDAC_I7CORE
189 tristate "Intel i7 Core (Nehalem) processors"
190 depends on PCI && X86 && X86_MCE_INTEL
191 help
192 Support for error detection and correction the Intel
193 i7 Core (Nehalem) Integrated Memory Controller that exists on
194 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
195 and Xeon 55xx processors.
196
197config EDAC_I82860
198 tristate "Intel 82860"
199 depends on PCI && X86_32
200 help
201 Support for error detection and correction on the Intel
202 82860 chipset.
203
204config EDAC_R82600
205 tristate "Radisys 82600 embedded chipset"
206 depends on PCI && X86_32
207 help
208 Support for error detection and correction on the Radisys
209 82600 embedded chipset.
210
211config EDAC_I5000
212 tristate "Intel Greencreek/Blackford chipset"
213 depends on X86 && PCI
214 depends on BROKEN
215 help
216 Support for error detection and correction the Intel
217 Greekcreek/Blackford chipsets.
218
219config EDAC_I5100
220 tristate "Intel San Clemente MCH"
221 depends on X86 && PCI
222 help
223 Support for error detection and correction the Intel
224 San Clemente MCH.
225
226config EDAC_I7300
227 tristate "Intel Clarksboro MCH"
228 depends on X86 && PCI
229 help
230 Support for error detection and correction the Intel
231 Clarksboro MCH (Intel 7300 chipset).
232
233config EDAC_SBRIDGE
234 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
235 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
236 help
237 Support for error detection and correction the Intel
238 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
239
240config EDAC_SKX
241 tristate "Intel Skylake server Integrated MC"
242 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
243 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
244 select DMI
245 select ACPI_ADXL
246 help
247 Support for error detection and correction the Intel
248 Skylake server Integrated Memory Controllers. If your
249 system has non-volatile DIMMs you should also manually
250 select CONFIG_ACPI_NFIT.
251
252config EDAC_I10NM
253 tristate "Intel 10nm server Integrated MC"
254 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
255 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
256 select DMI
257 select ACPI_ADXL
258 help
259 Support for error detection and correction the Intel
260 10nm server Integrated Memory Controllers. If your
261 system has non-volatile DIMMs you should also manually
262 select CONFIG_ACPI_NFIT.
263
264config EDAC_PND2
265 tristate "Intel Pondicherry2"
266 depends on PCI && X86_64 && X86_MCE_INTEL
267 select P2SB if X86
268 help
269 Support for error detection and correction on the Intel
270 Pondicherry2 Integrated Memory Controller. This SoC IP is
271 first used on the Apollo Lake platform and Denverton
272 micro-server but may appear on others in the future.
273
274config EDAC_IGEN6
275 tristate "Intel client SoC Integrated MC"
276 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
277 depends on X86_64 && X86_MCE_INTEL
278 help
279 Support for error detection and correction on the Intel
280 client SoC Integrated Memory Controller using In-Band ECC IP.
281 This In-Band ECC is first used on the Elkhart Lake SoC but
282 may appear on others in the future.
283
284config EDAC_MPC85XX
285 bool "Freescale MPC83xx / MPC85xx"
286 depends on FSL_SOC && EDAC=y
287 help
288 Support for error detection and correction on the Freescale
289 MPC8349, MPC8560, MPC8540, MPC8548, T4240
290
291config EDAC_LAYERSCAPE
292 tristate "Freescale Layerscape DDR"
293 depends on ARCH_LAYERSCAPE || SOC_LS1021A
294 help
295 Support for error detection and correction on Freescale memory
296 controllers on Layerscape SoCs.
297
298config EDAC_PASEMI
299 tristate "PA Semi PWRficient"
300 depends on PPC_PASEMI && PCI
301 help
302 Support for error detection and correction on PA Semi
303 PWRficient.
304
305config EDAC_CELL
306 tristate "Cell Broadband Engine memory controller"
307 depends on PPC_CELL_COMMON
308 help
309 Support for error detection and correction on the
310 Cell Broadband Engine internal memory controller
311 on platform without a hypervisor
312
313config EDAC_PPC4XX
314 tristate "PPC4xx IBM DDR2 Memory Controller"
315 depends on 4xx
316 help
317 This enables support for EDAC on the ECC memory used
318 with the IBM DDR2 memory controller found in various
319 PowerPC 4xx embedded processors such as the 405EX[r],
320 440SP, 440SPe, 460EX, 460GT and 460SX.
321
322config EDAC_AMD8131
323 tristate "AMD8131 HyperTransport PCI-X Tunnel"
324 depends on PCI && PPC_MAPLE
325 help
326 Support for error detection and correction on the
327 AMD8131 HyperTransport PCI-X Tunnel chip.
328 Note, add more Kconfig dependency if it's adopted
329 on some machine other than Maple.
330
331config EDAC_AMD8111
332 tristate "AMD8111 HyperTransport I/O Hub"
333 depends on PCI && PPC_MAPLE
334 help
335 Support for error detection and correction on the
336 AMD8111 HyperTransport I/O Hub chip.
337 Note, add more Kconfig dependency if it's adopted
338 on some machine other than Maple.
339
340config EDAC_CPC925
341 tristate "IBM CPC925 Memory Controller (PPC970FX)"
342 depends on PPC64
343 help
344 Support for error detection and correction on the
345 IBM CPC925 Bridge and Memory Controller, which is
346 a companion chip to the PowerPC 970 family of
347 processors.
348
349config EDAC_HIGHBANK_MC
350 tristate "Highbank Memory Controller"
351 depends on ARCH_HIGHBANK
352 help
353 Support for error detection and correction on the
354 Calxeda Highbank memory controller.
355
356config EDAC_HIGHBANK_L2
357 tristate "Highbank L2 Cache"
358 depends on ARCH_HIGHBANK
359 help
360 Support for error detection and correction on the
361 Calxeda Highbank memory controller.
362
363config EDAC_OCTEON_PC
364 tristate "Cavium Octeon Primary Caches"
365 depends on CPU_CAVIUM_OCTEON
366 help
367 Support for error detection and correction on the primary caches of
368 the cnMIPS cores of Cavium Octeon family SOCs.
369
370config EDAC_OCTEON_L2C
371 tristate "Cavium Octeon Secondary Caches (L2C)"
372 depends on CAVIUM_OCTEON_SOC
373 help
374 Support for error detection and correction on the
375 Cavium Octeon family of SOCs.
376
377config EDAC_OCTEON_LMC
378 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
379 depends on CAVIUM_OCTEON_SOC
380 help
381 Support for error detection and correction on the
382 Cavium Octeon family of SOCs.
383
384config EDAC_OCTEON_PCI
385 tristate "Cavium Octeon PCI Controller"
386 depends on PCI && CAVIUM_OCTEON_SOC
387 help
388 Support for error detection and correction on the
389 Cavium Octeon family of SOCs.
390
391config EDAC_THUNDERX
392 tristate "Cavium ThunderX EDAC"
393 depends on ARM64
394 depends on PCI
395 help
396 Support for error detection and correction on the
397 Cavium ThunderX memory controllers (LMC), Cache
398 Coherent Processor Interconnect (CCPI) and L2 cache
399 blocks (TAD, CBC, MCI).
400
401config EDAC_ALTERA
402 bool "Altera SOCFPGA ECC"
403 depends on EDAC=y && ARCH_INTEL_SOCFPGA
404 help
405 Support for error detection and correction on the
406 Altera SOCs. This is the global enable for the
407 various Altera peripherals.
408
409config EDAC_ALTERA_SDRAM
410 bool "Altera SDRAM ECC"
411 depends on EDAC_ALTERA=y
412 help
413 Support for error detection and correction on the
414 Altera SDRAM Memory for Altera SoCs. Note that the
415 preloader must initialize the SDRAM before loading
416 the kernel.
417
418config EDAC_ALTERA_L2C
419 bool "Altera L2 Cache ECC"
420 depends on EDAC_ALTERA=y && CACHE_L2X0
421 help
422 Support for error detection and correction on the
423 Altera L2 cache Memory for Altera SoCs. This option
424 requires L2 cache.
425
426config EDAC_ALTERA_OCRAM
427 bool "Altera On-Chip RAM ECC"
428 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
429 help
430 Support for error detection and correction on the
431 Altera On-Chip RAM Memory for Altera SoCs.
432
433config EDAC_ALTERA_ETHERNET
434 bool "Altera Ethernet FIFO ECC"
435 depends on EDAC_ALTERA=y
436 help
437 Support for error detection and correction on the
438 Altera Ethernet FIFO Memory for Altera SoCs.
439
440config EDAC_ALTERA_NAND
441 bool "Altera NAND FIFO ECC"
442 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
443 help
444 Support for error detection and correction on the
445 Altera NAND FIFO Memory for Altera SoCs.
446
447config EDAC_ALTERA_DMA
448 bool "Altera DMA FIFO ECC"
449 depends on EDAC_ALTERA=y && PL330_DMA=y
450 help
451 Support for error detection and correction on the
452 Altera DMA FIFO Memory for Altera SoCs.
453
454config EDAC_ALTERA_USB
455 bool "Altera USB FIFO ECC"
456 depends on EDAC_ALTERA=y && USB_DWC2
457 help
458 Support for error detection and correction on the
459 Altera USB FIFO Memory for Altera SoCs.
460
461config EDAC_ALTERA_QSPI
462 bool "Altera QSPI FIFO ECC"
463 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
464 help
465 Support for error detection and correction on the
466 Altera QSPI FIFO Memory for Altera SoCs.
467
468config EDAC_ALTERA_SDMMC
469 bool "Altera SDMMC FIFO ECC"
470 depends on EDAC_ALTERA=y && MMC_DW
471 help
472 Support for error detection and correction on the
473 Altera SDMMC FIFO Memory for Altera SoCs.
474
475config EDAC_SIFIVE
476 bool "Sifive platform EDAC driver"
477 depends on EDAC=y && SIFIVE_CCACHE
478 help
479 Support for error detection and correction on the SiFive SoCs.
480
481config EDAC_ARMADA_XP
482 bool "Marvell Armada XP DDR and L2 Cache ECC"
483 depends on MACH_MVEBU_V7
484 help
485 Support for error correction and detection on the Marvell Aramada XP
486 DDR RAM and L2 cache controllers.
487
488config EDAC_SYNOPSYS
489 tristate "Synopsys DDR Memory Controller"
490 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC
491 help
492 Support for error detection and correction on the Synopsys DDR
493 memory controller.
494
495config EDAC_XGENE
496 tristate "APM X-Gene SoC"
497 depends on (ARM64 || COMPILE_TEST)
498 help
499 Support for error detection and correction on the
500 APM X-Gene family of SOCs.
501
502config EDAC_TI
503 tristate "Texas Instruments DDR3 ECC Controller"
504 depends on ARCH_KEYSTONE || SOC_DRA7XX
505 help
506 Support for error detection and correction on the TI SoCs.
507
508config EDAC_QCOM
509 tristate "QCOM EDAC Controller"
510 depends on ARCH_QCOM && QCOM_LLCC
511 help
512 Support for error detection and correction on the
513 Qualcomm Technologies, Inc. SoCs.
514
515 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
516 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
517 of Tag RAM and Data RAM.
518
519 For debugging issues having to do with stability and overall system
520 health, you should probably say 'Y' here.
521
522config EDAC_ASPEED
523 tristate "Aspeed AST BMC SoC"
524 depends on ARCH_ASPEED
525 help
526 Support for error detection and correction on the Aspeed AST BMC SoC.
527
528 First, ECC must be configured in the bootloader. Then, this driver
529 will expose error counters via the EDAC kernel framework.
530
531config EDAC_BLUEFIELD
532 tristate "Mellanox BlueField Memory ECC"
533 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
534 help
535 Support for error detection and correction on the
536 Mellanox BlueField SoCs.
537
538config EDAC_DMC520
539 tristate "ARM DMC-520 ECC"
540 depends on ARM64
541 help
542 Support for error detection and correction on the
543 SoCs with ARM DMC-520 DRAM controller.
544
545endif # EDAC