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1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
3#include <linux/debugfs.h>
4#include <linux/device.h>
5#include <linux/module.h>
6#include <linux/pci.h>
7
8#include "cxlmem.h"
9#include "cxlpci.h"
10
11/**
12 * DOC: cxl mem
13 *
14 * CXL memory endpoint devices and switches are CXL capable devices that are
15 * participating in CXL.mem protocol. Their functionality builds on top of the
16 * CXL.io protocol that allows enumerating and configuring components via
17 * standard PCI mechanisms.
18 *
19 * The cxl_mem driver owns kicking off the enumeration of this CXL.mem
20 * capability. With the detection of a CXL capable endpoint, the driver will
21 * walk up to find the platform specific port it is connected to, and determine
22 * if there are intervening switches in the path. If there are switches, a
23 * secondary action is to enumerate those (implemented in cxl_core). Finally the
24 * cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use
25 * in higher level operations.
26 */
27
28static void enable_suspend(void *data)
29{
30 cxl_mem_active_dec();
31}
32
33static void remove_debugfs(void *dentry)
34{
35 debugfs_remove_recursive(dentry);
36}
37
38static int cxl_mem_dpa_show(struct seq_file *file, void *data)
39{
40 struct device *dev = file->private;
41 struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
42
43 cxl_dpa_debug(file, cxlmd->cxlds);
44
45 return 0;
46}
47
48static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
49 struct cxl_dport *parent_dport)
50{
51 struct cxl_port *parent_port = parent_dport->port;
52 struct cxl_port *endpoint, *iter, *down;
53 int rc;
54
55 /*
56 * Now that the path to the root is established record all the
57 * intervening ports in the chain.
58 */
59 for (iter = parent_port, down = NULL; !is_cxl_root(iter);
60 down = iter, iter = to_cxl_port(iter->dev.parent)) {
61 struct cxl_ep *ep;
62
63 ep = cxl_ep_load(iter, cxlmd);
64 ep->next = down;
65 }
66
67 /* Note: endpoint port component registers are derived from @cxlds */
68 endpoint = devm_cxl_add_port(host, &cxlmd->dev, CXL_RESOURCE_NONE,
69 parent_dport);
70 if (IS_ERR(endpoint))
71 return PTR_ERR(endpoint);
72
73 rc = cxl_endpoint_autoremove(cxlmd, endpoint);
74 if (rc)
75 return rc;
76
77 if (!endpoint->dev.driver) {
78 dev_err(&cxlmd->dev, "%s failed probe\n",
79 dev_name(&endpoint->dev));
80 return -ENXIO;
81 }
82
83 return 0;
84}
85
86static int cxl_debugfs_poison_inject(void *data, u64 dpa)
87{
88 struct cxl_memdev *cxlmd = data;
89
90 return cxl_inject_poison(cxlmd, dpa);
91}
92
93DEFINE_DEBUGFS_ATTRIBUTE(cxl_poison_inject_fops, NULL,
94 cxl_debugfs_poison_inject, "%llx\n");
95
96static int cxl_debugfs_poison_clear(void *data, u64 dpa)
97{
98 struct cxl_memdev *cxlmd = data;
99
100 return cxl_clear_poison(cxlmd, dpa);
101}
102
103DEFINE_DEBUGFS_ATTRIBUTE(cxl_poison_clear_fops, NULL,
104 cxl_debugfs_poison_clear, "%llx\n");
105
106static int cxl_mem_probe(struct device *dev)
107{
108 struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
109 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
110 struct cxl_dev_state *cxlds = cxlmd->cxlds;
111 struct device *endpoint_parent;
112 struct cxl_dport *dport;
113 struct dentry *dentry;
114 int rc;
115
116 if (!cxlds->media_ready)
117 return -EBUSY;
118
119 /*
120 * Someone is trying to reattach this device after it lost its port
121 * connection (an endpoint port previously registered by this memdev was
122 * disabled). This racy check is ok because if the port is still gone,
123 * no harm done, and if the port hierarchy comes back it will re-trigger
124 * this probe. Port rescan and memdev detach work share the same
125 * single-threaded workqueue.
126 */
127 if (work_pending(&cxlmd->detach_work))
128 return -EBUSY;
129
130 dentry = cxl_debugfs_create_dir(dev_name(dev));
131 debugfs_create_devm_seqfile(dev, "dpamem", dentry, cxl_mem_dpa_show);
132
133 if (test_bit(CXL_POISON_ENABLED_INJECT, mds->poison.enabled_cmds))
134 debugfs_create_file("inject_poison", 0200, dentry, cxlmd,
135 &cxl_poison_inject_fops);
136 if (test_bit(CXL_POISON_ENABLED_CLEAR, mds->poison.enabled_cmds))
137 debugfs_create_file("clear_poison", 0200, dentry, cxlmd,
138 &cxl_poison_clear_fops);
139
140 rc = devm_add_action_or_reset(dev, remove_debugfs, dentry);
141 if (rc)
142 return rc;
143
144 rc = devm_cxl_enumerate_ports(cxlmd);
145 if (rc)
146 return rc;
147
148 struct cxl_port *parent_port __free(put_cxl_port) =
149 cxl_mem_find_port(cxlmd, &dport);
150 if (!parent_port) {
151 dev_err(dev, "CXL port topology not found\n");
152 return -ENXIO;
153 }
154
155 if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM)) {
156 rc = devm_cxl_add_nvdimm(parent_port, cxlmd);
157 if (rc) {
158 if (rc == -ENODEV)
159 dev_info(dev, "PMEM disabled by platform\n");
160 return rc;
161 }
162 }
163
164 if (dport->rch)
165 endpoint_parent = parent_port->uport_dev;
166 else
167 endpoint_parent = &parent_port->dev;
168
169 cxl_dport_init_ras_reporting(dport, dev);
170
171 scoped_guard(device, endpoint_parent) {
172 if (!endpoint_parent->driver) {
173 dev_err(dev, "CXL port topology %s not enabled\n",
174 dev_name(endpoint_parent));
175 return -ENXIO;
176 }
177
178 rc = devm_cxl_add_endpoint(endpoint_parent, cxlmd, dport);
179 if (rc)
180 return rc;
181 }
182
183 /*
184 * The kernel may be operating out of CXL memory on this device,
185 * there is no spec defined way to determine whether this device
186 * preserves contents over suspend, and there is no simple way
187 * to arrange for the suspend image to avoid CXL memory which
188 * would setup a circular dependency between PCI resume and save
189 * state restoration.
190 *
191 * TODO: support suspend when all the regions this device is
192 * hosting are locked and covered by the system address map,
193 * i.e. platform firmware owns restoring the HDM configuration
194 * that it locked.
195 */
196 cxl_mem_active_inc();
197 return devm_add_action_or_reset(dev, enable_suspend, NULL);
198}
199
200static ssize_t trigger_poison_list_store(struct device *dev,
201 struct device_attribute *attr,
202 const char *buf, size_t len)
203{
204 bool trigger;
205 int rc;
206
207 if (kstrtobool(buf, &trigger) || !trigger)
208 return -EINVAL;
209
210 rc = cxl_trigger_poison_list(to_cxl_memdev(dev));
211
212 return rc ? rc : len;
213}
214static DEVICE_ATTR_WO(trigger_poison_list);
215
216static umode_t cxl_mem_visible(struct kobject *kobj, struct attribute *a, int n)
217{
218 struct device *dev = kobj_to_dev(kobj);
219 struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
220 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
221
222 if (a == &dev_attr_trigger_poison_list.attr)
223 if (!test_bit(CXL_POISON_ENABLED_LIST,
224 mds->poison.enabled_cmds))
225 return 0;
226
227 return a->mode;
228}
229
230static struct attribute *cxl_mem_attrs[] = {
231 &dev_attr_trigger_poison_list.attr,
232 NULL
233};
234
235static struct attribute_group cxl_mem_group = {
236 .attrs = cxl_mem_attrs,
237 .is_visible = cxl_mem_visible,
238};
239
240__ATTRIBUTE_GROUPS(cxl_mem);
241
242static struct cxl_driver cxl_mem_driver = {
243 .name = "cxl_mem",
244 .probe = cxl_mem_probe,
245 .id = CXL_DEVICE_MEMORY_EXPANDER,
246 .drv = {
247 .dev_groups = cxl_mem_groups,
248 },
249};
250
251module_cxl_driver(cxl_mem_driver);
252
253MODULE_DESCRIPTION("CXL: Memory Expansion");
254MODULE_LICENSE("GPL v2");
255MODULE_IMPORT_NS("CXL");
256MODULE_ALIAS_CXL(CXL_DEVICE_MEMORY_EXPANDER);
257/*
258 * create_endpoint() wants to validate port driver attach immediately after
259 * endpoint registration.
260 */
261MODULE_SOFTDEP("pre: cxl_port");
1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
3#include <linux/debugfs.h>
4#include <linux/device.h>
5#include <linux/module.h>
6#include <linux/pci.h>
7
8#include "cxlmem.h"
9#include "cxlpci.h"
10
11/**
12 * DOC: cxl mem
13 *
14 * CXL memory endpoint devices and switches are CXL capable devices that are
15 * participating in CXL.mem protocol. Their functionality builds on top of the
16 * CXL.io protocol that allows enumerating and configuring components via
17 * standard PCI mechanisms.
18 *
19 * The cxl_mem driver owns kicking off the enumeration of this CXL.mem
20 * capability. With the detection of a CXL capable endpoint, the driver will
21 * walk up to find the platform specific port it is connected to, and determine
22 * if there are intervening switches in the path. If there are switches, a
23 * secondary action is to enumerate those (implemented in cxl_core). Finally the
24 * cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use
25 * in higher level operations.
26 */
27
28static void enable_suspend(void *data)
29{
30 cxl_mem_active_dec();
31}
32
33static void remove_debugfs(void *dentry)
34{
35 debugfs_remove_recursive(dentry);
36}
37
38static int cxl_mem_dpa_show(struct seq_file *file, void *data)
39{
40 struct device *dev = file->private;
41 struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
42
43 cxl_dpa_debug(file, cxlmd->cxlds);
44
45 return 0;
46}
47
48static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
49 struct cxl_dport *parent_dport)
50{
51 struct cxl_port *parent_port = parent_dport->port;
52 struct cxl_dev_state *cxlds = cxlmd->cxlds;
53 struct cxl_port *endpoint, *iter, *down;
54 resource_size_t component_reg_phys;
55 int rc;
56
57 /*
58 * Now that the path to the root is established record all the
59 * intervening ports in the chain.
60 */
61 for (iter = parent_port, down = NULL; !is_cxl_root(iter);
62 down = iter, iter = to_cxl_port(iter->dev.parent)) {
63 struct cxl_ep *ep;
64
65 ep = cxl_ep_load(iter, cxlmd);
66 ep->next = down;
67 }
68
69 /*
70 * The component registers for an RCD might come from the
71 * host-bridge RCRB if they are not already mapped via the
72 * typical register locator mechanism.
73 */
74 if (parent_dport->rch && cxlds->component_reg_phys == CXL_RESOURCE_NONE)
75 component_reg_phys = cxl_rcrb_to_component(
76 &cxlmd->dev, parent_dport->rcrb, CXL_RCRB_UPSTREAM);
77 else
78 component_reg_phys = cxlds->component_reg_phys;
79 endpoint = devm_cxl_add_port(host, &cxlmd->dev, component_reg_phys,
80 parent_dport);
81 if (IS_ERR(endpoint))
82 return PTR_ERR(endpoint);
83
84 rc = cxl_endpoint_autoremove(cxlmd, endpoint);
85 if (rc)
86 return rc;
87
88 if (!endpoint->dev.driver) {
89 dev_err(&cxlmd->dev, "%s failed probe\n",
90 dev_name(&endpoint->dev));
91 return -ENXIO;
92 }
93
94 return 0;
95}
96
97static int cxl_mem_probe(struct device *dev)
98{
99 struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
100 struct cxl_dev_state *cxlds = cxlmd->cxlds;
101 struct device *endpoint_parent;
102 struct cxl_port *parent_port;
103 struct cxl_dport *dport;
104 struct dentry *dentry;
105 int rc;
106
107 /*
108 * Someone is trying to reattach this device after it lost its port
109 * connection (an endpoint port previously registered by this memdev was
110 * disabled). This racy check is ok because if the port is still gone,
111 * no harm done, and if the port hierarchy comes back it will re-trigger
112 * this probe. Port rescan and memdev detach work share the same
113 * single-threaded workqueue.
114 */
115 if (work_pending(&cxlmd->detach_work))
116 return -EBUSY;
117
118 dentry = cxl_debugfs_create_dir(dev_name(dev));
119 debugfs_create_devm_seqfile(dev, "dpamem", dentry, cxl_mem_dpa_show);
120 rc = devm_add_action_or_reset(dev, remove_debugfs, dentry);
121 if (rc)
122 return rc;
123
124 rc = devm_cxl_enumerate_ports(cxlmd);
125 if (rc)
126 return rc;
127
128 parent_port = cxl_mem_find_port(cxlmd, &dport);
129 if (!parent_port) {
130 dev_err(dev, "CXL port topology not found\n");
131 return -ENXIO;
132 }
133
134 if (dport->rch)
135 endpoint_parent = parent_port->uport;
136 else
137 endpoint_parent = &parent_port->dev;
138
139 device_lock(endpoint_parent);
140 if (!endpoint_parent->driver) {
141 dev_err(dev, "CXL port topology %s not enabled\n",
142 dev_name(endpoint_parent));
143 rc = -ENXIO;
144 goto unlock;
145 }
146
147 rc = devm_cxl_add_endpoint(endpoint_parent, cxlmd, dport);
148unlock:
149 device_unlock(endpoint_parent);
150 put_device(&parent_port->dev);
151 if (rc)
152 return rc;
153
154 if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM)) {
155 rc = devm_cxl_add_nvdimm(cxlmd);
156 if (rc == -ENODEV)
157 dev_info(dev, "PMEM disabled by platform\n");
158 else
159 return rc;
160 }
161
162 /*
163 * The kernel may be operating out of CXL memory on this device,
164 * there is no spec defined way to determine whether this device
165 * preserves contents over suspend, and there is no simple way
166 * to arrange for the suspend image to avoid CXL memory which
167 * would setup a circular dependency between PCI resume and save
168 * state restoration.
169 *
170 * TODO: support suspend when all the regions this device is
171 * hosting are locked and covered by the system address map,
172 * i.e. platform firmware owns restoring the HDM configuration
173 * that it locked.
174 */
175 cxl_mem_active_inc();
176 return devm_add_action_or_reset(dev, enable_suspend, NULL);
177}
178
179static struct cxl_driver cxl_mem_driver = {
180 .name = "cxl_mem",
181 .probe = cxl_mem_probe,
182 .id = CXL_DEVICE_MEMORY_EXPANDER,
183};
184
185module_cxl_driver(cxl_mem_driver);
186
187MODULE_LICENSE("GPL v2");
188MODULE_IMPORT_NS(CXL);
189MODULE_ALIAS_CXL(CXL_DEVICE_MEMORY_EXPANDER);
190/*
191 * create_endpoint() wants to validate port driver attach immediately after
192 * endpoint registration.
193 */
194MODULE_SOFTDEP("pre: cxl_port");