1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Device Tree for Klondike (APM8018X) board.
  4 *
  5 * Copyright (c) 2010, Applied Micro Circuits Corporation
  6 * Author: Tanmay Inamdar <tinamdar@apm.com>
  7 */
  8
  9/dts-v1/;
 10
 11/ {
 12	#address-cells = <1>;
 13	#size-cells = <1>;
 14	model = "apm,klondike";
 15	compatible = "apm,klondike";
 16	dcr-parent = <&{/cpus/cpu@0}>;
 17
 18	aliases {
 19		ethernet0 = &EMAC0;
 20		ethernet1 = &EMAC1;
 21	};
 22
 23	cpus {
 24		#address-cells = <1>;
 25		#size-cells = <0>;
 26
 27		cpu@0 {
 28			device_type = "cpu";
 29			model = "PowerPC,apm8018x";
 30			reg = <0x00000000>;
 31			clock-frequency = <300000000>; /* Filled in by U-Boot */
 32			timebase-frequency = <300000000>; /* Filled in by U-Boot */
 33			i-cache-line-size = <32>;
 34			d-cache-line-size = <32>;
 35			i-cache-size = <16384>; /* 16 kB */
 36			d-cache-size = <16384>; /* 16 kB */
 37			dcr-controller;
 38			dcr-access-method = "native";
 39		};
 40	};
 41
 42	memory {
 43		device_type = "memory";
 44		reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */
 45	};
 46
 47	UIC0: interrupt-controller {
 48		compatible = "ibm,uic";
 49		interrupt-controller;
 50		cell-index = <0>;
 51		dcr-reg = <0x0c0 0x010>;
 52		#address-cells = <0>;
 53		#size-cells = <0>;
 54		#interrupt-cells = <2>;
 55	};
 56
 57	UIC1: interrupt-controller1 {
 58		compatible = "ibm,uic";
 59		interrupt-controller;
 60		cell-index = <1>;
 61		dcr-reg = <0x0d0 0x010>;
 62		#address-cells = <0>;
 63		#size-cells = <0>;
 64		#interrupt-cells = <2>;
 65		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
 66		interrupt-parent = <&UIC0>;
 67	};
 68
 69	UIC2: interrupt-controller2 {
 70		compatible = "ibm,uic";
 71		interrupt-controller;
 72		cell-index = <2>;
 73		dcr-reg = <0x0e0 0x010>;
 74		#address-cells = <0>;
 75		#size-cells = <0>;
 76		#interrupt-cells = <2>;
 77		interrupts = <0x0a 0x4 0x0b 0x4>; /* cascade */
 78		interrupt-parent = <&UIC0>;
 79	};
 80
 81	UIC3: interrupt-controller3 {
 82		compatible = "ibm,uic";
 83		interrupt-controller;
 84		cell-index = <3>;
 85		dcr-reg = <0x0f0 0x010>;
 86		#address-cells = <0>;
 87		#size-cells = <0>;
 88		#interrupt-cells = <2>;
 89		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
 90		interrupt-parent = <&UIC0>;
 91	};
 92
 93	plb {
 94		compatible = "ibm,plb4";
 95		#address-cells = <1>;
 96		#size-cells = <1>;
 97		ranges;
 98		clock-frequency = <0>; /* Filled in by U-Boot */
 99
100		SDRAM0: memory-controller {
101			compatible = "ibm,sdram-apm8018x";
102			dcr-reg = <0x010 0x002>;
103		};
104
105		MAL0: mcmal {
106			compatible = "ibm,mcmal2";
107			dcr-reg = <0x180 0x062>;
108			num-tx-chans = <2>;
109			num-rx-chans = <16>;
110			#address-cells = <0>;
111			#size-cells = <0>;
112			interrupt-parent = <&UIC1>;
113			interrupts = </*TXEOB*/   0x6 0x4
114					/*RXEOB*/ 0x7 0x4
115					/*SERR*/  0x1 0x4
116					/*TXDE*/  0x2 0x4
117					/*RXDE*/  0x3 0x4>;
118		};
119
120		POB0: opb {
121			compatible = "ibm,opb";
122			#address-cells = <1>;
123			#size-cells = <1>;
124			ranges = <0x20000000 0x20000000 0x30000000
125				  0x50000000 0x50000000 0x10000000
126				  0x60000000 0x60000000 0x10000000
127				  0xFE000000 0xFE000000 0x00010000>;
128			dcr-reg = <0x100 0x020>;
129			clock-frequency = <300000000>; /* Filled in by U-Boot */
130
131			RGMII0: emac-rgmii@400a2000 {
132				compatible = "ibm,rgmii";
133				reg = <0x400a2000 0x00000010>;
134				has-mdio;
135			};
136
137			TAH0: emac-tah@400a3000 {
138				compatible = "ibm,tah";
139				reg = <0x400a3000 0x100>;
140			};
141
142			TAH1: emac-tah@400a4000 {
143				compatible = "ibm,tah";
144				reg = <0x400a4000 0x100>;
145			};
146
147			EMAC0: ethernet@400a0000 {
148				compatible = "ibm,emac4", "ibm-emac4sync";
149				interrupt-parent = <&EMAC0>;
150				interrupts = <0x0>;
151				#interrupt-cells = <1>;
152				#address-cells = <0>;
153				#size-cells = <0>;
154				interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4>;
155				reg = <0x400a0000 0x00000100>;
156				local-mac-address = [000000000000]; /* Filled in by U-Boot */
157				mal-device = <&MAL0>;
158				mal-tx-channel = <0x0>;
159				mal-rx-channel = <0x0>;
160				cell-index = <0>;
161				max-frame-size = <9000>;
162				rx-fifo-size = <4096>;
163				tx-fifo-size = <2048>;
164				phy-mode = "rgmii";
165				phy-address = <0x2>;
166				turbo = "no";
167				phy-map = <0x00000000>;
168				rgmii-device = <&RGMII0>;
169				rgmii-channel = <0>;
170				tah-device = <&TAH0>;
171				tah-channel = <0>;
172				has-inverted-stacr-oc;
173				has-new-stacr-staopc;
174			};
175
176			EMAC1: ethernet@400a1000 {
177				compatible = "ibm,emac4", "ibm-emac4sync";
178				status = "disabled";
179				interrupt-parent = <&EMAC1>;
180				interrupts = <0x0>;
181				#interrupt-cells = <1>;
182				#address-cells = <0>;
183				#size-cells = <0>;
184				interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4>;
185				reg = <0x400a1000 0x00000100>;
186				local-mac-address = [000000000000]; /* Filled in by U-Boot */
187				mal-device = <&MAL0>;
188				mal-tx-channel = <1>;
189				mal-rx-channel = <8>;
190				cell-index = <1>;
191				max-frame-size = <9000>;
192				rx-fifo-size = <4096>;
193				tx-fifo-size = <2048>;
194				phy-mode = "rgmii";
195				phy-address = <0x3>;
196				turbo = "no";
197				phy-map = <0x00000000>;
198				rgmii-device = <&RGMII0>;
199				rgmii-channel = <1>;
200				tah-device = <&TAH1>;
201				tah-channel = <0>;
202				has-inverted-stacr-oc;
203				has-new-stacr-staopc;
204				mdio-device = <&EMAC0>;
205			};
206		};
207	};
208
209	chosen {
210		stdout-path = "/plb/opb/serial@50001000";
211	};
212};