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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
4 *
5 * Copyright (C) 2013, Applied Micro Circuits Corporation
6 */
7
8/ {
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 cpus {
15 #address-cells = <2>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 device_type = "cpu";
20 compatible = "apm,potenza";
21 reg = <0x0 0x000>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
24 next-level-cache = <&xgene_L2_0>;
25 };
26 cpu@1 {
27 device_type = "cpu";
28 compatible = "apm,potenza";
29 reg = <0x0 0x001>;
30 enable-method = "spin-table";
31 cpu-release-addr = <0x1 0x0000fff8>;
32 next-level-cache = <&xgene_L2_0>;
33 };
34 cpu@100 {
35 device_type = "cpu";
36 compatible = "apm,potenza";
37 reg = <0x0 0x100>;
38 enable-method = "spin-table";
39 cpu-release-addr = <0x1 0x0000fff8>;
40 next-level-cache = <&xgene_L2_1>;
41 };
42 cpu@101 {
43 device_type = "cpu";
44 compatible = "apm,potenza";
45 reg = <0x0 0x101>;
46 enable-method = "spin-table";
47 cpu-release-addr = <0x1 0x0000fff8>;
48 next-level-cache = <&xgene_L2_1>;
49 };
50 cpu@200 {
51 device_type = "cpu";
52 compatible = "apm,potenza";
53 reg = <0x0 0x200>;
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
56 next-level-cache = <&xgene_L2_2>;
57 };
58 cpu@201 {
59 device_type = "cpu";
60 compatible = "apm,potenza";
61 reg = <0x0 0x201>;
62 enable-method = "spin-table";
63 cpu-release-addr = <0x1 0x0000fff8>;
64 next-level-cache = <&xgene_L2_2>;
65 };
66 cpu@300 {
67 device_type = "cpu";
68 compatible = "apm,potenza";
69 reg = <0x0 0x300>;
70 enable-method = "spin-table";
71 cpu-release-addr = <0x1 0x0000fff8>;
72 next-level-cache = <&xgene_L2_3>;
73 };
74 cpu@301 {
75 device_type = "cpu";
76 compatible = "apm,potenza";
77 reg = <0x0 0x301>;
78 enable-method = "spin-table";
79 cpu-release-addr = <0x1 0x0000fff8>;
80 next-level-cache = <&xgene_L2_3>;
81 };
82 xgene_L2_0: l2-cache-0 {
83 compatible = "cache";
84 cache-level = <2>;
85 cache-unified;
86 };
87 xgene_L2_1: l2-cache-1 {
88 compatible = "cache";
89 cache-level = <2>;
90 cache-unified;
91 };
92 xgene_L2_2: l2-cache-2 {
93 compatible = "cache";
94 cache-level = <2>;
95 cache-unified;
96 };
97 xgene_L2_3: l2-cache-3 {
98 compatible = "cache";
99 cache-level = <2>;
100 cache-unified;
101 };
102 };
103
104 gic: interrupt-controller@78010000 {
105 compatible = "arm,cortex-a15-gic";
106 #interrupt-cells = <3>;
107 interrupt-controller;
108 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
109 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
110 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
111 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
112 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
113 };
114
115 refclk: refclk {
116 compatible = "fixed-clock";
117 #clock-cells = <1>;
118 clock-frequency = <100000000>;
119 clock-output-names = "refclk";
120 };
121
122 timer {
123 compatible = "arm,armv8-timer";
124 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
125 <1 13 0xff08>, /* Non-secure Phys IRQ */
126 <1 14 0xff08>, /* Virt IRQ */
127 <1 15 0xff08>; /* Hyp IRQ */
128 clock-frequency = <50000000>;
129 };
130
131 pmu {
132 compatible = "apm,potenza-pmu";
133 interrupts = <1 12 0xff04>;
134 };
135
136 soc {
137 compatible = "simple-bus";
138 #address-cells = <2>;
139 #size-cells = <2>;
140 ranges;
141 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
142
143 clocks {
144 #address-cells = <2>;
145 #size-cells = <2>;
146 ranges;
147
148 pcppll: pcppll@17000100 {
149 compatible = "apm,xgene-pcppll-clock";
150 #clock-cells = <1>;
151 clocks = <&refclk 0>;
152 clock-names = "pcppll";
153 reg = <0x0 0x17000100 0x0 0x1000>;
154 clock-output-names = "pcppll";
155 type = <0>;
156 };
157
158 socpll: socpll@17000120 {
159 compatible = "apm,xgene-socpll-clock";
160 #clock-cells = <1>;
161 clocks = <&refclk 0>;
162 clock-names = "socpll";
163 reg = <0x0 0x17000120 0x0 0x1000>;
164 clock-output-names = "socpll";
165 type = <1>;
166 };
167
168 socplldiv2: socplldiv2 {
169 compatible = "fixed-factor-clock";
170 #clock-cells = <1>;
171 clocks = <&socpll 0>;
172 clock-names = "socplldiv2";
173 clock-mult = <1>;
174 clock-div = <2>;
175 clock-output-names = "socplldiv2";
176 };
177
178 ahbclk: ahbclk@17000000 {
179 compatible = "apm,xgene-device-clock";
180 #clock-cells = <1>;
181 clocks = <&socplldiv2 0>;
182 reg = <0x0 0x17000000 0x0 0x2000>;
183 reg-names = "div-reg";
184 divider-offset = <0x164>;
185 divider-width = <0x5>;
186 divider-shift = <0x0>;
187 clock-output-names = "ahbclk";
188 };
189
190 sdioclk: sdioclk@1f2ac000 {
191 compatible = "apm,xgene-device-clock";
192 #clock-cells = <1>;
193 clocks = <&socplldiv2 0>;
194 reg = <0x0 0x1f2ac000 0x0 0x1000
195 0x0 0x17000000 0x0 0x2000>;
196 reg-names = "csr-reg", "div-reg";
197 csr-offset = <0x0>;
198 csr-mask = <0x2>;
199 enable-offset = <0x8>;
200 enable-mask = <0x2>;
201 divider-offset = <0x178>;
202 divider-width = <0x8>;
203 divider-shift = <0x0>;
204 clock-output-names = "sdioclk";
205 };
206
207 ethclk: ethclk {
208 compatible = "apm,xgene-device-clock";
209 #clock-cells = <1>;
210 clocks = <&socplldiv2 0>;
211 clock-names = "ethclk";
212 reg = <0x0 0x17000000 0x0 0x1000>;
213 reg-names = "div-reg";
214 divider-offset = <0x238>;
215 divider-width = <0x9>;
216 divider-shift = <0x0>;
217 clock-output-names = "ethclk";
218 };
219
220 menetclk: menetclk {
221 compatible = "apm,xgene-device-clock";
222 #clock-cells = <1>;
223 clocks = <ðclk 0>;
224 reg = <0x0 0x1702c000 0x0 0x1000>;
225 reg-names = "csr-reg";
226 clock-output-names = "menetclk";
227 };
228
229 sge0clk: sge0clk@1f21c000 {
230 compatible = "apm,xgene-device-clock";
231 #clock-cells = <1>;
232 clocks = <&socplldiv2 0>;
233 reg = <0x0 0x1f21c000 0x0 0x1000>;
234 reg-names = "csr-reg";
235 csr-mask = <0xa>;
236 enable-mask = <0xf>;
237 clock-output-names = "sge0clk";
238 };
239
240 xge0clk: xge0clk@1f61c000 {
241 compatible = "apm,xgene-device-clock";
242 #clock-cells = <1>;
243 clocks = <&socplldiv2 0>;
244 reg = <0x0 0x1f61c000 0x0 0x1000>;
245 reg-names = "csr-reg";
246 csr-mask = <0x3>;
247 clock-output-names = "xge0clk";
248 };
249
250 xge1clk: xge1clk@1f62c000 {
251 compatible = "apm,xgene-device-clock";
252 status = "disabled";
253 #clock-cells = <1>;
254 clocks = <&socplldiv2 0>;
255 reg = <0x0 0x1f62c000 0x0 0x1000>;
256 reg-names = "csr-reg";
257 csr-mask = <0x3>;
258 clock-output-names = "xge1clk";
259 };
260
261 sataphy1clk: sataphy1clk@1f21c000 {
262 compatible = "apm,xgene-device-clock";
263 #clock-cells = <1>;
264 clocks = <&socplldiv2 0>;
265 reg = <0x0 0x1f21c000 0x0 0x1000>;
266 reg-names = "csr-reg";
267 clock-output-names = "sataphy1clk";
268 status = "disabled";
269 csr-offset = <0x4>;
270 csr-mask = <0x00>;
271 enable-offset = <0x0>;
272 enable-mask = <0x06>;
273 };
274
275 sataphy2clk: sataphy1clk@1f22c000 {
276 compatible = "apm,xgene-device-clock";
277 #clock-cells = <1>;
278 clocks = <&socplldiv2 0>;
279 reg = <0x0 0x1f22c000 0x0 0x1000>;
280 reg-names = "csr-reg";
281 clock-output-names = "sataphy2clk";
282 status = "okay";
283 csr-offset = <0x4>;
284 csr-mask = <0x3a>;
285 enable-offset = <0x0>;
286 enable-mask = <0x06>;
287 };
288
289 sataphy3clk: sataphy1clk@1f23c000 {
290 compatible = "apm,xgene-device-clock";
291 #clock-cells = <1>;
292 clocks = <&socplldiv2 0>;
293 reg = <0x0 0x1f23c000 0x0 0x1000>;
294 reg-names = "csr-reg";
295 clock-output-names = "sataphy3clk";
296 status = "okay";
297 csr-offset = <0x4>;
298 csr-mask = <0x3a>;
299 enable-offset = <0x0>;
300 enable-mask = <0x06>;
301 };
302
303 sata01clk: sata01clk@1f21c000 {
304 compatible = "apm,xgene-device-clock";
305 #clock-cells = <1>;
306 clocks = <&socplldiv2 0>;
307 reg = <0x0 0x1f21c000 0x0 0x1000>;
308 reg-names = "csr-reg";
309 clock-output-names = "sata01clk";
310 csr-offset = <0x4>;
311 csr-mask = <0x05>;
312 enable-offset = <0x0>;
313 enable-mask = <0x39>;
314 };
315
316 sata23clk: sata23clk@1f22c000 {
317 compatible = "apm,xgene-device-clock";
318 #clock-cells = <1>;
319 clocks = <&socplldiv2 0>;
320 reg = <0x0 0x1f22c000 0x0 0x1000>;
321 reg-names = "csr-reg";
322 clock-output-names = "sata23clk";
323 csr-offset = <0x4>;
324 csr-mask = <0x05>;
325 enable-offset = <0x0>;
326 enable-mask = <0x39>;
327 };
328
329 sata45clk: sata45clk@1f23c000 {
330 compatible = "apm,xgene-device-clock";
331 #clock-cells = <1>;
332 clocks = <&socplldiv2 0>;
333 reg = <0x0 0x1f23c000 0x0 0x1000>;
334 reg-names = "csr-reg";
335 clock-output-names = "sata45clk";
336 csr-offset = <0x4>;
337 csr-mask = <0x05>;
338 enable-offset = <0x0>;
339 enable-mask = <0x39>;
340 };
341
342 rtcclk: rtcclk@17000000 {
343 compatible = "apm,xgene-device-clock";
344 #clock-cells = <1>;
345 clocks = <&socplldiv2 0>;
346 reg = <0x0 0x17000000 0x0 0x2000>;
347 reg-names = "csr-reg";
348 csr-offset = <0xc>;
349 csr-mask = <0x2>;
350 enable-offset = <0x10>;
351 enable-mask = <0x2>;
352 clock-output-names = "rtcclk";
353 };
354
355 rngpkaclk: rngpkaclk@17000000 {
356 compatible = "apm,xgene-device-clock";
357 #clock-cells = <1>;
358 clocks = <&socplldiv2 0>;
359 reg = <0x0 0x17000000 0x0 0x2000>;
360 reg-names = "csr-reg";
361 csr-offset = <0xc>;
362 csr-mask = <0x10>;
363 enable-offset = <0x10>;
364 enable-mask = <0x10>;
365 clock-output-names = "rngpkaclk";
366 };
367
368 pcie0clk: pcie0clk@1f2bc000 {
369 status = "disabled";
370 compatible = "apm,xgene-device-clock";
371 #clock-cells = <1>;
372 clocks = <&socplldiv2 0>;
373 reg = <0x0 0x1f2bc000 0x0 0x1000>;
374 reg-names = "csr-reg";
375 clock-output-names = "pcie0clk";
376 };
377
378 pcie1clk: pcie1clk@1f2cc000 {
379 status = "disabled";
380 compatible = "apm,xgene-device-clock";
381 #clock-cells = <1>;
382 clocks = <&socplldiv2 0>;
383 reg = <0x0 0x1f2cc000 0x0 0x1000>;
384 reg-names = "csr-reg";
385 clock-output-names = "pcie1clk";
386 };
387
388 pcie2clk: pcie2clk@1f2dc000 {
389 status = "disabled";
390 compatible = "apm,xgene-device-clock";
391 #clock-cells = <1>;
392 clocks = <&socplldiv2 0>;
393 reg = <0x0 0x1f2dc000 0x0 0x1000>;
394 reg-names = "csr-reg";
395 clock-output-names = "pcie2clk";
396 };
397
398 pcie3clk: pcie3clk@1f50c000 {
399 status = "disabled";
400 compatible = "apm,xgene-device-clock";
401 #clock-cells = <1>;
402 clocks = <&socplldiv2 0>;
403 reg = <0x0 0x1f50c000 0x0 0x1000>;
404 reg-names = "csr-reg";
405 clock-output-names = "pcie3clk";
406 };
407
408 pcie4clk: pcie4clk@1f51c000 {
409 status = "disabled";
410 compatible = "apm,xgene-device-clock";
411 #clock-cells = <1>;
412 clocks = <&socplldiv2 0>;
413 reg = <0x0 0x1f51c000 0x0 0x1000>;
414 reg-names = "csr-reg";
415 clock-output-names = "pcie4clk";
416 };
417
418 dmaclk: dmaclk@1f27c000 {
419 compatible = "apm,xgene-device-clock";
420 #clock-cells = <1>;
421 clocks = <&socplldiv2 0>;
422 reg = <0x0 0x1f27c000 0x0 0x1000>;
423 reg-names = "csr-reg";
424 clock-output-names = "dmaclk";
425 };
426 };
427
428 msi: msi@79000000 {
429 compatible = "apm,xgene1-msi";
430 msi-controller;
431 reg = <0x00 0x79000000 0x0 0x900000>;
432 interrupts = < 0x0 0x10 0x4
433 0x0 0x11 0x4
434 0x0 0x12 0x4
435 0x0 0x13 0x4
436 0x0 0x14 0x4
437 0x0 0x15 0x4
438 0x0 0x16 0x4
439 0x0 0x17 0x4
440 0x0 0x18 0x4
441 0x0 0x19 0x4
442 0x0 0x1a 0x4
443 0x0 0x1b 0x4
444 0x0 0x1c 0x4
445 0x0 0x1d 0x4
446 0x0 0x1e 0x4
447 0x0 0x1f 0x4>;
448 };
449
450 scu: system-clk-controller@17000000 {
451 compatible = "apm,xgene-scu","syscon";
452 reg = <0x0 0x17000000 0x0 0x400>;
453 };
454
455 reboot: reboot@17000014 {
456 compatible = "syscon-reboot";
457 regmap = <&scu>;
458 offset = <0x14>;
459 mask = <0x1>;
460 };
461
462 csw: csw@7e200000 {
463 compatible = "apm,xgene-csw", "syscon";
464 reg = <0x0 0x7e200000 0x0 0x1000>;
465 };
466
467 mcba: mcba@7e700000 {
468 compatible = "apm,xgene-mcb", "syscon";
469 reg = <0x0 0x7e700000 0x0 0x1000>;
470 };
471
472 mcbb: mcbb@7e720000 {
473 compatible = "apm,xgene-mcb", "syscon";
474 reg = <0x0 0x7e720000 0x0 0x1000>;
475 };
476
477 efuse: efuse@1054a000 {
478 compatible = "apm,xgene-efuse", "syscon";
479 reg = <0x0 0x1054a000 0x0 0x20>;
480 };
481
482 rb: rb@7e000000 {
483 compatible = "apm,xgene-rb", "syscon";
484 reg = <0x0 0x7e000000 0x0 0x10>;
485 };
486
487 edac@78800000 {
488 compatible = "apm,xgene-edac";
489 #address-cells = <2>;
490 #size-cells = <2>;
491 ranges;
492 regmap-csw = <&csw>;
493 regmap-mcba = <&mcba>;
494 regmap-mcbb = <&mcbb>;
495 regmap-efuse = <&efuse>;
496 regmap-rb = <&rb>;
497 reg = <0x0 0x78800000 0x0 0x100>;
498 interrupts = <0x0 0x20 0x4>,
499 <0x0 0x21 0x4>,
500 <0x0 0x27 0x4>;
501
502 edacmc@7e800000 {
503 compatible = "apm,xgene-edac-mc";
504 reg = <0x0 0x7e800000 0x0 0x1000>;
505 memory-controller = <0>;
506 };
507
508 edacmc@7e840000 {
509 compatible = "apm,xgene-edac-mc";
510 reg = <0x0 0x7e840000 0x0 0x1000>;
511 memory-controller = <1>;
512 };
513
514 edacmc@7e880000 {
515 compatible = "apm,xgene-edac-mc";
516 reg = <0x0 0x7e880000 0x0 0x1000>;
517 memory-controller = <2>;
518 };
519
520 edacmc@7e8c0000 {
521 compatible = "apm,xgene-edac-mc";
522 reg = <0x0 0x7e8c0000 0x0 0x1000>;
523 memory-controller = <3>;
524 };
525
526 edacpmd@7c000000 {
527 compatible = "apm,xgene-edac-pmd";
528 reg = <0x0 0x7c000000 0x0 0x200000>;
529 pmd-controller = <0>;
530 };
531
532 edacpmd@7c200000 {
533 compatible = "apm,xgene-edac-pmd";
534 reg = <0x0 0x7c200000 0x0 0x200000>;
535 pmd-controller = <1>;
536 };
537
538 edacpmd@7c400000 {
539 compatible = "apm,xgene-edac-pmd";
540 reg = <0x0 0x7c400000 0x0 0x200000>;
541 pmd-controller = <2>;
542 };
543
544 edacpmd@7c600000 {
545 compatible = "apm,xgene-edac-pmd";
546 reg = <0x0 0x7c600000 0x0 0x200000>;
547 pmd-controller = <3>;
548 };
549
550 edacl3@7e600000 {
551 compatible = "apm,xgene-edac-l3";
552 reg = <0x0 0x7e600000 0x0 0x1000>;
553 };
554
555 edacsoc@7e930000 {
556 compatible = "apm,xgene-edac-soc-v1";
557 reg = <0x0 0x7e930000 0x0 0x1000>;
558 };
559 };
560
561 pmu: pmu@78810000 {
562 compatible = "apm,xgene-pmu-v2";
563 #address-cells = <2>;
564 #size-cells = <2>;
565 ranges;
566 regmap-csw = <&csw>;
567 regmap-mcba = <&mcba>;
568 regmap-mcbb = <&mcbb>;
569 reg = <0x0 0x78810000 0x0 0x1000>;
570 interrupts = <0x0 0x22 0x4>;
571
572 pmul3c@7e610000 {
573 compatible = "apm,xgene-pmu-l3c";
574 reg = <0x0 0x7e610000 0x0 0x1000>;
575 };
576
577 pmuiob@7e940000 {
578 compatible = "apm,xgene-pmu-iob";
579 reg = <0x0 0x7e940000 0x0 0x1000>;
580 };
581
582 pmucmcb@7e710000 {
583 compatible = "apm,xgene-pmu-mcb";
584 reg = <0x0 0x7e710000 0x0 0x1000>;
585 enable-bit-index = <0>;
586 };
587
588 pmucmcb@7e730000 {
589 compatible = "apm,xgene-pmu-mcb";
590 reg = <0x0 0x7e730000 0x0 0x1000>;
591 enable-bit-index = <1>;
592 };
593
594 pmucmc@7e810000 {
595 compatible = "apm,xgene-pmu-mc";
596 reg = <0x0 0x7e810000 0x0 0x1000>;
597 enable-bit-index = <0>;
598 };
599
600 pmucmc@7e850000 {
601 compatible = "apm,xgene-pmu-mc";
602 reg = <0x0 0x7e850000 0x0 0x1000>;
603 enable-bit-index = <1>;
604 };
605
606 pmucmc@7e890000 {
607 compatible = "apm,xgene-pmu-mc";
608 reg = <0x0 0x7e890000 0x0 0x1000>;
609 enable-bit-index = <2>;
610 };
611
612 pmucmc@7e8d0000 {
613 compatible = "apm,xgene-pmu-mc";
614 reg = <0x0 0x7e8d0000 0x0 0x1000>;
615 enable-bit-index = <3>;
616 };
617 };
618
619 pcie0: pcie@1f2b0000 {
620 status = "disabled";
621 device_type = "pci";
622 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
623 #interrupt-cells = <1>;
624 #size-cells = <2>;
625 #address-cells = <3>;
626 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
627 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
628 reg-names = "csr", "cfg";
629 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
630 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */
631 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
632 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
633 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
634 bus-range = <0x00 0xff>;
635 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
636 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
637 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
638 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
639 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
640 dma-coherent;
641 clocks = <&pcie0clk 0>;
642 msi-parent = <&msi>;
643 };
644
645 pcie1: pcie@1f2c0000 {
646 status = "disabled";
647 device_type = "pci";
648 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
649 #interrupt-cells = <1>;
650 #size-cells = <2>;
651 #address-cells = <3>;
652 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
653 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
654 reg-names = "csr", "cfg";
655 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
656 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */
657 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
658 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
659 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
660 bus-range = <0x00 0xff>;
661 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
662 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
663 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
664 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
665 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
666 dma-coherent;
667 clocks = <&pcie1clk 0>;
668 msi-parent = <&msi>;
669 };
670
671 pcie2: pcie@1f2d0000 {
672 status = "disabled";
673 device_type = "pci";
674 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
675 #interrupt-cells = <1>;
676 #size-cells = <2>;
677 #address-cells = <3>;
678 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
679 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
680 reg-names = "csr", "cfg";
681 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */
682 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */
683 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
684 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
685 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
686 bus-range = <0x00 0xff>;
687 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
688 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
689 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
690 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
691 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
692 dma-coherent;
693 clocks = <&pcie2clk 0>;
694 msi-parent = <&msi>;
695 };
696
697 pcie3: pcie@1f500000 {
698 status = "disabled";
699 device_type = "pci";
700 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
701 #interrupt-cells = <1>;
702 #size-cells = <2>;
703 #address-cells = <3>;
704 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
705 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
706 reg-names = "csr", "cfg";
707 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
708 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */
709 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
710 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
711 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
712 bus-range = <0x00 0xff>;
713 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
714 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
715 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
716 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
717 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
718 dma-coherent;
719 clocks = <&pcie3clk 0>;
720 msi-parent = <&msi>;
721 };
722
723 pcie4: pcie@1f510000 {
724 status = "disabled";
725 device_type = "pci";
726 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
727 #interrupt-cells = <1>;
728 #size-cells = <2>;
729 #address-cells = <3>;
730 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
731 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
732 reg-names = "csr", "cfg";
733 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
734 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */
735 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
736 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
737 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
738 bus-range = <0x00 0xff>;
739 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
740 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
741 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
742 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
743 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
744 dma-coherent;
745 clocks = <&pcie4clk 0>;
746 msi-parent = <&msi>;
747 };
748
749 mailbox: mailbox@10540000 {
750 compatible = "apm,xgene-slimpro-mbox";
751 reg = <0x0 0x10540000 0x0 0xa000>;
752 #mbox-cells = <1>;
753 interrupts = <0x0 0x0 0x4>,
754 <0x0 0x1 0x4>,
755 <0x0 0x2 0x4>,
756 <0x0 0x3 0x4>,
757 <0x0 0x4 0x4>,
758 <0x0 0x5 0x4>,
759 <0x0 0x6 0x4>,
760 <0x0 0x7 0x4>;
761 };
762
763 i2cslimpro {
764 compatible = "apm,xgene-slimpro-i2c";
765 mboxes = <&mailbox 0>;
766 };
767
768 hwmonslimpro {
769 compatible = "apm,xgene-slimpro-hwmon";
770 mboxes = <&mailbox 7>;
771 };
772
773 serial0: serial@1c020000 {
774 status = "disabled";
775 compatible = "ns16550a";
776 reg = <0 0x1c020000 0x0 0x1000>;
777 reg-shift = <2>;
778 clock-frequency = <10000000>; /* Updated by bootloader */
779 interrupt-parent = <&gic>;
780 interrupts = <0x0 0x4c 0x4>;
781 };
782
783 serial1: serial@1c021000 {
784 status = "disabled";
785 compatible = "ns16550a";
786 reg = <0 0x1c021000 0x0 0x1000>;
787 reg-shift = <2>;
788 clock-frequency = <10000000>; /* Updated by bootloader */
789 interrupt-parent = <&gic>;
790 interrupts = <0x0 0x4d 0x4>;
791 };
792
793 serial2: serial@1c022000 {
794 status = "disabled";
795 compatible = "ns16550a";
796 reg = <0 0x1c022000 0x0 0x1000>;
797 reg-shift = <2>;
798 clock-frequency = <10000000>; /* Updated by bootloader */
799 interrupt-parent = <&gic>;
800 interrupts = <0x0 0x4e 0x4>;
801 };
802
803 serial3: serial@1c023000 {
804 status = "disabled";
805 compatible = "ns16550a";
806 reg = <0 0x1c023000 0x0 0x1000>;
807 reg-shift = <2>;
808 clock-frequency = <10000000>; /* Updated by bootloader */
809 interrupt-parent = <&gic>;
810 interrupts = <0x0 0x4f 0x4>;
811 };
812
813 mmc0: mmc@1c000000 {
814 compatible = "arasan,sdhci-4.9a";
815 reg = <0x0 0x1c000000 0x0 0x100>;
816 interrupts = <0x0 0x49 0x4>;
817 dma-coherent;
818 no-1-8-v;
819 clock-names = "clk_xin", "clk_ahb";
820 clocks = <&sdioclk 0>, <&ahbclk 0>;
821 };
822
823 gfcgpio: gpio0@1701c000 {
824 compatible = "apm,xgene-gpio";
825 reg = <0x0 0x1701c000 0x0 0x40>;
826 gpio-controller;
827 #gpio-cells = <2>;
828 };
829
830 dwgpio: gpio@1c024000 {
831 compatible = "snps,dw-apb-gpio";
832 reg = <0x0 0x1c024000 0x0 0x1000>;
833 #address-cells = <1>;
834 #size-cells = <0>;
835
836 porta: gpio-controller@0 {
837 compatible = "snps,dw-apb-gpio-port";
838 gpio-controller;
839 #gpio-cells = <2>;
840 snps,nr-gpios = <32>;
841 reg = <0>;
842 };
843 };
844
845 i2c0: i2c@10512000 {
846 status = "disabled";
847 #address-cells = <1>;
848 #size-cells = <0>;
849 compatible = "snps,designware-i2c";
850 reg = <0x0 0x10512000 0x0 0x1000>;
851 interrupts = <0 0x44 0x4>;
852 #clock-cells = <1>;
853 clocks = <&ahbclk 0>;
854 };
855
856 phy1: phy@1f21a000 {
857 compatible = "apm,xgene-phy";
858 reg = <0x0 0x1f21a000 0x0 0x100>;
859 #phy-cells = <1>;
860 clocks = <&sataphy1clk 0>;
861 status = "disabled";
862 apm,tx-boost-gain = <30 30 30 30 30 30>;
863 apm,tx-eye-tuning = <2 10 10 2 10 10>;
864 };
865
866 phy2: phy@1f22a000 {
867 compatible = "apm,xgene-phy";
868 reg = <0x0 0x1f22a000 0x0 0x100>;
869 #phy-cells = <1>;
870 clocks = <&sataphy2clk 0>;
871 status = "okay";
872 apm,tx-boost-gain = <30 30 30 30 30 30>;
873 apm,tx-eye-tuning = <1 10 10 2 10 10>;
874 };
875
876 phy3: phy@1f23a000 {
877 compatible = "apm,xgene-phy";
878 reg = <0x0 0x1f23a000 0x0 0x100>;
879 #phy-cells = <1>;
880 clocks = <&sataphy3clk 0>;
881 status = "okay";
882 apm,tx-boost-gain = <31 31 31 31 31 31>;
883 apm,tx-eye-tuning = <2 10 10 2 10 10>;
884 };
885
886 sata1: sata@1a000000 {
887 compatible = "apm,xgene-ahci";
888 reg = <0x0 0x1a000000 0x0 0x1000>,
889 <0x0 0x1f210000 0x0 0x1000>,
890 <0x0 0x1f21d000 0x0 0x1000>,
891 <0x0 0x1f21e000 0x0 0x1000>,
892 <0x0 0x1f217000 0x0 0x1000>;
893 interrupts = <0x0 0x86 0x4>;
894 dma-coherent;
895 status = "disabled";
896 clocks = <&sata01clk 0>;
897 phys = <&phy1 0>;
898 phy-names = "sata-phy";
899 };
900
901 sata2: sata@1a400000 {
902 compatible = "apm,xgene-ahci";
903 reg = <0x0 0x1a400000 0x0 0x1000>,
904 <0x0 0x1f220000 0x0 0x1000>,
905 <0x0 0x1f22d000 0x0 0x1000>,
906 <0x0 0x1f22e000 0x0 0x1000>,
907 <0x0 0x1f227000 0x0 0x1000>;
908 interrupts = <0x0 0x87 0x4>;
909 dma-coherent;
910 status = "okay";
911 clocks = <&sata23clk 0>;
912 phys = <&phy2 0>;
913 phy-names = "sata-phy";
914 };
915
916 sata3: sata@1a800000 {
917 compatible = "apm,xgene-ahci";
918 reg = <0x0 0x1a800000 0x0 0x1000>,
919 <0x0 0x1f230000 0x0 0x1000>,
920 <0x0 0x1f23d000 0x0 0x1000>,
921 <0x0 0x1f23e000 0x0 0x1000>;
922 interrupts = <0x0 0x88 0x4>;
923 dma-coherent;
924 status = "okay";
925 clocks = <&sata45clk 0>;
926 phys = <&phy3 0>;
927 phy-names = "sata-phy";
928 };
929
930 /* Node-name might need to be coded as dwusb for backward compatibility */
931 usb0: usb@19000000 {
932 status = "disabled";
933 compatible = "snps,dwc3";
934 reg = <0x0 0x19000000 0x0 0x100000>;
935 interrupts = <0x0 0x89 0x4>;
936 dma-coherent;
937 dr_mode = "host";
938 };
939
940 usb1: usb@19800000 {
941 status = "disabled";
942 compatible = "snps,dwc3";
943 reg = <0x0 0x19800000 0x0 0x100000>;
944 interrupts = <0x0 0x8a 0x4>;
945 dma-coherent;
946 dr_mode = "host";
947 };
948
949 sbgpio: gpio@17001000 {
950 compatible = "apm,xgene-gpio-sb";
951 reg = <0x0 0x17001000 0x0 0x400>;
952 #gpio-cells = <2>;
953 gpio-controller;
954 interrupts = <0x0 0x28 0x1>,
955 <0x0 0x29 0x1>,
956 <0x0 0x2a 0x1>,
957 <0x0 0x2b 0x1>,
958 <0x0 0x2c 0x1>,
959 <0x0 0x2d 0x1>;
960 interrupt-parent = <&gic>;
961 #interrupt-cells = <2>;
962 interrupt-controller;
963 };
964
965 rtc: rtc@10510000 {
966 compatible = "apm,xgene-rtc";
967 reg = <0x0 0x10510000 0x0 0x400>;
968 interrupts = <0x0 0x46 0x4>;
969 #clock-cells = <1>;
970 clocks = <&rtcclk 0>;
971 };
972
973 mdio: mdio@17020000 {
974 compatible = "apm,xgene-mdio-rgmii";
975 #address-cells = <1>;
976 #size-cells = <0>;
977 reg = <0x0 0x17020000 0x0 0xd100>;
978 clocks = <&menetclk 0>;
979 };
980
981 menet: ethernet@17020000 {
982 compatible = "apm,xgene-enet";
983 status = "disabled";
984 reg = <0x0 0x17020000 0x0 0xd100>,
985 <0x0 0x17030000 0x0 0xc300>,
986 <0x0 0x10000000 0x0 0x200>;
987 reg-names = "enet_csr", "ring_csr", "ring_cmd";
988 interrupts = <0x0 0x3c 0x4>;
989 dma-coherent;
990 clocks = <&menetclk 0>;
991 /* mac address will be overwritten by the bootloader */
992 local-mac-address = [00 00 00 00 00 00];
993 phy-connection-type = "rgmii";
994 phy-handle = <&menetphy>,<&menet0phy>;
995 mdio {
996 compatible = "apm,xgene-mdio";
997 #address-cells = <1>;
998 #size-cells = <0>;
999 menetphy: ethernet-phy@3 {
1000 compatible = "ethernet-phy-id001c.c915";
1001 reg = <0x3>;
1002 };
1003
1004 };
1005 };
1006
1007 sgenet0: ethernet@1f210000 {
1008 compatible = "apm,xgene1-sgenet";
1009 status = "disabled";
1010 reg = <0x0 0x1f210000 0x0 0xd100>,
1011 <0x0 0x1f200000 0x0 0xc300>,
1012 <0x0 0x1b000000 0x0 0x200>;
1013 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1014 interrupts = <0x0 0xa0 0x4>,
1015 <0x0 0xa1 0x4>;
1016 dma-coherent;
1017 clocks = <&sge0clk 0>;
1018 local-mac-address = [00 00 00 00 00 00];
1019 phy-connection-type = "sgmii";
1020 phy-handle = <&sgenet0phy>;
1021 };
1022
1023 sgenet1: ethernet@1f210030 {
1024 compatible = "apm,xgene1-sgenet";
1025 status = "disabled";
1026 reg = <0x0 0x1f210030 0x0 0xd100>,
1027 <0x0 0x1f200000 0x0 0xc300>,
1028 <0x0 0x1b000000 0x0 0x8000>;
1029 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1030 interrupts = <0x0 0xac 0x4>,
1031 <0x0 0xad 0x4>;
1032 port-id = <1>;
1033 dma-coherent;
1034 local-mac-address = [00 00 00 00 00 00];
1035 phy-connection-type = "sgmii";
1036 phy-handle = <&sgenet1phy>;
1037 };
1038
1039 xgenet: ethernet@1f610000 {
1040 compatible = "apm,xgene1-xgenet";
1041 status = "disabled";
1042 reg = <0x0 0x1f610000 0x0 0xd100>,
1043 <0x0 0x1f600000 0x0 0xc300>,
1044 <0x0 0x18000000 0x0 0x200>;
1045 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1046 interrupts = <0x0 0x60 0x4>,
1047 <0x0 0x61 0x4>,
1048 <0x0 0x62 0x4>,
1049 <0x0 0x63 0x4>,
1050 <0x0 0x64 0x4>,
1051 <0x0 0x65 0x4>,
1052 <0x0 0x66 0x4>,
1053 <0x0 0x67 0x4>;
1054 channel = <0>;
1055 dma-coherent;
1056 clocks = <&xge0clk 0>;
1057 /* mac address will be overwritten by the bootloader */
1058 local-mac-address = [00 00 00 00 00 00];
1059 phy-connection-type = "xgmii";
1060 };
1061
1062 xgenet1: ethernet@1f620000 {
1063 compatible = "apm,xgene1-xgenet";
1064 status = "disabled";
1065 reg = <0x0 0x1f620000 0x0 0xd100>,
1066 <0x0 0x1f600000 0x0 0xc300>,
1067 <0x0 0x18000000 0x0 0x8000>;
1068 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1069 interrupts = <0x0 0x6c 0x4>,
1070 <0x0 0x6d 0x4>;
1071 port-id = <1>;
1072 dma-coherent;
1073 clocks = <&xge1clk 0>;
1074 /* mac address will be overwritten by the bootloader */
1075 local-mac-address = [00 00 00 00 00 00];
1076 phy-connection-type = "xgmii";
1077 };
1078
1079 rng: rng@10520000 {
1080 compatible = "apm,xgene-rng";
1081 reg = <0x0 0x10520000 0x0 0x100>;
1082 interrupts = <0x0 0x41 0x4>;
1083 clocks = <&rngpkaclk 0>;
1084 };
1085
1086 dma: dma@1f270000 {
1087 compatible = "apm,xgene-storm-dma";
1088 device_type = "dma";
1089 reg = <0x0 0x1f270000 0x0 0x10000>,
1090 <0x0 0x1f200000 0x0 0x10000>,
1091 <0x0 0x1b000000 0x0 0x400000>,
1092 <0x0 0x1054a000 0x0 0x100>;
1093 interrupts = <0x0 0x82 0x4>,
1094 <0x0 0xb8 0x4>,
1095 <0x0 0xb9 0x4>,
1096 <0x0 0xba 0x4>,
1097 <0x0 0xbb 0x4>;
1098 dma-coherent;
1099 clocks = <&dmaclk 0>;
1100 };
1101 };
1102};
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
4 *
5 * Copyright (C) 2013, Applied Micro Circuits Corporation
6 */
7
8/ {
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 cpus {
15 #address-cells = <2>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 device_type = "cpu";
20 compatible = "apm,potenza";
21 reg = <0x0 0x000>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
24 next-level-cache = <&xgene_L2_0>;
25 };
26 cpu@1 {
27 device_type = "cpu";
28 compatible = "apm,potenza";
29 reg = <0x0 0x001>;
30 enable-method = "spin-table";
31 cpu-release-addr = <0x1 0x0000fff8>;
32 next-level-cache = <&xgene_L2_0>;
33 };
34 cpu@100 {
35 device_type = "cpu";
36 compatible = "apm,potenza";
37 reg = <0x0 0x100>;
38 enable-method = "spin-table";
39 cpu-release-addr = <0x1 0x0000fff8>;
40 next-level-cache = <&xgene_L2_1>;
41 };
42 cpu@101 {
43 device_type = "cpu";
44 compatible = "apm,potenza";
45 reg = <0x0 0x101>;
46 enable-method = "spin-table";
47 cpu-release-addr = <0x1 0x0000fff8>;
48 next-level-cache = <&xgene_L2_1>;
49 };
50 cpu@200 {
51 device_type = "cpu";
52 compatible = "apm,potenza";
53 reg = <0x0 0x200>;
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
56 next-level-cache = <&xgene_L2_2>;
57 };
58 cpu@201 {
59 device_type = "cpu";
60 compatible = "apm,potenza";
61 reg = <0x0 0x201>;
62 enable-method = "spin-table";
63 cpu-release-addr = <0x1 0x0000fff8>;
64 next-level-cache = <&xgene_L2_2>;
65 };
66 cpu@300 {
67 device_type = "cpu";
68 compatible = "apm,potenza";
69 reg = <0x0 0x300>;
70 enable-method = "spin-table";
71 cpu-release-addr = <0x1 0x0000fff8>;
72 next-level-cache = <&xgene_L2_3>;
73 };
74 cpu@301 {
75 device_type = "cpu";
76 compatible = "apm,potenza";
77 reg = <0x0 0x301>;
78 enable-method = "spin-table";
79 cpu-release-addr = <0x1 0x0000fff8>;
80 next-level-cache = <&xgene_L2_3>;
81 };
82 xgene_L2_0: l2-cache-0 {
83 compatible = "cache";
84 };
85 xgene_L2_1: l2-cache-1 {
86 compatible = "cache";
87 };
88 xgene_L2_2: l2-cache-2 {
89 compatible = "cache";
90 };
91 xgene_L2_3: l2-cache-3 {
92 compatible = "cache";
93 };
94 };
95
96 gic: interrupt-controller@78010000 {
97 compatible = "arm,cortex-a15-gic";
98 #interrupt-cells = <3>;
99 interrupt-controller;
100 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
101 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
102 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
103 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
104 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
105 };
106
107 timer {
108 compatible = "arm,armv8-timer";
109 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
110 <1 13 0xff08>, /* Non-secure Phys IRQ */
111 <1 14 0xff08>, /* Virt IRQ */
112 <1 15 0xff08>; /* Hyp IRQ */
113 clock-frequency = <50000000>;
114 };
115
116 pmu {
117 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
118 interrupts = <1 12 0xff04>;
119 };
120
121 soc {
122 compatible = "simple-bus";
123 #address-cells = <2>;
124 #size-cells = <2>;
125 ranges;
126 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
127
128 clocks {
129 #address-cells = <2>;
130 #size-cells = <2>;
131 ranges;
132 refclk: refclk {
133 compatible = "fixed-clock";
134 #clock-cells = <1>;
135 clock-frequency = <100000000>;
136 clock-output-names = "refclk";
137 };
138
139 pcppll: pcppll@17000100 {
140 compatible = "apm,xgene-pcppll-clock";
141 #clock-cells = <1>;
142 clocks = <&refclk 0>;
143 clock-names = "pcppll";
144 reg = <0x0 0x17000100 0x0 0x1000>;
145 clock-output-names = "pcppll";
146 type = <0>;
147 };
148
149 socpll: socpll@17000120 {
150 compatible = "apm,xgene-socpll-clock";
151 #clock-cells = <1>;
152 clocks = <&refclk 0>;
153 clock-names = "socpll";
154 reg = <0x0 0x17000120 0x0 0x1000>;
155 clock-output-names = "socpll";
156 type = <1>;
157 };
158
159 socplldiv2: socplldiv2 {
160 compatible = "fixed-factor-clock";
161 #clock-cells = <1>;
162 clocks = <&socpll 0>;
163 clock-names = "socplldiv2";
164 clock-mult = <1>;
165 clock-div = <2>;
166 clock-output-names = "socplldiv2";
167 };
168
169 ahbclk: ahbclk@17000000 {
170 compatible = "apm,xgene-device-clock";
171 #clock-cells = <1>;
172 clocks = <&socplldiv2 0>;
173 reg = <0x0 0x17000000 0x0 0x2000>;
174 reg-names = "div-reg";
175 divider-offset = <0x164>;
176 divider-width = <0x5>;
177 divider-shift = <0x0>;
178 clock-output-names = "ahbclk";
179 };
180
181 sdioclk: sdioclk@1f2ac000 {
182 compatible = "apm,xgene-device-clock";
183 #clock-cells = <1>;
184 clocks = <&socplldiv2 0>;
185 reg = <0x0 0x1f2ac000 0x0 0x1000
186 0x0 0x17000000 0x0 0x2000>;
187 reg-names = "csr-reg", "div-reg";
188 csr-offset = <0x0>;
189 csr-mask = <0x2>;
190 enable-offset = <0x8>;
191 enable-mask = <0x2>;
192 divider-offset = <0x178>;
193 divider-width = <0x8>;
194 divider-shift = <0x0>;
195 clock-output-names = "sdioclk";
196 };
197
198 ethclk: ethclk {
199 compatible = "apm,xgene-device-clock";
200 #clock-cells = <1>;
201 clocks = <&socplldiv2 0>;
202 clock-names = "ethclk";
203 reg = <0x0 0x17000000 0x0 0x1000>;
204 reg-names = "div-reg";
205 divider-offset = <0x238>;
206 divider-width = <0x9>;
207 divider-shift = <0x0>;
208 clock-output-names = "ethclk";
209 };
210
211 menetclk: menetclk {
212 compatible = "apm,xgene-device-clock";
213 #clock-cells = <1>;
214 clocks = <ðclk 0>;
215 reg = <0x0 0x1702c000 0x0 0x1000>;
216 reg-names = "csr-reg";
217 clock-output-names = "menetclk";
218 };
219
220 sge0clk: sge0clk@1f21c000 {
221 compatible = "apm,xgene-device-clock";
222 #clock-cells = <1>;
223 clocks = <&socplldiv2 0>;
224 reg = <0x0 0x1f21c000 0x0 0x1000>;
225 reg-names = "csr-reg";
226 csr-mask = <0xa>;
227 enable-mask = <0xf>;
228 clock-output-names = "sge0clk";
229 };
230
231 xge0clk: xge0clk@1f61c000 {
232 compatible = "apm,xgene-device-clock";
233 #clock-cells = <1>;
234 clocks = <&socplldiv2 0>;
235 reg = <0x0 0x1f61c000 0x0 0x1000>;
236 reg-names = "csr-reg";
237 csr-mask = <0x3>;
238 clock-output-names = "xge0clk";
239 };
240
241 xge1clk: xge1clk@1f62c000 {
242 compatible = "apm,xgene-device-clock";
243 status = "disabled";
244 #clock-cells = <1>;
245 clocks = <&socplldiv2 0>;
246 reg = <0x0 0x1f62c000 0x0 0x1000>;
247 reg-names = "csr-reg";
248 csr-mask = <0x3>;
249 clock-output-names = "xge1clk";
250 };
251
252 sataphy1clk: sataphy1clk@1f21c000 {
253 compatible = "apm,xgene-device-clock";
254 #clock-cells = <1>;
255 clocks = <&socplldiv2 0>;
256 reg = <0x0 0x1f21c000 0x0 0x1000>;
257 reg-names = "csr-reg";
258 clock-output-names = "sataphy1clk";
259 status = "disabled";
260 csr-offset = <0x4>;
261 csr-mask = <0x00>;
262 enable-offset = <0x0>;
263 enable-mask = <0x06>;
264 };
265
266 sataphy2clk: sataphy1clk@1f22c000 {
267 compatible = "apm,xgene-device-clock";
268 #clock-cells = <1>;
269 clocks = <&socplldiv2 0>;
270 reg = <0x0 0x1f22c000 0x0 0x1000>;
271 reg-names = "csr-reg";
272 clock-output-names = "sataphy2clk";
273 status = "ok";
274 csr-offset = <0x4>;
275 csr-mask = <0x3a>;
276 enable-offset = <0x0>;
277 enable-mask = <0x06>;
278 };
279
280 sataphy3clk: sataphy1clk@1f23c000 {
281 compatible = "apm,xgene-device-clock";
282 #clock-cells = <1>;
283 clocks = <&socplldiv2 0>;
284 reg = <0x0 0x1f23c000 0x0 0x1000>;
285 reg-names = "csr-reg";
286 clock-output-names = "sataphy3clk";
287 status = "ok";
288 csr-offset = <0x4>;
289 csr-mask = <0x3a>;
290 enable-offset = <0x0>;
291 enable-mask = <0x06>;
292 };
293
294 sata01clk: sata01clk@1f21c000 {
295 compatible = "apm,xgene-device-clock";
296 #clock-cells = <1>;
297 clocks = <&socplldiv2 0>;
298 reg = <0x0 0x1f21c000 0x0 0x1000>;
299 reg-names = "csr-reg";
300 clock-output-names = "sata01clk";
301 csr-offset = <0x4>;
302 csr-mask = <0x05>;
303 enable-offset = <0x0>;
304 enable-mask = <0x39>;
305 };
306
307 sata23clk: sata23clk@1f22c000 {
308 compatible = "apm,xgene-device-clock";
309 #clock-cells = <1>;
310 clocks = <&socplldiv2 0>;
311 reg = <0x0 0x1f22c000 0x0 0x1000>;
312 reg-names = "csr-reg";
313 clock-output-names = "sata23clk";
314 csr-offset = <0x4>;
315 csr-mask = <0x05>;
316 enable-offset = <0x0>;
317 enable-mask = <0x39>;
318 };
319
320 sata45clk: sata45clk@1f23c000 {
321 compatible = "apm,xgene-device-clock";
322 #clock-cells = <1>;
323 clocks = <&socplldiv2 0>;
324 reg = <0x0 0x1f23c000 0x0 0x1000>;
325 reg-names = "csr-reg";
326 clock-output-names = "sata45clk";
327 csr-offset = <0x4>;
328 csr-mask = <0x05>;
329 enable-offset = <0x0>;
330 enable-mask = <0x39>;
331 };
332
333 rtcclk: rtcclk@17000000 {
334 compatible = "apm,xgene-device-clock";
335 #clock-cells = <1>;
336 clocks = <&socplldiv2 0>;
337 reg = <0x0 0x17000000 0x0 0x2000>;
338 reg-names = "csr-reg";
339 csr-offset = <0xc>;
340 csr-mask = <0x2>;
341 enable-offset = <0x10>;
342 enable-mask = <0x2>;
343 clock-output-names = "rtcclk";
344 };
345
346 rngpkaclk: rngpkaclk@17000000 {
347 compatible = "apm,xgene-device-clock";
348 #clock-cells = <1>;
349 clocks = <&socplldiv2 0>;
350 reg = <0x0 0x17000000 0x0 0x2000>;
351 reg-names = "csr-reg";
352 csr-offset = <0xc>;
353 csr-mask = <0x10>;
354 enable-offset = <0x10>;
355 enable-mask = <0x10>;
356 clock-output-names = "rngpkaclk";
357 };
358
359 pcie0clk: pcie0clk@1f2bc000 {
360 status = "disabled";
361 compatible = "apm,xgene-device-clock";
362 #clock-cells = <1>;
363 clocks = <&socplldiv2 0>;
364 reg = <0x0 0x1f2bc000 0x0 0x1000>;
365 reg-names = "csr-reg";
366 clock-output-names = "pcie0clk";
367 };
368
369 pcie1clk: pcie1clk@1f2cc000 {
370 status = "disabled";
371 compatible = "apm,xgene-device-clock";
372 #clock-cells = <1>;
373 clocks = <&socplldiv2 0>;
374 reg = <0x0 0x1f2cc000 0x0 0x1000>;
375 reg-names = "csr-reg";
376 clock-output-names = "pcie1clk";
377 };
378
379 pcie2clk: pcie2clk@1f2dc000 {
380 status = "disabled";
381 compatible = "apm,xgene-device-clock";
382 #clock-cells = <1>;
383 clocks = <&socplldiv2 0>;
384 reg = <0x0 0x1f2dc000 0x0 0x1000>;
385 reg-names = "csr-reg";
386 clock-output-names = "pcie2clk";
387 };
388
389 pcie3clk: pcie3clk@1f50c000 {
390 status = "disabled";
391 compatible = "apm,xgene-device-clock";
392 #clock-cells = <1>;
393 clocks = <&socplldiv2 0>;
394 reg = <0x0 0x1f50c000 0x0 0x1000>;
395 reg-names = "csr-reg";
396 clock-output-names = "pcie3clk";
397 };
398
399 pcie4clk: pcie4clk@1f51c000 {
400 status = "disabled";
401 compatible = "apm,xgene-device-clock";
402 #clock-cells = <1>;
403 clocks = <&socplldiv2 0>;
404 reg = <0x0 0x1f51c000 0x0 0x1000>;
405 reg-names = "csr-reg";
406 clock-output-names = "pcie4clk";
407 };
408
409 dmaclk: dmaclk@1f27c000 {
410 compatible = "apm,xgene-device-clock";
411 #clock-cells = <1>;
412 clocks = <&socplldiv2 0>;
413 reg = <0x0 0x1f27c000 0x0 0x1000>;
414 reg-names = "csr-reg";
415 clock-output-names = "dmaclk";
416 };
417 };
418
419 msi: msi@79000000 {
420 compatible = "apm,xgene1-msi";
421 msi-controller;
422 reg = <0x00 0x79000000 0x0 0x900000>;
423 interrupts = < 0x0 0x10 0x4
424 0x0 0x11 0x4
425 0x0 0x12 0x4
426 0x0 0x13 0x4
427 0x0 0x14 0x4
428 0x0 0x15 0x4
429 0x0 0x16 0x4
430 0x0 0x17 0x4
431 0x0 0x18 0x4
432 0x0 0x19 0x4
433 0x0 0x1a 0x4
434 0x0 0x1b 0x4
435 0x0 0x1c 0x4
436 0x0 0x1d 0x4
437 0x0 0x1e 0x4
438 0x0 0x1f 0x4>;
439 };
440
441 scu: system-clk-controller@17000000 {
442 compatible = "apm,xgene-scu","syscon";
443 reg = <0x0 0x17000000 0x0 0x400>;
444 };
445
446 reboot: reboot@17000014 {
447 compatible = "syscon-reboot";
448 regmap = <&scu>;
449 offset = <0x14>;
450 mask = <0x1>;
451 };
452
453 csw: csw@7e200000 {
454 compatible = "apm,xgene-csw", "syscon";
455 reg = <0x0 0x7e200000 0x0 0x1000>;
456 };
457
458 mcba: mcba@7e700000 {
459 compatible = "apm,xgene-mcb", "syscon";
460 reg = <0x0 0x7e700000 0x0 0x1000>;
461 };
462
463 mcbb: mcbb@7e720000 {
464 compatible = "apm,xgene-mcb", "syscon";
465 reg = <0x0 0x7e720000 0x0 0x1000>;
466 };
467
468 efuse: efuse@1054a000 {
469 compatible = "apm,xgene-efuse", "syscon";
470 reg = <0x0 0x1054a000 0x0 0x20>;
471 };
472
473 rb: rb@7e000000 {
474 compatible = "apm,xgene-rb", "syscon";
475 reg = <0x0 0x7e000000 0x0 0x10>;
476 };
477
478 edac@78800000 {
479 compatible = "apm,xgene-edac";
480 #address-cells = <2>;
481 #size-cells = <2>;
482 ranges;
483 regmap-csw = <&csw>;
484 regmap-mcba = <&mcba>;
485 regmap-mcbb = <&mcbb>;
486 regmap-efuse = <&efuse>;
487 regmap-rb = <&rb>;
488 reg = <0x0 0x78800000 0x0 0x100>;
489 interrupts = <0x0 0x20 0x4>,
490 <0x0 0x21 0x4>,
491 <0x0 0x27 0x4>;
492
493 edacmc@7e800000 {
494 compatible = "apm,xgene-edac-mc";
495 reg = <0x0 0x7e800000 0x0 0x1000>;
496 memory-controller = <0>;
497 };
498
499 edacmc@7e840000 {
500 compatible = "apm,xgene-edac-mc";
501 reg = <0x0 0x7e840000 0x0 0x1000>;
502 memory-controller = <1>;
503 };
504
505 edacmc@7e880000 {
506 compatible = "apm,xgene-edac-mc";
507 reg = <0x0 0x7e880000 0x0 0x1000>;
508 memory-controller = <2>;
509 };
510
511 edacmc@7e8c0000 {
512 compatible = "apm,xgene-edac-mc";
513 reg = <0x0 0x7e8c0000 0x0 0x1000>;
514 memory-controller = <3>;
515 };
516
517 edacpmd@7c000000 {
518 compatible = "apm,xgene-edac-pmd";
519 reg = <0x0 0x7c000000 0x0 0x200000>;
520 pmd-controller = <0>;
521 };
522
523 edacpmd@7c200000 {
524 compatible = "apm,xgene-edac-pmd";
525 reg = <0x0 0x7c200000 0x0 0x200000>;
526 pmd-controller = <1>;
527 };
528
529 edacpmd@7c400000 {
530 compatible = "apm,xgene-edac-pmd";
531 reg = <0x0 0x7c400000 0x0 0x200000>;
532 pmd-controller = <2>;
533 };
534
535 edacpmd@7c600000 {
536 compatible = "apm,xgene-edac-pmd";
537 reg = <0x0 0x7c600000 0x0 0x200000>;
538 pmd-controller = <3>;
539 };
540
541 edacl3@7e600000 {
542 compatible = "apm,xgene-edac-l3";
543 reg = <0x0 0x7e600000 0x0 0x1000>;
544 };
545
546 edacsoc@7e930000 {
547 compatible = "apm,xgene-edac-soc-v1";
548 reg = <0x0 0x7e930000 0x0 0x1000>;
549 };
550 };
551
552 pmu: pmu@78810000 {
553 compatible = "apm,xgene-pmu-v2";
554 #address-cells = <2>;
555 #size-cells = <2>;
556 ranges;
557 regmap-csw = <&csw>;
558 regmap-mcba = <&mcba>;
559 regmap-mcbb = <&mcbb>;
560 reg = <0x0 0x78810000 0x0 0x1000>;
561 interrupts = <0x0 0x22 0x4>;
562
563 pmul3c@7e610000 {
564 compatible = "apm,xgene-pmu-l3c";
565 reg = <0x0 0x7e610000 0x0 0x1000>;
566 };
567
568 pmuiob@7e940000 {
569 compatible = "apm,xgene-pmu-iob";
570 reg = <0x0 0x7e940000 0x0 0x1000>;
571 };
572
573 pmucmcb@7e710000 {
574 compatible = "apm,xgene-pmu-mcb";
575 reg = <0x0 0x7e710000 0x0 0x1000>;
576 enable-bit-index = <0>;
577 };
578
579 pmucmcb@7e730000 {
580 compatible = "apm,xgene-pmu-mcb";
581 reg = <0x0 0x7e730000 0x0 0x1000>;
582 enable-bit-index = <1>;
583 };
584
585 pmucmc@7e810000 {
586 compatible = "apm,xgene-pmu-mc";
587 reg = <0x0 0x7e810000 0x0 0x1000>;
588 enable-bit-index = <0>;
589 };
590
591 pmucmc@7e850000 {
592 compatible = "apm,xgene-pmu-mc";
593 reg = <0x0 0x7e850000 0x0 0x1000>;
594 enable-bit-index = <1>;
595 };
596
597 pmucmc@7e890000 {
598 compatible = "apm,xgene-pmu-mc";
599 reg = <0x0 0x7e890000 0x0 0x1000>;
600 enable-bit-index = <2>;
601 };
602
603 pmucmc@7e8d0000 {
604 compatible = "apm,xgene-pmu-mc";
605 reg = <0x0 0x7e8d0000 0x0 0x1000>;
606 enable-bit-index = <3>;
607 };
608 };
609
610 pcie0: pcie@1f2b0000 {
611 status = "disabled";
612 device_type = "pci";
613 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
614 #interrupt-cells = <1>;
615 #size-cells = <2>;
616 #address-cells = <3>;
617 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
618 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
619 reg-names = "csr", "cfg";
620 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
621 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */
622 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
623 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
624 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
625 bus-range = <0x00 0xff>;
626 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
627 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
628 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
629 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
630 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
631 dma-coherent;
632 clocks = <&pcie0clk 0>;
633 msi-parent = <&msi>;
634 };
635
636 pcie1: pcie@1f2c0000 {
637 status = "disabled";
638 device_type = "pci";
639 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
640 #interrupt-cells = <1>;
641 #size-cells = <2>;
642 #address-cells = <3>;
643 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
644 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
645 reg-names = "csr", "cfg";
646 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
647 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */
648 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
649 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
650 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
651 bus-range = <0x00 0xff>;
652 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
653 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
654 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
655 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
656 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
657 dma-coherent;
658 clocks = <&pcie1clk 0>;
659 msi-parent = <&msi>;
660 };
661
662 pcie2: pcie@1f2d0000 {
663 status = "disabled";
664 device_type = "pci";
665 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
666 #interrupt-cells = <1>;
667 #size-cells = <2>;
668 #address-cells = <3>;
669 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
670 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
671 reg-names = "csr", "cfg";
672 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */
673 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */
674 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
675 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
676 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
677 bus-range = <0x00 0xff>;
678 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
679 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
680 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
681 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
682 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
683 dma-coherent;
684 clocks = <&pcie2clk 0>;
685 msi-parent = <&msi>;
686 };
687
688 pcie3: pcie@1f500000 {
689 status = "disabled";
690 device_type = "pci";
691 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
692 #interrupt-cells = <1>;
693 #size-cells = <2>;
694 #address-cells = <3>;
695 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
696 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
697 reg-names = "csr", "cfg";
698 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
699 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */
700 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
701 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
702 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
703 bus-range = <0x00 0xff>;
704 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
705 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
706 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
707 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
708 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
709 dma-coherent;
710 clocks = <&pcie3clk 0>;
711 msi-parent = <&msi>;
712 };
713
714 pcie4: pcie@1f510000 {
715 status = "disabled";
716 device_type = "pci";
717 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
718 #interrupt-cells = <1>;
719 #size-cells = <2>;
720 #address-cells = <3>;
721 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
722 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
723 reg-names = "csr", "cfg";
724 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
725 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */
726 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
727 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
728 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
729 bus-range = <0x00 0xff>;
730 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
731 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
732 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
733 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
734 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
735 dma-coherent;
736 clocks = <&pcie4clk 0>;
737 msi-parent = <&msi>;
738 };
739
740 mailbox: mailbox@10540000 {
741 compatible = "apm,xgene-slimpro-mbox";
742 reg = <0x0 0x10540000 0x0 0xa000>;
743 #mbox-cells = <1>;
744 interrupts = <0x0 0x0 0x4>,
745 <0x0 0x1 0x4>,
746 <0x0 0x2 0x4>,
747 <0x0 0x3 0x4>,
748 <0x0 0x4 0x4>,
749 <0x0 0x5 0x4>,
750 <0x0 0x6 0x4>,
751 <0x0 0x7 0x4>;
752 };
753
754 i2cslimpro {
755 compatible = "apm,xgene-slimpro-i2c";
756 mboxes = <&mailbox 0>;
757 };
758
759 hwmonslimpro {
760 compatible = "apm,xgene-slimpro-hwmon";
761 mboxes = <&mailbox 7>;
762 };
763
764 serial0: serial@1c020000 {
765 status = "disabled";
766 device_type = "serial";
767 compatible = "ns16550a";
768 reg = <0 0x1c020000 0x0 0x1000>;
769 reg-shift = <2>;
770 clock-frequency = <10000000>; /* Updated by bootloader */
771 interrupt-parent = <&gic>;
772 interrupts = <0x0 0x4c 0x4>;
773 };
774
775 serial1: serial@1c021000 {
776 status = "disabled";
777 device_type = "serial";
778 compatible = "ns16550a";
779 reg = <0 0x1c021000 0x0 0x1000>;
780 reg-shift = <2>;
781 clock-frequency = <10000000>; /* Updated by bootloader */
782 interrupt-parent = <&gic>;
783 interrupts = <0x0 0x4d 0x4>;
784 };
785
786 serial2: serial@1c022000 {
787 status = "disabled";
788 device_type = "serial";
789 compatible = "ns16550a";
790 reg = <0 0x1c022000 0x0 0x1000>;
791 reg-shift = <2>;
792 clock-frequency = <10000000>; /* Updated by bootloader */
793 interrupt-parent = <&gic>;
794 interrupts = <0x0 0x4e 0x4>;
795 };
796
797 serial3: serial@1c023000 {
798 status = "disabled";
799 device_type = "serial";
800 compatible = "ns16550a";
801 reg = <0 0x1c023000 0x0 0x1000>;
802 reg-shift = <2>;
803 clock-frequency = <10000000>; /* Updated by bootloader */
804 interrupt-parent = <&gic>;
805 interrupts = <0x0 0x4f 0x4>;
806 };
807
808 mmc0: mmc@1c000000 {
809 compatible = "arasan,sdhci-4.9a";
810 reg = <0x0 0x1c000000 0x0 0x100>;
811 interrupts = <0x0 0x49 0x4>;
812 dma-coherent;
813 no-1-8-v;
814 clock-names = "clk_xin", "clk_ahb";
815 clocks = <&sdioclk 0>, <&ahbclk 0>;
816 };
817
818 gfcgpio: gpio0@1701c000 {
819 compatible = "apm,xgene-gpio";
820 reg = <0x0 0x1701c000 0x0 0x40>;
821 gpio-controller;
822 #gpio-cells = <2>;
823 };
824
825 dwgpio: gpio@1c024000 {
826 compatible = "snps,dw-apb-gpio";
827 reg = <0x0 0x1c024000 0x0 0x1000>;
828 #address-cells = <1>;
829 #size-cells = <0>;
830
831 porta: gpio-controller@0 {
832 compatible = "snps,dw-apb-gpio-port";
833 gpio-controller;
834 #gpio-cells = <2>;
835 snps,nr-gpios = <32>;
836 reg = <0>;
837 };
838 };
839
840 i2c0: i2c@10512000 {
841 status = "disabled";
842 #address-cells = <1>;
843 #size-cells = <0>;
844 compatible = "snps,designware-i2c";
845 reg = <0x0 0x10512000 0x0 0x1000>;
846 interrupts = <0 0x44 0x4>;
847 #clock-cells = <1>;
848 clocks = <&ahbclk 0>;
849 bus_num = <0>;
850 };
851
852 phy1: phy@1f21a000 {
853 compatible = "apm,xgene-phy";
854 reg = <0x0 0x1f21a000 0x0 0x100>;
855 #phy-cells = <1>;
856 clocks = <&sataphy1clk 0>;
857 status = "disabled";
858 apm,tx-boost-gain = <30 30 30 30 30 30>;
859 apm,tx-eye-tuning = <2 10 10 2 10 10>;
860 };
861
862 phy2: phy@1f22a000 {
863 compatible = "apm,xgene-phy";
864 reg = <0x0 0x1f22a000 0x0 0x100>;
865 #phy-cells = <1>;
866 clocks = <&sataphy2clk 0>;
867 status = "ok";
868 apm,tx-boost-gain = <30 30 30 30 30 30>;
869 apm,tx-eye-tuning = <1 10 10 2 10 10>;
870 };
871
872 phy3: phy@1f23a000 {
873 compatible = "apm,xgene-phy";
874 reg = <0x0 0x1f23a000 0x0 0x100>;
875 #phy-cells = <1>;
876 clocks = <&sataphy3clk 0>;
877 status = "ok";
878 apm,tx-boost-gain = <31 31 31 31 31 31>;
879 apm,tx-eye-tuning = <2 10 10 2 10 10>;
880 };
881
882 sata1: sata@1a000000 {
883 compatible = "apm,xgene-ahci";
884 reg = <0x0 0x1a000000 0x0 0x1000>,
885 <0x0 0x1f210000 0x0 0x1000>,
886 <0x0 0x1f21d000 0x0 0x1000>,
887 <0x0 0x1f21e000 0x0 0x1000>,
888 <0x0 0x1f217000 0x0 0x1000>;
889 interrupts = <0x0 0x86 0x4>;
890 dma-coherent;
891 status = "disabled";
892 clocks = <&sata01clk 0>;
893 phys = <&phy1 0>;
894 phy-names = "sata-phy";
895 };
896
897 sata2: sata@1a400000 {
898 compatible = "apm,xgene-ahci";
899 reg = <0x0 0x1a400000 0x0 0x1000>,
900 <0x0 0x1f220000 0x0 0x1000>,
901 <0x0 0x1f22d000 0x0 0x1000>,
902 <0x0 0x1f22e000 0x0 0x1000>,
903 <0x0 0x1f227000 0x0 0x1000>;
904 interrupts = <0x0 0x87 0x4>;
905 dma-coherent;
906 status = "ok";
907 clocks = <&sata23clk 0>;
908 phys = <&phy2 0>;
909 phy-names = "sata-phy";
910 };
911
912 sata3: sata@1a800000 {
913 compatible = "apm,xgene-ahci";
914 reg = <0x0 0x1a800000 0x0 0x1000>,
915 <0x0 0x1f230000 0x0 0x1000>,
916 <0x0 0x1f23d000 0x0 0x1000>,
917 <0x0 0x1f23e000 0x0 0x1000>;
918 interrupts = <0x0 0x88 0x4>;
919 dma-coherent;
920 status = "ok";
921 clocks = <&sata45clk 0>;
922 phys = <&phy3 0>;
923 phy-names = "sata-phy";
924 };
925
926 /* Node-name might need to be coded as dwusb for backward compatibility */
927 usb0: usb@19000000 {
928 status = "disabled";
929 compatible = "snps,dwc3";
930 reg = <0x0 0x19000000 0x0 0x100000>;
931 interrupts = <0x0 0x89 0x4>;
932 dma-coherent;
933 dr_mode = "host";
934 };
935
936 usb1: usb@19800000 {
937 status = "disabled";
938 compatible = "snps,dwc3";
939 reg = <0x0 0x19800000 0x0 0x100000>;
940 interrupts = <0x0 0x8a 0x4>;
941 dma-coherent;
942 dr_mode = "host";
943 };
944
945 sbgpio: gpio@17001000{
946 compatible = "apm,xgene-gpio-sb";
947 reg = <0x0 0x17001000 0x0 0x400>;
948 #gpio-cells = <2>;
949 gpio-controller;
950 interrupts = <0x0 0x28 0x1>,
951 <0x0 0x29 0x1>,
952 <0x0 0x2a 0x1>,
953 <0x0 0x2b 0x1>,
954 <0x0 0x2c 0x1>,
955 <0x0 0x2d 0x1>;
956 interrupt-parent = <&gic>;
957 #interrupt-cells = <2>;
958 interrupt-controller;
959 };
960
961 rtc: rtc@10510000 {
962 compatible = "apm,xgene-rtc";
963 reg = <0x0 0x10510000 0x0 0x400>;
964 interrupts = <0x0 0x46 0x4>;
965 #clock-cells = <1>;
966 clocks = <&rtcclk 0>;
967 };
968
969 mdio: mdio@17020000 {
970 compatible = "apm,xgene-mdio-rgmii";
971 #address-cells = <1>;
972 #size-cells = <0>;
973 reg = <0x0 0x17020000 0x0 0xd100>;
974 clocks = <&menetclk 0>;
975 };
976
977 menet: ethernet@17020000 {
978 compatible = "apm,xgene-enet";
979 status = "disabled";
980 reg = <0x0 0x17020000 0x0 0xd100>,
981 <0x0 0x17030000 0x0 0xc300>,
982 <0x0 0x10000000 0x0 0x200>;
983 reg-names = "enet_csr", "ring_csr", "ring_cmd";
984 interrupts = <0x0 0x3c 0x4>;
985 dma-coherent;
986 clocks = <&menetclk 0>;
987 /* mac address will be overwritten by the bootloader */
988 local-mac-address = [00 00 00 00 00 00];
989 phy-connection-type = "rgmii";
990 phy-handle = <&menetphy>,<&menet0phy>;
991 mdio {
992 compatible = "apm,xgene-mdio";
993 #address-cells = <1>;
994 #size-cells = <0>;
995 menetphy: menetphy@3 {
996 compatible = "ethernet-phy-id001c.c915";
997 reg = <0x3>;
998 };
999
1000 };
1001 };
1002
1003 sgenet0: ethernet@1f210000 {
1004 compatible = "apm,xgene1-sgenet";
1005 status = "disabled";
1006 reg = <0x0 0x1f210000 0x0 0xd100>,
1007 <0x0 0x1f200000 0x0 0xc300>,
1008 <0x0 0x1b000000 0x0 0x200>;
1009 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1010 interrupts = <0x0 0xa0 0x4>,
1011 <0x0 0xa1 0x4>;
1012 dma-coherent;
1013 clocks = <&sge0clk 0>;
1014 local-mac-address = [00 00 00 00 00 00];
1015 phy-connection-type = "sgmii";
1016 phy-handle = <&sgenet0phy>;
1017 };
1018
1019 sgenet1: ethernet@1f210030 {
1020 compatible = "apm,xgene1-sgenet";
1021 status = "disabled";
1022 reg = <0x0 0x1f210030 0x0 0xd100>,
1023 <0x0 0x1f200000 0x0 0xc300>,
1024 <0x0 0x1b000000 0x0 0x8000>;
1025 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1026 interrupts = <0x0 0xac 0x4>,
1027 <0x0 0xad 0x4>;
1028 port-id = <1>;
1029 dma-coherent;
1030 local-mac-address = [00 00 00 00 00 00];
1031 phy-connection-type = "sgmii";
1032 phy-handle = <&sgenet1phy>;
1033 };
1034
1035 xgenet: ethernet@1f610000 {
1036 compatible = "apm,xgene1-xgenet";
1037 status = "disabled";
1038 reg = <0x0 0x1f610000 0x0 0xd100>,
1039 <0x0 0x1f600000 0x0 0xc300>,
1040 <0x0 0x18000000 0x0 0x200>;
1041 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1042 interrupts = <0x0 0x60 0x4>,
1043 <0x0 0x61 0x4>,
1044 <0x0 0x62 0x4>,
1045 <0x0 0x63 0x4>,
1046 <0x0 0x64 0x4>,
1047 <0x0 0x65 0x4>,
1048 <0x0 0x66 0x4>,
1049 <0x0 0x67 0x4>;
1050 channel = <0>;
1051 dma-coherent;
1052 clocks = <&xge0clk 0>;
1053 /* mac address will be overwritten by the bootloader */
1054 local-mac-address = [00 00 00 00 00 00];
1055 phy-connection-type = "xgmii";
1056 };
1057
1058 xgenet1: ethernet@1f620000 {
1059 compatible = "apm,xgene1-xgenet";
1060 status = "disabled";
1061 reg = <0x0 0x1f620000 0x0 0xd100>,
1062 <0x0 0x1f600000 0x0 0xc300>,
1063 <0x0 0x18000000 0x0 0x8000>;
1064 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1065 interrupts = <0x0 0x6c 0x4>,
1066 <0x0 0x6d 0x4>;
1067 port-id = <1>;
1068 dma-coherent;
1069 clocks = <&xge1clk 0>;
1070 /* mac address will be overwritten by the bootloader */
1071 local-mac-address = [00 00 00 00 00 00];
1072 phy-connection-type = "xgmii";
1073 };
1074
1075 rng: rng@10520000 {
1076 compatible = "apm,xgene-rng";
1077 reg = <0x0 0x10520000 0x0 0x100>;
1078 interrupts = <0x0 0x41 0x4>;
1079 clocks = <&rngpkaclk 0>;
1080 };
1081
1082 dma: dma@1f270000 {
1083 compatible = "apm,xgene-storm-dma";
1084 device_type = "dma";
1085 reg = <0x0 0x1f270000 0x0 0x10000>,
1086 <0x0 0x1f200000 0x0 0x10000>,
1087 <0x0 0x1b000000 0x0 0x400000>,
1088 <0x0 0x1054a000 0x0 0x100>;
1089 interrupts = <0x0 0x82 0x4>,
1090 <0x0 0xb8 0x4>,
1091 <0x0 0xb9 0x4>,
1092 <0x0 0xba 0x4>,
1093 <0x0 0xbb 0x4>;
1094 dma-coherent;
1095 clocks = <&dmaclk 0>;
1096 };
1097 };
1098};