1// SPDX-License-Identifier: GPL-2.0
  2//
  3// Copyright (c) 2003-2004 Simtec Electronics
  4//	Ben Dooks <ben@simtec.co.uk>
  5//
  6// https://www.handhelds.org/projects/rx3715.html
  7
  8#include <linux/kernel.h>
  9#include <linux/types.h>
 10#include <linux/interrupt.h>
 11#include <linux/list.h>
 12#include <linux/memblock.h>
 13#include <linux/timer.h>
 14#include <linux/init.h>
 15#include <linux/tty.h>
 16#include <linux/console.h>
 17#include <linux/device.h>
 18#include <linux/platform_device.h>
 19#include <linux/serial_core.h>
 20#include <linux/serial_s3c.h>
 21#include <linux/serial.h>
 22#include <linux/io.h>
 23#include <linux/mtd/mtd.h>
 24#include <linux/mtd/rawnand.h>
 25#include <linux/mtd/nand-ecc-sw-hamming.h>
 26#include <linux/mtd/partitions.h>
 27
 28#include <asm/mach/arch.h>
 29#include <asm/mach/irq.h>
 30#include <asm/mach/map.h>
 31
 32#include <linux/platform_data/mtd-nand-s3c2410.h>
 33#include <linux/platform_data/fb-s3c2410.h>
 34
 35#include <asm/irq.h>
 36#include <asm/mach-types.h>
 37
 38#include "regs-gpio.h"
 39#include "gpio-samsung.h"
 40#include "gpio-cfg.h"
 41
 42#include "cpu.h"
 43#include "devs.h"
 44#include "pm.h"
 45
 46#include "s3c24xx.h"
 47#include "h1940.h"
 48
 49static struct map_desc rx3715_iodesc[] __initdata = {
 50	/* dump ISA space somewhere unused */
 51	{
 52		.virtual	= (u32)S3C24XX_VA_ISA_BYTE,
 53		.pfn		= __phys_to_pfn(S3C2410_CS3),
 54		.length		= SZ_1M,
 55		.type		= MT_DEVICE,
 56	},
 57};
 58
 59static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
 60	[0] = {
 61		.hwport	     = 0,
 62		.flags	     = 0,
 63		.ucon	     = 0x3c5,
 64		.ulcon	     = 0x03,
 65		.ufcon	     = 0x51,
 66		.clk_sel	= S3C2410_UCON_CLKSEL3,
 67	},
 68	[1] = {
 69		.hwport	     = 1,
 70		.flags	     = 0,
 71		.ucon	     = 0x3c5,
 72		.ulcon	     = 0x03,
 73		.ufcon	     = 0x00,
 74		.clk_sel	= S3C2410_UCON_CLKSEL3,
 75	},
 76	/* IR port */
 77	[2] = {
 78		.hwport	     = 2,
 79		.uart_flags  = UPF_CONS_FLOW,
 80		.ucon	     = 0x3c5,
 81		.ulcon	     = 0x43,
 82		.ufcon	     = 0x51,
 83		.clk_sel	= S3C2410_UCON_CLKSEL3,
 84	}
 85};
 86
 87/* framebuffer lcd controller information */
 88
 89static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
 90	.lcdcon5 =	S3C2410_LCDCON5_INVVLINE |
 91			S3C2410_LCDCON5_FRM565 |
 92			S3C2410_LCDCON5_HWSWP,
 93
 94	.type		= S3C2410_LCDCON1_TFT,
 95	.width		= 240,
 96	.height		= 320,
 97
 98	.pixclock	= 260000,
 99	.xres		= 240,
100	.yres		= 320,
101	.bpp		= 16,
102	.left_margin	= 36,
103	.right_margin	= 36,
104	.hsync_len	= 8,
105	.upper_margin	= 6,
106	.lower_margin	= 7,
107	.vsync_len	= 3,
108};
109
110static struct s3c2410fb_mach_info rx3715_fb_info __initdata = {
111
112	.displays =	&rx3715_lcdcfg,
113	.num_displays =	1,
114	.default_display = 0,
115
116	.lpcsel =	0xf82,
117
118	.gpccon =	0xaa955699,
119	.gpccon_mask =	0xffc003cc,
120	.gpccon_reg =	S3C2410_GPCCON,
121	.gpcup =	0x0000ffff,
122	.gpcup_mask =	0xffffffff,
123	.gpcup_reg =	S3C2410_GPCUP,
124
125	.gpdcon =	0xaa95aaa1,
126	.gpdcon_mask =	0xffc0fff0,
127	.gpdcon_reg =	S3C2410_GPDCON,
128	.gpdup =	0x0000faff,
129	.gpdup_mask =	0xffffffff,
130	.gpdup_reg =	S3C2410_GPDUP,
131};
132
133static struct mtd_partition __initdata rx3715_nand_part[] = {
134	[0] = {
135		.name		= "Whole Flash",
136		.offset		= 0,
137		.size		= MTDPART_SIZ_FULL,
138		.mask_flags	= MTD_WRITEABLE,
139	}
140};
141
142static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = {
143	[0] = {
144		.name		= "Internal",
145		.nr_chips	= 1,
146		.nr_partitions	= ARRAY_SIZE(rx3715_nand_part),
147		.partitions	= rx3715_nand_part,
148	},
149};
150
151static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
152	.tacls		= 25,
153	.twrph0		= 50,
154	.twrph1		= 15,
155	.nr_sets	= ARRAY_SIZE(rx3715_nand_sets),
156	.sets		= rx3715_nand_sets,
157	.engine_type	= NAND_ECC_ENGINE_TYPE_SOFT,
158};
159
160static struct platform_device *rx3715_devices[] __initdata = {
161	&s3c_device_ohci,
162	&s3c_device_lcd,
163	&s3c_device_wdt,
164	&s3c_device_i2c0,
165	&s3c_device_iis,
166	&s3c_device_nand,
167};
168
169static void __init rx3715_map_io(void)
170{
171	s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
172	s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
173	s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
174}
175
176static void __init rx3715_init_time(void)
177{
178	s3c2440_init_clocks(16934000);
179	s3c24xx_timer_init();
180}
181
182/* H1940 and RX3715 need to reserve this for suspend */
183static void __init rx3715_reserve(void)
184{
185	memblock_reserve(0x30003000, 0x1000);
186	memblock_reserve(0x30081000, 0x1000);
187}
188
189static void __init rx3715_init_machine(void)
190{
191#ifdef CONFIG_PM_H1940
192	memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
193#endif
194	s3c_pm_init();
195
196	s3c_nand_set_platdata(&rx3715_nand_info);
197	s3c24xx_fb_set_platdata(&rx3715_fb_info);
198	/* Configure the I2S pins (GPE0...GPE4) in correct mode */
199	s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
200			      S3C_GPIO_PULL_NONE);
201	platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
202}
203
204MACHINE_START(RX3715, "IPAQ-RX3715")
205	/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
206	.atag_offset	= 0x100,
207	.nr_irqs	= NR_IRQS_S3C2440,
208	.map_io		= rx3715_map_io,
209	.reserve	= rx3715_reserve,
210	.init_irq	= s3c2440_init_irq,
211	.init_machine	= rx3715_init_machine,
212	.init_time	= rx3715_init_time,
213MACHINE_END