1// SPDX-License-Identifier: GPL-2.0
  2//
  3// Copyright 2008 Openmoko, Inc.
  4// Copyright 2008 Simtec Electronics
  5//	Ben Dooks <ben@simtec.co.uk>
  6//	http://armlinux.simtec.co.uk/
  7// Copyright 2009 Kwangwoo Lee
  8//	Kwangwoo Lee <kwangwoo.lee@gmail.com>
  9
 10#include <linux/kernel.h>
 11#include <linux/types.h>
 12#include <linux/interrupt.h>
 13#include <linux/list.h>
 14#include <linux/timer.h>
 15#include <linux/init.h>
 16#include <linux/serial_core.h>
 17#include <linux/serial_s3c.h>
 18#include <linux/platform_device.h>
 19#include <linux/io.h>
 20#include <linux/i2c.h>
 21#include <linux/fb.h>
 22#include <linux/gpio.h>
 23#include <linux/delay.h>
 24#include <linux/dm9000.h>
 25
 26#include <video/platform_lcd.h>
 27#include <video/samsung_fimd.h>
 28
 29#include <asm/mach/arch.h>
 30#include <asm/mach/map.h>
 31#include <asm/mach/irq.h>
 32
 33#include "map.h"
 34
 35#include <asm/irq.h>
 36#include <asm/mach-types.h>
 37
 38#include <linux/platform_data/i2c-s3c2410.h>
 39#include "fb.h"
 40
 41#include "devs.h"
 42#include "cpu.h"
 43#include "irqs.h"
 44#include "regs-gpio.h"
 45#include "gpio-samsung.h"
 46
 47#include "s3c64xx.h"
 48#include "regs-modem-s3c64xx.h"
 49
 50/* DM9000 */
 51#define ANW6410_PA_DM9000	(0x18000000)
 52
 53/* A hardware buffer to control external devices is mapped at 0x30000000.
 54 * It can not be read. So current status must be kept in anw6410_extdev_status.
 55 */
 56#define ANW6410_VA_EXTDEV	S3C_ADDR(0x02000000)
 57#define ANW6410_PA_EXTDEV	(0x30000000)
 58
 59#define ANW6410_EN_DM9000	(1<<11)
 60#define ANW6410_EN_LCD		(1<<14)
 61
 62static __u32 anw6410_extdev_status;
 63
 64static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
 65	[0] = {
 66		.hwport	     = 0,
 67		.flags	     = 0,
 68		.ucon	     = 0x3c5,
 69		.ulcon	     = 0x03,
 70		.ufcon	     = 0x51,
 71	},
 72	[1] = {
 73		.hwport	     = 1,
 74		.flags	     = 0,
 75		.ucon	     = 0x3c5,
 76		.ulcon	     = 0x03,
 77		.ufcon	     = 0x51,
 78	},
 79};
 80
 81/* framebuffer and LCD setup. */
 82static void __init anw6410_lcd_mode_set(void)
 83{
 84	u32 tmp;
 85
 86	/* set the LCD type */
 87	tmp = __raw_readl(S3C64XX_SPCON);
 88	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
 89	tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
 90	__raw_writel(tmp, S3C64XX_SPCON);
 91
 92	/* remove the LCD bypass */
 93	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
 94	tmp &= ~MIFPCON_LCD_BYPASS;
 95	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
 96}
 97
 98/* GPF1 = LCD panel power
 99 * GPF4 = LCD backlight control
100 */
101static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
102				   unsigned int power)
103{
104	if (power) {
105		anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
106		__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
107
108		gpio_direction_output(S3C64XX_GPF(1), 1);
109		gpio_direction_output(S3C64XX_GPF(4), 1);
110	} else {
111		anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
112		__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
113
114		gpio_direction_output(S3C64XX_GPF(1), 0);
115		gpio_direction_output(S3C64XX_GPF(4), 0);
116	}
117}
118
119static struct plat_lcd_data anw6410_lcd_power_data = {
120	.set_power	= anw6410_lcd_power_set,
121};
122
123static struct platform_device anw6410_lcd_powerdev = {
124	.name			= "platform-lcd",
125	.dev.parent		= &s3c_device_fb.dev,
126	.dev.platform_data	= &anw6410_lcd_power_data,
127};
128
129static struct s3c_fb_pd_win anw6410_fb_win0 = {
130	.max_bpp	= 32,
131	.default_bpp	= 16,
132	.xres		= 800,
133	.yres		= 480,
134};
135
136static struct fb_videomode anw6410_lcd_timing = {
137	.left_margin	= 8,
138	.right_margin	= 13,
139	.upper_margin	= 7,
140	.lower_margin	= 5,
141	.hsync_len	= 3,
142	.vsync_len	= 1,
143	.xres		= 800,
144	.yres		= 480,
145};
146
147/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
148static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
149	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
150	.vtiming	= &anw6410_lcd_timing,
151	.win[0]		= &anw6410_fb_win0,
152	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
153	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
154};
155
156/* DM9000AEP 10/100 ethernet controller */
157static void __init anw6410_dm9000_enable(void)
158{
159	anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
160	__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
161}
162
163static struct resource anw6410_dm9000_resource[] = {
164	[0] = DEFINE_RES_MEM(ANW6410_PA_DM9000, 4),
165	[1] = DEFINE_RES_MEM(ANW6410_PA_DM9000 + 4, 501),
166	[2] = DEFINE_RES_NAMED(IRQ_EINT(15), 1, NULL, IORESOURCE_IRQ \
167					| IRQF_TRIGGER_HIGH),
168};
169
170static struct dm9000_plat_data anw6410_dm9000_pdata = {
171	.flags	  = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
172	/* dev_addr can be set to provide hwaddr. */
173};
174
175static struct platform_device anw6410_device_eth = {
176	.name	= "dm9000",
177	.id	= -1,
178	.num_resources	= ARRAY_SIZE(anw6410_dm9000_resource),
179	.resource	= anw6410_dm9000_resource,
180	.dev	= {
181		.platform_data  = &anw6410_dm9000_pdata,
182	},
183};
184
185static struct map_desc anw6410_iodesc[] __initdata = {
186	{
187		.virtual	= (unsigned long)ANW6410_VA_EXTDEV,
188		.pfn		= __phys_to_pfn(ANW6410_PA_EXTDEV),
189		.length		= SZ_64K,
190		.type		= MT_DEVICE,
191	},
192};
193
194static struct platform_device *anw6410_devices[] __initdata = {
195	&s3c_device_fb,
196	&anw6410_lcd_powerdev,
197	&anw6410_device_eth,
198};
199
200static void __init anw6410_map_io(void)
201{
202	s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
203	s3c64xx_set_xtal_freq(12000000);
204	s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
205	s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
206
207	anw6410_lcd_mode_set();
208}
209
210static void __init anw6410_machine_init(void)
211{
212	s3c_fb_set_platdata(&anw6410_lcd_pdata);
213
214	gpio_request(S3C64XX_GPF(1), "panel power");
215	gpio_request(S3C64XX_GPF(4), "LCD backlight");
216
217	anw6410_dm9000_enable();
218
219	platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
220}
221
222MACHINE_START(ANW6410, "A&W6410")
223	/* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
224	.atag_offset	= 0x100,
225	.nr_irqs	= S3C64XX_NR_IRQS,
226	.init_irq	= s3c6410_init_irq,
227	.map_io		= anw6410_map_io,
228	.init_machine	= anw6410_machine_init,
229	.init_time	= s3c64xx_timer_init,
230MACHINE_END