Loading...
Note: File does not exist in v6.13.7.
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __ASM_ARCH_REGS_UART_H
3#define __ASM_ARCH_REGS_UART_H
4
5#include "pxa-regs.h"
6
7/*
8 * UARTs
9 */
10
11/* Full Function UART (FFUART) */
12#define FFUART FFRBR
13#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
14#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
15#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
16#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
17#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
18#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
19#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
20#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
21#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
22#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
23#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
24#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
25#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
26
27/* Bluetooth UART (BTUART) */
28#define BTUART BTRBR
29#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
30#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
31#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
32#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
33#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
34#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
35#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
36#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
37#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
38#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
39#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
40#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
41#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
42
43/* Standard UART (STUART) */
44#define STUART STRBR
45#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
46#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
47#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
48#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
49#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
50#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
51#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
52#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
53#define STMSR __REG(0x40700018) /* Reserved */
54#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
55#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
56#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
57#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
58
59/* Hardware UART (HWUART) */
60#define HWUART HWRBR
61#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
62#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
63#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
64#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
65#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
66#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
67#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
68#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
69#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
70#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
71#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
72#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
73#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
74#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
75#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
76#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
77
78#define IER_DMAE (1 << 7) /* DMA Requests Enable */
79#define IER_UUE (1 << 6) /* UART Unit Enable */
80#define IER_NRZE (1 << 5) /* NRZ coding Enable */
81#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
82#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
83#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
84#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
85#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
86
87#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
88#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
89#define IIR_TOD (1 << 3) /* Time Out Detected */
90#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
91#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
92#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
93
94#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
95#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
96#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
97#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
98#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
99#define FCR_ITL_1 (0)
100#define FCR_ITL_8 (FCR_ITL1)
101#define FCR_ITL_16 (FCR_ITL2)
102#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
103
104#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
105#define LCR_SB (1 << 6) /* Set Break */
106#define LCR_STKYP (1 << 5) /* Sticky Parity */
107#define LCR_EPS (1 << 4) /* Even Parity Select */
108#define LCR_PEN (1 << 3) /* Parity Enable */
109#define LCR_STB (1 << 2) /* Stop Bit */
110#define LCR_WLS1 (1 << 1) /* Word Length Select */
111#define LCR_WLS0 (1 << 0) /* Word Length Select */
112
113#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
114#define LSR_TEMT (1 << 6) /* Transmitter Empty */
115#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
116#define LSR_BI (1 << 4) /* Break Interrupt */
117#define LSR_FE (1 << 3) /* Framing Error */
118#define LSR_PE (1 << 2) /* Parity Error */
119#define LSR_OE (1 << 1) /* Overrun Error */
120#define LSR_DR (1 << 0) /* Data Ready */
121
122#define MCR_LOOP (1 << 4)
123#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
124#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
125#define MCR_RTS (1 << 1) /* Request to Send */
126#define MCR_DTR (1 << 0) /* Data Terminal Ready */
127
128#define MSR_DCD (1 << 7) /* Data Carrier Detect */
129#define MSR_RI (1 << 6) /* Ring Indicator */
130#define MSR_DSR (1 << 5) /* Data Set Ready */
131#define MSR_CTS (1 << 4) /* Clear To Send */
132#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
133#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
134#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
135#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
136
137/*
138 * IrSR (Infrared Selection Register)
139 */
140#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
141#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
142#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
143#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
144#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
145
146#endif /* __ASM_ARCH_REGS_UART_H */