1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   4 *
   5 * Copyright (C) 2009-2011 Nokia Corporation
   6 * Copyright (C) 2012 Texas Instruments, Inc.
   7 * Paul Walmsley
   8 *
   9 * The data in this file should be completely autogeneratable from
  10 * the TI hardware database or other technical documentation.
  11 *
  12 * XXX these should be marked initdata for multi-OMAP kernels
  13 */
  14
  15#include <linux/platform_data/i2c-omap.h>
  16#include <linux/power/smartreflex.h>
  17#include <linux/platform_data/hsmmc-omap.h>
  18
  19#include "l3_3xxx.h"
  20#include "l4_3xxx.h"
  21
  22#include "soc.h"
  23#include "omap_hwmod.h"
  24#include "omap_hwmod_common_data.h"
  25#include "prm-regbits-34xx.h"
  26#include "cm-regbits-34xx.h"
  27
  28#include "i2c.h"
  29#include "wd_timer.h"
 
  30
  31/*
  32 * OMAP3xxx hardware module integration data
  33 *
  34 * All of the data in this section should be autogeneratable from the
  35 * TI hardware database or other technical documentation.  Data that
  36 * is driver-specific or driver-kernel integration-specific belongs
  37 * elsewhere.
  38 */
  39
  40#define AM35XX_IPSS_USBOTGSS_BASE      0x5C040000
  41
  42/*
  43 * IP blocks
  44 */
  45
  46/* L3 */
  47
  48static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  49	.name		= "l3_main",
  50	.class		= &l3_hwmod_class,
  51	.flags		= HWMOD_NO_IDLEST,
  52};
  53
  54/* L4 CORE */
  55static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  56	.name		= "l4_core",
  57	.class		= &l4_hwmod_class,
  58	.flags		= HWMOD_NO_IDLEST,
  59};
  60
  61/* L4 PER */
  62static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  63	.name		= "l4_per",
  64	.class		= &l4_hwmod_class,
  65	.flags		= HWMOD_NO_IDLEST,
  66};
  67
  68/* L4 WKUP */
  69static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  70	.name		= "l4_wkup",
  71	.class		= &l4_hwmod_class,
  72	.flags		= HWMOD_NO_IDLEST,
  73};
  74
  75/* L4 SEC */
  76static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  77	.name		= "l4_sec",
  78	.class		= &l4_hwmod_class,
  79	.flags		= HWMOD_NO_IDLEST,
  80};
  81
  82/* MPU */
  83
  84static struct omap_hwmod omap3xxx_mpu_hwmod = {
  85	.name		= "mpu",
  86	.class		= &mpu_hwmod_class,
  87	.main_clk	= "arm_fck",
  88};
  89
  90/* IVA2 (IVA2) */
  91static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
  92	{ .name = "logic", .rst_shift = 0, .st_shift = 8 },
  93	{ .name = "seq0", .rst_shift = 1, .st_shift = 9 },
  94	{ .name = "seq1", .rst_shift = 2, .st_shift = 10 },
  95};
  96
  97static struct omap_hwmod omap3xxx_iva_hwmod = {
  98	.name		= "iva",
  99	.class		= &iva_hwmod_class,
 100	.clkdm_name	= "iva2_clkdm",
 101	.rst_lines	= omap3xxx_iva_resets,
 102	.rst_lines_cnt	= ARRAY_SIZE(omap3xxx_iva_resets),
 103	.main_clk	= "iva2_ck",
 104	.prcm = {
 105		.omap2 = {
 106			.module_offs = OMAP3430_IVA2_MOD,
 107			.idlest_reg_id = 1,
 108			.idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 109		},
 110	},
 111};
 112
 113/*
 114 * 'debugss' class
 115 * debug and emulation sub system
 116 */
 117
 118static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
 119	.name	= "debugss",
 120};
 121
 122/* debugss */
 123static struct omap_hwmod omap3xxx_debugss_hwmod = {
 124	.name		= "debugss",
 125	.class		= &omap3xxx_debugss_hwmod_class,
 126	.clkdm_name	= "emu_clkdm",
 127	.main_clk	= "emu_src_ck",
 128	.flags		= HWMOD_NO_IDLEST,
 129};
 130
 131/* timer class */
 132static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 133	.rev_offs	= 0x0000,
 134	.sysc_offs	= 0x0010,
 135	.syss_offs	= 0x0014,
 136	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 137			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 138			   SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
 139			   SYSS_HAS_RESET_STATUS),
 140	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 141	.sysc_fields	= &omap_hwmod_sysc_type1,
 142};
 143
 144static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 145	.name = "timer",
 146	.sysc = &omap3xxx_timer_sysc,
 147};
 148
 149/* timer3 */
 150static struct omap_hwmod omap3xxx_timer3_hwmod = {
 151	.name		= "timer3",
 152	.main_clk	= "gpt3_fck",
 153	.prcm		= {
 154		.omap2 = {
 155			.module_offs = OMAP3430_PER_MOD,
 156			.idlest_reg_id = 1,
 157			.idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 158		},
 159	},
 160	.class		= &omap3xxx_timer_hwmod_class,
 161	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
 162};
 163
 164/* timer4 */
 165static struct omap_hwmod omap3xxx_timer4_hwmod = {
 166	.name		= "timer4",
 167	.main_clk	= "gpt4_fck",
 168	.prcm		= {
 169		.omap2 = {
 170			.module_offs = OMAP3430_PER_MOD,
 171			.idlest_reg_id = 1,
 172			.idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 173		},
 174	},
 175	.class		= &omap3xxx_timer_hwmod_class,
 176	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
 177};
 178
 179/* timer5 */
 180static struct omap_hwmod omap3xxx_timer5_hwmod = {
 181	.name		= "timer5",
 182	.main_clk	= "gpt5_fck",
 183	.prcm		= {
 184		.omap2 = {
 185			.module_offs = OMAP3430_PER_MOD,
 186			.idlest_reg_id = 1,
 187			.idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 188		},
 189	},
 190	.class		= &omap3xxx_timer_hwmod_class,
 191	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
 192};
 193
 194/* timer6 */
 195static struct omap_hwmod omap3xxx_timer6_hwmod = {
 196	.name		= "timer6",
 197	.main_clk	= "gpt6_fck",
 198	.prcm		= {
 199		.omap2 = {
 200			.module_offs = OMAP3430_PER_MOD,
 201			.idlest_reg_id = 1,
 202			.idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 203		},
 204	},
 205	.class		= &omap3xxx_timer_hwmod_class,
 206	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
 207};
 208
 209/* timer7 */
 210static struct omap_hwmod omap3xxx_timer7_hwmod = {
 211	.name		= "timer7",
 212	.main_clk	= "gpt7_fck",
 213	.prcm		= {
 214		.omap2 = {
 215			.module_offs = OMAP3430_PER_MOD,
 216			.idlest_reg_id = 1,
 217			.idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 218		},
 219	},
 220	.class		= &omap3xxx_timer_hwmod_class,
 221	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
 222};
 223
 224/* timer8 */
 225static struct omap_hwmod omap3xxx_timer8_hwmod = {
 226	.name		= "timer8",
 227	.main_clk	= "gpt8_fck",
 228	.prcm		= {
 229		.omap2 = {
 230			.module_offs = OMAP3430_PER_MOD,
 231			.idlest_reg_id = 1,
 232			.idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 233		},
 234	},
 235	.class		= &omap3xxx_timer_hwmod_class,
 236	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
 237};
 238
 239/* timer9 */
 240static struct omap_hwmod omap3xxx_timer9_hwmod = {
 241	.name		= "timer9",
 242	.main_clk	= "gpt9_fck",
 243	.prcm		= {
 244		.omap2 = {
 245			.module_offs = OMAP3430_PER_MOD,
 246			.idlest_reg_id = 1,
 247			.idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 248		},
 249	},
 250	.class		= &omap3xxx_timer_hwmod_class,
 251	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
 252};
 253
 254/* timer10 */
 255static struct omap_hwmod omap3xxx_timer10_hwmod = {
 256	.name		= "timer10",
 257	.main_clk	= "gpt10_fck",
 258	.prcm		= {
 259		.omap2 = {
 260			.module_offs = CORE_MOD,
 261			.idlest_reg_id = 1,
 262			.idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 263		},
 264	},
 265	.class		= &omap3xxx_timer_hwmod_class,
 266	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
 267};
 268
 269/* timer11 */
 270static struct omap_hwmod omap3xxx_timer11_hwmod = {
 271	.name		= "timer11",
 272	.main_clk	= "gpt11_fck",
 273	.prcm		= {
 274		.omap2 = {
 275			.module_offs = CORE_MOD,
 276			.idlest_reg_id = 1,
 277			.idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 278		},
 279	},
 280	.class		= &omap3xxx_timer_hwmod_class,
 281	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
 282};
 283
 284/*
 285 * 'wd_timer' class
 286 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 287 * overflow condition
 288 */
 289
 290static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 291	.rev_offs	= 0x0000,
 292	.sysc_offs	= 0x0010,
 293	.syss_offs	= 0x0014,
 294	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 295			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 296			   SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 297			   SYSS_HAS_RESET_STATUS),
 298	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 299	.sysc_fields    = &omap_hwmod_sysc_type1,
 300};
 301
 302/* I2C common */
 303static struct omap_hwmod_class_sysconfig i2c_sysc = {
 304	.rev_offs	= 0x00,
 305	.sysc_offs	= 0x20,
 306	.syss_offs	= 0x10,
 307	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 308			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 309			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 310	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 311	.sysc_fields    = &omap_hwmod_sysc_type1,
 312};
 313
 314static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 315	.name		= "wd_timer",
 316	.sysc		= &omap3xxx_wd_timer_sysc,
 317	.pre_shutdown	= &omap2_wd_timer_disable,
 318	.reset		= &omap2_wd_timer_reset,
 319};
 320
 321static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 322	.name		= "wd_timer2",
 323	.class		= &omap3xxx_wd_timer_hwmod_class,
 324	.main_clk	= "wdt2_fck",
 325	.prcm		= {
 326		.omap2 = {
 327			.module_offs = WKUP_MOD,
 328			.idlest_reg_id = 1,
 329			.idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 330		},
 331	},
 332	/*
 333	 * XXX: Use software supervised mode, HW supervised smartidle seems to
 334	 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 335	 */
 336	.flags		= HWMOD_SWSUP_SIDLE,
 337};
 338
 339/* UART1 */
 340static struct omap_hwmod omap3xxx_uart1_hwmod = {
 341	.name		= "uart1",
 342	.main_clk	= "uart1_fck",
 343	.flags		= DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
 344	.prcm		= {
 345		.omap2 = {
 346			.module_offs = CORE_MOD,
 347			.idlest_reg_id = 1,
 348			.idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 349		},
 350	},
 351	.class		= &omap2_uart_class,
 352};
 353
 354/* UART2 */
 355static struct omap_hwmod omap3xxx_uart2_hwmod = {
 356	.name		= "uart2",
 357	.main_clk	= "uart2_fck",
 358	.flags		= DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
 359	.prcm		= {
 360		.omap2 = {
 361			.module_offs = CORE_MOD,
 362			.idlest_reg_id = 1,
 363			.idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 364		},
 365	},
 366	.class		= &omap2_uart_class,
 367};
 368
 369/* UART3 */
 370static struct omap_hwmod omap3xxx_uart3_hwmod = {
 371	.name		= "uart3",
 372	.main_clk	= "uart3_fck",
 373	.flags		= DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
 374				HWMOD_SWSUP_SIDLE,
 375	.prcm		= {
 376		.omap2 = {
 377			.module_offs = OMAP3430_PER_MOD,
 378			.idlest_reg_id = 1,
 379			.idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 380		},
 381	},
 382	.class		= &omap2_uart_class,
 383};
 384
 385/* UART4 */
 386
 387
 388static struct omap_hwmod omap36xx_uart4_hwmod = {
 389	.name		= "uart4",
 390	.main_clk	= "uart4_fck",
 391	.flags		= DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
 392	.prcm		= {
 393		.omap2 = {
 394			.module_offs = OMAP3430_PER_MOD,
 395			.idlest_reg_id = 1,
 396			.idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 397		},
 398	},
 399	.class		= &omap2_uart_class,
 400};
 401
 402
 403
 404/*
 405 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 406 * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 407 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 408 * should not be needed.  The functional clock structure of the AM35xx
 409 * UART4 is extremely unclear and opaque; it is unclear what the role
 410 * of uart1/2_fck is for the UART4.  Any clarification from either
 411 * empirical testing or the AM3505/3517 hardware designers would be
 412 * most welcome.
 413 */
 414static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 415	{ .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 416};
 417
 418static struct omap_hwmod am35xx_uart4_hwmod = {
 419	.name		= "uart4",
 420	.main_clk	= "uart4_fck",
 421	.prcm		= {
 422		.omap2 = {
 423			.module_offs = CORE_MOD,
 424			.idlest_reg_id = 1,
 425			.idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 426		},
 427	},
 428	.opt_clks	= am35xx_uart4_opt_clks,
 429	.opt_clks_cnt	= ARRAY_SIZE(am35xx_uart4_opt_clks),
 430	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 431	.class		= &omap2_uart_class,
 432};
 433
 434static struct omap_hwmod_class i2c_class = {
 435	.name	= "i2c",
 436	.sysc	= &i2c_sysc,
 437	.reset	= &omap_i2c_reset,
 438};
 439
 440/* dss */
 441static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 442	/*
 443	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 444	 * driver does not use these clocks.
 445	 */
 446	{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
 447	{ .role = "tv_clk", .clk = "dss_tv_fck" },
 448	/* required only on OMAP3430 */
 449	{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 450};
 451
 452static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 453	.name		= "dss_core",
 454	.class		= &omap2_dss_hwmod_class,
 455	.main_clk	= "dss1_alwon_fck", /* instead of dss_fck */
 456	.prcm		= {
 457		.omap2 = {
 458			.module_offs = OMAP3430_DSS_MOD,
 459			.idlest_reg_id = 1,
 460		},
 461	},
 462	.opt_clks	= dss_opt_clks,
 463	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 464	.flags		= HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 465};
 466
 467static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 468	.name		= "dss_core",
 469	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 470	.class		= &omap2_dss_hwmod_class,
 471	.main_clk	= "dss1_alwon_fck", /* instead of dss_fck */
 472	.prcm		= {
 473		.omap2 = {
 474			.module_offs = OMAP3430_DSS_MOD,
 475			.idlest_reg_id = 1,
 476			.idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 477		},
 478	},
 479	.opt_clks	= dss_opt_clks,
 480	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 481};
 482
 483/*
 484 * 'dispc' class
 485 * display controller
 486 */
 487
 488static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 489	.rev_offs	= 0x0000,
 490	.sysc_offs	= 0x0010,
 491	.syss_offs	= 0x0014,
 492	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 493			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 494			   SYSC_HAS_ENAWAKEUP),
 495	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 496			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 497	.sysc_fields	= &omap_hwmod_sysc_type1,
 498};
 499
 500static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 501	.name	= "dispc",
 502	.sysc	= &omap3_dispc_sysc,
 503};
 504
 505static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 506	.name		= "dss_dispc",
 507	.class		= &omap3_dispc_hwmod_class,
 508	.main_clk	= "dss1_alwon_fck",
 509	.prcm		= {
 510		.omap2 = {
 511			.module_offs = OMAP3430_DSS_MOD,
 512		},
 513	},
 514	.flags		= HWMOD_NO_IDLEST,
 515	.dev_attr	= &omap2_3_dss_dispc_dev_attr,
 516};
 517
 518/*
 519 * 'dsi' class
 520 * display serial interface controller
 521 */
 522
 523static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
 524	.rev_offs	= 0x0000,
 525	.sysc_offs	= 0x0010,
 526	.syss_offs	= 0x0014,
 527	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 528			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 529			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 530	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 531	.sysc_fields	= &omap_hwmod_sysc_type1,
 532};
 533
 534static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 535	.name = "dsi",
 536	.sysc	= &omap3xxx_dsi_sysc,
 537};
 538
 539/* dss_dsi1 */
 540static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 541	{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
 542};
 543
 544static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 545	.name		= "dss_dsi1",
 546	.class		= &omap3xxx_dsi_hwmod_class,
 547	.main_clk	= "dss1_alwon_fck",
 548	.prcm		= {
 549		.omap2 = {
 550			.module_offs = OMAP3430_DSS_MOD,
 551		},
 552	},
 553	.opt_clks	= dss_dsi1_opt_clks,
 554	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi1_opt_clks),
 555	.flags		= HWMOD_NO_IDLEST,
 556};
 557
 558static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 559	{ .role = "ick", .clk = "dss_ick" },
 560};
 561
 562static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 563	.name		= "dss_rfbi",
 564	.class		= &omap2_rfbi_hwmod_class,
 565	.main_clk	= "dss1_alwon_fck",
 566	.prcm		= {
 567		.omap2 = {
 568			.module_offs = OMAP3430_DSS_MOD,
 569		},
 570	},
 571	.opt_clks	= dss_rfbi_opt_clks,
 572	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
 573	.flags		= HWMOD_NO_IDLEST,
 574};
 575
 576static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 577	/* required only on OMAP3430 */
 578	{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 579};
 580
 581static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 582	.name		= "dss_venc",
 583	.class		= &omap2_venc_hwmod_class,
 584	.main_clk	= "dss_tv_fck",
 585	.prcm		= {
 586		.omap2 = {
 587			.module_offs = OMAP3430_DSS_MOD,
 588		},
 589	},
 590	.opt_clks	= dss_venc_opt_clks,
 591	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
 592	.flags		= HWMOD_NO_IDLEST,
 593};
 594
 595/* I2C1 */
 596static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 597	.name		= "i2c1",
 598	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 599	.main_clk	= "i2c1_fck",
 600	.prcm		= {
 601		.omap2 = {
 602			.module_offs = CORE_MOD,
 603			.idlest_reg_id = 1,
 604			.idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 605		},
 606	},
 607	.class		= &i2c_class,
 608};
 609
 610/* I2C2 */
 611static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 612	.name		= "i2c2",
 613	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 614	.main_clk	= "i2c2_fck",
 615	.prcm		= {
 616		.omap2 = {
 617			.module_offs = CORE_MOD,
 618			.idlest_reg_id = 1,
 619			.idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 620		},
 621	},
 622	.class		= &i2c_class,
 623};
 624
 625/* I2C3 */
 626static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 627	.name		= "i2c3",
 628	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 629	.main_clk	= "i2c3_fck",
 630	.prcm		= {
 631		.omap2 = {
 632			.module_offs = CORE_MOD,
 633			.idlest_reg_id = 1,
 634			.idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 635		},
 636	},
 637	.class		= &i2c_class,
 638};
 639
 640/*
 641 * 'gpio' class
 642 * general purpose io module
 643 */
 644
 645static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 646	.rev_offs	= 0x0000,
 647	.sysc_offs	= 0x0010,
 648	.syss_offs	= 0x0014,
 649	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 650			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 651			   SYSS_HAS_RESET_STATUS),
 652	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 653	.sysc_fields    = &omap_hwmod_sysc_type1,
 654};
 655
 656static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 657	.name = "gpio",
 658	.sysc = &omap3xxx_gpio_sysc,
 659};
 660
 661/* gpio1 */
 662static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 663	{ .role = "dbclk", .clk = "gpio1_dbck", },
 664};
 665
 666static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 667	.name		= "gpio1",
 668	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 669	.main_clk	= "gpio1_ick",
 670	.opt_clks	= gpio1_opt_clks,
 671	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
 672	.prcm		= {
 673		.omap2 = {
 674			.module_offs = WKUP_MOD,
 675			.idlest_reg_id = 1,
 676			.idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 677		},
 678	},
 679	.class		= &omap3xxx_gpio_hwmod_class,
 680};
 681
 682/* gpio2 */
 683static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 684	{ .role = "dbclk", .clk = "gpio2_dbck", },
 685};
 686
 687static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 688	.name		= "gpio2",
 689	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 690	.main_clk	= "gpio2_ick",
 691	.opt_clks	= gpio2_opt_clks,
 692	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
 693	.prcm		= {
 694		.omap2 = {
 695			.module_offs = OMAP3430_PER_MOD,
 696			.idlest_reg_id = 1,
 697			.idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 698		},
 699	},
 700	.class		= &omap3xxx_gpio_hwmod_class,
 701};
 702
 703/* gpio3 */
 704static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 705	{ .role = "dbclk", .clk = "gpio3_dbck", },
 706};
 707
 708static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 709	.name		= "gpio3",
 710	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 711	.main_clk	= "gpio3_ick",
 712	.opt_clks	= gpio3_opt_clks,
 713	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
 714	.prcm		= {
 715		.omap2 = {
 716			.module_offs = OMAP3430_PER_MOD,
 717			.idlest_reg_id = 1,
 718			.idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 719		},
 720	},
 721	.class		= &omap3xxx_gpio_hwmod_class,
 722};
 723
 724/* gpio4 */
 725static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 726	{ .role = "dbclk", .clk = "gpio4_dbck", },
 727};
 728
 729static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 730	.name		= "gpio4",
 731	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 732	.main_clk	= "gpio4_ick",
 733	.opt_clks	= gpio4_opt_clks,
 734	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
 735	.prcm		= {
 736		.omap2 = {
 737			.module_offs = OMAP3430_PER_MOD,
 738			.idlest_reg_id = 1,
 739			.idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
 740		},
 741	},
 742	.class		= &omap3xxx_gpio_hwmod_class,
 743};
 744
 745/* gpio5 */
 746
 747static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 748	{ .role = "dbclk", .clk = "gpio5_dbck", },
 749};
 750
 751static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 752	.name		= "gpio5",
 753	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 754	.main_clk	= "gpio5_ick",
 755	.opt_clks	= gpio5_opt_clks,
 756	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
 757	.prcm		= {
 758		.omap2 = {
 759			.module_offs = OMAP3430_PER_MOD,
 760			.idlest_reg_id = 1,
 761			.idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
 762		},
 763	},
 764	.class		= &omap3xxx_gpio_hwmod_class,
 765};
 766
 767/* gpio6 */
 768
 769static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 770	{ .role = "dbclk", .clk = "gpio6_dbck", },
 771};
 772
 773static struct omap_hwmod omap3xxx_gpio6_hwmod = {
 774	.name		= "gpio6",
 775	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 776	.main_clk	= "gpio6_ick",
 777	.opt_clks	= gpio6_opt_clks,
 778	.opt_clks_cnt	= ARRAY_SIZE(gpio6_opt_clks),
 779	.prcm		= {
 780		.omap2 = {
 781			.module_offs = OMAP3430_PER_MOD,
 782			.idlest_reg_id = 1,
 783			.idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
 784		},
 785	},
 786	.class		= &omap3xxx_gpio_hwmod_class,
 787};
 788
 789/*
 790 * 'mcbsp' class
 791 * multi channel buffered serial port controller
 792 */
 793
 794static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
 795	.rev_offs	= -ENODEV,
 796	.sysc_offs	= 0x008c,
 797	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
 798			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 799	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 800	.sysc_fields	= &omap_hwmod_sysc_type1,
 801};
 802
 803static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
 804	.name = "mcbsp",
 805	.sysc = &omap3xxx_mcbsp_sysc,
 806};
 807
 808/* McBSP functional clock mapping */
 809static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
 810	{ .role = "pad_fck", .clk = "mcbsp_clks" },
 811	{ .role = "prcm_fck", .clk = "core_96m_fck" },
 812};
 813
 814static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
 815	{ .role = "pad_fck", .clk = "mcbsp_clks" },
 816	{ .role = "prcm_fck", .clk = "per_96m_fck" },
 817};
 818
 819/* mcbsp1 */
 820static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
 821	.name		= "mcbsp1",
 822	.class		= &omap3xxx_mcbsp_hwmod_class,
 823	.main_clk	= "mcbsp1_fck",
 824	.prcm		= {
 825		.omap2 = {
 826			.module_offs = CORE_MOD,
 827			.idlest_reg_id = 1,
 828			.idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
 829		},
 830	},
 831	.opt_clks	= mcbsp15_opt_clks,
 832	.opt_clks_cnt	= ARRAY_SIZE(mcbsp15_opt_clks),
 833};
 834
 835/* mcbsp2 */
 836static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
 837	.name		= "mcbsp2",
 838	.class		= &omap3xxx_mcbsp_hwmod_class,
 839	.main_clk	= "mcbsp2_fck",
 840	.prcm		= {
 841		.omap2 = {
 842			.module_offs = OMAP3430_PER_MOD,
 843			.idlest_reg_id = 1,
 844			.idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
 845		},
 846	},
 847	.opt_clks	= mcbsp234_opt_clks,
 848	.opt_clks_cnt	= ARRAY_SIZE(mcbsp234_opt_clks),
 849};
 850
 851/* mcbsp3 */
 852static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
 853	.name		= "mcbsp3",
 854	.class		= &omap3xxx_mcbsp_hwmod_class,
 855	.main_clk	= "mcbsp3_fck",
 856	.prcm		= {
 857		.omap2 = {
 858			.module_offs = OMAP3430_PER_MOD,
 859			.idlest_reg_id = 1,
 860			.idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
 861		},
 862	},
 863	.opt_clks	= mcbsp234_opt_clks,
 864	.opt_clks_cnt	= ARRAY_SIZE(mcbsp234_opt_clks),
 865};
 866
 867/* mcbsp4 */
 868static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
 869	.name		= "mcbsp4",
 870	.class		= &omap3xxx_mcbsp_hwmod_class,
 871	.main_clk	= "mcbsp4_fck",
 872	.prcm		= {
 873		.omap2 = {
 874			.module_offs = OMAP3430_PER_MOD,
 875			.idlest_reg_id = 1,
 876			.idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
 877		},
 878	},
 879	.opt_clks	= mcbsp234_opt_clks,
 880	.opt_clks_cnt	= ARRAY_SIZE(mcbsp234_opt_clks),
 881};
 882
 883/* mcbsp5 */
 884static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
 885	.name		= "mcbsp5",
 886	.class		= &omap3xxx_mcbsp_hwmod_class,
 887	.main_clk	= "mcbsp5_fck",
 888	.prcm		= {
 889		.omap2 = {
 890			.module_offs = CORE_MOD,
 891			.idlest_reg_id = 1,
 892			.idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
 893		},
 894	},
 895	.opt_clks	= mcbsp15_opt_clks,
 896	.opt_clks_cnt	= ARRAY_SIZE(mcbsp15_opt_clks),
 897};
 898
 899/* 'mcbsp sidetone' class */
 900static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
 901	.rev_offs	= -ENODEV,
 902	.sysc_offs	= 0x0010,
 903	.sysc_flags	= SYSC_HAS_AUTOIDLE,
 904	.sysc_fields	= &omap_hwmod_sysc_type1,
 905};
 906
 907static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
 908	.name = "mcbsp_sidetone",
 909	.sysc = &omap3xxx_mcbsp_sidetone_sysc,
 910};
 911
 912/* mcbsp2_sidetone */
 913static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
 914	.name		= "mcbsp2_sidetone",
 915	.class		= &omap3xxx_mcbsp_sidetone_hwmod_class,
 916	.main_clk	= "mcbsp2_ick",
 917	.flags		= HWMOD_NO_IDLEST,
 918};
 919
 920/* mcbsp3_sidetone */
 921static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
 922	.name		= "mcbsp3_sidetone",
 923	.class		= &omap3xxx_mcbsp_sidetone_hwmod_class,
 924	.main_clk	= "mcbsp3_ick",
 925	.flags		= HWMOD_NO_IDLEST,
 926};
 927
 928/* SR common */
 929static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
 930	.rev_offs	= -ENODEV,
 931	.sysc_offs	= 0x24,
 932	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
 933	.sysc_fields	= &omap34xx_sr_sysc_fields,
 934};
 935
 936static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
 937	.name = "smartreflex",
 938	.sysc = &omap34xx_sr_sysc,
 939};
 940
 941static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
 942	.rev_offs	= -ENODEV,
 943	.sysc_offs	= 0x38,
 944	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 945	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 946			SYSC_NO_CACHE),
 947	.sysc_fields	= &omap36xx_sr_sysc_fields,
 948};
 949
 950static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
 951	.name = "smartreflex",
 952	.sysc = &omap36xx_sr_sysc,
 953};
 954
 955/* SR1 */
 956static struct omap_smartreflex_dev_attr sr1_dev_attr = {
 957	.sensor_voltdm_name   = "mpu_iva",
 958};
 959
 960
 961static struct omap_hwmod omap34xx_sr1_hwmod = {
 962	.name		= "smartreflex_mpu_iva",
 963	.class		= &omap34xx_smartreflex_hwmod_class,
 964	.main_clk	= "sr1_fck",
 965	.prcm		= {
 966		.omap2 = {
 967			.module_offs = WKUP_MOD,
 968			.idlest_reg_id = 1,
 969			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
 970		},
 971	},
 972	.dev_attr	= &sr1_dev_attr,
 973	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
 974};
 975
 976static struct omap_hwmod omap36xx_sr1_hwmod = {
 977	.name		= "smartreflex_mpu_iva",
 978	.class		= &omap36xx_smartreflex_hwmod_class,
 979	.main_clk	= "sr1_fck",
 980	.prcm		= {
 981		.omap2 = {
 982			.module_offs = WKUP_MOD,
 983			.idlest_reg_id = 1,
 984			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
 985		},
 986	},
 987	.dev_attr	= &sr1_dev_attr,
 988};
 989
 990/* SR2 */
 991static struct omap_smartreflex_dev_attr sr2_dev_attr = {
 992	.sensor_voltdm_name	= "core",
 993};
 994
 995
 996static struct omap_hwmod omap34xx_sr2_hwmod = {
 997	.name		= "smartreflex_core",
 998	.class		= &omap34xx_smartreflex_hwmod_class,
 999	.main_clk	= "sr2_fck",
1000	.prcm		= {
1001		.omap2 = {
1002			.module_offs = WKUP_MOD,
1003			.idlest_reg_id = 1,
1004			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1005		},
1006	},
1007	.dev_attr	= &sr2_dev_attr,
1008	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
1009};
1010
1011static struct omap_hwmod omap36xx_sr2_hwmod = {
1012	.name		= "smartreflex_core",
1013	.class		= &omap36xx_smartreflex_hwmod_class,
1014	.main_clk	= "sr2_fck",
1015	.prcm		= {
1016		.omap2 = {
1017			.module_offs = WKUP_MOD,
1018			.idlest_reg_id = 1,
1019			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1020		},
1021	},
1022	.dev_attr	= &sr2_dev_attr,
1023};
1024
1025/*
1026 * 'mailbox' class
1027 * mailbox module allowing communication between the on-chip processors
1028 * using a queued mailbox-interrupt mechanism.
1029 */
1030
1031static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1032	.rev_offs	= 0x000,
1033	.sysc_offs	= 0x010,
1034	.syss_offs	= 0x014,
1035	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1036				SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1037	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1038	.sysc_fields	= &omap_hwmod_sysc_type1,
1039};
1040
1041static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1042	.name = "mailbox",
1043	.sysc = &omap3xxx_mailbox_sysc,
1044};
1045
1046static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1047	.name		= "mailbox",
1048	.class		= &omap3xxx_mailbox_hwmod_class,
1049	.main_clk	= "mailboxes_ick",
1050	.prcm		= {
1051		.omap2 = {
1052			.module_offs = CORE_MOD,
1053			.idlest_reg_id = 1,
1054			.idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1055		},
1056	},
1057};
1058
1059/*
1060 * 'mcspi' class
1061 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1062 * bus
1063 */
1064
1065static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1066	.rev_offs	= 0x0000,
1067	.sysc_offs	= 0x0010,
1068	.syss_offs	= 0x0014,
1069	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1070				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1071				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1072	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1073	.sysc_fields    = &omap_hwmod_sysc_type1,
1074};
1075
1076static struct omap_hwmod_class omap34xx_mcspi_class = {
1077	.name = "mcspi",
1078	.sysc = &omap34xx_mcspi_sysc,
1079};
1080
1081/* mcspi1 */
1082static struct omap_hwmod omap34xx_mcspi1 = {
1083	.name		= "mcspi1",
1084	.main_clk	= "mcspi1_fck",
1085	.prcm		= {
1086		.omap2 = {
1087			.module_offs = CORE_MOD,
1088			.idlest_reg_id = 1,
1089			.idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1090		},
1091	},
1092	.class		= &omap34xx_mcspi_class,
1093};
1094
1095/* mcspi2 */
1096static struct omap_hwmod omap34xx_mcspi2 = {
1097	.name		= "mcspi2",
1098	.main_clk	= "mcspi2_fck",
1099	.prcm		= {
1100		.omap2 = {
1101			.module_offs = CORE_MOD,
1102			.idlest_reg_id = 1,
1103			.idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1104		},
1105	},
1106	.class		= &omap34xx_mcspi_class,
1107};
1108
1109/* mcspi3 */
1110static struct omap_hwmod omap34xx_mcspi3 = {
1111	.name		= "mcspi3",
1112	.main_clk	= "mcspi3_fck",
1113	.prcm		= {
1114		.omap2 = {
1115			.module_offs = CORE_MOD,
1116			.idlest_reg_id = 1,
1117			.idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1118		},
1119	},
1120	.class		= &omap34xx_mcspi_class,
1121};
1122
1123/* mcspi4 */
1124static struct omap_hwmod omap34xx_mcspi4 = {
1125	.name		= "mcspi4",
1126	.main_clk	= "mcspi4_fck",
1127	.prcm		= {
1128		.omap2 = {
1129			.module_offs = CORE_MOD,
1130			.idlest_reg_id = 1,
1131			.idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1132		},
1133	},
1134	.class		= &omap34xx_mcspi_class,
1135};
1136
1137/* MMC/SD/SDIO common */
1138static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1139	.rev_offs	= 0x1fc,
1140	.sysc_offs	= 0x10,
1141	.syss_offs	= 0x14,
1142	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1143			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1144			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1145	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1146	.sysc_fields    = &omap_hwmod_sysc_type1,
1147};
1148
1149static struct omap_hwmod_class omap34xx_mmc_class = {
1150	.name = "mmc",
1151	.sysc = &omap34xx_mmc_sysc,
1152};
1153
1154/* MMC/SD/SDIO1 */
1155
1156
1157
1158static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1159	{ .role = "dbck", .clk = "omap_32k_fck", },
1160};
1161
1162static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1163	.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1164};
1165
1166/* See 35xx errata 2.1.1.128 in SPRZ278F */
1167static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1168	.flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1169		  OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1170};
1171
1172static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1173	.name		= "mmc1",
1174	.opt_clks	= omap34xx_mmc1_opt_clks,
1175	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1176	.main_clk	= "mmchs1_fck",
1177	.prcm		= {
1178		.omap2 = {
1179			.module_offs = CORE_MOD,
1180			.idlest_reg_id = 1,
1181			.idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1182		},
1183	},
1184	.dev_attr	= &mmc1_pre_es3_dev_attr,
1185	.class		= &omap34xx_mmc_class,
1186};
1187
1188static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1189	.name		= "mmc1",
1190	.opt_clks	= omap34xx_mmc1_opt_clks,
1191	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1192	.main_clk	= "mmchs1_fck",
1193	.prcm		= {
1194		.omap2 = {
1195			.module_offs = CORE_MOD,
1196			.idlest_reg_id = 1,
1197			.idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1198		},
1199	},
1200	.dev_attr	= &mmc1_dev_attr,
1201	.class		= &omap34xx_mmc_class,
1202};
1203
1204/* MMC/SD/SDIO2 */
1205
1206
1207
1208static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1209	{ .role = "dbck", .clk = "omap_32k_fck", },
1210};
1211
1212/* See 35xx errata 2.1.1.128 in SPRZ278F */
1213static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1214	.flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1215};
1216
1217static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1218	.name		= "mmc2",
1219	.opt_clks	= omap34xx_mmc2_opt_clks,
1220	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1221	.main_clk	= "mmchs2_fck",
1222	.prcm		= {
1223		.omap2 = {
1224			.module_offs = CORE_MOD,
1225			.idlest_reg_id = 1,
1226			.idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1227		},
1228	},
1229	.dev_attr	= &mmc2_pre_es3_dev_attr,
1230	.class		= &omap34xx_mmc_class,
1231};
1232
1233static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1234	.name		= "mmc2",
1235	.opt_clks	= omap34xx_mmc2_opt_clks,
1236	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1237	.main_clk	= "mmchs2_fck",
1238	.prcm		= {
1239		.omap2 = {
1240			.module_offs = CORE_MOD,
1241			.idlest_reg_id = 1,
1242			.idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1243		},
1244	},
1245	.class		= &omap34xx_mmc_class,
1246};
1247
1248/* MMC/SD/SDIO3 */
1249
1250
1251
1252static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1253	{ .role = "dbck", .clk = "omap_32k_fck", },
1254};
1255
1256static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1257	.name		= "mmc3",
1258	.opt_clks	= omap34xx_mmc3_opt_clks,
1259	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1260	.main_clk	= "mmchs3_fck",
1261	.prcm		= {
1262		.omap2 = {
1263			.module_offs = CORE_MOD,
1264			.idlest_reg_id = 1,
1265			.idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1266		},
1267	},
1268	.class		= &omap34xx_mmc_class,
1269};
1270
1271/*
1272 * 'usb_host_hs' class
1273 * high-speed multi-port usb host controller
1274 */
1275
1276static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1277	.rev_offs	= 0x0000,
1278	.sysc_offs	= 0x0010,
1279	.syss_offs	= 0x0014,
1280	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1281			   SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1282			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1283			   SYSS_HAS_RESET_STATUS),
1284	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1285			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1286	.sysc_fields	= &omap_hwmod_sysc_type1,
1287};
1288
1289static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1290	.name = "usb_host_hs",
1291	.sysc = &omap3xxx_usb_host_hs_sysc,
1292};
1293
1294
1295static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1296	.name		= "usb_host_hs",
1297	.class		= &omap3xxx_usb_host_hs_hwmod_class,
1298	.clkdm_name	= "usbhost_clkdm",
1299	.main_clk	= "usbhost_48m_fck",
1300	.prcm = {
1301		.omap2 = {
1302			.module_offs = OMAP3430ES2_USBHOST_MOD,
1303			.idlest_reg_id = 1,
1304			.idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1305		},
1306	},
1307
1308	/*
1309	 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1310	 * id: i660
1311	 *
1312	 * Description:
1313	 * In the following configuration :
1314	 * - USBHOST module is set to smart-idle mode
1315	 * - PRCM asserts idle_req to the USBHOST module ( This typically
1316	 *   happens when the system is going to a low power mode : all ports
1317	 *   have been suspended, the master part of the USBHOST module has
1318	 *   entered the standby state, and SW has cut the functional clocks)
1319	 * - an USBHOST interrupt occurs before the module is able to answer
1320	 *   idle_ack, typically a remote wakeup IRQ.
1321	 * Then the USB HOST module will enter a deadlock situation where it
1322	 * is no more accessible nor functional.
1323	 *
1324	 * Workaround:
1325	 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1326	 */
1327
1328	/*
1329	 * Errata: USB host EHCI may stall when entering smart-standby mode
1330	 * Id: i571
1331	 *
1332	 * Description:
1333	 * When the USBHOST module is set to smart-standby mode, and when it is
1334	 * ready to enter the standby state (i.e. all ports are suspended and
1335	 * all attached devices are in suspend mode), then it can wrongly assert
1336	 * the Mstandby signal too early while there are still some residual OCP
1337	 * transactions ongoing. If this condition occurs, the internal state
1338	 * machine may go to an undefined state and the USB link may be stuck
1339	 * upon the next resume.
1340	 *
1341	 * Workaround:
1342	 * Don't use smart standby; use only force standby,
1343	 * hence HWMOD_SWSUP_MSTANDBY
1344	 */
1345
1346	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1347};
1348
1349/*
1350 * 'usb_tll_hs' class
1351 * usb_tll_hs module is the adapter on the usb_host_hs ports
1352 */
1353static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1354	.rev_offs	= 0x0000,
1355	.sysc_offs	= 0x0010,
1356	.syss_offs	= 0x0014,
1357	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1358			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1359			   SYSC_HAS_AUTOIDLE),
1360	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1361	.sysc_fields	= &omap_hwmod_sysc_type1,
1362};
1363
1364static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1365	.name = "usb_tll_hs",
1366	.sysc = &omap3xxx_usb_tll_hs_sysc,
1367};
1368
1369
1370static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1371	.name		= "usb_tll_hs",
1372	.class		= &omap3xxx_usb_tll_hs_hwmod_class,
1373	.clkdm_name	= "core_l4_clkdm",
1374	.main_clk	= "usbtll_fck",
1375	.prcm = {
1376		.omap2 = {
1377			.module_offs = CORE_MOD,
1378			.idlest_reg_id = 3,
1379			.idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1380		},
1381	},
1382};
1383
1384static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1385	.name		= "hdq1w",
1386	.main_clk	= "hdq_fck",
1387	.prcm		= {
1388		.omap2 = {
1389			.module_offs = CORE_MOD,
1390			.idlest_reg_id = 1,
1391			.idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1392		},
1393	},
1394	.class		= &omap2_hdq1w_class,
1395};
1396
1397/* SAD2D */
1398static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
1399	{ .name = "rst_modem_pwron_sw", .rst_shift = 0 },
1400	{ .name = "rst_modem_sw", .rst_shift = 1 },
1401};
1402
1403static struct omap_hwmod_class omap3xxx_sad2d_class = {
1404	.name			= "sad2d",
1405};
1406
1407static struct omap_hwmod omap3xxx_sad2d_hwmod = {
1408	.name		= "sad2d",
1409	.rst_lines	= omap3xxx_sad2d_resets,
1410	.rst_lines_cnt	= ARRAY_SIZE(omap3xxx_sad2d_resets),
1411	.main_clk	= "sad2d_ick",
1412	.prcm		= {
1413		.omap2 = {
1414			.module_offs = CORE_MOD,
1415			.idlest_reg_id = 1,
1416			.idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
1417		},
1418	},
1419	.class		= &omap3xxx_sad2d_class,
1420};
1421
1422/*
1423 * 'gpmc' class
1424 * general purpose memory controller
1425 */
1426
1427static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
1428	.rev_offs	= 0x0000,
1429	.sysc_offs	= 0x0010,
1430	.syss_offs	= 0x0014,
1431	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1432			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1433	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1434	.sysc_fields	= &omap_hwmod_sysc_type1,
1435};
1436
1437static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
1438	.name	= "gpmc",
1439	.sysc	= &omap3xxx_gpmc_sysc,
1440};
1441
1442static struct omap_hwmod omap3xxx_gpmc_hwmod = {
1443	.name		= "gpmc",
1444	.class		= &omap3xxx_gpmc_hwmod_class,
1445	.clkdm_name	= "core_l3_clkdm",
1446	.main_clk	= "gpmc_fck",
1447	/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1448	.flags		= HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1449};
1450
1451/*
1452 * interfaces
1453 */
1454
1455/* L3 -> L4_CORE interface */
1456static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
1457	.master	= &omap3xxx_l3_main_hwmod,
1458	.slave	= &omap3xxx_l4_core_hwmod,
1459	.user	= OCP_USER_MPU | OCP_USER_SDMA,
1460};
1461
1462/* L3 -> L4_PER interface */
1463static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
1464	.master = &omap3xxx_l3_main_hwmod,
1465	.slave	= &omap3xxx_l4_per_hwmod,
1466	.user	= OCP_USER_MPU | OCP_USER_SDMA,
1467};
1468
1469
1470/* MPU -> L3 interface */
1471static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
1472	.master   = &omap3xxx_mpu_hwmod,
1473	.slave    = &omap3xxx_l3_main_hwmod,
1474	.user	= OCP_USER_MPU,
1475};
1476
1477
1478/* l3 -> debugss */
1479static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
1480	.master		= &omap3xxx_l3_main_hwmod,
1481	.slave		= &omap3xxx_debugss_hwmod,
1482	.user		= OCP_USER_MPU,
1483};
1484
1485/* DSS -> l3 */
1486static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
1487	.master		= &omap3430es1_dss_core_hwmod,
1488	.slave		= &omap3xxx_l3_main_hwmod,
1489	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1490};
1491
1492static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
1493	.master		= &omap3xxx_dss_core_hwmod,
1494	.slave		= &omap3xxx_l3_main_hwmod,
1495	.fw = {
1496		.omap2 = {
1497			.l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
1498			.flags	= OMAP_FIREWALL_L3,
1499		},
1500	},
1501	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1502};
1503
1504/* l3_core -> sad2d interface */
1505static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
1506	.master		= &omap3xxx_sad2d_hwmod,
1507	.slave		= &omap3xxx_l3_main_hwmod,
1508	.clk		= "core_l3_ick",
1509	.user		= OCP_USER_MPU,
1510};
1511
1512/* L4_CORE -> L4_WKUP interface */
1513static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
1514	.master	= &omap3xxx_l4_core_hwmod,
1515	.slave	= &omap3xxx_l4_wkup_hwmod,
1516	.user	= OCP_USER_MPU | OCP_USER_SDMA,
1517};
1518
1519/* L4 CORE -> MMC1 interface */
1520static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
1521	.master		= &omap3xxx_l4_core_hwmod,
1522	.slave		= &omap3xxx_pre_es3_mmc1_hwmod,
1523	.clk		= "mmchs1_ick",
1524	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1525	.flags		= OMAP_FIREWALL_L4,
1526};
1527
1528static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
1529	.master		= &omap3xxx_l4_core_hwmod,
1530	.slave		= &omap3xxx_es3plus_mmc1_hwmod,
1531	.clk		= "mmchs1_ick",
1532	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1533	.flags		= OMAP_FIREWALL_L4,
1534};
1535
1536/* L4 CORE -> MMC2 interface */
1537static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
1538	.master		= &omap3xxx_l4_core_hwmod,
1539	.slave		= &omap3xxx_pre_es3_mmc2_hwmod,
1540	.clk		= "mmchs2_ick",
1541	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1542	.flags		= OMAP_FIREWALL_L4,
1543};
1544
1545static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
1546	.master		= &omap3xxx_l4_core_hwmod,
1547	.slave		= &omap3xxx_es3plus_mmc2_hwmod,
1548	.clk		= "mmchs2_ick",
1549	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1550	.flags		= OMAP_FIREWALL_L4,
1551};
1552
1553/* L4 CORE -> MMC3 interface */
1554
1555static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
1556	.master		= &omap3xxx_l4_core_hwmod,
1557	.slave		= &omap3xxx_mmc3_hwmod,
1558	.clk		= "mmchs3_ick",
1559	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1560	.flags		= OMAP_FIREWALL_L4,
1561};
1562
1563/* L4 CORE -> UART1 interface */
1564
1565static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
1566	.master		= &omap3xxx_l4_core_hwmod,
1567	.slave		= &omap3xxx_uart1_hwmod,
1568	.clk		= "uart1_ick",
1569	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1570};
1571
1572/* L4 CORE -> UART2 interface */
1573
1574static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
1575	.master		= &omap3xxx_l4_core_hwmod,
1576	.slave		= &omap3xxx_uart2_hwmod,
1577	.clk		= "uart2_ick",
1578	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1579};
1580
1581/* L4 PER -> UART3 interface */
1582
1583static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
1584	.master		= &omap3xxx_l4_per_hwmod,
1585	.slave		= &omap3xxx_uart3_hwmod,
1586	.clk		= "uart3_ick",
1587	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1588};
1589
1590/* L4 PER -> UART4 interface */
1591
1592static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
1593	.master		= &omap3xxx_l4_per_hwmod,
1594	.slave		= &omap36xx_uart4_hwmod,
1595	.clk		= "uart4_ick",
1596	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1597};
1598
1599/* AM35xx: L4 CORE -> UART4 interface */
1600
1601static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
1602	.master		= &omap3xxx_l4_core_hwmod,
1603	.slave		= &am35xx_uart4_hwmod,
1604	.clk		= "uart4_ick",
1605	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1606};
1607
1608/* L4 CORE -> I2C1 interface */
1609static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
1610	.master		= &omap3xxx_l4_core_hwmod,
1611	.slave		= &omap3xxx_i2c1_hwmod,
1612	.clk		= "i2c1_ick",
1613	.fw = {
1614		.omap2 = {
1615			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
1616			.l4_prot_group = 7,
1617			.flags	= OMAP_FIREWALL_L4,
1618		},
1619	},
1620	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1621};
1622
1623/* L4 CORE -> I2C2 interface */
1624static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
1625	.master		= &omap3xxx_l4_core_hwmod,
1626	.slave		= &omap3xxx_i2c2_hwmod,
1627	.clk		= "i2c2_ick",
1628	.fw = {
1629		.omap2 = {
1630			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
1631			.l4_prot_group = 7,
1632			.flags = OMAP_FIREWALL_L4,
1633		},
1634	},
1635	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1636};
1637
1638/* L4 CORE -> I2C3 interface */
1639
1640static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
1641	.master		= &omap3xxx_l4_core_hwmod,
1642	.slave		= &omap3xxx_i2c3_hwmod,
1643	.clk		= "i2c3_ick",
1644	.fw = {
1645		.omap2 = {
1646			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
1647			.l4_prot_group = 7,
1648			.flags = OMAP_FIREWALL_L4,
1649		},
1650	},
1651	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1652};
1653
1654/* L4 CORE -> SR1 interface */
1655static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
1656	.master		= &omap3xxx_l4_core_hwmod,
1657	.slave		= &omap34xx_sr1_hwmod,
1658	.clk		= "sr_l4_ick",
1659	.user		= OCP_USER_MPU,
1660};
1661
1662static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
1663	.master		= &omap3xxx_l4_core_hwmod,
1664	.slave		= &omap36xx_sr1_hwmod,
1665	.clk		= "sr_l4_ick",
1666	.user		= OCP_USER_MPU,
1667};
1668
1669/* L4 CORE -> SR2 interface */
1670
1671static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
1672	.master		= &omap3xxx_l4_core_hwmod,
1673	.slave		= &omap34xx_sr2_hwmod,
1674	.clk		= "sr_l4_ick",
1675	.user		= OCP_USER_MPU,
1676};
1677
1678static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
1679	.master		= &omap3xxx_l4_core_hwmod,
1680	.slave		= &omap36xx_sr2_hwmod,
1681	.clk		= "sr_l4_ick",
1682	.user		= OCP_USER_MPU,
1683};
1684
1685/* L4_WKUP -> L4_SEC interface */
1686static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
1687	.master = &omap3xxx_l4_wkup_hwmod,
1688	.slave	= &omap3xxx_l4_sec_hwmod,
1689	.user	= OCP_USER_MPU | OCP_USER_SDMA,
1690};
1691
1692/* IVA2 <- L3 interface */
1693static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
1694	.master		= &omap3xxx_l3_main_hwmod,
1695	.slave		= &omap3xxx_iva_hwmod,
1696	.clk		= "core_l3_ick",
1697	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1698};
1699
1700/* l4_per -> timer3 */
1701static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
1702	.master		= &omap3xxx_l4_per_hwmod,
1703	.slave		= &omap3xxx_timer3_hwmod,
1704	.clk		= "gpt3_ick",
1705	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1706};
1707
1708
1709/* l4_per -> timer4 */
1710static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
1711	.master		= &omap3xxx_l4_per_hwmod,
1712	.slave		= &omap3xxx_timer4_hwmod,
1713	.clk		= "gpt4_ick",
1714	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1715};
1716
1717
1718/* l4_per -> timer5 */
1719static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
1720	.master		= &omap3xxx_l4_per_hwmod,
1721	.slave		= &omap3xxx_timer5_hwmod,
1722	.clk		= "gpt5_ick",
1723	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1724};
1725
1726
1727/* l4_per -> timer6 */
1728static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
1729	.master		= &omap3xxx_l4_per_hwmod,
1730	.slave		= &omap3xxx_timer6_hwmod,
1731	.clk		= "gpt6_ick",
1732	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1733};
1734
1735
1736/* l4_per -> timer7 */
1737static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
1738	.master		= &omap3xxx_l4_per_hwmod,
1739	.slave		= &omap3xxx_timer7_hwmod,
1740	.clk		= "gpt7_ick",
1741	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1742};
1743
1744
1745/* l4_per -> timer8 */
1746static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
1747	.master		= &omap3xxx_l4_per_hwmod,
1748	.slave		= &omap3xxx_timer8_hwmod,
1749	.clk		= "gpt8_ick",
1750	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1751};
1752
1753
1754/* l4_per -> timer9 */
1755static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1756	.master		= &omap3xxx_l4_per_hwmod,
1757	.slave		= &omap3xxx_timer9_hwmod,
1758	.clk		= "gpt9_ick",
1759	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1760};
1761
1762/* l4_core -> timer10 */
1763static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1764	.master		= &omap3xxx_l4_core_hwmod,
1765	.slave		= &omap3xxx_timer10_hwmod,
1766	.clk		= "gpt10_ick",
1767	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1768};
1769
1770/* l4_core -> timer11 */
1771static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1772	.master		= &omap3xxx_l4_core_hwmod,
1773	.slave		= &omap3xxx_timer11_hwmod,
1774	.clk		= "gpt11_ick",
1775	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1776};
1777
1778/* l4_wkup -> wd_timer2 */
1779
1780static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1781	.master		= &omap3xxx_l4_wkup_hwmod,
1782	.slave		= &omap3xxx_wd_timer2_hwmod,
1783	.clk		= "wdt2_ick",
1784	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1785};
1786
1787/* l4_core -> dss */
1788static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1789	.master		= &omap3xxx_l4_core_hwmod,
1790	.slave		= &omap3430es1_dss_core_hwmod,
1791	.clk		= "dss_ick",
1792	.fw = {
1793		.omap2 = {
1794			.l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1795			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1796			.flags	= OMAP_FIREWALL_L4,
1797		},
1798	},
1799	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1800};
1801
1802static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1803	.master		= &omap3xxx_l4_core_hwmod,
1804	.slave		= &omap3xxx_dss_core_hwmod,
1805	.clk		= "dss_ick",
1806	.fw = {
1807		.omap2 = {
1808			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1809			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1810			.flags	= OMAP_FIREWALL_L4,
1811		},
1812	},
1813	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1814};
1815
1816/* l4_core -> dss_dispc */
1817static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1818	.master		= &omap3xxx_l4_core_hwmod,
1819	.slave		= &omap3xxx_dss_dispc_hwmod,
1820	.clk		= "dss_ick",
1821	.fw = {
1822		.omap2 = {
1823			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1824			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1825			.flags	= OMAP_FIREWALL_L4,
1826		},
1827	},
1828	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1829};
1830
1831/* l4_core -> dss_dsi1 */
1832static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1833	.master		= &omap3xxx_l4_core_hwmod,
1834	.slave		= &omap3xxx_dss_dsi1_hwmod,
1835	.clk		= "dss_ick",
1836	.fw = {
1837		.omap2 = {
1838			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1839			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1840			.flags	= OMAP_FIREWALL_L4,
1841		},
1842	},
1843	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1844};
1845
1846/* l4_core -> dss_rfbi */
1847static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1848	.master		= &omap3xxx_l4_core_hwmod,
1849	.slave		= &omap3xxx_dss_rfbi_hwmod,
1850	.clk		= "dss_ick",
1851	.fw = {
1852		.omap2 = {
1853			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1854			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1855			.flags	= OMAP_FIREWALL_L4,
1856		},
1857	},
1858	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1859};
1860
1861/* l4_core -> dss_venc */
1862static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1863	.master		= &omap3xxx_l4_core_hwmod,
1864	.slave		= &omap3xxx_dss_venc_hwmod,
1865	.clk		= "dss_ick",
1866	.fw = {
1867		.omap2 = {
1868			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1869			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1870			.flags	= OMAP_FIREWALL_L4,
1871		},
1872	},
1873	.flags		= OCPIF_SWSUP_IDLE,
1874	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1875};
1876
1877/* l4_wkup -> gpio1 */
1878
1879static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1880	.master		= &omap3xxx_l4_wkup_hwmod,
1881	.slave		= &omap3xxx_gpio1_hwmod,
1882	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1883};
1884
1885/* l4_per -> gpio2 */
1886
1887static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1888	.master		= &omap3xxx_l4_per_hwmod,
1889	.slave		= &omap3xxx_gpio2_hwmod,
1890	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1891};
1892
1893/* l4_per -> gpio3 */
1894
1895static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1896	.master		= &omap3xxx_l4_per_hwmod,
1897	.slave		= &omap3xxx_gpio3_hwmod,
1898	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1899};
1900
1901/*
1902 * 'mmu' class
1903 * The memory management unit performs virtual to physical address translation
1904 * for its requestors.
1905 */
1906
1907static struct omap_hwmod_class_sysconfig mmu_sysc = {
1908	.rev_offs	= 0x000,
1909	.sysc_offs	= 0x010,
1910	.syss_offs	= 0x014,
1911	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1912			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1913	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1914	.sysc_fields	= &omap_hwmod_sysc_type1,
1915};
1916
1917static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
1918	.name = "mmu",
1919	.sysc = &mmu_sysc,
1920};
1921
1922/* mmu isp */
1923static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
1924
1925/* l4_core -> mmu isp */
1926static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
1927	.master		= &omap3xxx_l4_core_hwmod,
1928	.slave		= &omap3xxx_mmu_isp_hwmod,
1929	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1930};
1931
1932static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
1933	.name		= "mmu_isp",
1934	.class		= &omap3xxx_mmu_hwmod_class,
1935	.main_clk	= "cam_ick",
1936	.flags		= HWMOD_NO_IDLEST,
1937};
1938
1939/* mmu iva */
1940
1941static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
1942
1943static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
1944	{ .name = "mmu", .rst_shift = 1, .st_shift = 9 },
1945};
1946
1947/* l3_main -> iva mmu */
1948static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
1949	.master		= &omap3xxx_l3_main_hwmod,
1950	.slave		= &omap3xxx_mmu_iva_hwmod,
1951	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1952};
1953
1954static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
1955	.name		= "mmu_iva",
1956	.class		= &omap3xxx_mmu_hwmod_class,
1957	.clkdm_name	= "iva2_clkdm",
1958	.rst_lines	= omap3xxx_mmu_iva_resets,
1959	.rst_lines_cnt	= ARRAY_SIZE(omap3xxx_mmu_iva_resets),
1960	.main_clk	= "iva2_ck",
1961	.prcm = {
1962		.omap2 = {
1963			.module_offs = OMAP3430_IVA2_MOD,
1964			.idlest_reg_id = 1,
1965			.idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
1966		},
1967	},
1968	.flags		= HWMOD_NO_IDLEST,
1969};
1970
1971/* l4_per -> gpio4 */
1972
1973static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1974	.master		= &omap3xxx_l4_per_hwmod,
1975	.slave		= &omap3xxx_gpio4_hwmod,
1976	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1977};
1978
1979/* l4_per -> gpio5 */
1980
1981static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1982	.master		= &omap3xxx_l4_per_hwmod,
1983	.slave		= &omap3xxx_gpio5_hwmod,
1984	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1985};
1986
1987/* l4_per -> gpio6 */
1988
1989static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1990	.master		= &omap3xxx_l4_per_hwmod,
1991	.slave		= &omap3xxx_gpio6_hwmod,
1992	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1993};
1994
1995/* l4_core -> mcbsp1 */
1996static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
1997	.master		= &omap3xxx_l4_core_hwmod,
1998	.slave		= &omap3xxx_mcbsp1_hwmod,
1999	.clk		= "mcbsp1_ick",
2000	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2001};
2002
2003
2004/* l4_per -> mcbsp2 */
2005static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2006	.master		= &omap3xxx_l4_per_hwmod,
2007	.slave		= &omap3xxx_mcbsp2_hwmod,
2008	.clk		= "mcbsp2_ick",
2009	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2010};
2011
2012
2013/* l4_per -> mcbsp3 */
2014static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2015	.master		= &omap3xxx_l4_per_hwmod,
2016	.slave		= &omap3xxx_mcbsp3_hwmod,
2017	.clk		= "mcbsp3_ick",
2018	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2019};
2020
2021
2022/* l4_per -> mcbsp4 */
2023static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2024	.master		= &omap3xxx_l4_per_hwmod,
2025	.slave		= &omap3xxx_mcbsp4_hwmod,
2026	.clk		= "mcbsp4_ick",
2027	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2028};
2029
2030
2031/* l4_core -> mcbsp5 */
2032static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2033	.master		= &omap3xxx_l4_core_hwmod,
2034	.slave		= &omap3xxx_mcbsp5_hwmod,
2035	.clk		= "mcbsp5_ick",
2036	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2037};
2038
2039
2040/* l4_per -> mcbsp2_sidetone */
2041static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2042	.master		= &omap3xxx_l4_per_hwmod,
2043	.slave		= &omap3xxx_mcbsp2_sidetone_hwmod,
2044	.clk		= "mcbsp2_ick",
2045	.user		= OCP_USER_MPU,
2046};
2047
2048
2049/* l4_per -> mcbsp3_sidetone */
2050static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2051	.master		= &omap3xxx_l4_per_hwmod,
2052	.slave		= &omap3xxx_mcbsp3_sidetone_hwmod,
2053	.clk		= "mcbsp3_ick",
2054	.user		= OCP_USER_MPU,
2055};
2056
2057/* l4_core -> mailbox */
2058static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2059	.master		= &omap3xxx_l4_core_hwmod,
2060	.slave		= &omap3xxx_mailbox_hwmod,
2061	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2062};
2063
2064/* l4 core -> mcspi1 interface */
2065static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2066	.master		= &omap3xxx_l4_core_hwmod,
2067	.slave		= &omap34xx_mcspi1,
2068	.clk		= "mcspi1_ick",
2069	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2070};
2071
2072/* l4 core -> mcspi2 interface */
2073static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2074	.master		= &omap3xxx_l4_core_hwmod,
2075	.slave		= &omap34xx_mcspi2,
2076	.clk		= "mcspi2_ick",
2077	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2078};
2079
2080/* l4 core -> mcspi3 interface */
2081static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2082	.master		= &omap3xxx_l4_core_hwmod,
2083	.slave		= &omap34xx_mcspi3,
2084	.clk		= "mcspi3_ick",
2085	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2086};
2087
2088/* l4 core -> mcspi4 interface */
2089
2090static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2091	.master		= &omap3xxx_l4_core_hwmod,
2092	.slave		= &omap34xx_mcspi4,
2093	.clk		= "mcspi4_ick",
2094	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2095};
2096
2097static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
2098	.master		= &omap3xxx_usb_host_hs_hwmod,
2099	.slave		= &omap3xxx_l3_main_hwmod,
2100	.clk		= "core_l3_ick",
2101	.user		= OCP_USER_MPU,
2102};
2103
2104
2105static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
2106	.master		= &omap3xxx_l4_core_hwmod,
2107	.slave		= &omap3xxx_usb_host_hs_hwmod,
2108	.clk		= "usbhost_ick",
2109	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2110};
2111
2112
2113static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
2114	.master		= &omap3xxx_l4_core_hwmod,
2115	.slave		= &omap3xxx_usb_tll_hs_hwmod,
2116	.clk		= "usbtll_ick",
2117	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2118};
2119
2120/* l4_core -> hdq1w interface */
2121static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
2122	.master		= &omap3xxx_l4_core_hwmod,
2123	.slave		= &omap3xxx_hdq1w_hwmod,
2124	.clk		= "hdq_ick",
2125	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2126	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
2127};
2128
2129/* am35xx has Davinci MDIO & EMAC */
2130static struct omap_hwmod_class am35xx_mdio_class = {
2131	.name = "davinci_mdio",
2132};
2133
2134static struct omap_hwmod am35xx_mdio_hwmod = {
2135	.name		= "davinci_mdio",
2136	.class		= &am35xx_mdio_class,
2137	.flags		= HWMOD_NO_IDLEST,
2138};
2139
2140/*
2141 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2142 * but this will probably require some additional hwmod core support,
2143 * so is left as a future to-do item.
2144 */
2145static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
2146	.master		= &am35xx_mdio_hwmod,
2147	.slave		= &omap3xxx_l3_main_hwmod,
2148	.clk		= "emac_fck",
2149	.user		= OCP_USER_MPU,
2150};
2151
2152/* l4_core -> davinci mdio  */
2153/*
2154 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2155 * but this will probably require some additional hwmod core support,
2156 * so is left as a future to-do item.
2157 */
2158static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
2159	.master		= &omap3xxx_l4_core_hwmod,
2160	.slave		= &am35xx_mdio_hwmod,
2161	.clk		= "emac_fck",
2162	.user		= OCP_USER_MPU,
2163};
2164
2165static struct omap_hwmod_class am35xx_emac_class = {
2166	.name = "davinci_emac",
2167};
2168
2169static struct omap_hwmod am35xx_emac_hwmod = {
2170	.name		= "davinci_emac",
2171	.class		= &am35xx_emac_class,
2172	/*
2173	 * According to Mark Greer, the MPU will not return from WFI
2174	 * when the EMAC signals an interrupt.
2175	 * https://lore.kernel.org/all/1336770778-23044-3-git-send-email-mgreer@animalcreek.com/
2176	 */
2177	.flags		= (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
2178};
2179
2180/* l3_core -> davinci emac interface */
2181/*
2182 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2183 * but this will probably require some additional hwmod core support,
2184 * so is left as a future to-do item.
2185 */
2186static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
2187	.master		= &am35xx_emac_hwmod,
2188	.slave		= &omap3xxx_l3_main_hwmod,
2189	.clk		= "emac_ick",
2190	.user		= OCP_USER_MPU,
2191};
2192
2193/* l4_core -> davinci emac  */
2194/*
2195 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2196 * but this will probably require some additional hwmod core support,
2197 * so is left as a future to-do item.
2198 */
2199static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
2200	.master		= &omap3xxx_l4_core_hwmod,
2201	.slave		= &am35xx_emac_hwmod,
2202	.clk		= "emac_ick",
2203	.user		= OCP_USER_MPU,
2204};
2205
2206static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
2207	.master		= &omap3xxx_l3_main_hwmod,
2208	.slave		= &omap3xxx_gpmc_hwmod,
2209	.clk		= "core_l3_ick",
2210	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2211};
2212
2213/* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
2214static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
2215	.rev_offs	= 0x5c,
2216	.sysc_offs	= 0x60,
2217	.syss_offs	= 0x64,
2218	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2219			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2220	.sysc_fields	= &omap3_sham_sysc_fields,
2221};
2222
2223static struct omap_hwmod_class omap3xxx_sham_class = {
2224	.name	= "sham",
2225	.sysc	= &omap3_sham_sysc,
2226};
2227
2228
2229
2230static struct omap_hwmod omap3xxx_sham_hwmod = {
2231	.name		= "sham",
2232	.main_clk	= "sha12_ick",
2233	.prcm		= {
2234		.omap2 = {
2235			.module_offs = CORE_MOD,
2236			.idlest_reg_id = 1,
2237			.idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
2238		},
2239	},
2240	.class		= &omap3xxx_sham_class,
2241};
2242
2243
2244static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
2245	.master		= &omap3xxx_l4_core_hwmod,
2246	.slave		= &omap3xxx_sham_hwmod,
2247	.clk		= "sha12_ick",
2248	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2249};
2250
2251/*
2252 * 'ssi' class
2253 * synchronous serial interface (multichannel and full-duplex serial if)
2254 */
2255
2256static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
2257	.rev_offs	= 0x0000,
2258	.sysc_offs	= 0x0010,
2259	.syss_offs	= 0x0014,
2260	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
2261			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2262	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2263	.sysc_fields	= &omap_hwmod_sysc_type1,
2264};
2265
2266static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
2267	.name	= "ssi",
2268	.sysc	= &omap34xx_ssi_sysc,
2269};
2270
2271static struct omap_hwmod omap3xxx_ssi_hwmod = {
2272	.name		= "ssi",
2273	.class		= &omap3xxx_ssi_hwmod_class,
2274	.clkdm_name	= "core_l4_clkdm",
2275	.main_clk	= "ssi_ssr_fck",
2276	.prcm		= {
2277		.omap2 = {
2278			.module_offs		= CORE_MOD,
2279			.idlest_reg_id		= 1,
2280			.idlest_idle_bit	= OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2281		},
2282	},
2283};
2284
2285/* L4 CORE -> SSI */
2286static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
2287	.master		= &omap3xxx_l4_core_hwmod,
2288	.slave		= &omap3xxx_ssi_hwmod,
2289	.clk		= "ssi_ick",
2290	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2291};
2292
2293static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
2294	&omap3xxx_l3_main__l4_core,
2295	&omap3xxx_l3_main__l4_per,
2296	&omap3xxx_mpu__l3_main,
2297	&omap3xxx_l3_main__l4_debugss,
2298	&omap3xxx_l4_core__l4_wkup,
2299	&omap3xxx_l4_core__mmc3,
2300	&omap3_l4_core__uart1,
2301	&omap3_l4_core__uart2,
2302	&omap3_l4_per__uart3,
2303	&omap3_l4_core__i2c1,
2304	&omap3_l4_core__i2c2,
2305	&omap3_l4_core__i2c3,
2306	&omap3xxx_l4_wkup__l4_sec,
2307	&omap3xxx_l4_per__timer3,
2308	&omap3xxx_l4_per__timer4,
2309	&omap3xxx_l4_per__timer5,
2310	&omap3xxx_l4_per__timer6,
2311	&omap3xxx_l4_per__timer7,
2312	&omap3xxx_l4_per__timer8,
2313	&omap3xxx_l4_per__timer9,
2314	&omap3xxx_l4_core__timer10,
2315	&omap3xxx_l4_core__timer11,
2316	&omap3xxx_l4_wkup__wd_timer2,
2317	&omap3xxx_l4_wkup__gpio1,
2318	&omap3xxx_l4_per__gpio2,
2319	&omap3xxx_l4_per__gpio3,
2320	&omap3xxx_l4_per__gpio4,
2321	&omap3xxx_l4_per__gpio5,
2322	&omap3xxx_l4_per__gpio6,
2323	&omap3xxx_l4_core__mcbsp1,
2324	&omap3xxx_l4_per__mcbsp2,
2325	&omap3xxx_l4_per__mcbsp3,
2326	&omap3xxx_l4_per__mcbsp4,
2327	&omap3xxx_l4_core__mcbsp5,
2328	&omap3xxx_l4_per__mcbsp2_sidetone,
2329	&omap3xxx_l4_per__mcbsp3_sidetone,
2330	&omap34xx_l4_core__mcspi1,
2331	&omap34xx_l4_core__mcspi2,
2332	&omap34xx_l4_core__mcspi3,
2333	&omap34xx_l4_core__mcspi4,
2334	&omap3xxx_l3_main__gpmc,
2335	NULL,
2336};
2337
2338/* crypto hwmod links */
2339static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
2340	&omap3xxx_l4_core__sham,
2341	NULL,
2342};
2343
2344static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
2345	&omap3xxx_l4_core__sham,
2346	NULL
2347};
2348
 
2349/*
2350 * Apparently the SHA/MD5 and AES accelerator IP blocks are
2351 * only present on some AM35xx chips, and no one knows which
2352 * ones.
2353 * See https://lore.kernel.org/all/20130108203853.GB1876@animalcreek.com/
2354 * So if you need these IP blocks on an AM35xx, try uncommenting
2355 * the following lines.
2356 */
2357static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
2358	/* &omap3xxx_l4_core__sham, */
2359	NULL
2360};
2361
2362/* 3430ES1-only hwmod links */
2363static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
2364	&omap3430es1_dss__l3,
2365	&omap3430es1_l4_core__dss,
2366	NULL,
2367};
2368
2369/* 3430ES2+-only hwmod links */
2370static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
2371	&omap3xxx_dss__l3,
2372	&omap3xxx_l4_core__dss,
2373	&omap3xxx_usb_host_hs__l3_main_2,
2374	&omap3xxx_l4_core__usb_host_hs,
2375	&omap3xxx_l4_core__usb_tll_hs,
2376	NULL,
2377};
2378
2379/* <= 3430ES3-only hwmod links */
2380static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
2381	&omap3xxx_l4_core__pre_es3_mmc1,
2382	&omap3xxx_l4_core__pre_es3_mmc2,
2383	NULL,
2384};
2385
2386/* 3430ES3+-only hwmod links */
2387static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
2388	&omap3xxx_l4_core__es3plus_mmc1,
2389	&omap3xxx_l4_core__es3plus_mmc2,
2390	NULL,
2391};
2392
2393/* 34xx-only hwmod links (all ES revisions) */
2394static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
2395	&omap3xxx_l3__iva,
2396	&omap34xx_l4_core__sr1,
2397	&omap34xx_l4_core__sr2,
2398	&omap3xxx_l4_core__mailbox,
2399	&omap3xxx_l4_core__hdq1w,
2400	&omap3xxx_sad2d__l3,
2401	&omap3xxx_l4_core__mmu_isp,
2402	&omap3xxx_l3_main__mmu_iva,
2403	&omap3xxx_l4_core__ssi,
2404	NULL,
2405};
2406
2407/* 36xx-only hwmod links (all ES revisions) */
2408static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
2409	&omap3xxx_l3__iva,
2410	&omap36xx_l4_per__uart4,
2411	&omap3xxx_dss__l3,
2412	&omap3xxx_l4_core__dss,
2413	&omap36xx_l4_core__sr1,
2414	&omap36xx_l4_core__sr2,
2415	&omap3xxx_l4_core__mailbox,
2416	&omap3xxx_usb_host_hs__l3_main_2,
2417	&omap3xxx_l4_core__usb_host_hs,
2418	&omap3xxx_l4_core__usb_tll_hs,
2419	&omap3xxx_l4_core__es3plus_mmc1,
2420	&omap3xxx_l4_core__es3plus_mmc2,
2421	&omap3xxx_l4_core__hdq1w,
2422	&omap3xxx_sad2d__l3,
2423	&omap3xxx_l4_core__mmu_isp,
2424	&omap3xxx_l3_main__mmu_iva,
2425	&omap3xxx_l4_core__ssi,
2426	NULL,
2427};
2428
2429static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
2430	&omap3xxx_dss__l3,
2431	&omap3xxx_l4_core__dss,
2432	&am35xx_l4_core__uart4,
2433	&omap3xxx_usb_host_hs__l3_main_2,
2434	&omap3xxx_l4_core__usb_host_hs,
2435	&omap3xxx_l4_core__usb_tll_hs,
2436	&omap3xxx_l4_core__es3plus_mmc1,
2437	&omap3xxx_l4_core__es3plus_mmc2,
2438	&omap3xxx_l4_core__hdq1w,
2439	&am35xx_mdio__l3,
2440	&am35xx_l4_core__mdio,
2441	&am35xx_emac__l3,
2442	&am35xx_l4_core__emac,
2443	NULL,
2444};
2445
2446static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
2447	&omap3xxx_l4_core__dss_dispc,
2448	&omap3xxx_l4_core__dss_dsi1,
2449	&omap3xxx_l4_core__dss_rfbi,
2450	&omap3xxx_l4_core__dss_venc,
2451	NULL,
2452};
2453
2454/**
2455 * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
2456 * @bus: struct device_node * for the top-level OMAP DT data
2457 * @dev_name: device name used in the DT file
2458 *
2459 * Determine whether a "secure" IP block @dev_name is usable by Linux.
2460 * There doesn't appear to be a 100% reliable way to determine this,
2461 * so we rely on heuristics.  If @bus is null, meaning there's no DT
2462 * data, then we only assume the IP block is accessible if the OMAP is
2463 * fused as a 'general-purpose' SoC.  If however DT data is present,
2464 * test to see if the IP block is described in the DT data and set to
2465 * 'status = "okay"'.  If so then we assume the ODM has configured the
2466 * OMAP firewalls to allow access to the IP block.
2467 *
2468 * Return: 0 if device named @dev_name is not likely to be accessible,
2469 * or 1 if it is likely to be accessible.
2470 */
2471static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
2472							const char *dev_name)
2473{
2474	struct device_node *node;
2475	bool available;
2476
2477	if (!bus)
2478		return omap_type() == OMAP2_DEVICE_TYPE_GP;
2479
2480	node = of_get_child_by_name(bus, dev_name);
2481	available = of_device_is_available(node);
2482	of_node_put(node);
2483
2484	return available;
2485}
2486
2487int __init omap3xxx_hwmod_init(void)
2488{
2489	int r;
2490	struct omap_hwmod_ocp_if **h = NULL, **h_sham = NULL;
2491	struct device_node *bus;
2492	unsigned int rev;
2493
2494	omap_hwmod_init();
2495
2496	/* Register hwmod links common to all OMAP3 */
2497	r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
2498	if (r < 0)
2499		return r;
2500
2501	rev = omap_rev();
2502
2503	/*
2504	 * Register hwmod links common to individual OMAP3 families, all
2505	 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
2506	 * All possible revisions should be included in this conditional.
2507	 */
2508	if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
2509	    rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
2510	    rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
2511		h = omap34xx_hwmod_ocp_ifs;
2512		h_sham = omap34xx_sham_hwmod_ocp_ifs;
2513	} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
2514		h = am35xx_hwmod_ocp_ifs;
2515		h_sham = am35xx_sham_hwmod_ocp_ifs;
2516	} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
2517		   rev == OMAP3630_REV_ES1_2) {
2518		h = omap36xx_hwmod_ocp_ifs;
2519		h_sham = omap36xx_sham_hwmod_ocp_ifs;
2520	} else {
2521		WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
2522		return -EINVAL;
2523	}
2524
2525	r = omap_hwmod_register_links(h);
2526	if (r < 0)
2527		return r;
2528
2529	/*
2530	 * Register crypto hwmod links only if they are not disabled in DT.
2531	 * If DT information is missing, enable them only for GP devices.
2532	 */
2533
2534	bus = of_find_node_by_name(NULL, "ocp");
2535
2536	if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
2537		r = omap_hwmod_register_links(h_sham);
2538		if (r < 0)
2539			goto put_node;
2540	}
2541
2542	of_node_put(bus);
2543
2544	/*
2545	 * Register hwmod links specific to certain ES levels of a
2546	 * particular family of silicon (e.g., 34xx ES1.0)
2547	 */
2548	h = NULL;
2549	if (rev == OMAP3430_REV_ES1_0) {
2550		h = omap3430es1_hwmod_ocp_ifs;
2551	} else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
2552		   rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
2553		   rev == OMAP3430_REV_ES3_1_2) {
2554		h = omap3430es2plus_hwmod_ocp_ifs;
2555	}
2556
2557	if (h) {
2558		r = omap_hwmod_register_links(h);
2559		if (r < 0)
2560			return r;
2561	}
2562
2563	h = NULL;
2564	if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
2565	    rev == OMAP3430_REV_ES2_1) {
2566		h = omap3430_pre_es3_hwmod_ocp_ifs;
2567	} else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
2568		   rev == OMAP3430_REV_ES3_1_2) {
2569		h = omap3430_es3plus_hwmod_ocp_ifs;
2570	}
2571
2572	if (h)
2573		r = omap_hwmod_register_links(h);
2574	if (r < 0)
2575		return r;
2576
2577	/*
2578	 * DSS code presumes that dss_core hwmod is handled first,
2579	 * _before_ any other DSS related hwmods so register common
2580	 * DSS hwmod links last to ensure that dss_core is already
2581	 * registered.  Otherwise some change things may happen, for
2582	 * ex. if dispc is handled before dss_core and DSS is enabled
2583	 * in bootloader DISPC will be reset with outputs enabled
2584	 * which sometimes leads to unrecoverable L3 error.  XXX The
2585	 * long-term fix to this is to ensure hwmods are set up in
2586	 * dependency order in the hwmod core code.
2587	 */
2588	r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
2589
2590	return r;
2591
2592put_node:
2593	of_node_put(bus);
2594	return r;
2595}