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1/*
2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include <dt-bindings/interrupt-controller/arm-gic.h>
45#include <dt-bindings/clock/sun6i-rtc.h>
46#include <dt-bindings/clock/sun8i-de2.h>
47#include <dt-bindings/clock/sun8i-r40-ccu.h>
48#include <dt-bindings/clock/sun8i-tcon-top.h>
49#include <dt-bindings/reset/sun8i-r40-ccu.h>
50#include <dt-bindings/reset/sun8i-de2.h>
51#include <dt-bindings/thermal/thermal.h>
52
53/ {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 interrupt-parent = <&gic>;
57
58 clocks {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62
63 osc24M: osc24M {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <24000000>;
67 clock-accuracy = <50000>;
68 clock-output-names = "osc24M";
69 };
70
71 osc32k: osc32k {
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-frequency = <32768>;
75 clock-accuracy = <20000>;
76 clock-output-names = "ext-osc32k";
77 };
78 };
79
80 cpus {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 cpu0: cpu@0 {
85 compatible = "arm,cortex-a7";
86 device_type = "cpu";
87 reg = <0>;
88 clocks = <&ccu CLK_CPU>;
89 clock-names = "cpu";
90 #cooling-cells = <2>;
91 };
92
93 cpu1: cpu@1 {
94 compatible = "arm,cortex-a7";
95 device_type = "cpu";
96 reg = <1>;
97 clocks = <&ccu CLK_CPU>;
98 clock-names = "cpu";
99 #cooling-cells = <2>;
100 };
101
102 cpu2: cpu@2 {
103 compatible = "arm,cortex-a7";
104 device_type = "cpu";
105 reg = <2>;
106 clocks = <&ccu CLK_CPU>;
107 clock-names = "cpu";
108 #cooling-cells = <2>;
109 };
110
111 cpu3: cpu@3 {
112 compatible = "arm,cortex-a7";
113 device_type = "cpu";
114 reg = <3>;
115 clocks = <&ccu CLK_CPU>;
116 clock-names = "cpu";
117 #cooling-cells = <2>;
118 };
119 };
120
121 de: display-engine {
122 compatible = "allwinner,sun8i-r40-display-engine";
123 allwinner,pipelines = <&mixer0>, <&mixer1>;
124 status = "disabled";
125 };
126
127 thermal-zones {
128 cpu_thermal: cpu0-thermal {
129 /* milliseconds */
130 polling-delay-passive = <0>;
131 polling-delay = <0>;
132 thermal-sensors = <&ths 0>;
133
134 trips {
135 cpu_hot_trip: cpu-hot {
136 temperature = <80000>;
137 hysteresis = <2000>;
138 type = "passive";
139 };
140
141 cpu_very_hot_trip: cpu-very-hot {
142 temperature = <115000>;
143 hysteresis = <0>;
144 type = "critical";
145 };
146 };
147
148 cooling-maps {
149 cpu-hot-limit {
150 trip = <&cpu_hot_trip>;
151 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
152 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
153 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
154 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
155 };
156 };
157 };
158
159 gpu_thermal: gpu-thermal {
160 /* milliseconds */
161 polling-delay-passive = <0>;
162 polling-delay = <0>;
163 thermal-sensors = <&ths 1>;
164 };
165 };
166
167 soc {
168 compatible = "simple-bus";
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges;
172
173 display_clocks: clock@1000000 {
174 compatible = "allwinner,sun8i-r40-de2-clk",
175 "allwinner,sun8i-h3-de2-clk";
176 reg = <0x01000000 0x10000>;
177 clocks = <&ccu CLK_BUS_DE>,
178 <&ccu CLK_DE>;
179 clock-names = "bus",
180 "mod";
181 resets = <&ccu RST_BUS_DE>;
182 #clock-cells = <1>;
183 #reset-cells = <1>;
184 };
185
186 mixer0: mixer@1100000 {
187 compatible = "allwinner,sun8i-r40-de2-mixer-0";
188 reg = <0x01100000 0x100000>;
189 clocks = <&display_clocks CLK_BUS_MIXER0>,
190 <&display_clocks CLK_MIXER0>;
191 clock-names = "bus",
192 "mod";
193 resets = <&display_clocks RST_MIXER0>;
194
195 ports {
196 #address-cells = <1>;
197 #size-cells = <0>;
198
199 mixer0_out: port@1 {
200 reg = <1>;
201 mixer0_out_tcon_top: endpoint {
202 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
203 };
204 };
205 };
206 };
207
208 mixer1: mixer@1200000 {
209 compatible = "allwinner,sun8i-r40-de2-mixer-1";
210 reg = <0x01200000 0x100000>;
211 clocks = <&display_clocks CLK_BUS_MIXER1>,
212 <&display_clocks CLK_MIXER1>;
213 clock-names = "bus",
214 "mod";
215 resets = <&display_clocks RST_WB>;
216
217 ports {
218 #address-cells = <1>;
219 #size-cells = <0>;
220
221 mixer1_out: port@1 {
222 reg = <1>;
223 mixer1_out_tcon_top: endpoint {
224 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
225 };
226 };
227 };
228 };
229
230 deinterlace: deinterlace@1400000 {
231 compatible = "allwinner,sun8i-r40-deinterlace",
232 "allwinner,sun8i-h3-deinterlace";
233 reg = <0x01400000 0x20000>;
234 clocks = <&ccu CLK_BUS_DEINTERLACE>,
235 <&ccu CLK_DEINTERLACE>,
236 /*
237 * NOTE: Contrary to what datasheet claims,
238 * DRAM deinterlace gate doesn't exist and
239 * it's shared with CSI1.
240 */
241 <&ccu CLK_DRAM_CSI1>;
242 clock-names = "bus", "mod", "ram";
243 resets = <&ccu RST_BUS_DEINTERLACE>;
244 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
245 interconnects = <&mbus 9>;
246 interconnect-names = "dma-mem";
247 };
248
249 syscon: system-control@1c00000 {
250 compatible = "allwinner,sun8i-r40-system-control",
251 "allwinner,sun4i-a10-system-control";
252 reg = <0x01c00000 0x30>;
253 #address-cells = <1>;
254 #size-cells = <1>;
255 ranges;
256
257 sram_c: sram@1d00000 {
258 compatible = "mmio-sram";
259 reg = <0x01d00000 0xd0000>;
260 #address-cells = <1>;
261 #size-cells = <1>;
262 ranges = <0 0x01d00000 0xd0000>;
263
264 ve_sram: sram-section@0 {
265 compatible = "allwinner,sun8i-r40-sram-c1",
266 "allwinner,sun4i-a10-sram-c1";
267 reg = <0x000000 0x80000>;
268 };
269 };
270 };
271
272 nmi_intc: interrupt-controller@1c00030 {
273 compatible = "allwinner,sun7i-a20-sc-nmi";
274 interrupt-controller;
275 #interrupt-cells = <2>;
276 reg = <0x01c00030 0x0c>;
277 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
278 };
279
280 dma: dma-controller@1c02000 {
281 compatible = "allwinner,sun8i-r40-dma",
282 "allwinner,sun50i-a64-dma";
283 reg = <0x01c02000 0x1000>;
284 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&ccu CLK_BUS_DMA>;
286 dma-channels = <16>;
287 dma-requests = <31>;
288 resets = <&ccu RST_BUS_DMA>;
289 #dma-cells = <1>;
290 };
291
292 spi0: spi@1c05000 {
293 compatible = "allwinner,sun8i-r40-spi",
294 "allwinner,sun8i-h3-spi";
295 reg = <0x01c05000 0x1000>;
296 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
298 clock-names = "ahb", "mod";
299 resets = <&ccu RST_BUS_SPI0>;
300 status = "disabled";
301 #address-cells = <1>;
302 #size-cells = <0>;
303 };
304
305 spi1: spi@1c06000 {
306 compatible = "allwinner,sun8i-r40-spi",
307 "allwinner,sun8i-h3-spi";
308 reg = <0x01c06000 0x1000>;
309 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
311 clock-names = "ahb", "mod";
312 resets = <&ccu RST_BUS_SPI1>;
313 status = "disabled";
314 #address-cells = <1>;
315 #size-cells = <0>;
316 };
317
318 csi0: csi@1c09000 {
319 compatible = "allwinner,sun8i-r40-csi0",
320 "allwinner,sun7i-a20-csi0";
321 reg = <0x01c09000 0x1000>;
322 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
324 <&ccu CLK_DRAM_CSI0>;
325 clock-names = "bus", "isp", "ram";
326 resets = <&ccu RST_BUS_CSI0>;
327 interconnects = <&mbus 5>;
328 interconnect-names = "dma-mem";
329 status = "disabled";
330 };
331
332 video-codec@1c0e000 {
333 compatible = "allwinner,sun8i-r40-video-engine";
334 reg = <0x01c0e000 0x1000>;
335 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
336 <&ccu CLK_DRAM_VE>;
337 clock-names = "ahb", "mod", "ram";
338 resets = <&ccu RST_BUS_VE>;
339 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
340 allwinner,sram = <&ve_sram 1>;
341 };
342
343 mmc0: mmc@1c0f000 {
344 compatible = "allwinner,sun8i-r40-mmc",
345 "allwinner,sun50i-a64-mmc";
346 reg = <0x01c0f000 0x1000>;
347 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
348 clock-names = "ahb", "mmc";
349 resets = <&ccu RST_BUS_MMC0>;
350 reset-names = "ahb";
351 pinctrl-0 = <&mmc0_pins>;
352 pinctrl-names = "default";
353 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
354 status = "disabled";
355 #address-cells = <1>;
356 #size-cells = <0>;
357 };
358
359 mmc1: mmc@1c10000 {
360 compatible = "allwinner,sun8i-r40-mmc",
361 "allwinner,sun50i-a64-mmc";
362 reg = <0x01c10000 0x1000>;
363 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
364 clock-names = "ahb", "mmc";
365 resets = <&ccu RST_BUS_MMC1>;
366 reset-names = "ahb";
367 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
368 status = "disabled";
369 #address-cells = <1>;
370 #size-cells = <0>;
371 };
372
373 mmc2: mmc@1c11000 {
374 compatible = "allwinner,sun8i-r40-emmc",
375 "allwinner,sun50i-a64-emmc";
376 reg = <0x01c11000 0x1000>;
377 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
378 clock-names = "ahb", "mmc";
379 resets = <&ccu RST_BUS_MMC2>;
380 reset-names = "ahb";
381 pinctrl-0 = <&mmc2_pins>;
382 pinctrl-names = "default";
383 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
384 status = "disabled";
385 #address-cells = <1>;
386 #size-cells = <0>;
387 };
388
389 mmc3: mmc@1c12000 {
390 compatible = "allwinner,sun8i-r40-mmc",
391 "allwinner,sun50i-a64-mmc";
392 reg = <0x01c12000 0x1000>;
393 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
394 clock-names = "ahb", "mmc";
395 resets = <&ccu RST_BUS_MMC3>;
396 reset-names = "ahb";
397 pinctrl-0 = <&mmc3_pins>;
398 pinctrl-names = "default";
399 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
400 status = "disabled";
401 #address-cells = <1>;
402 #size-cells = <0>;
403 };
404
405 usbphy: phy@1c13400 {
406 compatible = "allwinner,sun8i-r40-usb-phy";
407 reg = <0x01c13400 0x14>,
408 <0x01c14800 0x4>,
409 <0x01c19800 0x4>,
410 <0x01c1c800 0x4>;
411 reg-names = "phy_ctrl",
412 "pmu0",
413 "pmu1",
414 "pmu2";
415 clocks = <&ccu CLK_USB_PHY0>,
416 <&ccu CLK_USB_PHY1>,
417 <&ccu CLK_USB_PHY2>;
418 clock-names = "usb0_phy",
419 "usb1_phy",
420 "usb2_phy";
421 resets = <&ccu RST_USB_PHY0>,
422 <&ccu RST_USB_PHY1>,
423 <&ccu RST_USB_PHY2>;
424 reset-names = "usb0_reset",
425 "usb1_reset",
426 "usb2_reset";
427 status = "disabled";
428 #phy-cells = <1>;
429 };
430
431 crypto: crypto@1c15000 {
432 compatible = "allwinner,sun8i-r40-crypto";
433 reg = <0x01c15000 0x1000>;
434 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
436 clock-names = "bus", "mod";
437 resets = <&ccu RST_BUS_CE>;
438 };
439
440 spi2: spi@1c17000 {
441 compatible = "allwinner,sun8i-r40-spi",
442 "allwinner,sun8i-h3-spi";
443 reg = <0x01c17000 0x1000>;
444 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
446 clock-names = "ahb", "mod";
447 resets = <&ccu RST_BUS_SPI2>;
448 status = "disabled";
449 #address-cells = <1>;
450 #size-cells = <0>;
451 };
452
453 ahci: sata@1c18000 {
454 compatible = "allwinner,sun8i-r40-ahci";
455 reg = <0x01c18000 0x1000>;
456 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
458 resets = <&ccu RST_BUS_SATA>;
459 reset-names = "ahci";
460 status = "disabled";
461 };
462
463 ehci1: usb@1c19000 {
464 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
465 reg = <0x01c19000 0x100>;
466 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&ccu CLK_BUS_EHCI1>;
468 resets = <&ccu RST_BUS_EHCI1>;
469 phys = <&usbphy 1>;
470 phy-names = "usb";
471 status = "disabled";
472 };
473
474 ohci1: usb@1c19400 {
475 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
476 reg = <0x01c19400 0x100>;
477 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&ccu CLK_BUS_OHCI1>,
479 <&ccu CLK_USB_OHCI1>;
480 resets = <&ccu RST_BUS_OHCI1>;
481 phys = <&usbphy 1>;
482 phy-names = "usb";
483 status = "disabled";
484 };
485
486 ehci2: usb@1c1c000 {
487 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
488 reg = <0x01c1c000 0x100>;
489 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&ccu CLK_BUS_EHCI2>;
491 resets = <&ccu RST_BUS_EHCI2>;
492 phys = <&usbphy 2>;
493 phy-names = "usb";
494 status = "disabled";
495 };
496
497 ohci2: usb@1c1c400 {
498 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
499 reg = <0x01c1c400 0x100>;
500 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&ccu CLK_BUS_OHCI2>,
502 <&ccu CLK_USB_OHCI2>;
503 resets = <&ccu RST_BUS_OHCI2>;
504 phys = <&usbphy 2>;
505 phy-names = "usb";
506 status = "disabled";
507 };
508
509 spi3: spi@1c1f000 {
510 compatible = "allwinner,sun8i-r40-spi",
511 "allwinner,sun8i-h3-spi";
512 reg = <0x01c1f000 0x1000>;
513 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
515 clock-names = "ahb", "mod";
516 resets = <&ccu RST_BUS_SPI3>;
517 status = "disabled";
518 #address-cells = <1>;
519 #size-cells = <0>;
520 };
521
522 ccu: clock@1c20000 {
523 compatible = "allwinner,sun8i-r40-ccu";
524 reg = <0x01c20000 0x400>;
525 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
526 clock-names = "hosc", "losc";
527 #clock-cells = <1>;
528 #reset-cells = <1>;
529 };
530
531 rtc: rtc@1c20400 {
532 compatible = "allwinner,sun8i-r40-rtc";
533 reg = <0x01c20400 0x400>;
534 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
535 clock-output-names = "osc32k", "osc32k-out";
536 clocks = <&osc32k>;
537 #clock-cells = <1>;
538 };
539
540 pio: pinctrl@1c20800 {
541 compatible = "allwinner,sun8i-r40-pinctrl";
542 reg = <0x01c20800 0x400>;
543 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
545 <&rtc CLK_OSC32K>;
546 clock-names = "apb", "hosc", "losc";
547 gpio-controller;
548 interrupt-controller;
549 #interrupt-cells = <3>;
550 #gpio-cells = <3>;
551
552 can_ph_pins: can-ph-pins {
553 pins = "PH20", "PH21";
554 function = "can";
555 };
556
557 can_pa_pins: can-pa-pins {
558 pins = "PA16", "PA17";
559 function = "can";
560 };
561
562 clk_out_a_pin: clk-out-a-pin {
563 pins = "PI12";
564 function = "clk_out_a";
565 };
566
567 /omit-if-no-ref/
568 csi0_8bits_pins: csi0-8bits-pins {
569 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
570 "PE6", "PE7", "PE8", "PE9", "PE10",
571 "PE11";
572 function = "csi0";
573 };
574
575 /omit-if-no-ref/
576 csi0_mclk_pin: csi0-mclk-pin {
577 pins = "PE1";
578 function = "csi0";
579 };
580
581 gmac_rgmii_pins: gmac-rgmii-pins {
582 pins = "PA0", "PA1", "PA2", "PA3",
583 "PA4", "PA5", "PA6", "PA7",
584 "PA8", "PA10", "PA11", "PA12",
585 "PA13", "PA15", "PA16";
586 function = "gmac";
587 /*
588 * data lines in RGMII mode use DDR mode
589 * and need a higher signal drive strength
590 */
591 drive-strength = <40>;
592 };
593
594 i2c0_pins: i2c0-pins {
595 pins = "PB0", "PB1";
596 function = "i2c0";
597 };
598
599 i2c1_pins: i2c1-pins {
600 pins = "PB18", "PB19";
601 function = "i2c1";
602 };
603
604 i2c2_pins: i2c2-pins {
605 pins = "PB20", "PB21";
606 function = "i2c2";
607 };
608
609 i2c3_pins: i2c3-pins {
610 pins = "PI0", "PI1";
611 function = "i2c3";
612 };
613
614 i2c4_pins: i2c4-pins {
615 pins = "PI2", "PI3";
616 function = "i2c4";
617 };
618
619 ir0_pins: ir0-pins {
620 pins = "PB4";
621 function = "ir0";
622 };
623
624 ir1_pins: ir1-pins {
625 pins = "PB23";
626 function = "ir1";
627 };
628
629 mmc0_pins: mmc0-pins {
630 pins = "PF0", "PF1", "PF2",
631 "PF3", "PF4", "PF5";
632 function = "mmc0";
633 drive-strength = <30>;
634 bias-pull-up;
635 };
636
637 mmc1_pg_pins: mmc1-pg-pins {
638 pins = "PG0", "PG1", "PG2",
639 "PG3", "PG4", "PG5";
640 function = "mmc1";
641 drive-strength = <30>;
642 bias-pull-up;
643 };
644
645 mmc2_pins: mmc2-pins {
646 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
647 "PC10", "PC11", "PC12", "PC13", "PC14",
648 "PC15", "PC24";
649 function = "mmc2";
650 drive-strength = <30>;
651 bias-pull-up;
652 };
653
654 /omit-if-no-ref/
655 mmc3_pins: mmc3-pins {
656 pins = "PI4", "PI5", "PI6",
657 "PI7", "PI8", "PI9";
658 function = "mmc3";
659 drive-strength = <30>;
660 bias-pull-up;
661 };
662
663 /omit-if-no-ref/
664 spi0_pc_pins: spi0-pc-pins {
665 pins = "PC0", "PC1", "PC2";
666 function = "spi0";
667 };
668
669 /omit-if-no-ref/
670 spi0_cs0_pc_pin: spi0-cs0-pc-pin {
671 pins = "PC23";
672 function = "spi0";
673 };
674
675 /omit-if-no-ref/
676 spi1_pi_pins: spi1-pi-pins {
677 pins = "PI17", "PI18", "PI19";
678 function = "spi1";
679 };
680
681 /omit-if-no-ref/
682 spi1_cs0_pi_pin: spi1-cs0-pi-pin {
683 pins = "PI16";
684 function = "spi1";
685 };
686
687 /omit-if-no-ref/
688 spi1_cs1_pi_pin: spi1-cs1-pi-pin {
689 pins = "PI15";
690 function = "spi1";
691 };
692
693 /omit-if-no-ref/
694 uart0_pb_pins: uart0-pb-pins {
695 pins = "PB22", "PB23";
696 function = "uart0";
697 };
698
699 /omit-if-no-ref/
700 uart2_pi_pins: uart2-pi-pins {
701 pins = "PI18", "PI19";
702 function = "uart2";
703 };
704
705 /omit-if-no-ref/
706 uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{
707 pins = "PI16", "PI17";
708 function = "uart2";
709 };
710
711 /omit-if-no-ref/
712 uart3_pg_pins: uart3-pg-pins {
713 pins = "PG6", "PG7";
714 function = "uart3";
715 };
716
717 /omit-if-no-ref/
718 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
719 pins = "PG8", "PG9";
720 function = "uart3";
721 };
722
723 /omit-if-no-ref/
724 uart4_pg_pins: uart4-pg-pins {
725 pins = "PG10", "PG11";
726 function = "uart4";
727 };
728
729 /omit-if-no-ref/
730 uart5_ph_pins: uart5-ph-pins {
731 pins = "PH6", "PH7";
732 function = "uart5";
733 };
734
735 /omit-if-no-ref/
736 uart7_pi_pins: uart7-pi-pins {
737 pins = "PI20", "PI21";
738 function = "uart7";
739 };
740 };
741
742 timer@1c20c00 {
743 compatible = "allwinner,sun4i-a10-timer";
744 reg = <0x01c20c00 0x90>;
745 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&osc24M>;
752 };
753
754 wdt: watchdog@1c20c90 {
755 compatible = "allwinner,sun4i-a10-wdt";
756 reg = <0x01c20c90 0x10>;
757 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&osc24M>;
759 };
760
761 ir0: ir@1c21800 {
762 compatible = "allwinner,sun8i-r40-ir",
763 "allwinner,sun6i-a31-ir";
764 reg = <0x01c21800 0x400>;
765 pinctrl-0 = <&ir0_pins>;
766 pinctrl-names = "default";
767 clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>;
768 clock-names = "apb", "ir";
769 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
770 resets = <&ccu RST_BUS_IR0>;
771 status = "disabled";
772 };
773
774 ir1: ir@1c21c00 {
775 compatible = "allwinner,sun8i-r40-ir",
776 "allwinner,sun6i-a31-ir";
777 reg = <0x01c21c00 0x400>;
778 pinctrl-0 = <&ir1_pins>;
779 pinctrl-names = "default";
780 clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>;
781 clock-names = "apb", "ir";
782 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
783 resets = <&ccu RST_BUS_IR1>;
784 status = "disabled";
785 };
786
787 i2s0: i2s@1c22000 {
788 #sound-dai-cells = <0>;
789 compatible = "allwinner,sun8i-r40-i2s",
790 "allwinner,sun8i-h3-i2s";
791 reg = <0x01c22000 0x400>;
792 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
794 clock-names = "apb", "mod";
795 resets = <&ccu RST_BUS_I2S0>;
796 dmas = <&dma 3>, <&dma 3>;
797 dma-names = "rx", "tx";
798 };
799
800 i2s1: i2s@1c22400 {
801 #sound-dai-cells = <0>;
802 compatible = "allwinner,sun8i-r40-i2s",
803 "allwinner,sun8i-h3-i2s";
804 reg = <0x01c22400 0x400>;
805 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
807 clock-names = "apb", "mod";
808 resets = <&ccu RST_BUS_I2S1>;
809 dmas = <&dma 4>, <&dma 4>;
810 dma-names = "rx", "tx";
811 };
812
813 i2s2: i2s@1c22800 {
814 #sound-dai-cells = <0>;
815 compatible = "allwinner,sun8i-r40-i2s",
816 "allwinner,sun8i-h3-i2s";
817 reg = <0x01c22800 0x400>;
818 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
820 clock-names = "apb", "mod";
821 resets = <&ccu RST_BUS_I2S2>;
822 dmas = <&dma 6>, <&dma 6>;
823 dma-names = "rx", "tx";
824 };
825
826 ths: thermal-sensor@1c24c00 {
827 compatible = "allwinner,sun8i-r40-ths";
828 reg = <0x01c24c00 0x100>;
829 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
830 clock-names = "bus", "mod";
831 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
832 resets = <&ccu RST_BUS_THS>;
833 /* TODO: add nvmem-cells for calibration */
834 #thermal-sensor-cells = <1>;
835 };
836
837 uart0: serial@1c28000 {
838 compatible = "snps,dw-apb-uart";
839 reg = <0x01c28000 0x400>;
840 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
841 reg-shift = <2>;
842 reg-io-width = <4>;
843 clocks = <&ccu CLK_BUS_UART0>;
844 resets = <&ccu RST_BUS_UART0>;
845 status = "disabled";
846 };
847
848 uart1: serial@1c28400 {
849 compatible = "snps,dw-apb-uart";
850 reg = <0x01c28400 0x400>;
851 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
852 reg-shift = <2>;
853 reg-io-width = <4>;
854 clocks = <&ccu CLK_BUS_UART1>;
855 resets = <&ccu RST_BUS_UART1>;
856 status = "disabled";
857 };
858
859 uart2: serial@1c28800 {
860 compatible = "snps,dw-apb-uart";
861 reg = <0x01c28800 0x400>;
862 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
863 reg-shift = <2>;
864 reg-io-width = <4>;
865 clocks = <&ccu CLK_BUS_UART2>;
866 resets = <&ccu RST_BUS_UART2>;
867 status = "disabled";
868 };
869
870 uart3: serial@1c28c00 {
871 compatible = "snps,dw-apb-uart";
872 reg = <0x01c28c00 0x400>;
873 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
874 reg-shift = <2>;
875 reg-io-width = <4>;
876 clocks = <&ccu CLK_BUS_UART3>;
877 resets = <&ccu RST_BUS_UART3>;
878 status = "disabled";
879 };
880
881 uart4: serial@1c29000 {
882 compatible = "snps,dw-apb-uart";
883 reg = <0x01c29000 0x400>;
884 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
885 reg-shift = <2>;
886 reg-io-width = <4>;
887 clocks = <&ccu CLK_BUS_UART4>;
888 resets = <&ccu RST_BUS_UART4>;
889 status = "disabled";
890 };
891
892 uart5: serial@1c29400 {
893 compatible = "snps,dw-apb-uart";
894 reg = <0x01c29400 0x400>;
895 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
896 reg-shift = <2>;
897 reg-io-width = <4>;
898 clocks = <&ccu CLK_BUS_UART5>;
899 resets = <&ccu RST_BUS_UART5>;
900 status = "disabled";
901 };
902
903 uart6: serial@1c29800 {
904 compatible = "snps,dw-apb-uart";
905 reg = <0x01c29800 0x400>;
906 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
907 reg-shift = <2>;
908 reg-io-width = <4>;
909 clocks = <&ccu CLK_BUS_UART6>;
910 resets = <&ccu RST_BUS_UART6>;
911 status = "disabled";
912 };
913
914 uart7: serial@1c29c00 {
915 compatible = "snps,dw-apb-uart";
916 reg = <0x01c29c00 0x400>;
917 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
918 reg-shift = <2>;
919 reg-io-width = <4>;
920 clocks = <&ccu CLK_BUS_UART7>;
921 resets = <&ccu RST_BUS_UART7>;
922 status = "disabled";
923 };
924
925 i2c0: i2c@1c2ac00 {
926 compatible = "allwinner,sun6i-a31-i2c";
927 reg = <0x01c2ac00 0x400>;
928 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&ccu CLK_BUS_I2C0>;
930 resets = <&ccu RST_BUS_I2C0>;
931 pinctrl-0 = <&i2c0_pins>;
932 pinctrl-names = "default";
933 status = "disabled";
934 #address-cells = <1>;
935 #size-cells = <0>;
936 };
937
938 i2c1: i2c@1c2b000 {
939 compatible = "allwinner,sun6i-a31-i2c";
940 reg = <0x01c2b000 0x400>;
941 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
942 clocks = <&ccu CLK_BUS_I2C1>;
943 resets = <&ccu RST_BUS_I2C1>;
944 pinctrl-0 = <&i2c1_pins>;
945 pinctrl-names = "default";
946 status = "disabled";
947 #address-cells = <1>;
948 #size-cells = <0>;
949 };
950
951 i2c2: i2c@1c2b400 {
952 compatible = "allwinner,sun6i-a31-i2c";
953 reg = <0x01c2b400 0x400>;
954 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&ccu CLK_BUS_I2C2>;
956 resets = <&ccu RST_BUS_I2C2>;
957 pinctrl-0 = <&i2c2_pins>;
958 pinctrl-names = "default";
959 status = "disabled";
960 #address-cells = <1>;
961 #size-cells = <0>;
962 };
963
964 i2c3: i2c@1c2b800 {
965 compatible = "allwinner,sun6i-a31-i2c";
966 reg = <0x01c2b800 0x400>;
967 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&ccu CLK_BUS_I2C3>;
969 resets = <&ccu RST_BUS_I2C3>;
970 pinctrl-0 = <&i2c3_pins>;
971 pinctrl-names = "default";
972 status = "disabled";
973 #address-cells = <1>;
974 #size-cells = <0>;
975 };
976
977 can0: can@1c2bc00 {
978 compatible = "allwinner,sun8i-r40-can";
979 reg = <0x01c2bc00 0x400>;
980 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&ccu CLK_BUS_CAN>;
982 resets = <&ccu RST_BUS_CAN>;
983 status = "disabled";
984 };
985
986 i2c4: i2c@1c2c000 {
987 compatible = "allwinner,sun6i-a31-i2c";
988 reg = <0x01c2c000 0x400>;
989 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
990 clocks = <&ccu CLK_BUS_I2C4>;
991 resets = <&ccu RST_BUS_I2C4>;
992 pinctrl-0 = <&i2c4_pins>;
993 pinctrl-names = "default";
994 status = "disabled";
995 #address-cells = <1>;
996 #size-cells = <0>;
997 };
998
999 mali: gpu@1c40000 {
1000 compatible = "allwinner,sun8i-r40-mali", "arm,mali-400";
1001 reg = <0x01c40000 0x10000>;
1002 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1004 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1006 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1007 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1008 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1009 interrupt-names = "gp",
1010 "gpmmu",
1011 "pp0",
1012 "ppmmu0",
1013 "pp1",
1014 "ppmmu1",
1015 "pmu";
1016 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1017 clock-names = "bus", "core";
1018 resets = <&ccu RST_BUS_GPU>;
1019 };
1020
1021 gmac: ethernet@1c50000 {
1022 compatible = "allwinner,sun8i-r40-gmac";
1023 syscon = <&ccu>;
1024 reg = <0x01c50000 0x10000>;
1025 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1026 interrupt-names = "macirq";
1027 resets = <&ccu RST_BUS_GMAC>;
1028 reset-names = "stmmaceth";
1029 clocks = <&ccu CLK_BUS_GMAC>;
1030 clock-names = "stmmaceth";
1031 status = "disabled";
1032
1033 gmac_mdio: mdio {
1034 compatible = "snps,dwmac-mdio";
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1037 };
1038 };
1039
1040 mbus: dram-controller@1c62000 {
1041 compatible = "allwinner,sun8i-r40-mbus";
1042 reg = <0x01c62000 0x1000>;
1043 clocks = <&ccu 155>;
1044 #address-cells = <1>;
1045 #size-cells = <1>;
1046 dma-ranges = <0x00000000 0x40000000 0x80000000>;
1047 #interconnect-cells = <1>;
1048 };
1049
1050 tcon_top: tcon-top@1c70000 {
1051 compatible = "allwinner,sun8i-r40-tcon-top";
1052 reg = <0x01c70000 0x1000>;
1053 clocks = <&ccu CLK_BUS_TCON_TOP>,
1054 <&ccu CLK_TCON_TV0>,
1055 <&ccu CLK_TVE0>,
1056 <&ccu CLK_TCON_TV1>,
1057 <&ccu CLK_TVE1>,
1058 <&ccu CLK_DSI_DPHY>;
1059 clock-names = "bus",
1060 "tcon-tv0",
1061 "tve0",
1062 "tcon-tv1",
1063 "tve1",
1064 "dsi";
1065 clock-output-names = "tcon-top-tv0",
1066 "tcon-top-tv1",
1067 "tcon-top-dsi";
1068 resets = <&ccu RST_BUS_TCON_TOP>;
1069 #clock-cells = <1>;
1070
1071 ports {
1072 #address-cells = <1>;
1073 #size-cells = <0>;
1074
1075 tcon_top_mixer0_in: port@0 {
1076 reg = <0>;
1077
1078 tcon_top_mixer0_in_mixer0: endpoint {
1079 remote-endpoint = <&mixer0_out_tcon_top>;
1080 };
1081 };
1082
1083 tcon_top_mixer0_out: port@1 {
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1086 reg = <1>;
1087
1088 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
1089 reg = <0>;
1090 };
1091
1092 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
1093 reg = <1>;
1094 };
1095
1096 tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
1097 reg = <2>;
1098 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
1099 };
1100
1101 tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
1102 reg = <3>;
1103 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
1104 };
1105 };
1106
1107 tcon_top_mixer1_in: port@2 {
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1110 reg = <2>;
1111
1112 tcon_top_mixer1_in_mixer1: endpoint@1 {
1113 reg = <1>;
1114 remote-endpoint = <&mixer1_out_tcon_top>;
1115 };
1116 };
1117
1118 tcon_top_mixer1_out: port@3 {
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1121 reg = <3>;
1122
1123 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
1124 reg = <0>;
1125 };
1126
1127 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
1128 reg = <1>;
1129 };
1130
1131 tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
1132 reg = <2>;
1133 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
1134 };
1135
1136 tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
1137 reg = <3>;
1138 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
1139 };
1140 };
1141
1142 tcon_top_hdmi_in: port@4 {
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1145 reg = <4>;
1146
1147 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
1148 reg = <0>;
1149 remote-endpoint = <&tcon_tv0_out_tcon_top>;
1150 };
1151
1152 tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
1153 reg = <1>;
1154 remote-endpoint = <&tcon_tv1_out_tcon_top>;
1155 };
1156 };
1157
1158 tcon_top_hdmi_out: port@5 {
1159 reg = <5>;
1160
1161 tcon_top_hdmi_out_hdmi: endpoint {
1162 remote-endpoint = <&hdmi_in_tcon_top>;
1163 };
1164 };
1165 };
1166 };
1167
1168 tcon_tv0: lcd-controller@1c73000 {
1169 compatible = "allwinner,sun8i-r40-tcon-tv";
1170 reg = <0x01c73000 0x1000>;
1171 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1172 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
1173 clock-names = "ahb", "tcon-ch1";
1174 resets = <&ccu RST_BUS_TCON_TV0>;
1175 reset-names = "lcd";
1176 status = "disabled";
1177
1178 ports {
1179 #address-cells = <1>;
1180 #size-cells = <0>;
1181
1182 tcon_tv0_in: port@0 {
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1185 reg = <0>;
1186
1187 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
1188 reg = <0>;
1189 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
1190 };
1191
1192 tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
1193 reg = <1>;
1194 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
1195 };
1196 };
1197
1198 tcon_tv0_out: port@1 {
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1201 reg = <1>;
1202
1203 tcon_tv0_out_tcon_top: endpoint@1 {
1204 reg = <1>;
1205 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
1206 };
1207 };
1208 };
1209 };
1210
1211 tcon_tv1: lcd-controller@1c74000 {
1212 compatible = "allwinner,sun8i-r40-tcon-tv";
1213 reg = <0x01c74000 0x1000>;
1214 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
1216 clock-names = "ahb", "tcon-ch1";
1217 resets = <&ccu RST_BUS_TCON_TV1>;
1218 reset-names = "lcd";
1219 status = "disabled";
1220
1221 ports {
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1224
1225 tcon_tv1_in: port@0 {
1226 #address-cells = <1>;
1227 #size-cells = <0>;
1228 reg = <0>;
1229
1230 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
1231 reg = <0>;
1232 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
1233 };
1234
1235 tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
1236 reg = <1>;
1237 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
1238 };
1239 };
1240
1241 tcon_tv1_out: port@1 {
1242 #address-cells = <1>;
1243 #size-cells = <0>;
1244 reg = <1>;
1245
1246 tcon_tv1_out_tcon_top: endpoint@1 {
1247 reg = <1>;
1248 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
1249 };
1250 };
1251 };
1252 };
1253
1254 gic: interrupt-controller@1c81000 {
1255 compatible = "arm,gic-400";
1256 reg = <0x01c81000 0x1000>,
1257 <0x01c82000 0x2000>,
1258 <0x01c84000 0x2000>,
1259 <0x01c86000 0x2000>;
1260 interrupt-controller;
1261 #interrupt-cells = <3>;
1262 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1263 };
1264
1265 hdmi: hdmi@1ee0000 {
1266 compatible = "allwinner,sun8i-r40-dw-hdmi",
1267 "allwinner,sun8i-a83t-dw-hdmi";
1268 reg = <0x01ee0000 0x10000>;
1269 reg-io-width = <1>;
1270 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1271 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
1272 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
1273 clock-names = "iahb", "isfr", "tmds", "cec";
1274 resets = <&ccu RST_BUS_HDMI1>;
1275 reset-names = "ctrl";
1276 phys = <&hdmi_phy>;
1277 phy-names = "phy";
1278 status = "disabled";
1279
1280 ports {
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1283
1284 hdmi_in: port@0 {
1285 reg = <0>;
1286
1287 hdmi_in_tcon_top: endpoint {
1288 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
1289 };
1290 };
1291
1292 hdmi_out: port@1 {
1293 reg = <1>;
1294 };
1295 };
1296 };
1297
1298 hdmi_phy: hdmi-phy@1ef0000 {
1299 compatible = "allwinner,sun8i-r40-hdmi-phy";
1300 reg = <0x01ef0000 0x10000>;
1301 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
1302 <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
1303 clock-names = "bus", "mod", "pll-0", "pll-1";
1304 resets = <&ccu RST_BUS_HDMI0>;
1305 reset-names = "phy";
1306 #phy-cells = <0>;
1307 };
1308 };
1309
1310 pmu {
1311 compatible = "arm,cortex-a7-pmu";
1312 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1313 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1314 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1315 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1316 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1317 };
1318
1319 timer {
1320 compatible = "arm,armv7-timer";
1321 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1322 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1323 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1324 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1325 };
1326};