1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
  4 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
  5 */
  6
  7/dts-v1/;
  8#include "rv1126.dtsi"
  9#include "rv1126-edgeble-neu2.dtsi"
 10
 11/ {
 12	model = "Edgeble Neu2 IO Board";
 13	compatible = "edgeble,neural-compute-module-2-io",
 14		     "edgeble,neural-compute-module-2", "rockchip,rv1126";
 15
 16	aliases {
 17		serial2 = &uart2;
 18	};
 19
 20	chosen {
 21		stdout-path = "serial2:1500000n8";
 22	};
 23
 24	vcc12v_dcin: regulator-vcc12v-dcin {
 25		compatible = "regulator-fixed";
 26		regulator-name = "vcc12v_dcin";
 27		regulator-always-on;
 28		regulator-boot-on;
 29		regulator-min-microvolt = <12000000>;
 30		regulator-max-microvolt = <12000000>;
 31	};
 32
 33	vcc5v0_sys: regulator-vcc5v0-sys {
 34		compatible = "regulator-fixed";
 35		regulator-name = "vcc5v0_sys";
 36		regulator-always-on;
 37		regulator-boot-on;
 38		regulator-min-microvolt = <5000000>;
 39		regulator-max-microvolt = <5000000>;
 40		vin-supply = <&vcc12v_dcin>;
 41	};
 42
 43	v3v3_sys: regulator-v3v3-sys {
 44		compatible = "regulator-fixed";
 45		regulator-name = "v3v3_sys";
 46		regulator-always-on;
 47		regulator-boot-on;
 48		regulator-min-microvolt = <3300000>;
 49		regulator-max-microvolt = <3300000>;
 50		vin-supply = <&vcc5v0_sys>;
 51	};
 52};
 53
 54&gmac {
 55	assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
 56			  <&cru CLK_GMAC_ETHERNET_OUT>;
 57	assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
 58	assigned-clock-rates = <125000000>, <0>, <25000000>;
 59	clock_in_out = "input";
 60	phy-handle = <&phy>;
 61	phy-mode = "rgmii";
 62	phy-supply = <&vcc_3v3>;
 63	pinctrl-names = "default";
 64	pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clk_out_ethernetm1_pins>;
 65	tx_delay = <0x2a>;
 66	rx_delay = <0x1a>;
 67	status = "okay";
 68};
 69
 70&mdio {
 71	phy: ethernet-phy@0 {
 72		compatible = "ethernet-phy-id001c.c916";
 73		reg = <0x0>;
 74		pinctrl-names = "default";
 75		pinctrl-0 = <&eth_phy_rst>;
 76		reset-assert-us = <20000>;
 77		reset-deassert-us = <100000>;
 78		reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
 79	};
 80};
 81
 82&pinctrl {
 83	ethernet {
 84		eth_phy_rst: eth-phy-rst {
 85			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
 86		};
 87	};
 88};
 89
 90&pwm11 {
 91	status = "okay";
 92};
 93
 94&sdmmc {
 95	bus-width = <4>;
 96	cap-mmc-highspeed;
 97	cap-sd-highspeed;
 98	card-detect-delay = <200>;
 99	pinctrl-names = "default";
100	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
101	rockchip,default-sample-phase = <90>;
102	sd-uhs-sdr12;
103	sd-uhs-sdr25;
104	sd-uhs-sdr104;
105	vqmmc-supply = <&vccio_sd>;
106	status = "okay";
107};
108
109&uart2 {
110	status = "okay";
111};