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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */
7&cm_clocks {
8 clock@a00 {
9 compatible = "ti,clksel";
10 reg = <0xa00>;
11 #clock-cells = <2>;
12 #address-cells = <0>;
13
14 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {
15 #clock-cells = <0>;
16 compatible = "ti,composite-no-wait-gate-clock";
17 clock-output-names = "ssi_ssr_gate_fck_3430es2";
18 clocks = <&corex2_fck>;
19 ti,bit-shift = <0>;
20 };
21 };
22
23 clock@a40 {
24 compatible = "ti,clksel";
25 reg = <0xa40>;
26 #clock-cells = <2>;
27 #address-cells = <0>;
28
29 ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 {
30 #clock-cells = <0>;
31 compatible = "ti,composite-divider-clock";
32 clock-output-names = "ssi_ssr_div_fck_3430es2";
33 clocks = <&corex2_fck>;
34 ti,bit-shift = <8>;
35 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
36 };
37 };
38
39 ssi_ssr_fck: ssi_ssr_fck_3430es2 {
40 #clock-cells = <0>;
41 compatible = "ti,composite-clock";
42 clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
43 };
44
45 ssi_sst_fck: ssi_sst_fck_3430es2 {
46 #clock-cells = <0>;
47 compatible = "fixed-factor-clock";
48 clocks = <&ssi_ssr_fck>;
49 clock-mult = <1>;
50 clock-div = <2>;
51 };
52
53 clock@a10 {
54 compatible = "ti,clksel";
55 reg = <0xa10>;
56 #clock-cells = <2>;
57 #address-cells = <0>;
58
59 hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 {
60 #clock-cells = <0>;
61 compatible = "ti,omap3-hsotgusb-interface-clock";
62 clock-output-names = "hsotgusb_ick_3430es2";
63 clocks = <&core_l3_ick>;
64 ti,bit-shift = <4>;
65 };
66
67 ssi_ick: clock-ssi-ick-3430es2 {
68 #clock-cells = <0>;
69 compatible = "ti,omap3-ssi-interface-clock";
70 clock-output-names = "ssi_ick_3430es2";
71 clocks = <&ssi_l4_ick>;
72 ti,bit-shift = <0>;
73 };
74 };
75
76 ssi_l4_ick: ssi_l4_ick {
77 #clock-cells = <0>;
78 compatible = "fixed-factor-clock";
79 clocks = <&l4_ick>;
80 clock-mult = <1>;
81 clock-div = <1>;
82 };
83
84 clock@c00 {
85 compatible = "ti,clksel";
86 reg = <0xc00>;
87 #clock-cells = <2>;
88 #address-cells = <0>;
89
90 usim_gate_fck: clock-usim-gate-fck {
91 #clock-cells = <0>;
92 compatible = "ti,composite-gate-clock";
93 clock-output-names = "usim_gate_fck";
94 clocks = <&omap_96m_fck>;
95 ti,bit-shift = <9>;
96 };
97 };
98
99 sys_d2_ck: sys_d2_ck {
100 #clock-cells = <0>;
101 compatible = "fixed-factor-clock";
102 clocks = <&sys_ck>;
103 clock-mult = <1>;
104 clock-div = <2>;
105 };
106
107 omap_96m_d2_fck: omap_96m_d2_fck {
108 #clock-cells = <0>;
109 compatible = "fixed-factor-clock";
110 clocks = <&omap_96m_fck>;
111 clock-mult = <1>;
112 clock-div = <2>;
113 };
114
115 omap_96m_d4_fck: omap_96m_d4_fck {
116 #clock-cells = <0>;
117 compatible = "fixed-factor-clock";
118 clocks = <&omap_96m_fck>;
119 clock-mult = <1>;
120 clock-div = <4>;
121 };
122
123 omap_96m_d8_fck: omap_96m_d8_fck {
124 #clock-cells = <0>;
125 compatible = "fixed-factor-clock";
126 clocks = <&omap_96m_fck>;
127 clock-mult = <1>;
128 clock-div = <8>;
129 };
130
131 omap_96m_d10_fck: omap_96m_d10_fck {
132 #clock-cells = <0>;
133 compatible = "fixed-factor-clock";
134 clocks = <&omap_96m_fck>;
135 clock-mult = <1>;
136 clock-div = <10>;
137 };
138
139 dpll5_m2_d4_ck: dpll5_m2_d4_ck {
140 #clock-cells = <0>;
141 compatible = "fixed-factor-clock";
142 clocks = <&dpll5_m2_ck>;
143 clock-mult = <1>;
144 clock-div = <4>;
145 };
146
147 dpll5_m2_d8_ck: dpll5_m2_d8_ck {
148 #clock-cells = <0>;
149 compatible = "fixed-factor-clock";
150 clocks = <&dpll5_m2_ck>;
151 clock-mult = <1>;
152 clock-div = <8>;
153 };
154
155 dpll5_m2_d16_ck: dpll5_m2_d16_ck {
156 #clock-cells = <0>;
157 compatible = "fixed-factor-clock";
158 clocks = <&dpll5_m2_ck>;
159 clock-mult = <1>;
160 clock-div = <16>;
161 };
162
163 dpll5_m2_d20_ck: dpll5_m2_d20_ck {
164 #clock-cells = <0>;
165 compatible = "fixed-factor-clock";
166 clocks = <&dpll5_m2_ck>;
167 clock-mult = <1>;
168 clock-div = <20>;
169 };
170
171 clock@c40 {
172 compatible = "ti,clksel";
173 reg = <0xc40>;
174 #clock-cells = <2>;
175 #address-cells = <0>;
176
177 usim_mux_fck: clock-usim-mux-fck {
178 #clock-cells = <0>;
179 compatible = "ti,composite-mux-clock";
180 clock-output-names = "usim_mux_fck";
181 clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
182 ti,bit-shift = <3>;
183 ti,index-starts-at-one;
184 };
185 };
186
187 usim_fck: usim_fck {
188 #clock-cells = <0>;
189 compatible = "ti,composite-clock";
190 clocks = <&usim_gate_fck>, <&usim_mux_fck>;
191 };
192
193 clock@c10 {
194 compatible = "ti,clksel";
195 reg = <0xc10>;
196 #clock-cells = <2>;
197 #address-cells = <0>;
198
199 usim_ick: clock-usim-ick {
200 #clock-cells = <0>;
201 compatible = "ti,omap3-interface-clock";
202 clock-output-names = "usim_ick";
203 clocks = <&wkup_l4_ick>;
204 ti,bit-shift = <9>;
205 };
206 };
207};
208
209&cm_clockdomains {
210 core_l3_clkdm: core_l3_clkdm {
211 compatible = "ti,clockdomain";
212 clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
213 };
214
215 wkup_clkdm: wkup_clkdm {
216 compatible = "ti,clockdomain";
217 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
218 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
219 <&gpt1_ick>, <&usim_ick>;
220 };
221
222 core_l4_clkdm: core_l4_clkdm {
223 compatible = "ti,clockdomain";
224 clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
225 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
226 <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
227 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
228 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
229 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
230 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
231 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
232 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
233 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
234 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
235 <&ssi_ick>;
236 };
237};