1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Device Tree Source for OMAP34xx/OMAP35xx SoC
  4 *
  5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  6 */
  7
  8#include <dt-bindings/bus/ti-sysc.h>
  9#include <dt-bindings/media/omap3-isp.h>
 10
 11#include "omap3.dtsi"
 12
 13/ {
 14	cpus {
 15		cpu: cpu@0 {
 16			/* OMAP343x/OMAP35xx variants OPP1-6 */
 17			operating-points-v2 = <&cpu0_opp_table>;
 18
 19			clock-latency = <300000>; /* From legacy driver */
 20			#cooling-cells = <2>;
 21		};
 22	};
 23
 24	cpu0_opp_table: opp-table {
 25		compatible = "operating-points-v2-ti-cpu";
 26		syscon = <&scm_conf>;
 27
 28		opp1-125000000 {
 29			opp-hz = /bits/ 64 <125000000>;
 30			/*
 31			 * we currently only select the max voltage from table
 32			 * Table 3-3 of the omap3530 Data sheet (SPRS507F).
 33			 * Format is: <target min max>
 34			 */
 35			opp-microvolt = <975000 975000 975000>;
 36			/*
 37			 * first value is silicon revision bit mask
 38			 * second one 720MHz Device Identification bit mask
 39			 */
 40			opp-supported-hw = <0xffffffff 3>;
 41		};
 42
 43		opp2-250000000 {
 44			opp-hz = /bits/ 64 <250000000>;
 45			opp-microvolt = <1075000 1075000 1075000>;
 46			opp-supported-hw = <0xffffffff 3>;
 47			opp-suspend;
 48		};
 49
 50		opp3-500000000 {
 51			opp-hz = /bits/ 64 <500000000>;
 52			opp-microvolt = <1200000 1200000 1200000>;
 53			opp-supported-hw = <0xffffffff 3>;
 54		};
 55
 56		opp4-550000000 {
 57			opp-hz = /bits/ 64 <550000000>;
 58			opp-microvolt = <1275000 1275000 1275000>;
 59			opp-supported-hw = <0xffffffff 3>;
 60		};
 61
 62		opp5-600000000 {
 63			opp-hz = /bits/ 64 <600000000>;
 64			opp-microvolt = <1350000 1350000 1350000>;
 65			opp-supported-hw = <0xffffffff 3>;
 66		};
 67
 68		opp6-720000000 {
 69			opp-hz = /bits/ 64 <720000000>;
 70			opp-microvolt = <1350000 1350000 1350000>;
 71			/* only high-speed grade omap3530 devices */
 72			opp-supported-hw = <0xffffffff 2>;
 73			turbo-mode;
 74		};
 75	};
 76
 77	ocp@68000000 {
 78		omap3_pmx_core2: pinmux@480025d8 {
 79			compatible = "ti,omap3-padconf", "pinctrl-single";
 80			reg = <0x480025d8 0x24>;
 81			#address-cells = <1>;
 82			#size-cells = <0>;
 83			#pinctrl-cells = <1>;
 84			#interrupt-cells = <1>;
 85			interrupt-controller;
 86			pinctrl-single,register-width = <16>;
 87			pinctrl-single,function-mask = <0xff1f>;
 88		};
 89
 90		isp: isp@480bc000 {
 91			compatible = "ti,omap3-isp";
 92			reg = <0x480bc000 0x12fc
 93			       0x480bd800 0x017c>;
 94			interrupts = <24>;
 95			iommus = <&mmu_isp>;
 96			syscon = <&scm_conf 0x6c>;
 97			ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
 98			#clock-cells = <1>;
 99			ports {
100				#address-cells = <1>;
101				#size-cells = <0>;
102			};
103		};
104
105		bandgap: bandgap@48002524 {
106			reg = <0x48002524 0x4>;
107			compatible = "ti,omap34xx-bandgap";
108			#thermal-sensor-cells = <0>;
109		};
110
111		target-module@480cb000 {
112			compatible = "ti,sysc-omap3430-sr", "ti,sysc";
113			ti,hwmods = "smartreflex_core";
114			reg = <0x480cb024 0x4>;
115			reg-names = "sysc";
116			ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
117			clocks = <&sr2_fck>;
118			clock-names = "fck";
119			#address-cells = <1>;
120			#size-cells = <1>;
121			ranges = <0 0x480cb000 0x001000>;
122
123			smartreflex_core: smartreflex@0 {
124				compatible = "ti,omap3-smartreflex-core";
125				reg = <0 0x400>;
126				interrupts = <19>;
127			};
128		};
129
130		target-module@480c9000 {
131			compatible = "ti,sysc-omap3430-sr", "ti,sysc";
132			ti,hwmods = "smartreflex_mpu_iva";
133			reg = <0x480c9024 0x4>;
134			reg-names = "sysc";
135			ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
136			clocks = <&sr1_fck>;
137			clock-names = "fck";
138			#address-cells = <1>;
139			#size-cells = <1>;
140			ranges = <0 0x480c9000 0x001000>;
141
142			smartreflex_mpu_iva: smartreflex@480c9000 {
143				compatible = "ti,omap3-smartreflex-mpu-iva";
144				reg = <0 0x400>;
145				interrupts = <18>;
146			};
147		};
148
149		/*
150		 * On omap34xx the OCP registers do not seem to be accessible
151		 * at all unlike on 36xx. Maybe SGX is permanently set to
152		 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
153		 * write-only at 0x50000e10. We detect SGX based on the SGX
154		 * revision register instead of the unreadable OCP revision
155		 * register. Also note that on early 34xx es1 revision there
156		 * are also different clocks, but we do not have any dts users
157		 * for it.
158		 */
159		sgx_module: target-module@50000000 {
160			compatible = "ti,sysc-omap2", "ti,sysc";
161			reg = <0x50000014 0x4>;
162			reg-names = "rev";
163			clocks = <&sgx_fck>, <&sgx_ick>;
164			clock-names = "fck", "ick";
165			#address-cells = <1>;
166			#size-cells = <1>;
167			ranges = <0 0x50000000 0x4000>;
168
169			/*
170			 * Closed source PowerVR driver, no child device
171			 * binding or driver in mainline
172			 */
173		};
174	};
175
176	thermal_zones: thermal-zones {
177		#include "omap3-cpu-thermal.dtsi"
178	};
179};
180
181&ssi {
182	status = "okay";
183
184	clocks = <&ssi_ssr_fck>,
185		 <&ssi_sst_fck>,
186		 <&ssi_ick>;
187	clock-names = "ssi_ssr_fck",
188		      "ssi_sst_fck",
189		      "ssi_ick";
190};
191
192&usb_otg_target {
193	clocks = <&hsotgusb_ick_3430es2>;
194};
195
196/include/ "omap34xx-omap36xx-clocks.dtsi"
197/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
198/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"