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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for the PCM512x CODECs
4 *
5 * Author: Mark Brown <broonie@kernel.org>
6 * Copyright 2014 Linaro Ltd
7 */
8
9
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/clk.h>
13#include <linux/kernel.h>
14#include <linux/pm_runtime.h>
15#include <linux/regmap.h>
16#include <linux/regulator/consumer.h>
17#include <linux/gcd.h>
18#include <sound/soc.h>
19#include <sound/soc-dapm.h>
20#include <sound/pcm_params.h>
21#include <sound/tlv.h>
22
23#include "pcm512x.h"
24
25#define PCM512x_NUM_SUPPLIES 3
26static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = {
27 "AVDD",
28 "DVDD",
29 "CPVDD",
30};
31
32struct pcm512x_priv {
33 struct regmap *regmap;
34 struct clk *sclk;
35 struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES];
36 struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES];
37 int fmt;
38 int pll_in;
39 int pll_out;
40 int pll_r;
41 int pll_j;
42 int pll_d;
43 int pll_p;
44 unsigned long real_pll;
45 unsigned long overclock_pll;
46 unsigned long overclock_dac;
47 unsigned long overclock_dsp;
48 int mute;
49 struct mutex mutex;
50 unsigned int bclk_ratio;
51 int force_pll_on;
52};
53
54/*
55 * We can't use the same notifier block for more than one supply and
56 * there's no way I can see to get from a callback to the caller
57 * except container_of().
58 */
59#define PCM512x_REGULATOR_EVENT(n) \
60static int pcm512x_regulator_event_##n(struct notifier_block *nb, \
61 unsigned long event, void *data) \
62{ \
63 struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \
64 supply_nb[n]); \
65 if (event & REGULATOR_EVENT_DISABLE) { \
66 regcache_mark_dirty(pcm512x->regmap); \
67 regcache_cache_only(pcm512x->regmap, true); \
68 } \
69 return 0; \
70}
71
72PCM512x_REGULATOR_EVENT(0)
73PCM512x_REGULATOR_EVENT(1)
74PCM512x_REGULATOR_EVENT(2)
75
76static const struct reg_default pcm512x_reg_defaults[] = {
77 { PCM512x_RESET, 0x00 },
78 { PCM512x_POWER, 0x00 },
79 { PCM512x_MUTE, 0x00 },
80 { PCM512x_DSP, 0x00 },
81 { PCM512x_PLL_REF, 0x00 },
82 { PCM512x_DAC_REF, 0x00 },
83 { PCM512x_DAC_ROUTING, 0x11 },
84 { PCM512x_DSP_PROGRAM, 0x01 },
85 { PCM512x_CLKDET, 0x00 },
86 { PCM512x_AUTO_MUTE, 0x00 },
87 { PCM512x_ERROR_DETECT, 0x00 },
88 { PCM512x_DIGITAL_VOLUME_1, 0x00 },
89 { PCM512x_DIGITAL_VOLUME_2, 0x30 },
90 { PCM512x_DIGITAL_VOLUME_3, 0x30 },
91 { PCM512x_DIGITAL_MUTE_1, 0x22 },
92 { PCM512x_DIGITAL_MUTE_2, 0x00 },
93 { PCM512x_DIGITAL_MUTE_3, 0x07 },
94 { PCM512x_OUTPUT_AMPLITUDE, 0x00 },
95 { PCM512x_ANALOG_GAIN_CTRL, 0x00 },
96 { PCM512x_UNDERVOLTAGE_PROT, 0x00 },
97 { PCM512x_ANALOG_MUTE_CTRL, 0x00 },
98 { PCM512x_ANALOG_GAIN_BOOST, 0x00 },
99 { PCM512x_VCOM_CTRL_1, 0x00 },
100 { PCM512x_VCOM_CTRL_2, 0x01 },
101 { PCM512x_BCLK_LRCLK_CFG, 0x00 },
102 { PCM512x_MASTER_MODE, 0x7c },
103 { PCM512x_GPIO_DACIN, 0x00 },
104 { PCM512x_GPIO_PLLIN, 0x00 },
105 { PCM512x_SYNCHRONIZE, 0x10 },
106 { PCM512x_PLL_COEFF_0, 0x00 },
107 { PCM512x_PLL_COEFF_1, 0x00 },
108 { PCM512x_PLL_COEFF_2, 0x00 },
109 { PCM512x_PLL_COEFF_3, 0x00 },
110 { PCM512x_PLL_COEFF_4, 0x00 },
111 { PCM512x_DSP_CLKDIV, 0x00 },
112 { PCM512x_DAC_CLKDIV, 0x00 },
113 { PCM512x_NCP_CLKDIV, 0x00 },
114 { PCM512x_OSR_CLKDIV, 0x00 },
115 { PCM512x_MASTER_CLKDIV_1, 0x00 },
116 { PCM512x_MASTER_CLKDIV_2, 0x00 },
117 { PCM512x_FS_SPEED_MODE, 0x00 },
118 { PCM512x_IDAC_1, 0x01 },
119 { PCM512x_IDAC_2, 0x00 },
120 { PCM512x_I2S_1, 0x02 },
121 { PCM512x_I2S_2, 0x00 },
122};
123
124static bool pcm512x_readable(struct device *dev, unsigned int reg)
125{
126 switch (reg) {
127 case PCM512x_RESET:
128 case PCM512x_POWER:
129 case PCM512x_MUTE:
130 case PCM512x_PLL_EN:
131 case PCM512x_SPI_MISO_FUNCTION:
132 case PCM512x_DSP:
133 case PCM512x_GPIO_EN:
134 case PCM512x_BCLK_LRCLK_CFG:
135 case PCM512x_DSP_GPIO_INPUT:
136 case PCM512x_MASTER_MODE:
137 case PCM512x_PLL_REF:
138 case PCM512x_DAC_REF:
139 case PCM512x_GPIO_DACIN:
140 case PCM512x_GPIO_PLLIN:
141 case PCM512x_SYNCHRONIZE:
142 case PCM512x_PLL_COEFF_0:
143 case PCM512x_PLL_COEFF_1:
144 case PCM512x_PLL_COEFF_2:
145 case PCM512x_PLL_COEFF_3:
146 case PCM512x_PLL_COEFF_4:
147 case PCM512x_DSP_CLKDIV:
148 case PCM512x_DAC_CLKDIV:
149 case PCM512x_NCP_CLKDIV:
150 case PCM512x_OSR_CLKDIV:
151 case PCM512x_MASTER_CLKDIV_1:
152 case PCM512x_MASTER_CLKDIV_2:
153 case PCM512x_FS_SPEED_MODE:
154 case PCM512x_IDAC_1:
155 case PCM512x_IDAC_2:
156 case PCM512x_ERROR_DETECT:
157 case PCM512x_I2S_1:
158 case PCM512x_I2S_2:
159 case PCM512x_DAC_ROUTING:
160 case PCM512x_DSP_PROGRAM:
161 case PCM512x_CLKDET:
162 case PCM512x_AUTO_MUTE:
163 case PCM512x_DIGITAL_VOLUME_1:
164 case PCM512x_DIGITAL_VOLUME_2:
165 case PCM512x_DIGITAL_VOLUME_3:
166 case PCM512x_DIGITAL_MUTE_1:
167 case PCM512x_DIGITAL_MUTE_2:
168 case PCM512x_DIGITAL_MUTE_3:
169 case PCM512x_GPIO_OUTPUT_1:
170 case PCM512x_GPIO_OUTPUT_2:
171 case PCM512x_GPIO_OUTPUT_3:
172 case PCM512x_GPIO_OUTPUT_4:
173 case PCM512x_GPIO_OUTPUT_5:
174 case PCM512x_GPIO_OUTPUT_6:
175 case PCM512x_GPIO_CONTROL_1:
176 case PCM512x_GPIO_CONTROL_2:
177 case PCM512x_OVERFLOW:
178 case PCM512x_RATE_DET_1:
179 case PCM512x_RATE_DET_2:
180 case PCM512x_RATE_DET_3:
181 case PCM512x_RATE_DET_4:
182 case PCM512x_CLOCK_STATUS:
183 case PCM512x_ANALOG_MUTE_DET:
184 case PCM512x_GPIN:
185 case PCM512x_DIGITAL_MUTE_DET:
186 case PCM512x_OUTPUT_AMPLITUDE:
187 case PCM512x_ANALOG_GAIN_CTRL:
188 case PCM512x_UNDERVOLTAGE_PROT:
189 case PCM512x_ANALOG_MUTE_CTRL:
190 case PCM512x_ANALOG_GAIN_BOOST:
191 case PCM512x_VCOM_CTRL_1:
192 case PCM512x_VCOM_CTRL_2:
193 case PCM512x_CRAM_CTRL:
194 case PCM512x_FLEX_A:
195 case PCM512x_FLEX_B:
196 return true;
197 default:
198 /* There are 256 raw register addresses */
199 return reg < 0xff;
200 }
201}
202
203static bool pcm512x_volatile(struct device *dev, unsigned int reg)
204{
205 switch (reg) {
206 case PCM512x_PLL_EN:
207 case PCM512x_OVERFLOW:
208 case PCM512x_RATE_DET_1:
209 case PCM512x_RATE_DET_2:
210 case PCM512x_RATE_DET_3:
211 case PCM512x_RATE_DET_4:
212 case PCM512x_CLOCK_STATUS:
213 case PCM512x_ANALOG_MUTE_DET:
214 case PCM512x_GPIN:
215 case PCM512x_DIGITAL_MUTE_DET:
216 case PCM512x_CRAM_CTRL:
217 return true;
218 default:
219 /* There are 256 raw register addresses */
220 return reg < 0xff;
221 }
222}
223
224static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol,
225 struct snd_ctl_elem_value *ucontrol)
226{
227 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
228 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
229
230 ucontrol->value.integer.value[0] = pcm512x->overclock_pll;
231 return 0;
232}
233
234static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol,
235 struct snd_ctl_elem_value *ucontrol)
236{
237 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
238 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
239
240 switch (snd_soc_component_get_bias_level(component)) {
241 case SND_SOC_BIAS_OFF:
242 case SND_SOC_BIAS_STANDBY:
243 break;
244 default:
245 return -EBUSY;
246 }
247
248 pcm512x->overclock_pll = ucontrol->value.integer.value[0];
249 return 0;
250}
251
252static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol,
253 struct snd_ctl_elem_value *ucontrol)
254{
255 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
256 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
257
258 ucontrol->value.integer.value[0] = pcm512x->overclock_dsp;
259 return 0;
260}
261
262static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol,
263 struct snd_ctl_elem_value *ucontrol)
264{
265 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
266 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
267
268 switch (snd_soc_component_get_bias_level(component)) {
269 case SND_SOC_BIAS_OFF:
270 case SND_SOC_BIAS_STANDBY:
271 break;
272 default:
273 return -EBUSY;
274 }
275
276 pcm512x->overclock_dsp = ucontrol->value.integer.value[0];
277 return 0;
278}
279
280static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol,
281 struct snd_ctl_elem_value *ucontrol)
282{
283 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
284 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
285
286 ucontrol->value.integer.value[0] = pcm512x->overclock_dac;
287 return 0;
288}
289
290static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol,
291 struct snd_ctl_elem_value *ucontrol)
292{
293 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
294 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
295
296 switch (snd_soc_component_get_bias_level(component)) {
297 case SND_SOC_BIAS_OFF:
298 case SND_SOC_BIAS_STANDBY:
299 break;
300 default:
301 return -EBUSY;
302 }
303
304 pcm512x->overclock_dac = ucontrol->value.integer.value[0];
305 return 0;
306}
307
308static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1);
309static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0);
310static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0);
311
312static const char * const pcm512x_dsp_program_texts[] = {
313 "FIR interpolation with de-emphasis",
314 "Low latency IIR with de-emphasis",
315 "High attenuation with de-emphasis",
316 "Fixed process flow",
317 "Ringing-less low latency FIR",
318};
319
320static const unsigned int pcm512x_dsp_program_values[] = {
321 1,
322 2,
323 3,
324 5,
325 7,
326};
327
328static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program,
329 PCM512x_DSP_PROGRAM, 0, 0x1f,
330 pcm512x_dsp_program_texts,
331 pcm512x_dsp_program_values);
332
333static const char * const pcm512x_clk_missing_text[] = {
334 "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s"
335};
336
337static const struct soc_enum pcm512x_clk_missing =
338 SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text);
339
340static const char * const pcm512x_autom_text[] = {
341 "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s"
342};
343
344static const struct soc_enum pcm512x_autom_l =
345 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8,
346 pcm512x_autom_text);
347
348static const struct soc_enum pcm512x_autom_r =
349 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8,
350 pcm512x_autom_text);
351
352static const char * const pcm512x_ramp_rate_text[] = {
353 "1 sample/update", "2 samples/update", "4 samples/update",
354 "Immediate"
355};
356
357static const struct soc_enum pcm512x_vndf =
358 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4,
359 pcm512x_ramp_rate_text);
360
361static const struct soc_enum pcm512x_vnuf =
362 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4,
363 pcm512x_ramp_rate_text);
364
365static const struct soc_enum pcm512x_vedf =
366 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4,
367 pcm512x_ramp_rate_text);
368
369static const char * const pcm512x_ramp_step_text[] = {
370 "4dB/step", "2dB/step", "1dB/step", "0.5dB/step"
371};
372
373static const struct soc_enum pcm512x_vnds =
374 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4,
375 pcm512x_ramp_step_text);
376
377static const struct soc_enum pcm512x_vnus =
378 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4,
379 pcm512x_ramp_step_text);
380
381static const struct soc_enum pcm512x_veds =
382 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4,
383 pcm512x_ramp_step_text);
384
385static int pcm512x_update_mute(struct pcm512x_priv *pcm512x)
386{
387 return regmap_update_bits(
388 pcm512x->regmap, PCM512x_MUTE, PCM512x_RQML | PCM512x_RQMR,
389 (!!(pcm512x->mute & 0x5) << PCM512x_RQML_SHIFT)
390 | (!!(pcm512x->mute & 0x3) << PCM512x_RQMR_SHIFT));
391}
392
393static int pcm512x_digital_playback_switch_get(struct snd_kcontrol *kcontrol,
394 struct snd_ctl_elem_value *ucontrol)
395{
396 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
397 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
398
399 mutex_lock(&pcm512x->mutex);
400 ucontrol->value.integer.value[0] = !(pcm512x->mute & 0x4);
401 ucontrol->value.integer.value[1] = !(pcm512x->mute & 0x2);
402 mutex_unlock(&pcm512x->mutex);
403
404 return 0;
405}
406
407static int pcm512x_digital_playback_switch_put(struct snd_kcontrol *kcontrol,
408 struct snd_ctl_elem_value *ucontrol)
409{
410 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
411 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
412 int ret, changed = 0;
413
414 mutex_lock(&pcm512x->mutex);
415
416 if ((pcm512x->mute & 0x4) == (ucontrol->value.integer.value[0] << 2)) {
417 pcm512x->mute ^= 0x4;
418 changed = 1;
419 }
420 if ((pcm512x->mute & 0x2) == (ucontrol->value.integer.value[1] << 1)) {
421 pcm512x->mute ^= 0x2;
422 changed = 1;
423 }
424
425 if (changed) {
426 ret = pcm512x_update_mute(pcm512x);
427 if (ret != 0) {
428 dev_err(component->dev,
429 "Failed to update digital mute: %d\n", ret);
430 mutex_unlock(&pcm512x->mutex);
431 return ret;
432 }
433 }
434
435 mutex_unlock(&pcm512x->mutex);
436
437 return changed;
438}
439
440static const struct snd_kcontrol_new pcm512x_controls[] = {
441SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2,
442 PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv),
443SOC_DOUBLE_TLV("Analogue Playback Volume", PCM512x_ANALOG_GAIN_CTRL,
444 PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv),
445SOC_DOUBLE_TLV("Analogue Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST,
446 PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv),
447{
448 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
449 .name = "Digital Playback Switch",
450 .index = 0,
451 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
452 .info = snd_ctl_boolean_stereo_info,
453 .get = pcm512x_digital_playback_switch_get,
454 .put = pcm512x_digital_playback_switch_put
455},
456
457SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1),
458SOC_ENUM("DSP Program", pcm512x_dsp_program),
459
460SOC_ENUM("Clock Missing Period", pcm512x_clk_missing),
461SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l),
462SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r),
463SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3,
464 PCM512x_ACTL_SHIFT, 1, 0),
465SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT,
466 PCM512x_AMRE_SHIFT, 1, 0),
467
468SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf),
469SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds),
470SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf),
471SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus),
472SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf),
473SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds),
474
475SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0,
476 pcm512x_overclock_pll_get, pcm512x_overclock_pll_put),
477SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0,
478 pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put),
479SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0,
480 pcm512x_overclock_dac_get, pcm512x_overclock_dac_put),
481};
482
483static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = {
484SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
485SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
486
487SND_SOC_DAPM_OUTPUT("OUTL"),
488SND_SOC_DAPM_OUTPUT("OUTR"),
489};
490
491static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = {
492 { "DACL", NULL, "Playback" },
493 { "DACR", NULL, "Playback" },
494
495 { "OUTL", NULL, "DACL" },
496 { "OUTR", NULL, "DACR" },
497};
498
499static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x)
500{
501 return 25000000 + 25000000 * pcm512x->overclock_pll / 100;
502}
503
504static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x)
505{
506 return 50000000 + 50000000 * pcm512x->overclock_dsp / 100;
507}
508
509static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x,
510 unsigned long rate)
511{
512 return rate + rate * pcm512x->overclock_dac / 100;
513}
514
515static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x)
516{
517 if (!pcm512x->pll_out)
518 return 25000000;
519 return pcm512x_pll_max(pcm512x);
520}
521
522static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x,
523 unsigned long dac_rate)
524{
525 /*
526 * If the DAC is not actually overclocked, use the good old
527 * NCP target rate...
528 */
529 if (dac_rate <= 6144000)
530 return 1536000;
531 /*
532 * ...but if the DAC is in fact overclocked, bump the NCP target
533 * rate to get the recommended dividers even when overclocking.
534 */
535 return pcm512x_dac_max(pcm512x, 1536000);
536}
537
538static const u32 pcm512x_dai_rates[] = {
539 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
540 88200, 96000, 176400, 192000, 384000,
541};
542
543static const struct snd_pcm_hw_constraint_list constraints_slave = {
544 .count = ARRAY_SIZE(pcm512x_dai_rates),
545 .list = pcm512x_dai_rates,
546};
547
548static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params,
549 struct snd_pcm_hw_rule *rule)
550{
551 struct pcm512x_priv *pcm512x = rule->private;
552 struct snd_interval ranges[2];
553 int frame_size;
554
555 frame_size = snd_soc_params_to_frame_size(params);
556 if (frame_size < 0)
557 return frame_size;
558
559 switch (frame_size) {
560 case 32:
561 /* No hole when the frame size is 32. */
562 return 0;
563 case 48:
564 case 64:
565 /* There is only one hole in the range of supported
566 * rates, but it moves with the frame size.
567 */
568 memset(ranges, 0, sizeof(ranges));
569 ranges[0].min = 8000;
570 ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2;
571 ranges[1].min = DIV_ROUND_UP(16000000, frame_size);
572 ranges[1].max = 384000;
573 break;
574 default:
575 return -EINVAL;
576 }
577
578 return snd_interval_ranges(hw_param_interval(params, rule->var),
579 ARRAY_SIZE(ranges), ranges, 0);
580}
581
582static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream,
583 struct snd_soc_dai *dai)
584{
585 struct snd_soc_component *component = dai->component;
586 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
587 struct device *dev = dai->dev;
588 struct snd_pcm_hw_constraint_ratnums *constraints_no_pll;
589 struct snd_ratnum *rats_no_pll;
590
591 if (IS_ERR(pcm512x->sclk)) {
592 dev_err(dev, "Need SCLK for master mode: %ld\n",
593 PTR_ERR(pcm512x->sclk));
594 return PTR_ERR(pcm512x->sclk);
595 }
596
597 if (pcm512x->pll_out)
598 return snd_pcm_hw_rule_add(substream->runtime, 0,
599 SNDRV_PCM_HW_PARAM_RATE,
600 pcm512x_hw_rule_rate,
601 pcm512x,
602 SNDRV_PCM_HW_PARAM_FRAME_BITS,
603 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
604
605 constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll),
606 GFP_KERNEL);
607 if (!constraints_no_pll)
608 return -ENOMEM;
609 constraints_no_pll->nrats = 1;
610 rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL);
611 if (!rats_no_pll)
612 return -ENOMEM;
613 constraints_no_pll->rats = rats_no_pll;
614 rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;
615 rats_no_pll->den_min = 1;
616 rats_no_pll->den_max = 128;
617 rats_no_pll->den_step = 1;
618
619 return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
620 SNDRV_PCM_HW_PARAM_RATE,
621 constraints_no_pll);
622}
623
624static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream,
625 struct snd_soc_dai *dai)
626{
627 struct snd_soc_component *component = dai->component;
628 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
629 struct device *dev = dai->dev;
630 struct regmap *regmap = pcm512x->regmap;
631
632 if (IS_ERR(pcm512x->sclk)) {
633 dev_info(dev, "No SCLK, using BCLK: %ld\n",
634 PTR_ERR(pcm512x->sclk));
635
636 /* Disable reporting of missing SCLK as an error */
637 regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
638 PCM512x_IDCH, PCM512x_IDCH);
639
640 /* Switch PLL input to BCLK */
641 regmap_update_bits(regmap, PCM512x_PLL_REF,
642 PCM512x_SREF, PCM512x_SREF_BCK);
643 }
644
645 return snd_pcm_hw_constraint_list(substream->runtime, 0,
646 SNDRV_PCM_HW_PARAM_RATE,
647 &constraints_slave);
648}
649
650static int pcm512x_dai_startup(struct snd_pcm_substream *substream,
651 struct snd_soc_dai *dai)
652{
653 struct snd_soc_component *component = dai->component;
654 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
655
656 switch (pcm512x->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
657 case SND_SOC_DAIFMT_CBP_CFP:
658 case SND_SOC_DAIFMT_CBP_CFC:
659 return pcm512x_dai_startup_master(substream, dai);
660
661 case SND_SOC_DAIFMT_CBC_CFC:
662 return pcm512x_dai_startup_slave(substream, dai);
663
664 default:
665 return -EINVAL;
666 }
667}
668
669static int pcm512x_set_bias_level(struct snd_soc_component *component,
670 enum snd_soc_bias_level level)
671{
672 struct pcm512x_priv *pcm512x = dev_get_drvdata(component->dev);
673 int ret;
674
675 switch (level) {
676 case SND_SOC_BIAS_ON:
677 case SND_SOC_BIAS_PREPARE:
678 break;
679
680 case SND_SOC_BIAS_STANDBY:
681 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
682 PCM512x_RQST, 0);
683 if (ret != 0) {
684 dev_err(component->dev, "Failed to remove standby: %d\n",
685 ret);
686 return ret;
687 }
688 break;
689
690 case SND_SOC_BIAS_OFF:
691 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
692 PCM512x_RQST, PCM512x_RQST);
693 if (ret != 0) {
694 dev_err(component->dev, "Failed to request standby: %d\n",
695 ret);
696 return ret;
697 }
698 break;
699 }
700
701 return 0;
702}
703
704static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai,
705 unsigned long bclk_rate)
706{
707 struct device *dev = dai->dev;
708 struct snd_soc_component *component = dai->component;
709 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
710 unsigned long sck_rate;
711 int pow2;
712
713 /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */
714 /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */
715
716 /* select sck_rate as a multiple of bclk_rate but still with
717 * as many factors of 2 as possible, as that makes it easier
718 * to find a fast DAC rate
719 */
720 pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate);
721 for (; pow2; pow2 >>= 1) {
722 sck_rate = rounddown(pcm512x_pll_max(pcm512x),
723 bclk_rate * pow2);
724 if (sck_rate >= 16000000)
725 break;
726 }
727 if (!pow2) {
728 dev_err(dev, "Impossible to generate a suitable SCK\n");
729 return 0;
730 }
731
732 dev_dbg(dev, "sck_rate %lu\n", sck_rate);
733 return sck_rate;
734}
735
736/* pll_rate = pllin_rate * R * J.D / P
737 * 1 <= R <= 16
738 * 1 <= J <= 63
739 * 0 <= D <= 9999
740 * 1 <= P <= 15
741 * 64 MHz <= pll_rate <= 100 MHz
742 * if D == 0
743 * 1 MHz <= pllin_rate / P <= 20 MHz
744 * else if D > 0
745 * 6.667 MHz <= pllin_rate / P <= 20 MHz
746 * 4 <= J <= 11
747 * R = 1
748 */
749static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai,
750 unsigned long pllin_rate,
751 unsigned long pll_rate)
752{
753 struct device *dev = dai->dev;
754 struct snd_soc_component *component = dai->component;
755 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
756 unsigned long common;
757 int R, J, D, P;
758 unsigned long K; /* 10000 * J.D */
759 unsigned long num;
760 unsigned long den;
761
762 common = gcd(pll_rate, pllin_rate);
763 dev_dbg(dev, "pll %lu pllin %lu common %lu\n",
764 pll_rate, pllin_rate, common);
765 num = pll_rate / common;
766 den = pllin_rate / common;
767
768 /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */
769 if (pllin_rate / den > 20000000 && num < 8) {
770 num *= DIV_ROUND_UP(pllin_rate / den, 20000000);
771 den *= DIV_ROUND_UP(pllin_rate / den, 20000000);
772 }
773 dev_dbg(dev, "num / den = %lu / %lu\n", num, den);
774
775 P = den;
776 if (den <= 15 && num <= 16 * 63
777 && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) {
778 /* Try the case with D = 0 */
779 D = 0;
780 /* factor 'num' into J and R, such that R <= 16 and J <= 63 */
781 for (R = 16; R; R--) {
782 if (num % R)
783 continue;
784 J = num / R;
785 if (J == 0 || J > 63)
786 continue;
787
788 dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P);
789 pcm512x->real_pll = pll_rate;
790 goto done;
791 }
792 /* no luck */
793 }
794
795 R = 1;
796
797 if (num > 0xffffffffUL / 10000)
798 goto fallback;
799
800 /* Try to find an exact pll_rate using the D > 0 case */
801 common = gcd(10000 * num, den);
802 num = 10000 * num / common;
803 den /= common;
804 dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common);
805
806 for (P = den; P <= 15; P++) {
807 if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P)
808 continue;
809 if (num * P % den)
810 continue;
811 K = num * P / den;
812 /* J == 12 is ok if D == 0 */
813 if (K < 40000 || K > 120000)
814 continue;
815
816 J = K / 10000;
817 D = K % 10000;
818 dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P);
819 pcm512x->real_pll = pll_rate;
820 goto done;
821 }
822
823 /* Fall back to an approximate pll_rate */
824
825fallback:
826 /* find smallest possible P */
827 P = DIV_ROUND_UP(pllin_rate, 20000000);
828 if (!P)
829 P = 1;
830 else if (P > 15) {
831 dev_err(dev, "Need a slower clock as pll-input\n");
832 return -EINVAL;
833 }
834 if (pllin_rate / P < 6667000) {
835 dev_err(dev, "Need a faster clock as pll-input\n");
836 return -EINVAL;
837 }
838 K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate);
839 if (K < 40000)
840 K = 40000;
841 /* J == 12 is ok if D == 0 */
842 if (K > 120000)
843 K = 120000;
844 J = K / 10000;
845 D = K % 10000;
846 dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P);
847 pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P);
848
849done:
850 pcm512x->pll_r = R;
851 pcm512x->pll_j = J;
852 pcm512x->pll_d = D;
853 pcm512x->pll_p = P;
854 return 0;
855}
856
857static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai,
858 unsigned long osr_rate,
859 unsigned long pllin_rate)
860{
861 struct snd_soc_component *component = dai->component;
862 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
863 unsigned long dac_rate;
864
865 if (!pcm512x->pll_out)
866 return 0; /* no PLL to bypass, force SCK as DAC input */
867
868 if (pllin_rate % osr_rate)
869 return 0; /* futile, quit early */
870
871 /* run DAC no faster than 6144000 Hz */
872 for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate);
873 dac_rate;
874 dac_rate -= osr_rate) {
875
876 if (pllin_rate / dac_rate > 128)
877 return 0; /* DAC divider would be too big */
878
879 if (!(pllin_rate % dac_rate))
880 return dac_rate;
881
882 dac_rate -= osr_rate;
883 }
884
885 return 0;
886}
887
888static int pcm512x_set_dividers(struct snd_soc_dai *dai,
889 struct snd_pcm_hw_params *params)
890{
891 struct device *dev = dai->dev;
892 struct snd_soc_component *component = dai->component;
893 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
894 unsigned long pllin_rate = 0;
895 unsigned long pll_rate;
896 unsigned long sck_rate;
897 unsigned long mck_rate;
898 unsigned long bclk_rate;
899 unsigned long sample_rate;
900 unsigned long osr_rate;
901 unsigned long dacsrc_rate;
902 int bclk_div;
903 int lrclk_div;
904 int dsp_div;
905 int dac_div;
906 unsigned long dac_rate;
907 int ncp_div;
908 int osr_div;
909 int ret;
910 int idac;
911 int fssp;
912 int gpio;
913
914 if (pcm512x->bclk_ratio > 0) {
915 lrclk_div = pcm512x->bclk_ratio;
916 } else {
917 lrclk_div = snd_soc_params_to_frame_size(params);
918
919 if (lrclk_div == 0) {
920 dev_err(dev, "No LRCLK?\n");
921 return -EINVAL;
922 }
923 }
924
925 if (!pcm512x->pll_out) {
926 sck_rate = clk_get_rate(pcm512x->sclk);
927 bclk_rate = params_rate(params) * lrclk_div;
928 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
929
930 mck_rate = sck_rate;
931 } else {
932 ret = snd_soc_params_to_bclk(params);
933 if (ret < 0) {
934 dev_err(dev, "Failed to find suitable BCLK: %d\n", ret);
935 return ret;
936 }
937 if (ret == 0) {
938 dev_err(dev, "No BCLK?\n");
939 return -EINVAL;
940 }
941 bclk_rate = ret;
942
943 pllin_rate = clk_get_rate(pcm512x->sclk);
944
945 sck_rate = pcm512x_find_sck(dai, bclk_rate);
946 if (!sck_rate)
947 return -EINVAL;
948 pll_rate = 4 * sck_rate;
949
950 ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate);
951 if (ret != 0)
952 return ret;
953
954 ret = regmap_write(pcm512x->regmap,
955 PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1);
956 if (ret != 0) {
957 dev_err(dev, "Failed to write PLL P: %d\n", ret);
958 return ret;
959 }
960
961 ret = regmap_write(pcm512x->regmap,
962 PCM512x_PLL_COEFF_1, pcm512x->pll_j);
963 if (ret != 0) {
964 dev_err(dev, "Failed to write PLL J: %d\n", ret);
965 return ret;
966 }
967
968 ret = regmap_write(pcm512x->regmap,
969 PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8);
970 if (ret != 0) {
971 dev_err(dev, "Failed to write PLL D msb: %d\n", ret);
972 return ret;
973 }
974
975 ret = regmap_write(pcm512x->regmap,
976 PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff);
977 if (ret != 0) {
978 dev_err(dev, "Failed to write PLL D lsb: %d\n", ret);
979 return ret;
980 }
981
982 ret = regmap_write(pcm512x->regmap,
983 PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1);
984 if (ret != 0) {
985 dev_err(dev, "Failed to write PLL R: %d\n", ret);
986 return ret;
987 }
988
989 mck_rate = pcm512x->real_pll;
990
991 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
992 }
993
994 if (bclk_div > 128) {
995 dev_err(dev, "Failed to find BCLK divider\n");
996 return -EINVAL;
997 }
998
999 /* the actual rate */
1000 sample_rate = sck_rate / bclk_div / lrclk_div;
1001 osr_rate = 16 * sample_rate;
1002
1003 /* run DSP no faster than 50 MHz */
1004 dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1;
1005
1006 dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate);
1007 if (dac_rate) {
1008 /* the desired clock rate is "compatible" with the pll input
1009 * clock, so use that clock as dac input instead of the pll
1010 * output clock since the pll will introduce jitter and thus
1011 * noise.
1012 */
1013 dev_dbg(dev, "using pll input as dac input\n");
1014 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
1015 PCM512x_SDAC, PCM512x_SDAC_GPIO);
1016 if (ret != 0) {
1017 dev_err(component->dev,
1018 "Failed to set gpio as dacref: %d\n", ret);
1019 return ret;
1020 }
1021
1022 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
1023 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN,
1024 PCM512x_GREF, gpio);
1025 if (ret != 0) {
1026 dev_err(component->dev,
1027 "Failed to set gpio %d as dacin: %d\n",
1028 pcm512x->pll_in, ret);
1029 return ret;
1030 }
1031
1032 dacsrc_rate = pllin_rate;
1033 } else {
1034 /* run DAC no faster than 6144000 Hz */
1035 unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000)
1036 / osr_rate;
1037 unsigned long sck_mul = sck_rate / osr_rate;
1038
1039 for (; dac_mul; dac_mul--) {
1040 if (!(sck_mul % dac_mul))
1041 break;
1042 }
1043 if (!dac_mul) {
1044 dev_err(dev, "Failed to find DAC rate\n");
1045 return -EINVAL;
1046 }
1047
1048 dac_rate = dac_mul * osr_rate;
1049 dev_dbg(dev, "dac_rate %lu sample_rate %lu\n",
1050 dac_rate, sample_rate);
1051
1052 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
1053 PCM512x_SDAC, PCM512x_SDAC_SCK);
1054 if (ret != 0) {
1055 dev_err(component->dev,
1056 "Failed to set sck as dacref: %d\n", ret);
1057 return ret;
1058 }
1059
1060 dacsrc_rate = sck_rate;
1061 }
1062
1063 osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate);
1064 if (osr_div > 128) {
1065 dev_err(dev, "Failed to find OSR divider\n");
1066 return -EINVAL;
1067 }
1068
1069 dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate);
1070 if (dac_div > 128) {
1071 dev_err(dev, "Failed to find DAC divider\n");
1072 return -EINVAL;
1073 }
1074 dac_rate = dacsrc_rate / dac_div;
1075
1076 ncp_div = DIV_ROUND_CLOSEST(dac_rate,
1077 pcm512x_ncp_target(pcm512x, dac_rate));
1078 if (ncp_div > 128 || dac_rate / ncp_div > 2048000) {
1079 /* run NCP no faster than 2048000 Hz, but why? */
1080 ncp_div = DIV_ROUND_UP(dac_rate, 2048000);
1081 if (ncp_div > 128) {
1082 dev_err(dev, "Failed to find NCP divider\n");
1083 return -EINVAL;
1084 }
1085 }
1086
1087 idac = mck_rate / (dsp_div * sample_rate);
1088
1089 ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1);
1090 if (ret != 0) {
1091 dev_err(dev, "Failed to write DSP divider: %d\n", ret);
1092 return ret;
1093 }
1094
1095 ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1);
1096 if (ret != 0) {
1097 dev_err(dev, "Failed to write DAC divider: %d\n", ret);
1098 return ret;
1099 }
1100
1101 ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1);
1102 if (ret != 0) {
1103 dev_err(dev, "Failed to write NCP divider: %d\n", ret);
1104 return ret;
1105 }
1106
1107 ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1);
1108 if (ret != 0) {
1109 dev_err(dev, "Failed to write OSR divider: %d\n", ret);
1110 return ret;
1111 }
1112
1113 ret = regmap_write(pcm512x->regmap,
1114 PCM512x_MASTER_CLKDIV_1, bclk_div - 1);
1115 if (ret != 0) {
1116 dev_err(dev, "Failed to write BCLK divider: %d\n", ret);
1117 return ret;
1118 }
1119
1120 ret = regmap_write(pcm512x->regmap,
1121 PCM512x_MASTER_CLKDIV_2, lrclk_div - 1);
1122 if (ret != 0) {
1123 dev_err(dev, "Failed to write LRCLK divider: %d\n", ret);
1124 return ret;
1125 }
1126
1127 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8);
1128 if (ret != 0) {
1129 dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret);
1130 return ret;
1131 }
1132
1133 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff);
1134 if (ret != 0) {
1135 dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret);
1136 return ret;
1137 }
1138
1139 if (sample_rate <= pcm512x_dac_max(pcm512x, 48000))
1140 fssp = PCM512x_FSSP_48KHZ;
1141 else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000))
1142 fssp = PCM512x_FSSP_96KHZ;
1143 else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000))
1144 fssp = PCM512x_FSSP_192KHZ;
1145 else
1146 fssp = PCM512x_FSSP_384KHZ;
1147 ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE,
1148 PCM512x_FSSP, fssp);
1149 if (ret != 0) {
1150 dev_err(component->dev, "Failed to set fs speed: %d\n", ret);
1151 return ret;
1152 }
1153
1154 dev_dbg(component->dev, "DSP divider %d\n", dsp_div);
1155 dev_dbg(component->dev, "DAC divider %d\n", dac_div);
1156 dev_dbg(component->dev, "NCP divider %d\n", ncp_div);
1157 dev_dbg(component->dev, "OSR divider %d\n", osr_div);
1158 dev_dbg(component->dev, "BCK divider %d\n", bclk_div);
1159 dev_dbg(component->dev, "LRCK divider %d\n", lrclk_div);
1160 dev_dbg(component->dev, "IDAC %d\n", idac);
1161 dev_dbg(component->dev, "1<<FSSP %d\n", 1 << fssp);
1162
1163 return 0;
1164}
1165
1166static int pcm512x_hw_params(struct snd_pcm_substream *substream,
1167 struct snd_pcm_hw_params *params,
1168 struct snd_soc_dai *dai)
1169{
1170 struct snd_soc_component *component = dai->component;
1171 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
1172 int alen;
1173 int gpio;
1174 int ret;
1175
1176 dev_dbg(component->dev, "hw_params %u Hz, %u channels\n",
1177 params_rate(params),
1178 params_channels(params));
1179
1180 switch (params_width(params)) {
1181 case 16:
1182 alen = PCM512x_ALEN_16;
1183 break;
1184 case 20:
1185 alen = PCM512x_ALEN_20;
1186 break;
1187 case 24:
1188 alen = PCM512x_ALEN_24;
1189 break;
1190 case 32:
1191 alen = PCM512x_ALEN_32;
1192 break;
1193 default:
1194 dev_err(component->dev, "Bad frame size: %d\n",
1195 params_width(params));
1196 return -EINVAL;
1197 }
1198
1199 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
1200 PCM512x_ALEN, alen);
1201 if (ret != 0) {
1202 dev_err(component->dev, "Failed to set frame size: %d\n", ret);
1203 return ret;
1204 }
1205
1206 if ((pcm512x->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
1207 SND_SOC_DAIFMT_CBC_CFC) {
1208 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1209 PCM512x_DCAS, 0);
1210 if (ret != 0) {
1211 dev_err(component->dev,
1212 "Failed to enable clock divider autoset: %d\n",
1213 ret);
1214 return ret;
1215 }
1216 goto skip_pll;
1217 }
1218
1219 if (pcm512x->pll_out) {
1220 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11);
1221 if (ret != 0) {
1222 dev_err(component->dev, "Failed to set FLEX_A: %d\n", ret);
1223 return ret;
1224 }
1225
1226 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff);
1227 if (ret != 0) {
1228 dev_err(component->dev, "Failed to set FLEX_B: %d\n", ret);
1229 return ret;
1230 }
1231
1232 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1233 PCM512x_IDFS | PCM512x_IDBK
1234 | PCM512x_IDSK | PCM512x_IDCH
1235 | PCM512x_IDCM | PCM512x_DCAS
1236 | PCM512x_IPLK,
1237 PCM512x_IDFS | PCM512x_IDBK
1238 | PCM512x_IDSK | PCM512x_IDCH
1239 | PCM512x_DCAS);
1240 if (ret != 0) {
1241 dev_err(component->dev,
1242 "Failed to ignore auto-clock failures: %d\n",
1243 ret);
1244 return ret;
1245 }
1246 } else {
1247 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1248 PCM512x_IDFS | PCM512x_IDBK
1249 | PCM512x_IDSK | PCM512x_IDCH
1250 | PCM512x_IDCM | PCM512x_DCAS
1251 | PCM512x_IPLK,
1252 PCM512x_IDFS | PCM512x_IDBK
1253 | PCM512x_IDSK | PCM512x_IDCH
1254 | PCM512x_DCAS | PCM512x_IPLK);
1255 if (ret != 0) {
1256 dev_err(component->dev,
1257 "Failed to ignore auto-clock failures: %d\n",
1258 ret);
1259 return ret;
1260 }
1261
1262 if (!pcm512x->force_pll_on) {
1263 ret = regmap_update_bits(pcm512x->regmap,
1264 PCM512x_PLL_EN, PCM512x_PLLE, 0);
1265 } else {
1266 /* provide minimum PLL config for TAS575x clocking
1267 * and leave PLL enabled
1268 */
1269 ret = regmap_write(pcm512x->regmap,
1270 PCM512x_PLL_COEFF_0, 0x01);
1271 if (ret != 0) {
1272 dev_err(component->dev,
1273 "Failed to set pll coefficient: %d\n", ret);
1274 return ret;
1275 }
1276 ret = regmap_write(pcm512x->regmap,
1277 PCM512x_PLL_COEFF_1, 0x04);
1278 if (ret != 0) {
1279 dev_err(component->dev,
1280 "Failed to set pll coefficient: %d\n", ret);
1281 return ret;
1282 }
1283 ret = regmap_write(pcm512x->regmap,
1284 PCM512x_PLL_EN, 0x01);
1285 dev_dbg(component->dev, "Enabling PLL for TAS575x\n");
1286 }
1287
1288 if (ret != 0) {
1289 dev_err(component->dev, "Failed to set pll mode: %d\n", ret);
1290 return ret;
1291 }
1292 }
1293
1294 ret = pcm512x_set_dividers(dai, params);
1295 if (ret != 0)
1296 return ret;
1297
1298 if (pcm512x->pll_out) {
1299 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF,
1300 PCM512x_SREF, PCM512x_SREF_GPIO);
1301 if (ret != 0) {
1302 dev_err(component->dev,
1303 "Failed to set gpio as pllref: %d\n", ret);
1304 return ret;
1305 }
1306
1307 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
1308 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN,
1309 PCM512x_GREF, gpio);
1310 if (ret != 0) {
1311 dev_err(component->dev,
1312 "Failed to set gpio %d as pllin: %d\n",
1313 pcm512x->pll_in, ret);
1314 return ret;
1315 }
1316
1317 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1318 PCM512x_PLLE, PCM512x_PLLE);
1319 if (ret != 0) {
1320 dev_err(component->dev, "Failed to enable pll: %d\n", ret);
1321 return ret;
1322 }
1323
1324 gpio = PCM512x_G1OE << (pcm512x->pll_out - 1);
1325 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN,
1326 gpio, gpio);
1327 if (ret != 0) {
1328 dev_err(component->dev, "Failed to enable gpio %d: %d\n",
1329 pcm512x->pll_out, ret);
1330 return ret;
1331 }
1332
1333 gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1;
1334 ret = regmap_update_bits(pcm512x->regmap, gpio,
1335 PCM512x_GxSL, PCM512x_GxSL_PLLCK);
1336 if (ret != 0) {
1337 dev_err(component->dev, "Failed to output pll on %d: %d\n",
1338 ret, pcm512x->pll_out);
1339 return ret;
1340 }
1341 }
1342
1343 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1344 PCM512x_RQSY, PCM512x_RQSY_HALT);
1345 if (ret != 0) {
1346 dev_err(component->dev, "Failed to halt clocks: %d\n", ret);
1347 return ret;
1348 }
1349
1350 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1351 PCM512x_RQSY, PCM512x_RQSY_RESUME);
1352 if (ret != 0) {
1353 dev_err(component->dev, "Failed to resume clocks: %d\n", ret);
1354 return ret;
1355 }
1356
1357skip_pll:
1358 return 0;
1359}
1360
1361static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1362{
1363 struct snd_soc_component *component = dai->component;
1364 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
1365 int afmt;
1366 int offset = 0;
1367 int clock_output;
1368 int provider_mode;
1369 int ret;
1370
1371 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1372 case SND_SOC_DAIFMT_CBC_CFC:
1373 clock_output = 0;
1374 provider_mode = 0;
1375 break;
1376 case SND_SOC_DAIFMT_CBP_CFP:
1377 clock_output = PCM512x_BCKO | PCM512x_LRKO;
1378 provider_mode = PCM512x_RLRK | PCM512x_RBCK;
1379 break;
1380 case SND_SOC_DAIFMT_CBP_CFC:
1381 clock_output = PCM512x_BCKO;
1382 provider_mode = PCM512x_RBCK;
1383 break;
1384 default:
1385 return -EINVAL;
1386 }
1387
1388 ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG,
1389 PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO,
1390 clock_output);
1391 if (ret != 0) {
1392 dev_err(component->dev, "Failed to enable clock output: %d\n", ret);
1393 return ret;
1394 }
1395
1396 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE,
1397 PCM512x_RLRK | PCM512x_RBCK,
1398 provider_mode);
1399 if (ret != 0) {
1400 dev_err(component->dev, "Failed to enable provider mode: %d\n", ret);
1401 return ret;
1402 }
1403
1404 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1405 case SND_SOC_DAIFMT_I2S:
1406 afmt = PCM512x_AFMT_I2S;
1407 break;
1408 case SND_SOC_DAIFMT_RIGHT_J:
1409 afmt = PCM512x_AFMT_RTJ;
1410 break;
1411 case SND_SOC_DAIFMT_LEFT_J:
1412 afmt = PCM512x_AFMT_LTJ;
1413 break;
1414 case SND_SOC_DAIFMT_DSP_A:
1415 offset = 1;
1416 fallthrough;
1417 case SND_SOC_DAIFMT_DSP_B:
1418 afmt = PCM512x_AFMT_DSP;
1419 break;
1420 default:
1421 dev_err(component->dev, "unsupported DAI format: 0x%x\n",
1422 pcm512x->fmt);
1423 return -EINVAL;
1424 }
1425
1426 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
1427 PCM512x_AFMT, afmt);
1428 if (ret != 0) {
1429 dev_err(component->dev, "Failed to set data format: %d\n", ret);
1430 return ret;
1431 }
1432
1433 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_2,
1434 0xFF, offset);
1435 if (ret != 0) {
1436 dev_err(component->dev, "Failed to set data offset: %d\n", ret);
1437 return ret;
1438 }
1439
1440 pcm512x->fmt = fmt;
1441
1442 return 0;
1443}
1444
1445static int pcm512x_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
1446{
1447 struct snd_soc_component *component = dai->component;
1448 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
1449
1450 if (ratio > 256)
1451 return -EINVAL;
1452
1453 pcm512x->bclk_ratio = ratio;
1454
1455 return 0;
1456}
1457
1458static int pcm512x_mute(struct snd_soc_dai *dai, int mute, int direction)
1459{
1460 struct snd_soc_component *component = dai->component;
1461 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
1462 int ret;
1463 unsigned int mute_det;
1464
1465 mutex_lock(&pcm512x->mutex);
1466
1467 if (mute) {
1468 pcm512x->mute |= 0x1;
1469 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MUTE,
1470 PCM512x_RQML | PCM512x_RQMR,
1471 PCM512x_RQML | PCM512x_RQMR);
1472 if (ret != 0) {
1473 dev_err(component->dev,
1474 "Failed to set digital mute: %d\n", ret);
1475 goto unlock;
1476 }
1477
1478 regmap_read_poll_timeout(pcm512x->regmap,
1479 PCM512x_ANALOG_MUTE_DET,
1480 mute_det, (mute_det & 0x3) == 0,
1481 200, 10000);
1482 } else {
1483 pcm512x->mute &= ~0x1;
1484 ret = pcm512x_update_mute(pcm512x);
1485 if (ret != 0) {
1486 dev_err(component->dev,
1487 "Failed to update digital mute: %d\n", ret);
1488 goto unlock;
1489 }
1490
1491 regmap_read_poll_timeout(pcm512x->regmap,
1492 PCM512x_ANALOG_MUTE_DET,
1493 mute_det,
1494 (mute_det & 0x3)
1495 == ((~pcm512x->mute >> 1) & 0x3),
1496 200, 10000);
1497 }
1498
1499unlock:
1500 mutex_unlock(&pcm512x->mutex);
1501
1502 return ret;
1503}
1504
1505static const struct snd_soc_dai_ops pcm512x_dai_ops = {
1506 .startup = pcm512x_dai_startup,
1507 .hw_params = pcm512x_hw_params,
1508 .set_fmt = pcm512x_set_fmt,
1509 .mute_stream = pcm512x_mute,
1510 .set_bclk_ratio = pcm512x_set_bclk_ratio,
1511 .no_capture_mute = 1,
1512};
1513
1514static struct snd_soc_dai_driver pcm512x_dai = {
1515 .name = "pcm512x-hifi",
1516 .playback = {
1517 .stream_name = "Playback",
1518 .channels_min = 2,
1519 .channels_max = 2,
1520 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1521 .rate_min = 8000,
1522 .rate_max = 384000,
1523 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1524 SNDRV_PCM_FMTBIT_S24_LE |
1525 SNDRV_PCM_FMTBIT_S32_LE
1526 },
1527 .ops = &pcm512x_dai_ops,
1528};
1529
1530static const struct snd_soc_component_driver pcm512x_component_driver = {
1531 .set_bias_level = pcm512x_set_bias_level,
1532 .controls = pcm512x_controls,
1533 .num_controls = ARRAY_SIZE(pcm512x_controls),
1534 .dapm_widgets = pcm512x_dapm_widgets,
1535 .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets),
1536 .dapm_routes = pcm512x_dapm_routes,
1537 .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes),
1538 .use_pmdown_time = 1,
1539 .endianness = 1,
1540};
1541
1542static const struct regmap_range_cfg pcm512x_range = {
1543 .name = "Pages", .range_min = PCM512x_VIRT_BASE,
1544 .range_max = PCM512x_MAX_REGISTER,
1545 .selector_reg = PCM512x_PAGE,
1546 .selector_mask = 0xff,
1547 .window_start = 0, .window_len = 0x100,
1548};
1549
1550const struct regmap_config pcm512x_regmap = {
1551 .reg_bits = 8,
1552 .val_bits = 8,
1553
1554 .readable_reg = pcm512x_readable,
1555 .volatile_reg = pcm512x_volatile,
1556
1557 .ranges = &pcm512x_range,
1558 .num_ranges = 1,
1559
1560 .max_register = PCM512x_MAX_REGISTER,
1561 .reg_defaults = pcm512x_reg_defaults,
1562 .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults),
1563 .cache_type = REGCACHE_RBTREE,
1564};
1565EXPORT_SYMBOL_GPL(pcm512x_regmap);
1566
1567int pcm512x_probe(struct device *dev, struct regmap *regmap)
1568{
1569 struct pcm512x_priv *pcm512x;
1570 int i, ret;
1571
1572 pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL);
1573 if (!pcm512x)
1574 return -ENOMEM;
1575
1576 mutex_init(&pcm512x->mutex);
1577
1578 dev_set_drvdata(dev, pcm512x);
1579 pcm512x->regmap = regmap;
1580
1581 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++)
1582 pcm512x->supplies[i].supply = pcm512x_supply_names[i];
1583
1584 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies),
1585 pcm512x->supplies);
1586 if (ret != 0) {
1587 dev_err(dev, "Failed to get supplies: %d\n", ret);
1588 return ret;
1589 }
1590
1591 pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0;
1592 pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1;
1593 pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2;
1594
1595 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) {
1596 ret = devm_regulator_register_notifier(
1597 pcm512x->supplies[i].consumer,
1598 &pcm512x->supply_nb[i]);
1599 if (ret != 0) {
1600 dev_err(dev,
1601 "Failed to register regulator notifier: %d\n",
1602 ret);
1603 }
1604 }
1605
1606 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1607 pcm512x->supplies);
1608 if (ret != 0) {
1609 dev_err(dev, "Failed to enable supplies: %d\n", ret);
1610 return ret;
1611 }
1612
1613 /* Reset the device, verifying I/O in the process for I2C */
1614 ret = regmap_write(regmap, PCM512x_RESET,
1615 PCM512x_RSTM | PCM512x_RSTR);
1616 if (ret != 0) {
1617 dev_err(dev, "Failed to reset device: %d\n", ret);
1618 goto err;
1619 }
1620
1621 ret = regmap_write(regmap, PCM512x_RESET, 0);
1622 if (ret != 0) {
1623 dev_err(dev, "Failed to reset device: %d\n", ret);
1624 goto err;
1625 }
1626
1627 pcm512x->sclk = devm_clk_get(dev, NULL);
1628 if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) {
1629 ret = -EPROBE_DEFER;
1630 goto err;
1631 }
1632 if (!IS_ERR(pcm512x->sclk)) {
1633 ret = clk_prepare_enable(pcm512x->sclk);
1634 if (ret != 0) {
1635 dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1636 goto err;
1637 }
1638 }
1639
1640 /* Default to standby mode */
1641 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1642 PCM512x_RQST, PCM512x_RQST);
1643 if (ret != 0) {
1644 dev_err(dev, "Failed to request standby: %d\n",
1645 ret);
1646 goto err_clk;
1647 }
1648
1649 pm_runtime_set_active(dev);
1650 pm_runtime_enable(dev);
1651 pm_runtime_idle(dev);
1652
1653#ifdef CONFIG_OF
1654 if (dev->of_node) {
1655 const struct device_node *np = dev->of_node;
1656 u32 val;
1657
1658 if (of_property_read_u32(np, "pll-in", &val) >= 0) {
1659 if (val > 6) {
1660 dev_err(dev, "Invalid pll-in\n");
1661 ret = -EINVAL;
1662 goto err_pm;
1663 }
1664 pcm512x->pll_in = val;
1665 }
1666
1667 if (of_property_read_u32(np, "pll-out", &val) >= 0) {
1668 if (val > 6) {
1669 dev_err(dev, "Invalid pll-out\n");
1670 ret = -EINVAL;
1671 goto err_pm;
1672 }
1673 pcm512x->pll_out = val;
1674 }
1675
1676 if (!pcm512x->pll_in != !pcm512x->pll_out) {
1677 dev_err(dev,
1678 "Error: both pll-in and pll-out, or none\n");
1679 ret = -EINVAL;
1680 goto err_pm;
1681 }
1682 if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) {
1683 dev_err(dev, "Error: pll-in == pll-out\n");
1684 ret = -EINVAL;
1685 goto err_pm;
1686 }
1687
1688 if (!strcmp(np->name, "tas5756") ||
1689 !strcmp(np->name, "tas5754"))
1690 pcm512x->force_pll_on = 1;
1691 dev_dbg(dev, "Device ID: %s\n", np->name);
1692 }
1693#endif
1694
1695 ret = devm_snd_soc_register_component(dev, &pcm512x_component_driver,
1696 &pcm512x_dai, 1);
1697 if (ret != 0) {
1698 dev_err(dev, "Failed to register CODEC: %d\n", ret);
1699 goto err_pm;
1700 }
1701
1702 return 0;
1703
1704err_pm:
1705 pm_runtime_disable(dev);
1706err_clk:
1707 if (!IS_ERR(pcm512x->sclk))
1708 clk_disable_unprepare(pcm512x->sclk);
1709err:
1710 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1711 pcm512x->supplies);
1712 return ret;
1713}
1714EXPORT_SYMBOL_GPL(pcm512x_probe);
1715
1716void pcm512x_remove(struct device *dev)
1717{
1718 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1719
1720 pm_runtime_disable(dev);
1721 if (!IS_ERR(pcm512x->sclk))
1722 clk_disable_unprepare(pcm512x->sclk);
1723 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1724 pcm512x->supplies);
1725}
1726EXPORT_SYMBOL_GPL(pcm512x_remove);
1727
1728#ifdef CONFIG_PM
1729static int pcm512x_suspend(struct device *dev)
1730{
1731 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1732 int ret;
1733
1734 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1735 PCM512x_RQPD, PCM512x_RQPD);
1736 if (ret != 0) {
1737 dev_err(dev, "Failed to request power down: %d\n", ret);
1738 return ret;
1739 }
1740
1741 ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1742 pcm512x->supplies);
1743 if (ret != 0) {
1744 dev_err(dev, "Failed to disable supplies: %d\n", ret);
1745 return ret;
1746 }
1747
1748 if (!IS_ERR(pcm512x->sclk))
1749 clk_disable_unprepare(pcm512x->sclk);
1750
1751 return 0;
1752}
1753
1754static int pcm512x_resume(struct device *dev)
1755{
1756 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1757 int ret;
1758
1759 if (!IS_ERR(pcm512x->sclk)) {
1760 ret = clk_prepare_enable(pcm512x->sclk);
1761 if (ret != 0) {
1762 dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1763 return ret;
1764 }
1765 }
1766
1767 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1768 pcm512x->supplies);
1769 if (ret != 0) {
1770 dev_err(dev, "Failed to enable supplies: %d\n", ret);
1771 return ret;
1772 }
1773
1774 regcache_cache_only(pcm512x->regmap, false);
1775 ret = regcache_sync(pcm512x->regmap);
1776 if (ret != 0) {
1777 dev_err(dev, "Failed to sync cache: %d\n", ret);
1778 return ret;
1779 }
1780
1781 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1782 PCM512x_RQPD, 0);
1783 if (ret != 0) {
1784 dev_err(dev, "Failed to remove power down: %d\n", ret);
1785 return ret;
1786 }
1787
1788 return 0;
1789}
1790#endif
1791
1792const struct dev_pm_ops pcm512x_pm_ops = {
1793 SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL)
1794};
1795EXPORT_SYMBOL_GPL(pcm512x_pm_ops);
1796
1797MODULE_DESCRIPTION("ASoC PCM512x codec driver");
1798MODULE_AUTHOR("Mark Brown <broonie@kernel.org>");
1799MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for the PCM512x CODECs
4 *
5 * Author: Mark Brown <broonie@kernel.org>
6 * Copyright 2014 Linaro Ltd
7 */
8
9
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/clk.h>
13#include <linux/kernel.h>
14#include <linux/pm_runtime.h>
15#include <linux/regmap.h>
16#include <linux/regulator/consumer.h>
17#include <linux/gcd.h>
18#include <sound/soc.h>
19#include <sound/soc-dapm.h>
20#include <sound/pcm_params.h>
21#include <sound/tlv.h>
22
23#include "pcm512x.h"
24
25#define PCM512x_NUM_SUPPLIES 3
26static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = {
27 "AVDD",
28 "DVDD",
29 "CPVDD",
30};
31
32struct pcm512x_priv {
33 struct regmap *regmap;
34 struct clk *sclk;
35 struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES];
36 struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES];
37 int fmt;
38 int pll_in;
39 int pll_out;
40 int pll_r;
41 int pll_j;
42 int pll_d;
43 int pll_p;
44 unsigned long real_pll;
45 unsigned long overclock_pll;
46 unsigned long overclock_dac;
47 unsigned long overclock_dsp;
48 int mute;
49 struct mutex mutex;
50 unsigned int bclk_ratio;
51};
52
53/*
54 * We can't use the same notifier block for more than one supply and
55 * there's no way I can see to get from a callback to the caller
56 * except container_of().
57 */
58#define PCM512x_REGULATOR_EVENT(n) \
59static int pcm512x_regulator_event_##n(struct notifier_block *nb, \
60 unsigned long event, void *data) \
61{ \
62 struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \
63 supply_nb[n]); \
64 if (event & REGULATOR_EVENT_DISABLE) { \
65 regcache_mark_dirty(pcm512x->regmap); \
66 regcache_cache_only(pcm512x->regmap, true); \
67 } \
68 return 0; \
69}
70
71PCM512x_REGULATOR_EVENT(0)
72PCM512x_REGULATOR_EVENT(1)
73PCM512x_REGULATOR_EVENT(2)
74
75static const struct reg_default pcm512x_reg_defaults[] = {
76 { PCM512x_RESET, 0x00 },
77 { PCM512x_POWER, 0x00 },
78 { PCM512x_MUTE, 0x00 },
79 { PCM512x_DSP, 0x00 },
80 { PCM512x_PLL_REF, 0x00 },
81 { PCM512x_DAC_REF, 0x00 },
82 { PCM512x_DAC_ROUTING, 0x11 },
83 { PCM512x_DSP_PROGRAM, 0x01 },
84 { PCM512x_CLKDET, 0x00 },
85 { PCM512x_AUTO_MUTE, 0x00 },
86 { PCM512x_ERROR_DETECT, 0x00 },
87 { PCM512x_DIGITAL_VOLUME_1, 0x00 },
88 { PCM512x_DIGITAL_VOLUME_2, 0x30 },
89 { PCM512x_DIGITAL_VOLUME_3, 0x30 },
90 { PCM512x_DIGITAL_MUTE_1, 0x22 },
91 { PCM512x_DIGITAL_MUTE_2, 0x00 },
92 { PCM512x_DIGITAL_MUTE_3, 0x07 },
93 { PCM512x_OUTPUT_AMPLITUDE, 0x00 },
94 { PCM512x_ANALOG_GAIN_CTRL, 0x00 },
95 { PCM512x_UNDERVOLTAGE_PROT, 0x00 },
96 { PCM512x_ANALOG_MUTE_CTRL, 0x00 },
97 { PCM512x_ANALOG_GAIN_BOOST, 0x00 },
98 { PCM512x_VCOM_CTRL_1, 0x00 },
99 { PCM512x_VCOM_CTRL_2, 0x01 },
100 { PCM512x_BCLK_LRCLK_CFG, 0x00 },
101 { PCM512x_MASTER_MODE, 0x7c },
102 { PCM512x_GPIO_DACIN, 0x00 },
103 { PCM512x_GPIO_PLLIN, 0x00 },
104 { PCM512x_SYNCHRONIZE, 0x10 },
105 { PCM512x_PLL_COEFF_0, 0x00 },
106 { PCM512x_PLL_COEFF_1, 0x00 },
107 { PCM512x_PLL_COEFF_2, 0x00 },
108 { PCM512x_PLL_COEFF_3, 0x00 },
109 { PCM512x_PLL_COEFF_4, 0x00 },
110 { PCM512x_DSP_CLKDIV, 0x00 },
111 { PCM512x_DAC_CLKDIV, 0x00 },
112 { PCM512x_NCP_CLKDIV, 0x00 },
113 { PCM512x_OSR_CLKDIV, 0x00 },
114 { PCM512x_MASTER_CLKDIV_1, 0x00 },
115 { PCM512x_MASTER_CLKDIV_2, 0x00 },
116 { PCM512x_FS_SPEED_MODE, 0x00 },
117 { PCM512x_IDAC_1, 0x01 },
118 { PCM512x_IDAC_2, 0x00 },
119 { PCM512x_I2S_1, 0x02 },
120 { PCM512x_I2S_2, 0x00 },
121};
122
123static bool pcm512x_readable(struct device *dev, unsigned int reg)
124{
125 switch (reg) {
126 case PCM512x_RESET:
127 case PCM512x_POWER:
128 case PCM512x_MUTE:
129 case PCM512x_PLL_EN:
130 case PCM512x_SPI_MISO_FUNCTION:
131 case PCM512x_DSP:
132 case PCM512x_GPIO_EN:
133 case PCM512x_BCLK_LRCLK_CFG:
134 case PCM512x_DSP_GPIO_INPUT:
135 case PCM512x_MASTER_MODE:
136 case PCM512x_PLL_REF:
137 case PCM512x_DAC_REF:
138 case PCM512x_GPIO_DACIN:
139 case PCM512x_GPIO_PLLIN:
140 case PCM512x_SYNCHRONIZE:
141 case PCM512x_PLL_COEFF_0:
142 case PCM512x_PLL_COEFF_1:
143 case PCM512x_PLL_COEFF_2:
144 case PCM512x_PLL_COEFF_3:
145 case PCM512x_PLL_COEFF_4:
146 case PCM512x_DSP_CLKDIV:
147 case PCM512x_DAC_CLKDIV:
148 case PCM512x_NCP_CLKDIV:
149 case PCM512x_OSR_CLKDIV:
150 case PCM512x_MASTER_CLKDIV_1:
151 case PCM512x_MASTER_CLKDIV_2:
152 case PCM512x_FS_SPEED_MODE:
153 case PCM512x_IDAC_1:
154 case PCM512x_IDAC_2:
155 case PCM512x_ERROR_DETECT:
156 case PCM512x_I2S_1:
157 case PCM512x_I2S_2:
158 case PCM512x_DAC_ROUTING:
159 case PCM512x_DSP_PROGRAM:
160 case PCM512x_CLKDET:
161 case PCM512x_AUTO_MUTE:
162 case PCM512x_DIGITAL_VOLUME_1:
163 case PCM512x_DIGITAL_VOLUME_2:
164 case PCM512x_DIGITAL_VOLUME_3:
165 case PCM512x_DIGITAL_MUTE_1:
166 case PCM512x_DIGITAL_MUTE_2:
167 case PCM512x_DIGITAL_MUTE_3:
168 case PCM512x_GPIO_OUTPUT_1:
169 case PCM512x_GPIO_OUTPUT_2:
170 case PCM512x_GPIO_OUTPUT_3:
171 case PCM512x_GPIO_OUTPUT_4:
172 case PCM512x_GPIO_OUTPUT_5:
173 case PCM512x_GPIO_OUTPUT_6:
174 case PCM512x_GPIO_CONTROL_1:
175 case PCM512x_GPIO_CONTROL_2:
176 case PCM512x_OVERFLOW:
177 case PCM512x_RATE_DET_1:
178 case PCM512x_RATE_DET_2:
179 case PCM512x_RATE_DET_3:
180 case PCM512x_RATE_DET_4:
181 case PCM512x_CLOCK_STATUS:
182 case PCM512x_ANALOG_MUTE_DET:
183 case PCM512x_GPIN:
184 case PCM512x_DIGITAL_MUTE_DET:
185 case PCM512x_OUTPUT_AMPLITUDE:
186 case PCM512x_ANALOG_GAIN_CTRL:
187 case PCM512x_UNDERVOLTAGE_PROT:
188 case PCM512x_ANALOG_MUTE_CTRL:
189 case PCM512x_ANALOG_GAIN_BOOST:
190 case PCM512x_VCOM_CTRL_1:
191 case PCM512x_VCOM_CTRL_2:
192 case PCM512x_CRAM_CTRL:
193 case PCM512x_FLEX_A:
194 case PCM512x_FLEX_B:
195 return true;
196 default:
197 /* There are 256 raw register addresses */
198 return reg < 0xff;
199 }
200}
201
202static bool pcm512x_volatile(struct device *dev, unsigned int reg)
203{
204 switch (reg) {
205 case PCM512x_PLL_EN:
206 case PCM512x_OVERFLOW:
207 case PCM512x_RATE_DET_1:
208 case PCM512x_RATE_DET_2:
209 case PCM512x_RATE_DET_3:
210 case PCM512x_RATE_DET_4:
211 case PCM512x_CLOCK_STATUS:
212 case PCM512x_ANALOG_MUTE_DET:
213 case PCM512x_GPIN:
214 case PCM512x_DIGITAL_MUTE_DET:
215 case PCM512x_CRAM_CTRL:
216 return true;
217 default:
218 /* There are 256 raw register addresses */
219 return reg < 0xff;
220 }
221}
222
223static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol,
224 struct snd_ctl_elem_value *ucontrol)
225{
226 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
227 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
228
229 ucontrol->value.integer.value[0] = pcm512x->overclock_pll;
230 return 0;
231}
232
233static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol,
234 struct snd_ctl_elem_value *ucontrol)
235{
236 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
237 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
238
239 switch (snd_soc_component_get_bias_level(component)) {
240 case SND_SOC_BIAS_OFF:
241 case SND_SOC_BIAS_STANDBY:
242 break;
243 default:
244 return -EBUSY;
245 }
246
247 pcm512x->overclock_pll = ucontrol->value.integer.value[0];
248 return 0;
249}
250
251static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol,
252 struct snd_ctl_elem_value *ucontrol)
253{
254 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
255 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
256
257 ucontrol->value.integer.value[0] = pcm512x->overclock_dsp;
258 return 0;
259}
260
261static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol,
262 struct snd_ctl_elem_value *ucontrol)
263{
264 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
265 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
266
267 switch (snd_soc_component_get_bias_level(component)) {
268 case SND_SOC_BIAS_OFF:
269 case SND_SOC_BIAS_STANDBY:
270 break;
271 default:
272 return -EBUSY;
273 }
274
275 pcm512x->overclock_dsp = ucontrol->value.integer.value[0];
276 return 0;
277}
278
279static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol,
280 struct snd_ctl_elem_value *ucontrol)
281{
282 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
283 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
284
285 ucontrol->value.integer.value[0] = pcm512x->overclock_dac;
286 return 0;
287}
288
289static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol,
290 struct snd_ctl_elem_value *ucontrol)
291{
292 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
293 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
294
295 switch (snd_soc_component_get_bias_level(component)) {
296 case SND_SOC_BIAS_OFF:
297 case SND_SOC_BIAS_STANDBY:
298 break;
299 default:
300 return -EBUSY;
301 }
302
303 pcm512x->overclock_dac = ucontrol->value.integer.value[0];
304 return 0;
305}
306
307static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1);
308static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0);
309static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0);
310
311static const char * const pcm512x_dsp_program_texts[] = {
312 "FIR interpolation with de-emphasis",
313 "Low latency IIR with de-emphasis",
314 "High attenuation with de-emphasis",
315 "Fixed process flow",
316 "Ringing-less low latency FIR",
317};
318
319static const unsigned int pcm512x_dsp_program_values[] = {
320 1,
321 2,
322 3,
323 5,
324 7,
325};
326
327static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program,
328 PCM512x_DSP_PROGRAM, 0, 0x1f,
329 pcm512x_dsp_program_texts,
330 pcm512x_dsp_program_values);
331
332static const char * const pcm512x_clk_missing_text[] = {
333 "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s"
334};
335
336static const struct soc_enum pcm512x_clk_missing =
337 SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text);
338
339static const char * const pcm512x_autom_text[] = {
340 "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s"
341};
342
343static const struct soc_enum pcm512x_autom_l =
344 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8,
345 pcm512x_autom_text);
346
347static const struct soc_enum pcm512x_autom_r =
348 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8,
349 pcm512x_autom_text);
350
351static const char * const pcm512x_ramp_rate_text[] = {
352 "1 sample/update", "2 samples/update", "4 samples/update",
353 "Immediate"
354};
355
356static const struct soc_enum pcm512x_vndf =
357 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4,
358 pcm512x_ramp_rate_text);
359
360static const struct soc_enum pcm512x_vnuf =
361 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4,
362 pcm512x_ramp_rate_text);
363
364static const struct soc_enum pcm512x_vedf =
365 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4,
366 pcm512x_ramp_rate_text);
367
368static const char * const pcm512x_ramp_step_text[] = {
369 "4dB/step", "2dB/step", "1dB/step", "0.5dB/step"
370};
371
372static const struct soc_enum pcm512x_vnds =
373 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4,
374 pcm512x_ramp_step_text);
375
376static const struct soc_enum pcm512x_vnus =
377 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4,
378 pcm512x_ramp_step_text);
379
380static const struct soc_enum pcm512x_veds =
381 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4,
382 pcm512x_ramp_step_text);
383
384static int pcm512x_update_mute(struct pcm512x_priv *pcm512x)
385{
386 return regmap_update_bits(
387 pcm512x->regmap, PCM512x_MUTE, PCM512x_RQML | PCM512x_RQMR,
388 (!!(pcm512x->mute & 0x5) << PCM512x_RQML_SHIFT)
389 | (!!(pcm512x->mute & 0x3) << PCM512x_RQMR_SHIFT));
390}
391
392static int pcm512x_digital_playback_switch_get(struct snd_kcontrol *kcontrol,
393 struct snd_ctl_elem_value *ucontrol)
394{
395 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
396 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
397
398 mutex_lock(&pcm512x->mutex);
399 ucontrol->value.integer.value[0] = !(pcm512x->mute & 0x4);
400 ucontrol->value.integer.value[1] = !(pcm512x->mute & 0x2);
401 mutex_unlock(&pcm512x->mutex);
402
403 return 0;
404}
405
406static int pcm512x_digital_playback_switch_put(struct snd_kcontrol *kcontrol,
407 struct snd_ctl_elem_value *ucontrol)
408{
409 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
410 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
411 int ret, changed = 0;
412
413 mutex_lock(&pcm512x->mutex);
414
415 if ((pcm512x->mute & 0x4) == (ucontrol->value.integer.value[0] << 2)) {
416 pcm512x->mute ^= 0x4;
417 changed = 1;
418 }
419 if ((pcm512x->mute & 0x2) == (ucontrol->value.integer.value[1] << 1)) {
420 pcm512x->mute ^= 0x2;
421 changed = 1;
422 }
423
424 if (changed) {
425 ret = pcm512x_update_mute(pcm512x);
426 if (ret != 0) {
427 dev_err(component->dev,
428 "Failed to update digital mute: %d\n", ret);
429 mutex_unlock(&pcm512x->mutex);
430 return ret;
431 }
432 }
433
434 mutex_unlock(&pcm512x->mutex);
435
436 return changed;
437}
438
439static const struct snd_kcontrol_new pcm512x_controls[] = {
440SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2,
441 PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv),
442SOC_DOUBLE_TLV("Analogue Playback Volume", PCM512x_ANALOG_GAIN_CTRL,
443 PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv),
444SOC_DOUBLE_TLV("Analogue Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST,
445 PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv),
446{
447 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
448 .name = "Digital Playback Switch",
449 .index = 0,
450 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
451 .info = snd_ctl_boolean_stereo_info,
452 .get = pcm512x_digital_playback_switch_get,
453 .put = pcm512x_digital_playback_switch_put
454},
455
456SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1),
457SOC_ENUM("DSP Program", pcm512x_dsp_program),
458
459SOC_ENUM("Clock Missing Period", pcm512x_clk_missing),
460SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l),
461SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r),
462SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3,
463 PCM512x_ACTL_SHIFT, 1, 0),
464SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT,
465 PCM512x_AMRE_SHIFT, 1, 0),
466
467SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf),
468SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds),
469SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf),
470SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus),
471SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf),
472SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds),
473
474SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0,
475 pcm512x_overclock_pll_get, pcm512x_overclock_pll_put),
476SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0,
477 pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put),
478SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0,
479 pcm512x_overclock_dac_get, pcm512x_overclock_dac_put),
480};
481
482static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = {
483SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
484SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
485
486SND_SOC_DAPM_OUTPUT("OUTL"),
487SND_SOC_DAPM_OUTPUT("OUTR"),
488};
489
490static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = {
491 { "DACL", NULL, "Playback" },
492 { "DACR", NULL, "Playback" },
493
494 { "OUTL", NULL, "DACL" },
495 { "OUTR", NULL, "DACR" },
496};
497
498static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x)
499{
500 return 25000000 + 25000000 * pcm512x->overclock_pll / 100;
501}
502
503static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x)
504{
505 return 50000000 + 50000000 * pcm512x->overclock_dsp / 100;
506}
507
508static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x,
509 unsigned long rate)
510{
511 return rate + rate * pcm512x->overclock_dac / 100;
512}
513
514static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x)
515{
516 if (!pcm512x->pll_out)
517 return 25000000;
518 return pcm512x_pll_max(pcm512x);
519}
520
521static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x,
522 unsigned long dac_rate)
523{
524 /*
525 * If the DAC is not actually overclocked, use the good old
526 * NCP target rate...
527 */
528 if (dac_rate <= 6144000)
529 return 1536000;
530 /*
531 * ...but if the DAC is in fact overclocked, bump the NCP target
532 * rate to get the recommended dividers even when overclocking.
533 */
534 return pcm512x_dac_max(pcm512x, 1536000);
535}
536
537static const u32 pcm512x_dai_rates[] = {
538 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
539 88200, 96000, 176400, 192000, 384000,
540};
541
542static const struct snd_pcm_hw_constraint_list constraints_slave = {
543 .count = ARRAY_SIZE(pcm512x_dai_rates),
544 .list = pcm512x_dai_rates,
545};
546
547static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params,
548 struct snd_pcm_hw_rule *rule)
549{
550 struct pcm512x_priv *pcm512x = rule->private;
551 struct snd_interval ranges[2];
552 int frame_size;
553
554 frame_size = snd_soc_params_to_frame_size(params);
555 if (frame_size < 0)
556 return frame_size;
557
558 switch (frame_size) {
559 case 32:
560 /* No hole when the frame size is 32. */
561 return 0;
562 case 48:
563 case 64:
564 /* There is only one hole in the range of supported
565 * rates, but it moves with the frame size.
566 */
567 memset(ranges, 0, sizeof(ranges));
568 ranges[0].min = 8000;
569 ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2;
570 ranges[1].min = DIV_ROUND_UP(16000000, frame_size);
571 ranges[1].max = 384000;
572 break;
573 default:
574 return -EINVAL;
575 }
576
577 return snd_interval_ranges(hw_param_interval(params, rule->var),
578 ARRAY_SIZE(ranges), ranges, 0);
579}
580
581static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream,
582 struct snd_soc_dai *dai)
583{
584 struct snd_soc_component *component = dai->component;
585 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
586 struct device *dev = dai->dev;
587 struct snd_pcm_hw_constraint_ratnums *constraints_no_pll;
588 struct snd_ratnum *rats_no_pll;
589
590 if (IS_ERR(pcm512x->sclk)) {
591 dev_err(dev, "Need SCLK for master mode: %ld\n",
592 PTR_ERR(pcm512x->sclk));
593 return PTR_ERR(pcm512x->sclk);
594 }
595
596 if (pcm512x->pll_out)
597 return snd_pcm_hw_rule_add(substream->runtime, 0,
598 SNDRV_PCM_HW_PARAM_RATE,
599 pcm512x_hw_rule_rate,
600 pcm512x,
601 SNDRV_PCM_HW_PARAM_FRAME_BITS,
602 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
603
604 constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll),
605 GFP_KERNEL);
606 if (!constraints_no_pll)
607 return -ENOMEM;
608 constraints_no_pll->nrats = 1;
609 rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL);
610 if (!rats_no_pll)
611 return -ENOMEM;
612 constraints_no_pll->rats = rats_no_pll;
613 rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;
614 rats_no_pll->den_min = 1;
615 rats_no_pll->den_max = 128;
616 rats_no_pll->den_step = 1;
617
618 return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
619 SNDRV_PCM_HW_PARAM_RATE,
620 constraints_no_pll);
621}
622
623static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream,
624 struct snd_soc_dai *dai)
625{
626 struct snd_soc_component *component = dai->component;
627 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
628 struct device *dev = dai->dev;
629 struct regmap *regmap = pcm512x->regmap;
630
631 if (IS_ERR(pcm512x->sclk)) {
632 dev_info(dev, "No SCLK, using BCLK: %ld\n",
633 PTR_ERR(pcm512x->sclk));
634
635 /* Disable reporting of missing SCLK as an error */
636 regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
637 PCM512x_IDCH, PCM512x_IDCH);
638
639 /* Switch PLL input to BCLK */
640 regmap_update_bits(regmap, PCM512x_PLL_REF,
641 PCM512x_SREF, PCM512x_SREF_BCK);
642 }
643
644 return snd_pcm_hw_constraint_list(substream->runtime, 0,
645 SNDRV_PCM_HW_PARAM_RATE,
646 &constraints_slave);
647}
648
649static int pcm512x_dai_startup(struct snd_pcm_substream *substream,
650 struct snd_soc_dai *dai)
651{
652 struct snd_soc_component *component = dai->component;
653 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
654
655 switch (pcm512x->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
656 case SND_SOC_DAIFMT_CBP_CFP:
657 case SND_SOC_DAIFMT_CBP_CFC:
658 return pcm512x_dai_startup_master(substream, dai);
659
660 case SND_SOC_DAIFMT_CBC_CFC:
661 return pcm512x_dai_startup_slave(substream, dai);
662
663 default:
664 return -EINVAL;
665 }
666}
667
668static int pcm512x_set_bias_level(struct snd_soc_component *component,
669 enum snd_soc_bias_level level)
670{
671 struct pcm512x_priv *pcm512x = dev_get_drvdata(component->dev);
672 int ret;
673
674 switch (level) {
675 case SND_SOC_BIAS_ON:
676 case SND_SOC_BIAS_PREPARE:
677 break;
678
679 case SND_SOC_BIAS_STANDBY:
680 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
681 PCM512x_RQST, 0);
682 if (ret != 0) {
683 dev_err(component->dev, "Failed to remove standby: %d\n",
684 ret);
685 return ret;
686 }
687 break;
688
689 case SND_SOC_BIAS_OFF:
690 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
691 PCM512x_RQST, PCM512x_RQST);
692 if (ret != 0) {
693 dev_err(component->dev, "Failed to request standby: %d\n",
694 ret);
695 return ret;
696 }
697 break;
698 }
699
700 return 0;
701}
702
703static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai,
704 unsigned long bclk_rate)
705{
706 struct device *dev = dai->dev;
707 struct snd_soc_component *component = dai->component;
708 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
709 unsigned long sck_rate;
710 int pow2;
711
712 /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */
713 /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */
714
715 /* select sck_rate as a multiple of bclk_rate but still with
716 * as many factors of 2 as possible, as that makes it easier
717 * to find a fast DAC rate
718 */
719 pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate);
720 for (; pow2; pow2 >>= 1) {
721 sck_rate = rounddown(pcm512x_pll_max(pcm512x),
722 bclk_rate * pow2);
723 if (sck_rate >= 16000000)
724 break;
725 }
726 if (!pow2) {
727 dev_err(dev, "Impossible to generate a suitable SCK\n");
728 return 0;
729 }
730
731 dev_dbg(dev, "sck_rate %lu\n", sck_rate);
732 return sck_rate;
733}
734
735/* pll_rate = pllin_rate * R * J.D / P
736 * 1 <= R <= 16
737 * 1 <= J <= 63
738 * 0 <= D <= 9999
739 * 1 <= P <= 15
740 * 64 MHz <= pll_rate <= 100 MHz
741 * if D == 0
742 * 1 MHz <= pllin_rate / P <= 20 MHz
743 * else if D > 0
744 * 6.667 MHz <= pllin_rate / P <= 20 MHz
745 * 4 <= J <= 11
746 * R = 1
747 */
748static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai,
749 unsigned long pllin_rate,
750 unsigned long pll_rate)
751{
752 struct device *dev = dai->dev;
753 struct snd_soc_component *component = dai->component;
754 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
755 unsigned long common;
756 int R, J, D, P;
757 unsigned long K; /* 10000 * J.D */
758 unsigned long num;
759 unsigned long den;
760
761 common = gcd(pll_rate, pllin_rate);
762 dev_dbg(dev, "pll %lu pllin %lu common %lu\n",
763 pll_rate, pllin_rate, common);
764 num = pll_rate / common;
765 den = pllin_rate / common;
766
767 /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */
768 if (pllin_rate / den > 20000000 && num < 8) {
769 num *= DIV_ROUND_UP(pllin_rate / den, 20000000);
770 den *= DIV_ROUND_UP(pllin_rate / den, 20000000);
771 }
772 dev_dbg(dev, "num / den = %lu / %lu\n", num, den);
773
774 P = den;
775 if (den <= 15 && num <= 16 * 63
776 && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) {
777 /* Try the case with D = 0 */
778 D = 0;
779 /* factor 'num' into J and R, such that R <= 16 and J <= 63 */
780 for (R = 16; R; R--) {
781 if (num % R)
782 continue;
783 J = num / R;
784 if (J == 0 || J > 63)
785 continue;
786
787 dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P);
788 pcm512x->real_pll = pll_rate;
789 goto done;
790 }
791 /* no luck */
792 }
793
794 R = 1;
795
796 if (num > 0xffffffffUL / 10000)
797 goto fallback;
798
799 /* Try to find an exact pll_rate using the D > 0 case */
800 common = gcd(10000 * num, den);
801 num = 10000 * num / common;
802 den /= common;
803 dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common);
804
805 for (P = den; P <= 15; P++) {
806 if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P)
807 continue;
808 if (num * P % den)
809 continue;
810 K = num * P / den;
811 /* J == 12 is ok if D == 0 */
812 if (K < 40000 || K > 120000)
813 continue;
814
815 J = K / 10000;
816 D = K % 10000;
817 dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P);
818 pcm512x->real_pll = pll_rate;
819 goto done;
820 }
821
822 /* Fall back to an approximate pll_rate */
823
824fallback:
825 /* find smallest possible P */
826 P = DIV_ROUND_UP(pllin_rate, 20000000);
827 if (!P)
828 P = 1;
829 else if (P > 15) {
830 dev_err(dev, "Need a slower clock as pll-input\n");
831 return -EINVAL;
832 }
833 if (pllin_rate / P < 6667000) {
834 dev_err(dev, "Need a faster clock as pll-input\n");
835 return -EINVAL;
836 }
837 K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate);
838 if (K < 40000)
839 K = 40000;
840 /* J == 12 is ok if D == 0 */
841 if (K > 120000)
842 K = 120000;
843 J = K / 10000;
844 D = K % 10000;
845 dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P);
846 pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P);
847
848done:
849 pcm512x->pll_r = R;
850 pcm512x->pll_j = J;
851 pcm512x->pll_d = D;
852 pcm512x->pll_p = P;
853 return 0;
854}
855
856static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai,
857 unsigned long osr_rate,
858 unsigned long pllin_rate)
859{
860 struct snd_soc_component *component = dai->component;
861 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
862 unsigned long dac_rate;
863
864 if (!pcm512x->pll_out)
865 return 0; /* no PLL to bypass, force SCK as DAC input */
866
867 if (pllin_rate % osr_rate)
868 return 0; /* futile, quit early */
869
870 /* run DAC no faster than 6144000 Hz */
871 for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate);
872 dac_rate;
873 dac_rate -= osr_rate) {
874
875 if (pllin_rate / dac_rate > 128)
876 return 0; /* DAC divider would be too big */
877
878 if (!(pllin_rate % dac_rate))
879 return dac_rate;
880
881 dac_rate -= osr_rate;
882 }
883
884 return 0;
885}
886
887static int pcm512x_set_dividers(struct snd_soc_dai *dai,
888 struct snd_pcm_hw_params *params)
889{
890 struct device *dev = dai->dev;
891 struct snd_soc_component *component = dai->component;
892 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
893 unsigned long pllin_rate = 0;
894 unsigned long pll_rate;
895 unsigned long sck_rate;
896 unsigned long mck_rate;
897 unsigned long bclk_rate;
898 unsigned long sample_rate;
899 unsigned long osr_rate;
900 unsigned long dacsrc_rate;
901 int bclk_div;
902 int lrclk_div;
903 int dsp_div;
904 int dac_div;
905 unsigned long dac_rate;
906 int ncp_div;
907 int osr_div;
908 int ret;
909 int idac;
910 int fssp;
911 int gpio;
912
913 if (pcm512x->bclk_ratio > 0) {
914 lrclk_div = pcm512x->bclk_ratio;
915 } else {
916 lrclk_div = snd_soc_params_to_frame_size(params);
917
918 if (lrclk_div == 0) {
919 dev_err(dev, "No LRCLK?\n");
920 return -EINVAL;
921 }
922 }
923
924 if (!pcm512x->pll_out) {
925 sck_rate = clk_get_rate(pcm512x->sclk);
926 bclk_rate = params_rate(params) * lrclk_div;
927 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
928
929 mck_rate = sck_rate;
930 } else {
931 ret = snd_soc_params_to_bclk(params);
932 if (ret < 0) {
933 dev_err(dev, "Failed to find suitable BCLK: %d\n", ret);
934 return ret;
935 }
936 if (ret == 0) {
937 dev_err(dev, "No BCLK?\n");
938 return -EINVAL;
939 }
940 bclk_rate = ret;
941
942 pllin_rate = clk_get_rate(pcm512x->sclk);
943
944 sck_rate = pcm512x_find_sck(dai, bclk_rate);
945 if (!sck_rate)
946 return -EINVAL;
947 pll_rate = 4 * sck_rate;
948
949 ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate);
950 if (ret != 0)
951 return ret;
952
953 ret = regmap_write(pcm512x->regmap,
954 PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1);
955 if (ret != 0) {
956 dev_err(dev, "Failed to write PLL P: %d\n", ret);
957 return ret;
958 }
959
960 ret = regmap_write(pcm512x->regmap,
961 PCM512x_PLL_COEFF_1, pcm512x->pll_j);
962 if (ret != 0) {
963 dev_err(dev, "Failed to write PLL J: %d\n", ret);
964 return ret;
965 }
966
967 ret = regmap_write(pcm512x->regmap,
968 PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8);
969 if (ret != 0) {
970 dev_err(dev, "Failed to write PLL D msb: %d\n", ret);
971 return ret;
972 }
973
974 ret = regmap_write(pcm512x->regmap,
975 PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff);
976 if (ret != 0) {
977 dev_err(dev, "Failed to write PLL D lsb: %d\n", ret);
978 return ret;
979 }
980
981 ret = regmap_write(pcm512x->regmap,
982 PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1);
983 if (ret != 0) {
984 dev_err(dev, "Failed to write PLL R: %d\n", ret);
985 return ret;
986 }
987
988 mck_rate = pcm512x->real_pll;
989
990 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
991 }
992
993 if (bclk_div > 128) {
994 dev_err(dev, "Failed to find BCLK divider\n");
995 return -EINVAL;
996 }
997
998 /* the actual rate */
999 sample_rate = sck_rate / bclk_div / lrclk_div;
1000 osr_rate = 16 * sample_rate;
1001
1002 /* run DSP no faster than 50 MHz */
1003 dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1;
1004
1005 dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate);
1006 if (dac_rate) {
1007 /* the desired clock rate is "compatible" with the pll input
1008 * clock, so use that clock as dac input instead of the pll
1009 * output clock since the pll will introduce jitter and thus
1010 * noise.
1011 */
1012 dev_dbg(dev, "using pll input as dac input\n");
1013 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
1014 PCM512x_SDAC, PCM512x_SDAC_GPIO);
1015 if (ret != 0) {
1016 dev_err(component->dev,
1017 "Failed to set gpio as dacref: %d\n", ret);
1018 return ret;
1019 }
1020
1021 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
1022 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN,
1023 PCM512x_GREF, gpio);
1024 if (ret != 0) {
1025 dev_err(component->dev,
1026 "Failed to set gpio %d as dacin: %d\n",
1027 pcm512x->pll_in, ret);
1028 return ret;
1029 }
1030
1031 dacsrc_rate = pllin_rate;
1032 } else {
1033 /* run DAC no faster than 6144000 Hz */
1034 unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000)
1035 / osr_rate;
1036 unsigned long sck_mul = sck_rate / osr_rate;
1037
1038 for (; dac_mul; dac_mul--) {
1039 if (!(sck_mul % dac_mul))
1040 break;
1041 }
1042 if (!dac_mul) {
1043 dev_err(dev, "Failed to find DAC rate\n");
1044 return -EINVAL;
1045 }
1046
1047 dac_rate = dac_mul * osr_rate;
1048 dev_dbg(dev, "dac_rate %lu sample_rate %lu\n",
1049 dac_rate, sample_rate);
1050
1051 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
1052 PCM512x_SDAC, PCM512x_SDAC_SCK);
1053 if (ret != 0) {
1054 dev_err(component->dev,
1055 "Failed to set sck as dacref: %d\n", ret);
1056 return ret;
1057 }
1058
1059 dacsrc_rate = sck_rate;
1060 }
1061
1062 osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate);
1063 if (osr_div > 128) {
1064 dev_err(dev, "Failed to find OSR divider\n");
1065 return -EINVAL;
1066 }
1067
1068 dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate);
1069 if (dac_div > 128) {
1070 dev_err(dev, "Failed to find DAC divider\n");
1071 return -EINVAL;
1072 }
1073 dac_rate = dacsrc_rate / dac_div;
1074
1075 ncp_div = DIV_ROUND_CLOSEST(dac_rate,
1076 pcm512x_ncp_target(pcm512x, dac_rate));
1077 if (ncp_div > 128 || dac_rate / ncp_div > 2048000) {
1078 /* run NCP no faster than 2048000 Hz, but why? */
1079 ncp_div = DIV_ROUND_UP(dac_rate, 2048000);
1080 if (ncp_div > 128) {
1081 dev_err(dev, "Failed to find NCP divider\n");
1082 return -EINVAL;
1083 }
1084 }
1085
1086 idac = mck_rate / (dsp_div * sample_rate);
1087
1088 ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1);
1089 if (ret != 0) {
1090 dev_err(dev, "Failed to write DSP divider: %d\n", ret);
1091 return ret;
1092 }
1093
1094 ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1);
1095 if (ret != 0) {
1096 dev_err(dev, "Failed to write DAC divider: %d\n", ret);
1097 return ret;
1098 }
1099
1100 ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1);
1101 if (ret != 0) {
1102 dev_err(dev, "Failed to write NCP divider: %d\n", ret);
1103 return ret;
1104 }
1105
1106 ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1);
1107 if (ret != 0) {
1108 dev_err(dev, "Failed to write OSR divider: %d\n", ret);
1109 return ret;
1110 }
1111
1112 ret = regmap_write(pcm512x->regmap,
1113 PCM512x_MASTER_CLKDIV_1, bclk_div - 1);
1114 if (ret != 0) {
1115 dev_err(dev, "Failed to write BCLK divider: %d\n", ret);
1116 return ret;
1117 }
1118
1119 ret = regmap_write(pcm512x->regmap,
1120 PCM512x_MASTER_CLKDIV_2, lrclk_div - 1);
1121 if (ret != 0) {
1122 dev_err(dev, "Failed to write LRCLK divider: %d\n", ret);
1123 return ret;
1124 }
1125
1126 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8);
1127 if (ret != 0) {
1128 dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret);
1129 return ret;
1130 }
1131
1132 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff);
1133 if (ret != 0) {
1134 dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret);
1135 return ret;
1136 }
1137
1138 if (sample_rate <= pcm512x_dac_max(pcm512x, 48000))
1139 fssp = PCM512x_FSSP_48KHZ;
1140 else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000))
1141 fssp = PCM512x_FSSP_96KHZ;
1142 else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000))
1143 fssp = PCM512x_FSSP_192KHZ;
1144 else
1145 fssp = PCM512x_FSSP_384KHZ;
1146 ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE,
1147 PCM512x_FSSP, fssp);
1148 if (ret != 0) {
1149 dev_err(component->dev, "Failed to set fs speed: %d\n", ret);
1150 return ret;
1151 }
1152
1153 dev_dbg(component->dev, "DSP divider %d\n", dsp_div);
1154 dev_dbg(component->dev, "DAC divider %d\n", dac_div);
1155 dev_dbg(component->dev, "NCP divider %d\n", ncp_div);
1156 dev_dbg(component->dev, "OSR divider %d\n", osr_div);
1157 dev_dbg(component->dev, "BCK divider %d\n", bclk_div);
1158 dev_dbg(component->dev, "LRCK divider %d\n", lrclk_div);
1159 dev_dbg(component->dev, "IDAC %d\n", idac);
1160 dev_dbg(component->dev, "1<<FSSP %d\n", 1 << fssp);
1161
1162 return 0;
1163}
1164
1165static int pcm512x_hw_params(struct snd_pcm_substream *substream,
1166 struct snd_pcm_hw_params *params,
1167 struct snd_soc_dai *dai)
1168{
1169 struct snd_soc_component *component = dai->component;
1170 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
1171 int alen;
1172 int gpio;
1173 int ret;
1174
1175 dev_dbg(component->dev, "hw_params %u Hz, %u channels\n",
1176 params_rate(params),
1177 params_channels(params));
1178
1179 switch (params_width(params)) {
1180 case 16:
1181 alen = PCM512x_ALEN_16;
1182 break;
1183 case 20:
1184 alen = PCM512x_ALEN_20;
1185 break;
1186 case 24:
1187 alen = PCM512x_ALEN_24;
1188 break;
1189 case 32:
1190 alen = PCM512x_ALEN_32;
1191 break;
1192 default:
1193 dev_err(component->dev, "Bad frame size: %d\n",
1194 params_width(params));
1195 return -EINVAL;
1196 }
1197
1198 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
1199 PCM512x_ALEN, alen);
1200 if (ret != 0) {
1201 dev_err(component->dev, "Failed to set frame size: %d\n", ret);
1202 return ret;
1203 }
1204
1205 if ((pcm512x->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
1206 SND_SOC_DAIFMT_CBC_CFC) {
1207 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1208 PCM512x_DCAS, 0);
1209 if (ret != 0) {
1210 dev_err(component->dev,
1211 "Failed to enable clock divider autoset: %d\n",
1212 ret);
1213 return ret;
1214 }
1215 goto skip_pll;
1216 }
1217
1218 if (pcm512x->pll_out) {
1219 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11);
1220 if (ret != 0) {
1221 dev_err(component->dev, "Failed to set FLEX_A: %d\n", ret);
1222 return ret;
1223 }
1224
1225 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff);
1226 if (ret != 0) {
1227 dev_err(component->dev, "Failed to set FLEX_B: %d\n", ret);
1228 return ret;
1229 }
1230
1231 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1232 PCM512x_IDFS | PCM512x_IDBK
1233 | PCM512x_IDSK | PCM512x_IDCH
1234 | PCM512x_IDCM | PCM512x_DCAS
1235 | PCM512x_IPLK,
1236 PCM512x_IDFS | PCM512x_IDBK
1237 | PCM512x_IDSK | PCM512x_IDCH
1238 | PCM512x_DCAS);
1239 if (ret != 0) {
1240 dev_err(component->dev,
1241 "Failed to ignore auto-clock failures: %d\n",
1242 ret);
1243 return ret;
1244 }
1245 } else {
1246 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1247 PCM512x_IDFS | PCM512x_IDBK
1248 | PCM512x_IDSK | PCM512x_IDCH
1249 | PCM512x_IDCM | PCM512x_DCAS
1250 | PCM512x_IPLK,
1251 PCM512x_IDFS | PCM512x_IDBK
1252 | PCM512x_IDSK | PCM512x_IDCH
1253 | PCM512x_DCAS | PCM512x_IPLK);
1254 if (ret != 0) {
1255 dev_err(component->dev,
1256 "Failed to ignore auto-clock failures: %d\n",
1257 ret);
1258 return ret;
1259 }
1260
1261 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1262 PCM512x_PLLE, 0);
1263 if (ret != 0) {
1264 dev_err(component->dev, "Failed to disable pll: %d\n", ret);
1265 return ret;
1266 }
1267 }
1268
1269 ret = pcm512x_set_dividers(dai, params);
1270 if (ret != 0)
1271 return ret;
1272
1273 if (pcm512x->pll_out) {
1274 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF,
1275 PCM512x_SREF, PCM512x_SREF_GPIO);
1276 if (ret != 0) {
1277 dev_err(component->dev,
1278 "Failed to set gpio as pllref: %d\n", ret);
1279 return ret;
1280 }
1281
1282 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
1283 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN,
1284 PCM512x_GREF, gpio);
1285 if (ret != 0) {
1286 dev_err(component->dev,
1287 "Failed to set gpio %d as pllin: %d\n",
1288 pcm512x->pll_in, ret);
1289 return ret;
1290 }
1291
1292 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1293 PCM512x_PLLE, PCM512x_PLLE);
1294 if (ret != 0) {
1295 dev_err(component->dev, "Failed to enable pll: %d\n", ret);
1296 return ret;
1297 }
1298
1299 gpio = PCM512x_G1OE << (pcm512x->pll_out - 1);
1300 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN,
1301 gpio, gpio);
1302 if (ret != 0) {
1303 dev_err(component->dev, "Failed to enable gpio %d: %d\n",
1304 pcm512x->pll_out, ret);
1305 return ret;
1306 }
1307
1308 gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1;
1309 ret = regmap_update_bits(pcm512x->regmap, gpio,
1310 PCM512x_GxSL, PCM512x_GxSL_PLLCK);
1311 if (ret != 0) {
1312 dev_err(component->dev, "Failed to output pll on %d: %d\n",
1313 ret, pcm512x->pll_out);
1314 return ret;
1315 }
1316 }
1317
1318 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1319 PCM512x_RQSY, PCM512x_RQSY_HALT);
1320 if (ret != 0) {
1321 dev_err(component->dev, "Failed to halt clocks: %d\n", ret);
1322 return ret;
1323 }
1324
1325 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1326 PCM512x_RQSY, PCM512x_RQSY_RESUME);
1327 if (ret != 0) {
1328 dev_err(component->dev, "Failed to resume clocks: %d\n", ret);
1329 return ret;
1330 }
1331
1332skip_pll:
1333 return 0;
1334}
1335
1336static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1337{
1338 struct snd_soc_component *component = dai->component;
1339 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
1340 int afmt;
1341 int offset = 0;
1342 int clock_output;
1343 int provider_mode;
1344 int ret;
1345
1346 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1347 case SND_SOC_DAIFMT_CBC_CFC:
1348 clock_output = 0;
1349 provider_mode = 0;
1350 break;
1351 case SND_SOC_DAIFMT_CBP_CFP:
1352 clock_output = PCM512x_BCKO | PCM512x_LRKO;
1353 provider_mode = PCM512x_RLRK | PCM512x_RBCK;
1354 break;
1355 case SND_SOC_DAIFMT_CBP_CFC:
1356 clock_output = PCM512x_BCKO;
1357 provider_mode = PCM512x_RBCK;
1358 break;
1359 default:
1360 return -EINVAL;
1361 }
1362
1363 ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG,
1364 PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO,
1365 clock_output);
1366 if (ret != 0) {
1367 dev_err(component->dev, "Failed to enable clock output: %d\n", ret);
1368 return ret;
1369 }
1370
1371 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE,
1372 PCM512x_RLRK | PCM512x_RBCK,
1373 provider_mode);
1374 if (ret != 0) {
1375 dev_err(component->dev, "Failed to enable provider mode: %d\n", ret);
1376 return ret;
1377 }
1378
1379 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1380 case SND_SOC_DAIFMT_I2S:
1381 afmt = PCM512x_AFMT_I2S;
1382 break;
1383 case SND_SOC_DAIFMT_RIGHT_J:
1384 afmt = PCM512x_AFMT_RTJ;
1385 break;
1386 case SND_SOC_DAIFMT_LEFT_J:
1387 afmt = PCM512x_AFMT_LTJ;
1388 break;
1389 case SND_SOC_DAIFMT_DSP_A:
1390 offset = 1;
1391 fallthrough;
1392 case SND_SOC_DAIFMT_DSP_B:
1393 afmt = PCM512x_AFMT_DSP;
1394 break;
1395 default:
1396 dev_err(component->dev, "unsupported DAI format: 0x%x\n",
1397 pcm512x->fmt);
1398 return -EINVAL;
1399 }
1400
1401 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
1402 PCM512x_AFMT, afmt);
1403 if (ret != 0) {
1404 dev_err(component->dev, "Failed to set data format: %d\n", ret);
1405 return ret;
1406 }
1407
1408 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_2,
1409 0xFF, offset);
1410 if (ret != 0) {
1411 dev_err(component->dev, "Failed to set data offset: %d\n", ret);
1412 return ret;
1413 }
1414
1415 pcm512x->fmt = fmt;
1416
1417 return 0;
1418}
1419
1420static int pcm512x_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
1421{
1422 struct snd_soc_component *component = dai->component;
1423 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
1424
1425 if (ratio > 256)
1426 return -EINVAL;
1427
1428 pcm512x->bclk_ratio = ratio;
1429
1430 return 0;
1431}
1432
1433static int pcm512x_mute(struct snd_soc_dai *dai, int mute, int direction)
1434{
1435 struct snd_soc_component *component = dai->component;
1436 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
1437 int ret;
1438 unsigned int mute_det;
1439
1440 mutex_lock(&pcm512x->mutex);
1441
1442 if (mute) {
1443 pcm512x->mute |= 0x1;
1444 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MUTE,
1445 PCM512x_RQML | PCM512x_RQMR,
1446 PCM512x_RQML | PCM512x_RQMR);
1447 if (ret != 0) {
1448 dev_err(component->dev,
1449 "Failed to set digital mute: %d\n", ret);
1450 goto unlock;
1451 }
1452
1453 regmap_read_poll_timeout(pcm512x->regmap,
1454 PCM512x_ANALOG_MUTE_DET,
1455 mute_det, (mute_det & 0x3) == 0,
1456 200, 10000);
1457 } else {
1458 pcm512x->mute &= ~0x1;
1459 ret = pcm512x_update_mute(pcm512x);
1460 if (ret != 0) {
1461 dev_err(component->dev,
1462 "Failed to update digital mute: %d\n", ret);
1463 goto unlock;
1464 }
1465
1466 regmap_read_poll_timeout(pcm512x->regmap,
1467 PCM512x_ANALOG_MUTE_DET,
1468 mute_det,
1469 (mute_det & 0x3)
1470 == ((~pcm512x->mute >> 1) & 0x3),
1471 200, 10000);
1472 }
1473
1474unlock:
1475 mutex_unlock(&pcm512x->mutex);
1476
1477 return ret;
1478}
1479
1480static const struct snd_soc_dai_ops pcm512x_dai_ops = {
1481 .startup = pcm512x_dai_startup,
1482 .hw_params = pcm512x_hw_params,
1483 .set_fmt = pcm512x_set_fmt,
1484 .mute_stream = pcm512x_mute,
1485 .set_bclk_ratio = pcm512x_set_bclk_ratio,
1486 .no_capture_mute = 1,
1487};
1488
1489static struct snd_soc_dai_driver pcm512x_dai = {
1490 .name = "pcm512x-hifi",
1491 .playback = {
1492 .stream_name = "Playback",
1493 .channels_min = 2,
1494 .channels_max = 2,
1495 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1496 .rate_min = 8000,
1497 .rate_max = 384000,
1498 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1499 SNDRV_PCM_FMTBIT_S24_LE |
1500 SNDRV_PCM_FMTBIT_S32_LE
1501 },
1502 .ops = &pcm512x_dai_ops,
1503};
1504
1505static const struct snd_soc_component_driver pcm512x_component_driver = {
1506 .set_bias_level = pcm512x_set_bias_level,
1507 .controls = pcm512x_controls,
1508 .num_controls = ARRAY_SIZE(pcm512x_controls),
1509 .dapm_widgets = pcm512x_dapm_widgets,
1510 .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets),
1511 .dapm_routes = pcm512x_dapm_routes,
1512 .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes),
1513 .use_pmdown_time = 1,
1514 .endianness = 1,
1515};
1516
1517static const struct regmap_range_cfg pcm512x_range = {
1518 .name = "Pages", .range_min = PCM512x_VIRT_BASE,
1519 .range_max = PCM512x_MAX_REGISTER,
1520 .selector_reg = PCM512x_PAGE,
1521 .selector_mask = 0xff,
1522 .window_start = 0, .window_len = 0x100,
1523};
1524
1525const struct regmap_config pcm512x_regmap = {
1526 .reg_bits = 8,
1527 .val_bits = 8,
1528
1529 .readable_reg = pcm512x_readable,
1530 .volatile_reg = pcm512x_volatile,
1531
1532 .ranges = &pcm512x_range,
1533 .num_ranges = 1,
1534
1535 .max_register = PCM512x_MAX_REGISTER,
1536 .reg_defaults = pcm512x_reg_defaults,
1537 .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults),
1538 .cache_type = REGCACHE_RBTREE,
1539};
1540EXPORT_SYMBOL_GPL(pcm512x_regmap);
1541
1542int pcm512x_probe(struct device *dev, struct regmap *regmap)
1543{
1544 struct pcm512x_priv *pcm512x;
1545 int i, ret;
1546
1547 pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL);
1548 if (!pcm512x)
1549 return -ENOMEM;
1550
1551 mutex_init(&pcm512x->mutex);
1552
1553 dev_set_drvdata(dev, pcm512x);
1554 pcm512x->regmap = regmap;
1555
1556 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++)
1557 pcm512x->supplies[i].supply = pcm512x_supply_names[i];
1558
1559 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies),
1560 pcm512x->supplies);
1561 if (ret != 0) {
1562 dev_err(dev, "Failed to get supplies: %d\n", ret);
1563 return ret;
1564 }
1565
1566 pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0;
1567 pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1;
1568 pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2;
1569
1570 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) {
1571 ret = devm_regulator_register_notifier(
1572 pcm512x->supplies[i].consumer,
1573 &pcm512x->supply_nb[i]);
1574 if (ret != 0) {
1575 dev_err(dev,
1576 "Failed to register regulator notifier: %d\n",
1577 ret);
1578 }
1579 }
1580
1581 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1582 pcm512x->supplies);
1583 if (ret != 0) {
1584 dev_err(dev, "Failed to enable supplies: %d\n", ret);
1585 return ret;
1586 }
1587
1588 /* Reset the device, verifying I/O in the process for I2C */
1589 ret = regmap_write(regmap, PCM512x_RESET,
1590 PCM512x_RSTM | PCM512x_RSTR);
1591 if (ret != 0) {
1592 dev_err(dev, "Failed to reset device: %d\n", ret);
1593 goto err;
1594 }
1595
1596 ret = regmap_write(regmap, PCM512x_RESET, 0);
1597 if (ret != 0) {
1598 dev_err(dev, "Failed to reset device: %d\n", ret);
1599 goto err;
1600 }
1601
1602 pcm512x->sclk = devm_clk_get(dev, NULL);
1603 if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) {
1604 ret = -EPROBE_DEFER;
1605 goto err;
1606 }
1607 if (!IS_ERR(pcm512x->sclk)) {
1608 ret = clk_prepare_enable(pcm512x->sclk);
1609 if (ret != 0) {
1610 dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1611 goto err;
1612 }
1613 }
1614
1615 /* Default to standby mode */
1616 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1617 PCM512x_RQST, PCM512x_RQST);
1618 if (ret != 0) {
1619 dev_err(dev, "Failed to request standby: %d\n",
1620 ret);
1621 goto err_clk;
1622 }
1623
1624 pm_runtime_set_active(dev);
1625 pm_runtime_enable(dev);
1626 pm_runtime_idle(dev);
1627
1628#ifdef CONFIG_OF
1629 if (dev->of_node) {
1630 const struct device_node *np = dev->of_node;
1631 u32 val;
1632
1633 if (of_property_read_u32(np, "pll-in", &val) >= 0) {
1634 if (val > 6) {
1635 dev_err(dev, "Invalid pll-in\n");
1636 ret = -EINVAL;
1637 goto err_pm;
1638 }
1639 pcm512x->pll_in = val;
1640 }
1641
1642 if (of_property_read_u32(np, "pll-out", &val) >= 0) {
1643 if (val > 6) {
1644 dev_err(dev, "Invalid pll-out\n");
1645 ret = -EINVAL;
1646 goto err_pm;
1647 }
1648 pcm512x->pll_out = val;
1649 }
1650
1651 if (!pcm512x->pll_in != !pcm512x->pll_out) {
1652 dev_err(dev,
1653 "Error: both pll-in and pll-out, or none\n");
1654 ret = -EINVAL;
1655 goto err_pm;
1656 }
1657 if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) {
1658 dev_err(dev, "Error: pll-in == pll-out\n");
1659 ret = -EINVAL;
1660 goto err_pm;
1661 }
1662 }
1663#endif
1664
1665 ret = devm_snd_soc_register_component(dev, &pcm512x_component_driver,
1666 &pcm512x_dai, 1);
1667 if (ret != 0) {
1668 dev_err(dev, "Failed to register CODEC: %d\n", ret);
1669 goto err_pm;
1670 }
1671
1672 return 0;
1673
1674err_pm:
1675 pm_runtime_disable(dev);
1676err_clk:
1677 if (!IS_ERR(pcm512x->sclk))
1678 clk_disable_unprepare(pcm512x->sclk);
1679err:
1680 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1681 pcm512x->supplies);
1682 return ret;
1683}
1684EXPORT_SYMBOL_GPL(pcm512x_probe);
1685
1686void pcm512x_remove(struct device *dev)
1687{
1688 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1689
1690 pm_runtime_disable(dev);
1691 if (!IS_ERR(pcm512x->sclk))
1692 clk_disable_unprepare(pcm512x->sclk);
1693 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1694 pcm512x->supplies);
1695}
1696EXPORT_SYMBOL_GPL(pcm512x_remove);
1697
1698#ifdef CONFIG_PM
1699static int pcm512x_suspend(struct device *dev)
1700{
1701 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1702 int ret;
1703
1704 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1705 PCM512x_RQPD, PCM512x_RQPD);
1706 if (ret != 0) {
1707 dev_err(dev, "Failed to request power down: %d\n", ret);
1708 return ret;
1709 }
1710
1711 ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1712 pcm512x->supplies);
1713 if (ret != 0) {
1714 dev_err(dev, "Failed to disable supplies: %d\n", ret);
1715 return ret;
1716 }
1717
1718 if (!IS_ERR(pcm512x->sclk))
1719 clk_disable_unprepare(pcm512x->sclk);
1720
1721 return 0;
1722}
1723
1724static int pcm512x_resume(struct device *dev)
1725{
1726 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1727 int ret;
1728
1729 if (!IS_ERR(pcm512x->sclk)) {
1730 ret = clk_prepare_enable(pcm512x->sclk);
1731 if (ret != 0) {
1732 dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1733 return ret;
1734 }
1735 }
1736
1737 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1738 pcm512x->supplies);
1739 if (ret != 0) {
1740 dev_err(dev, "Failed to enable supplies: %d\n", ret);
1741 return ret;
1742 }
1743
1744 regcache_cache_only(pcm512x->regmap, false);
1745 ret = regcache_sync(pcm512x->regmap);
1746 if (ret != 0) {
1747 dev_err(dev, "Failed to sync cache: %d\n", ret);
1748 return ret;
1749 }
1750
1751 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1752 PCM512x_RQPD, 0);
1753 if (ret != 0) {
1754 dev_err(dev, "Failed to remove power down: %d\n", ret);
1755 return ret;
1756 }
1757
1758 return 0;
1759}
1760#endif
1761
1762const struct dev_pm_ops pcm512x_pm_ops = {
1763 SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL)
1764};
1765EXPORT_SYMBOL_GPL(pcm512x_pm_ops);
1766
1767MODULE_DESCRIPTION("ASoC PCM512x codec driver");
1768MODULE_AUTHOR("Mark Brown <broonie@kernel.org>");
1769MODULE_LICENSE("GPL v2");