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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * max98927.c -- MAX98927 ALSA Soc Audio driver
4 *
5 * Copyright (C) 2016-2017 Maxim Integrated Products
6 * Author: Ryan Lee <ryans.lee@maximintegrated.com>
7 */
8
9#include <linux/acpi.h>
10#include <linux/i2c.h>
11#include <linux/module.h>
12#include <linux/regmap.h>
13#include <linux/slab.h>
14#include <linux/cdev.h>
15#include <sound/pcm.h>
16#include <sound/pcm_params.h>
17#include <sound/soc.h>
18#include <linux/gpio/consumer.h>
19#include <sound/tlv.h>
20#include "max98927.h"
21
22static struct reg_default max98927_reg[] = {
23 {MAX98927_R0001_INT_RAW1, 0x00},
24 {MAX98927_R0002_INT_RAW2, 0x00},
25 {MAX98927_R0003_INT_RAW3, 0x00},
26 {MAX98927_R0004_INT_STATE1, 0x00},
27 {MAX98927_R0005_INT_STATE2, 0x00},
28 {MAX98927_R0006_INT_STATE3, 0x00},
29 {MAX98927_R0007_INT_FLAG1, 0x00},
30 {MAX98927_R0008_INT_FLAG2, 0x00},
31 {MAX98927_R0009_INT_FLAG3, 0x00},
32 {MAX98927_R000A_INT_EN1, 0x00},
33 {MAX98927_R000B_INT_EN2, 0x00},
34 {MAX98927_R000C_INT_EN3, 0x00},
35 {MAX98927_R000D_INT_FLAG_CLR1, 0x00},
36 {MAX98927_R000E_INT_FLAG_CLR2, 0x00},
37 {MAX98927_R000F_INT_FLAG_CLR3, 0x00},
38 {MAX98927_R0010_IRQ_CTRL, 0x00},
39 {MAX98927_R0011_CLK_MON, 0x00},
40 {MAX98927_R0012_WDOG_CTRL, 0x00},
41 {MAX98927_R0013_WDOG_RST, 0x00},
42 {MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH, 0x75},
43 {MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH, 0x8c},
44 {MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS, 0x08},
45 {MAX98927_R0017_PIN_CFG, 0x55},
46 {MAX98927_R0018_PCM_RX_EN_A, 0x00},
47 {MAX98927_R0019_PCM_RX_EN_B, 0x00},
48 {MAX98927_R001A_PCM_TX_EN_A, 0x00},
49 {MAX98927_R001B_PCM_TX_EN_B, 0x00},
50 {MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0x00},
51 {MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0x00},
52 {MAX98927_R001E_PCM_TX_CH_SRC_A, 0x00},
53 {MAX98927_R001F_PCM_TX_CH_SRC_B, 0x00},
54 {MAX98927_R0020_PCM_MODE_CFG, 0x40},
55 {MAX98927_R0021_PCM_MASTER_MODE, 0x00},
56 {MAX98927_R0022_PCM_CLK_SETUP, 0x22},
57 {MAX98927_R0023_PCM_SR_SETUP1, 0x00},
58 {MAX98927_R0024_PCM_SR_SETUP2, 0x00},
59 {MAX98927_R0025_PCM_TO_SPK_MONOMIX_A, 0x00},
60 {MAX98927_R0026_PCM_TO_SPK_MONOMIX_B, 0x00},
61 {MAX98927_R0027_ICC_RX_EN_A, 0x00},
62 {MAX98927_R0028_ICC_RX_EN_B, 0x00},
63 {MAX98927_R002B_ICC_TX_EN_A, 0x00},
64 {MAX98927_R002C_ICC_TX_EN_B, 0x00},
65 {MAX98927_R002E_ICC_HIZ_MANUAL_MODE, 0x00},
66 {MAX98927_R002F_ICC_TX_HIZ_EN_A, 0x00},
67 {MAX98927_R0030_ICC_TX_HIZ_EN_B, 0x00},
68 {MAX98927_R0031_ICC_LNK_EN, 0x00},
69 {MAX98927_R0032_PDM_TX_EN, 0x00},
70 {MAX98927_R0033_PDM_TX_HIZ_CTRL, 0x00},
71 {MAX98927_R0034_PDM_TX_CTRL, 0x00},
72 {MAX98927_R0035_PDM_RX_CTRL, 0x00},
73 {MAX98927_R0036_AMP_VOL_CTRL, 0x00},
74 {MAX98927_R0037_AMP_DSP_CFG, 0x02},
75 {MAX98927_R0038_TONE_GEN_DC_CFG, 0x00},
76 {MAX98927_R0039_DRE_CTRL, 0x01},
77 {MAX98927_R003A_AMP_EN, 0x00},
78 {MAX98927_R003B_SPK_SRC_SEL, 0x00},
79 {MAX98927_R003C_SPK_GAIN, 0x00},
80 {MAX98927_R003D_SSM_CFG, 0x04},
81 {MAX98927_R003E_MEAS_EN, 0x00},
82 {MAX98927_R003F_MEAS_DSP_CFG, 0x04},
83 {MAX98927_R0040_BOOST_CTRL0, 0x00},
84 {MAX98927_R0041_BOOST_CTRL3, 0x00},
85 {MAX98927_R0042_BOOST_CTRL1, 0x00},
86 {MAX98927_R0043_MEAS_ADC_CFG, 0x00},
87 {MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x01},
88 {MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x00},
89 {MAX98927_R0046_ADC_CH0_DIVIDE, 0x00},
90 {MAX98927_R0047_ADC_CH1_DIVIDE, 0x00},
91 {MAX98927_R0048_ADC_CH2_DIVIDE, 0x00},
92 {MAX98927_R0049_ADC_CH0_FILT_CFG, 0x00},
93 {MAX98927_R004A_ADC_CH1_FILT_CFG, 0x00},
94 {MAX98927_R004B_ADC_CH2_FILT_CFG, 0x00},
95 {MAX98927_R004C_MEAS_ADC_CH0_READ, 0x00},
96 {MAX98927_R004D_MEAS_ADC_CH1_READ, 0x00},
97 {MAX98927_R004E_MEAS_ADC_CH2_READ, 0x00},
98 {MAX98927_R0051_BROWNOUT_STATUS, 0x00},
99 {MAX98927_R0052_BROWNOUT_EN, 0x00},
100 {MAX98927_R0053_BROWNOUT_INFINITE_HOLD, 0x00},
101 {MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR, 0x00},
102 {MAX98927_R0055_BROWNOUT_LVL_HOLD, 0x00},
103 {MAX98927_R005A_BROWNOUT_LVL1_THRESH, 0x00},
104 {MAX98927_R005B_BROWNOUT_LVL2_THRESH, 0x00},
105 {MAX98927_R005C_BROWNOUT_LVL3_THRESH, 0x00},
106 {MAX98927_R005D_BROWNOUT_LVL4_THRESH, 0x00},
107 {MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS, 0x00},
108 {MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL, 0x00},
109 {MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL, 0x00},
110 {MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE, 0x00},
111 {MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT, 0x00},
112 {MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1, 0x00},
113 {MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2, 0x00},
114 {MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3, 0x00},
115 {MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT, 0x00},
116 {MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1, 0x00},
117 {MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2, 0x00},
118 {MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3, 0x00},
119 {MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT, 0x00},
120 {MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1, 0x00},
121 {MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2, 0x00},
122 {MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3, 0x00},
123 {MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT, 0x00},
124 {MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1, 0x00},
125 {MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2, 0x00},
126 {MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3, 0x00},
127 {MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM, 0x00},
128 {MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY, 0x00},
129 {MAX98927_R0084_ENV_TRACK_REL_RATE, 0x00},
130 {MAX98927_R0085_ENV_TRACK_HOLD_RATE, 0x00},
131 {MAX98927_R0086_ENV_TRACK_CTRL, 0x00},
132 {MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ, 0x00},
133 {MAX98927_R00FF_GLOBAL_SHDN, 0x00},
134 {MAX98927_R0100_SOFT_RESET, 0x00},
135 {MAX98927_R01FF_REV_ID, 0x40},
136};
137
138static int max98927_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
139{
140 struct snd_soc_component *component = codec_dai->component;
141 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
142 unsigned int mode = 0;
143 unsigned int format = 0;
144 bool use_pdm = false;
145 unsigned int invert = 0;
146
147 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
148
149 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
150 case SND_SOC_DAIFMT_CBC_CFC:
151 max98927->provider = false;
152 mode = MAX98927_PCM_MASTER_MODE_SLAVE;
153 break;
154 case SND_SOC_DAIFMT_CBP_CFP:
155 max98927->provider = true;
156 mode = MAX98927_PCM_MASTER_MODE_MASTER;
157 break;
158 default:
159 dev_err(component->dev, "DAI clock mode unsupported\n");
160 return -EINVAL;
161 }
162
163 regmap_update_bits(max98927->regmap, MAX98927_R0021_PCM_MASTER_MODE,
164 MAX98927_PCM_MASTER_MODE_MASK, mode);
165
166 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
167 case SND_SOC_DAIFMT_NB_NF:
168 break;
169 case SND_SOC_DAIFMT_IB_NF:
170 invert = MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE;
171 break;
172 default:
173 dev_err(component->dev, "DAI invert mode unsupported\n");
174 return -EINVAL;
175 }
176
177 regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG,
178 MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE, invert);
179
180 /* interface format */
181 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
182 case SND_SOC_DAIFMT_I2S:
183 format = MAX98927_PCM_FORMAT_I2S;
184 break;
185 case SND_SOC_DAIFMT_LEFT_J:
186 format = MAX98927_PCM_FORMAT_LJ;
187 break;
188 case SND_SOC_DAIFMT_DSP_A:
189 format = MAX98927_PCM_FORMAT_TDM_MODE1;
190 break;
191 case SND_SOC_DAIFMT_DSP_B:
192 format = MAX98927_PCM_FORMAT_TDM_MODE0;
193 break;
194 case SND_SOC_DAIFMT_PDM:
195 use_pdm = true;
196 break;
197 default:
198 return -EINVAL;
199 }
200 max98927->iface = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
201
202 if (!use_pdm) {
203 /* pcm channel configuration */
204 regmap_update_bits(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A,
205 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN,
206 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN);
207
208 regmap_update_bits(max98927->regmap,
209 MAX98927_R0020_PCM_MODE_CFG,
210 MAX98927_PCM_MODE_CFG_FORMAT_MASK,
211 format << MAX98927_PCM_MODE_CFG_FORMAT_SHIFT);
212
213 regmap_update_bits(max98927->regmap, MAX98927_R003B_SPK_SRC_SEL,
214 MAX98927_SPK_SRC_MASK, 0);
215
216 regmap_update_bits(max98927->regmap, MAX98927_R0035_PDM_RX_CTRL,
217 MAX98927_PDM_RX_EN_MASK, 0);
218 } else {
219 /* pdm channel configuration */
220 regmap_update_bits(max98927->regmap, MAX98927_R0035_PDM_RX_CTRL,
221 MAX98927_PDM_RX_EN_MASK, 1);
222
223 regmap_update_bits(max98927->regmap, MAX98927_R003B_SPK_SRC_SEL,
224 MAX98927_SPK_SRC_MASK, 3);
225
226 regmap_update_bits(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A,
227 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN,
228 0);
229 }
230 return 0;
231}
232
233/* codec MCLK rate in master mode */
234static const int rate_table[] = {
235 5644800, 6000000, 6144000, 6500000,
236 9600000, 11289600, 12000000, 12288000,
237 13000000, 19200000,
238};
239
240/* BCLKs per LRCLK */
241static const int bclk_sel_table[] = {
242 32, 48, 64, 96, 128, 192, 256, 384, 512,
243};
244
245static int max98927_get_bclk_sel(int bclk)
246{
247 int i;
248 /* match BCLKs per LRCLK */
249 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
250 if (bclk_sel_table[i] == bclk)
251 return i + 2;
252 }
253 return 0;
254}
255static int max98927_set_clock(struct max98927_priv *max98927,
256 struct snd_pcm_hw_params *params)
257{
258 struct snd_soc_component *component = max98927->component;
259 /* BCLK/LRCLK ratio calculation */
260 int blr_clk_ratio = params_channels(params) * max98927->ch_size;
261 int value;
262
263 if (max98927->provider) {
264 int i;
265 /* match rate to closest value */
266 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
267 if (rate_table[i] >= max98927->sysclk)
268 break;
269 }
270 if (i == ARRAY_SIZE(rate_table)) {
271 dev_err(component->dev, "failed to find proper clock rate.\n");
272 return -EINVAL;
273 }
274 regmap_update_bits(max98927->regmap,
275 MAX98927_R0021_PCM_MASTER_MODE,
276 MAX98927_PCM_MASTER_MODE_MCLK_MASK,
277 i << MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT);
278 }
279
280 if (!max98927->tdm_mode) {
281 /* BCLK configuration */
282 value = max98927_get_bclk_sel(blr_clk_ratio);
283 if (!value) {
284 dev_err(component->dev, "format unsupported %d\n",
285 params_format(params));
286 return -EINVAL;
287 }
288
289 regmap_update_bits(max98927->regmap,
290 MAX98927_R0022_PCM_CLK_SETUP,
291 MAX98927_PCM_CLK_SETUP_BSEL_MASK, value);
292 }
293 return 0;
294}
295
296static int max98927_dai_hw_params(struct snd_pcm_substream *substream,
297 struct snd_pcm_hw_params *params,
298 struct snd_soc_dai *dai)
299{
300 struct snd_soc_component *component = dai->component;
301 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
302 unsigned int sampling_rate = 0;
303 unsigned int chan_sz = 0;
304
305 /* pcm mode configuration */
306 switch (snd_pcm_format_width(params_format(params))) {
307 case 16:
308 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
309 break;
310 case 24:
311 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
312 break;
313 case 32:
314 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
315 break;
316 default:
317 dev_err(component->dev, "format unsupported %d\n",
318 params_format(params));
319 goto err;
320 }
321
322 max98927->ch_size = snd_pcm_format_width(params_format(params));
323
324 regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG,
325 MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
326
327 dev_dbg(component->dev, "format supported %d",
328 params_format(params));
329
330 /* sampling rate configuration */
331 switch (params_rate(params)) {
332 case 8000:
333 sampling_rate = MAX98927_PCM_SR_SET1_SR_8000;
334 break;
335 case 11025:
336 sampling_rate = MAX98927_PCM_SR_SET1_SR_11025;
337 break;
338 case 12000:
339 sampling_rate = MAX98927_PCM_SR_SET1_SR_12000;
340 break;
341 case 16000:
342 sampling_rate = MAX98927_PCM_SR_SET1_SR_16000;
343 break;
344 case 22050:
345 sampling_rate = MAX98927_PCM_SR_SET1_SR_22050;
346 break;
347 case 24000:
348 sampling_rate = MAX98927_PCM_SR_SET1_SR_24000;
349 break;
350 case 32000:
351 sampling_rate = MAX98927_PCM_SR_SET1_SR_32000;
352 break;
353 case 44100:
354 sampling_rate = MAX98927_PCM_SR_SET1_SR_44100;
355 break;
356 case 48000:
357 sampling_rate = MAX98927_PCM_SR_SET1_SR_48000;
358 break;
359 default:
360 dev_err(component->dev, "rate %d not supported\n",
361 params_rate(params));
362 goto err;
363 }
364 /* set DAI_SR to correct LRCLK frequency */
365 regmap_update_bits(max98927->regmap, MAX98927_R0023_PCM_SR_SETUP1,
366 MAX98927_PCM_SR_SET1_SR_MASK, sampling_rate);
367 regmap_update_bits(max98927->regmap, MAX98927_R0024_PCM_SR_SETUP2,
368 MAX98927_PCM_SR_SET2_SR_MASK,
369 sampling_rate << MAX98927_PCM_SR_SET2_SR_SHIFT);
370
371 /* set sampling rate of IV */
372 if (max98927->interleave_mode &&
373 sampling_rate > MAX98927_PCM_SR_SET1_SR_16000)
374 regmap_update_bits(max98927->regmap,
375 MAX98927_R0024_PCM_SR_SETUP2,
376 MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
377 sampling_rate - 3);
378 else
379 regmap_update_bits(max98927->regmap,
380 MAX98927_R0024_PCM_SR_SETUP2,
381 MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
382 sampling_rate);
383 return max98927_set_clock(max98927, params);
384err:
385 return -EINVAL;
386}
387
388static int max98927_dai_tdm_slot(struct snd_soc_dai *dai,
389 unsigned int tx_mask, unsigned int rx_mask,
390 int slots, int slot_width)
391{
392 struct snd_soc_component *component = dai->component;
393 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
394 int bsel = 0;
395 unsigned int chan_sz = 0;
396
397 max98927->tdm_mode = true;
398
399 /* BCLK configuration */
400 bsel = max98927_get_bclk_sel(slots * slot_width);
401 if (bsel == 0) {
402 dev_err(component->dev, "BCLK %d not supported\n",
403 slots * slot_width);
404 return -EINVAL;
405 }
406
407 regmap_update_bits(max98927->regmap, MAX98927_R0022_PCM_CLK_SETUP,
408 MAX98927_PCM_CLK_SETUP_BSEL_MASK, bsel);
409
410 /* Channel size configuration */
411 switch (slot_width) {
412 case 16:
413 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
414 break;
415 case 24:
416 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
417 break;
418 case 32:
419 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
420 break;
421 default:
422 dev_err(component->dev, "format unsupported %d\n",
423 slot_width);
424 return -EINVAL;
425 }
426
427 regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG,
428 MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
429
430 /* Rx slot configuration */
431 regmap_write(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A,
432 rx_mask & 0xFF);
433 regmap_write(max98927->regmap, MAX98927_R0019_PCM_RX_EN_B,
434 (rx_mask & 0xFF00) >> 8);
435
436 /* Tx slot configuration */
437 regmap_write(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A,
438 tx_mask & 0xFF);
439 regmap_write(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B,
440 (tx_mask & 0xFF00) >> 8);
441
442 /* Tx slot Hi-Z configuration */
443 regmap_write(max98927->regmap, MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
444 ~tx_mask & 0xFF);
445 regmap_write(max98927->regmap, MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
446 (~tx_mask & 0xFF00) >> 8);
447
448 return 0;
449}
450
451#define MAX98927_RATES SNDRV_PCM_RATE_8000_48000
452
453#define MAX98927_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
454 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
455
456static int max98927_dai_set_sysclk(struct snd_soc_dai *dai,
457 int clk_id, unsigned int freq, int dir)
458{
459 struct snd_soc_component *component = dai->component;
460 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
461
462 max98927->sysclk = freq;
463 return 0;
464}
465
466static const struct snd_soc_dai_ops max98927_dai_ops = {
467 .set_sysclk = max98927_dai_set_sysclk,
468 .set_fmt = max98927_dai_set_fmt,
469 .hw_params = max98927_dai_hw_params,
470 .set_tdm_slot = max98927_dai_tdm_slot,
471};
472
473static int max98927_dac_event(struct snd_soc_dapm_widget *w,
474 struct snd_kcontrol *kcontrol, int event)
475{
476 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
477 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
478
479 switch (event) {
480 case SND_SOC_DAPM_PRE_PMU:
481 max98927->tdm_mode = false;
482 break;
483 case SND_SOC_DAPM_POST_PMU:
484 regmap_update_bits(max98927->regmap, MAX98927_R003A_AMP_EN,
485 MAX98927_AMP_EN_MASK, 1);
486 regmap_update_bits(max98927->regmap, MAX98927_R00FF_GLOBAL_SHDN,
487 MAX98927_GLOBAL_EN_MASK, 1);
488 break;
489 case SND_SOC_DAPM_POST_PMD:
490 regmap_update_bits(max98927->regmap, MAX98927_R00FF_GLOBAL_SHDN,
491 MAX98927_GLOBAL_EN_MASK, 0);
492 regmap_update_bits(max98927->regmap, MAX98927_R003A_AMP_EN,
493 MAX98927_AMP_EN_MASK, 0);
494 break;
495 default:
496 return 0;
497 }
498 return 0;
499}
500
501static const char * const max98927_switch_text[] = {
502 "Left", "Right", "LeftRight"};
503
504static const struct soc_enum dai_sel_enum =
505 SOC_ENUM_SINGLE(MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
506 MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT, 3,
507 max98927_switch_text);
508
509static const struct snd_kcontrol_new max98927_dai_controls =
510 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
511
512static const struct snd_kcontrol_new max98927_vi_control =
513 SOC_DAPM_SINGLE("Switch", MAX98927_R003F_MEAS_DSP_CFG, 2, 1, 0);
514
515static const struct snd_soc_dapm_widget max98927_dapm_widgets[] = {
516 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", MAX98927_R003A_AMP_EN,
517 0, 0, max98927_dac_event,
518 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
519 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
520 &max98927_dai_controls),
521 SND_SOC_DAPM_OUTPUT("BE_OUT"),
522 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
523 MAX98927_R003E_MEAS_EN, 0, 0),
524 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
525 MAX98927_R003E_MEAS_EN, 1, 0),
526 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
527 &max98927_vi_control),
528 SND_SOC_DAPM_SIGGEN("VMON"),
529 SND_SOC_DAPM_SIGGEN("IMON"),
530};
531
532static DECLARE_TLV_DB_SCALE(max98927_spk_tlv, 300, 300, 0);
533static DECLARE_TLV_DB_SCALE(max98927_digital_tlv, -1600, 25, 0);
534
535static bool max98927_readable_register(struct device *dev, unsigned int reg)
536{
537 switch (reg) {
538 case MAX98927_R0001_INT_RAW1 ... MAX98927_R0028_ICC_RX_EN_B:
539 case MAX98927_R002B_ICC_TX_EN_A ... MAX98927_R002C_ICC_TX_EN_B:
540 case MAX98927_R002E_ICC_HIZ_MANUAL_MODE
541 ... MAX98927_R004E_MEAS_ADC_CH2_READ:
542 case MAX98927_R0051_BROWNOUT_STATUS
543 ... MAX98927_R0055_BROWNOUT_LVL_HOLD:
544 case MAX98927_R005A_BROWNOUT_LVL1_THRESH
545 ... MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE:
546 case MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT
547 ... MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
548 case MAX98927_R00FF_GLOBAL_SHDN:
549 case MAX98927_R0100_SOFT_RESET:
550 case MAX98927_R01FF_REV_ID:
551 return true;
552 default:
553 return false;
554 }
555};
556
557static bool max98927_volatile_reg(struct device *dev, unsigned int reg)
558{
559 switch (reg) {
560 case MAX98927_R0001_INT_RAW1 ... MAX98927_R0009_INT_FLAG3:
561 case MAX98927_R004C_MEAS_ADC_CH0_READ:
562 case MAX98927_R004D_MEAS_ADC_CH1_READ:
563 case MAX98927_R004E_MEAS_ADC_CH2_READ:
564 case MAX98927_R0051_BROWNOUT_STATUS:
565 case MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
566 case MAX98927_R01FF_REV_ID:
567 case MAX98927_R0100_SOFT_RESET:
568 return true;
569 default:
570 return false;
571 }
572}
573
574static const char * const max98927_boost_voltage_text[] = {
575 "6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V",
576 "7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V",
577 "8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V",
578 "9.5V", "9.625V", "9.75V", "9.875V", "10V"
579};
580
581static SOC_ENUM_SINGLE_DECL(max98927_boost_voltage,
582 MAX98927_R0040_BOOST_CTRL0, 0,
583 max98927_boost_voltage_text);
584
585static const char * const max98927_current_limit_text[] = {
586 "1.00A", "1.10A", "1.20A", "1.30A", "1.40A", "1.50A", "1.60A", "1.70A",
587 "1.80A", "1.90A", "2.00A", "2.10A", "2.20A", "2.30A", "2.40A", "2.50A",
588 "2.60A", "2.70A", "2.80A", "2.90A", "3.00A", "3.10A", "3.20A", "3.30A",
589 "3.40A", "3.50A", "3.60A", "3.70A", "3.80A", "3.90A", "4.00A", "4.10A"
590};
591
592static SOC_ENUM_SINGLE_DECL(max98927_current_limit,
593 MAX98927_R0042_BOOST_CTRL1, 1,
594 max98927_current_limit_text);
595
596static const struct snd_kcontrol_new max98927_snd_controls[] = {
597 SOC_SINGLE_TLV("Speaker Volume", MAX98927_R003C_SPK_GAIN, 0, 6, 0,
598 max98927_spk_tlv),
599 SOC_SINGLE_TLV("Digital Volume", MAX98927_R0036_AMP_VOL_CTRL,
600 0, (1 << MAX98927_AMP_VOL_WIDTH) - 1, 0,
601 max98927_digital_tlv),
602 SOC_SINGLE("Amp DSP Switch", MAX98927_R0052_BROWNOUT_EN,
603 MAX98927_BROWNOUT_DSP_SHIFT, 1, 0),
604 SOC_SINGLE("Ramp Switch", MAX98927_R0037_AMP_DSP_CFG,
605 MAX98927_AMP_DSP_CFG_RMP_SHIFT, 1, 0),
606 SOC_SINGLE("DRE Switch", MAX98927_R0039_DRE_CTRL, MAX98927_DRE_EN_SHIFT,
607 1, 0),
608 SOC_SINGLE("Volume Location Switch", MAX98927_R0036_AMP_VOL_CTRL,
609 MAX98927_AMP_VOL_SEL_SHIFT, 1, 0),
610 SOC_ENUM("Boost Output Voltage", max98927_boost_voltage),
611 SOC_ENUM("Current Limit", max98927_current_limit),
612};
613
614static const struct snd_soc_dapm_route max98927_audio_map[] = {
615 /* Plabyack */
616 {"DAI Sel Mux", "Left", "Amp Enable"},
617 {"DAI Sel Mux", "Right", "Amp Enable"},
618 {"DAI Sel Mux", "LeftRight", "Amp Enable"},
619 {"BE_OUT", NULL, "DAI Sel Mux"},
620 /* Capture */
621 { "VI Sense", "Switch", "VMON" },
622 { "VI Sense", "Switch", "IMON" },
623 { "Voltage Sense", NULL, "VI Sense" },
624 { "Current Sense", NULL, "VI Sense" },
625};
626
627static struct snd_soc_dai_driver max98927_dai[] = {
628 {
629 .name = "max98927-aif1",
630 .playback = {
631 .stream_name = "HiFi Playback",
632 .channels_min = 1,
633 .channels_max = 2,
634 .rates = MAX98927_RATES,
635 .formats = MAX98927_FORMATS,
636 },
637 .capture = {
638 .stream_name = "HiFi Capture",
639 .channels_min = 1,
640 .channels_max = 2,
641 .rates = MAX98927_RATES,
642 .formats = MAX98927_FORMATS,
643 },
644 .ops = &max98927_dai_ops,
645 }
646};
647
648static int max98927_probe(struct snd_soc_component *component)
649{
650 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
651
652 max98927->component = component;
653
654 /* Software Reset */
655 regmap_write(max98927->regmap, MAX98927_R0100_SOFT_RESET,
656 MAX98927_SOFT_RESET);
657
658 /* IV default slot configuration */
659 regmap_write(max98927->regmap, MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0xFF);
660 regmap_write(max98927->regmap, MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0xFF);
661 regmap_write(max98927->regmap, MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
662 0x80);
663 regmap_write(max98927->regmap, MAX98927_R0026_PCM_TO_SPK_MONOMIX_B,
664 0x1);
665 /* Set inital volume (+13dB) */
666 regmap_write(max98927->regmap, MAX98927_R0036_AMP_VOL_CTRL, 0x38);
667 regmap_write(max98927->regmap, MAX98927_R003C_SPK_GAIN, 0x05);
668 /* Enable DC blocker */
669 regmap_write(max98927->regmap, MAX98927_R0037_AMP_DSP_CFG, 0x03);
670 /* Enable IMON VMON DC blocker */
671 regmap_write(max98927->regmap, MAX98927_R003F_MEAS_DSP_CFG, 0xF7);
672 /* Boost Output Voltage & Current limit */
673 regmap_write(max98927->regmap, MAX98927_R0040_BOOST_CTRL0, 0x1C);
674 regmap_write(max98927->regmap, MAX98927_R0042_BOOST_CTRL1, 0x3E);
675 /* Measurement ADC config */
676 regmap_write(max98927->regmap, MAX98927_R0043_MEAS_ADC_CFG, 0x04);
677 regmap_write(max98927->regmap, MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x00);
678 regmap_write(max98927->regmap, MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x24);
679 /* Brownout Level */
680 regmap_write(max98927->regmap, MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1,
681 0x06);
682 /* Envelope Tracking configuration */
683 regmap_write(max98927->regmap, MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM,
684 0x08);
685 regmap_write(max98927->regmap, MAX98927_R0086_ENV_TRACK_CTRL, 0x01);
686 regmap_write(max98927->regmap, MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ,
687 0x10);
688
689 /* voltage, current slot configuration */
690 regmap_write(max98927->regmap, MAX98927_R001E_PCM_TX_CH_SRC_A,
691 (max98927->i_l_slot << MAX98927_PCM_TX_CH_SRC_A_I_SHIFT | max98927->v_l_slot) & 0xFF);
692
693 if (max98927->v_l_slot < 8) {
694 regmap_update_bits(max98927->regmap,
695 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
696 1 << max98927->v_l_slot, 0);
697 regmap_update_bits(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A,
698 1 << max98927->v_l_slot,
699 1 << max98927->v_l_slot);
700 } else {
701 regmap_update_bits(max98927->regmap,
702 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
703 1 << (max98927->v_l_slot - 8), 0);
704 regmap_update_bits(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B,
705 1 << (max98927->v_l_slot - 8),
706 1 << (max98927->v_l_slot - 8));
707 }
708
709 if (max98927->i_l_slot < 8) {
710 regmap_update_bits(max98927->regmap,
711 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
712 1 << max98927->i_l_slot, 0);
713 regmap_update_bits(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A,
714 1 << max98927->i_l_slot,
715 1 << max98927->i_l_slot);
716 } else {
717 regmap_update_bits(max98927->regmap,
718 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
719 1 << (max98927->i_l_slot - 8), 0);
720 regmap_update_bits(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B,
721 1 << (max98927->i_l_slot - 8),
722 1 << (max98927->i_l_slot - 8));
723 }
724
725 /* Set interleave mode */
726 if (max98927->interleave_mode)
727 regmap_update_bits(max98927->regmap,
728 MAX98927_R001F_PCM_TX_CH_SRC_B,
729 MAX98927_PCM_TX_CH_INTERLEAVE_MASK,
730 MAX98927_PCM_TX_CH_INTERLEAVE_MASK);
731 return 0;
732}
733
734#ifdef CONFIG_PM_SLEEP
735static int max98927_suspend(struct device *dev)
736{
737 struct max98927_priv *max98927 = dev_get_drvdata(dev);
738
739 regcache_cache_only(max98927->regmap, true);
740 regcache_mark_dirty(max98927->regmap);
741 return 0;
742}
743static int max98927_resume(struct device *dev)
744{
745 struct max98927_priv *max98927 = dev_get_drvdata(dev);
746
747 regmap_write(max98927->regmap, MAX98927_R0100_SOFT_RESET,
748 MAX98927_SOFT_RESET);
749 regcache_cache_only(max98927->regmap, false);
750 regcache_sync(max98927->regmap);
751 return 0;
752}
753#endif
754
755static const struct dev_pm_ops max98927_pm = {
756 SET_SYSTEM_SLEEP_PM_OPS(max98927_suspend, max98927_resume)
757};
758
759static const struct snd_soc_component_driver soc_component_dev_max98927 = {
760 .probe = max98927_probe,
761 .controls = max98927_snd_controls,
762 .num_controls = ARRAY_SIZE(max98927_snd_controls),
763 .dapm_widgets = max98927_dapm_widgets,
764 .num_dapm_widgets = ARRAY_SIZE(max98927_dapm_widgets),
765 .dapm_routes = max98927_audio_map,
766 .num_dapm_routes = ARRAY_SIZE(max98927_audio_map),
767 .idle_bias_on = 1,
768 .use_pmdown_time = 1,
769 .endianness = 1,
770};
771
772static const struct regmap_config max98927_regmap = {
773 .reg_bits = 16,
774 .val_bits = 8,
775 .max_register = MAX98927_R01FF_REV_ID,
776 .reg_defaults = max98927_reg,
777 .num_reg_defaults = ARRAY_SIZE(max98927_reg),
778 .readable_reg = max98927_readable_register,
779 .volatile_reg = max98927_volatile_reg,
780 .cache_type = REGCACHE_RBTREE,
781};
782
783static void max98927_slot_config(struct i2c_client *i2c,
784 struct max98927_priv *max98927)
785{
786 int value;
787 struct device *dev = &i2c->dev;
788
789 if (!device_property_read_u32(dev, "vmon-slot-no", &value))
790 max98927->v_l_slot = value & 0xF;
791 else
792 max98927->v_l_slot = 0;
793
794 if (!device_property_read_u32(dev, "imon-slot-no", &value))
795 max98927->i_l_slot = value & 0xF;
796 else
797 max98927->i_l_slot = 1;
798}
799
800static int max98927_i2c_probe(struct i2c_client *i2c)
801{
802
803 int ret = 0, value;
804 int reg = 0;
805 struct max98927_priv *max98927 = NULL;
806
807 max98927 = devm_kzalloc(&i2c->dev, sizeof(*max98927), GFP_KERNEL);
808 if (!max98927) {
809 ret = -ENOMEM;
810 return ret;
811 }
812 i2c_set_clientdata(i2c, max98927);
813
814 /* update interleave mode info */
815 if (of_property_read_bool(i2c->dev.of_node, "maxim,interleave-mode")) {
816 max98927->interleave_mode = true;
817 } else {
818 if (!of_property_read_u32(i2c->dev.of_node, "interleave_mode",
819 &value))
820 if (value > 0)
821 max98927->interleave_mode = true;
822 }
823
824 /* regmap initialization */
825 max98927->regmap
826 = devm_regmap_init_i2c(i2c, &max98927_regmap);
827 if (IS_ERR(max98927->regmap)) {
828 ret = PTR_ERR(max98927->regmap);
829 dev_err(&i2c->dev,
830 "Failed to allocate regmap: %d\n", ret);
831 return ret;
832 }
833
834 max98927->reset_gpio = devm_gpiod_get_optional(&i2c->dev, "reset",
835 GPIOD_OUT_HIGH);
836 if (IS_ERR(max98927->reset_gpio)) {
837 ret = PTR_ERR(max98927->reset_gpio);
838 return dev_err_probe(&i2c->dev, ret, "failed to request GPIO reset pin");
839 }
840
841 if (max98927->reset_gpio) {
842 gpiod_set_value_cansleep(max98927->reset_gpio, 0);
843 /* Wait for i2c port to be ready */
844 usleep_range(5000, 6000);
845 }
846
847 /* Check Revision ID */
848 ret = regmap_read(max98927->regmap, MAX98927_R01FF_REV_ID, ®);
849 if (ret < 0) {
850 dev_err(&i2c->dev,
851 "Failed to read: 0x%02X\n", MAX98927_R01FF_REV_ID);
852 return ret;
853 }
854 dev_info(&i2c->dev, "MAX98927 revisionID: 0x%02X\n", reg);
855
856 /* voltage/current slot configuration */
857 max98927_slot_config(i2c, max98927);
858
859 /* codec registeration */
860 ret = devm_snd_soc_register_component(&i2c->dev,
861 &soc_component_dev_max98927,
862 max98927_dai, ARRAY_SIZE(max98927_dai));
863 if (ret < 0)
864 dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
865
866 return ret;
867}
868
869static void max98927_i2c_remove(struct i2c_client *i2c)
870{
871 struct max98927_priv *max98927 = i2c_get_clientdata(i2c);
872
873 if (max98927->reset_gpio)
874 gpiod_set_value_cansleep(max98927->reset_gpio, 1);
875}
876
877static const struct i2c_device_id max98927_i2c_id[] = {
878 { "max98927"},
879 { },
880};
881
882MODULE_DEVICE_TABLE(i2c, max98927_i2c_id);
883
884#if defined(CONFIG_OF)
885static const struct of_device_id max98927_of_match[] = {
886 { .compatible = "maxim,max98927", },
887 { }
888};
889MODULE_DEVICE_TABLE(of, max98927_of_match);
890#endif
891
892#ifdef CONFIG_ACPI
893static const struct acpi_device_id max98927_acpi_match[] = {
894 { "MX98927", 0 },
895 {},
896};
897MODULE_DEVICE_TABLE(acpi, max98927_acpi_match);
898#endif
899
900static struct i2c_driver max98927_i2c_driver = {
901 .driver = {
902 .name = "max98927",
903 .of_match_table = of_match_ptr(max98927_of_match),
904 .acpi_match_table = ACPI_PTR(max98927_acpi_match),
905 .pm = &max98927_pm,
906 },
907 .probe = max98927_i2c_probe,
908 .remove = max98927_i2c_remove,
909 .id_table = max98927_i2c_id,
910};
911
912module_i2c_driver(max98927_i2c_driver)
913
914MODULE_DESCRIPTION("ALSA SoC MAX98927 driver");
915MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
916MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * max98927.c -- MAX98927 ALSA Soc Audio driver
4 *
5 * Copyright (C) 2016-2017 Maxim Integrated Products
6 * Author: Ryan Lee <ryans.lee@maximintegrated.com>
7 */
8
9#include <linux/acpi.h>
10#include <linux/i2c.h>
11#include <linux/module.h>
12#include <linux/regmap.h>
13#include <linux/slab.h>
14#include <linux/cdev.h>
15#include <sound/pcm.h>
16#include <sound/pcm_params.h>
17#include <sound/soc.h>
18#include <linux/gpio.h>
19#include <linux/gpio/consumer.h>
20#include <linux/of_gpio.h>
21#include <sound/tlv.h>
22#include "max98927.h"
23
24static struct reg_default max98927_reg[] = {
25 {MAX98927_R0001_INT_RAW1, 0x00},
26 {MAX98927_R0002_INT_RAW2, 0x00},
27 {MAX98927_R0003_INT_RAW3, 0x00},
28 {MAX98927_R0004_INT_STATE1, 0x00},
29 {MAX98927_R0005_INT_STATE2, 0x00},
30 {MAX98927_R0006_INT_STATE3, 0x00},
31 {MAX98927_R0007_INT_FLAG1, 0x00},
32 {MAX98927_R0008_INT_FLAG2, 0x00},
33 {MAX98927_R0009_INT_FLAG3, 0x00},
34 {MAX98927_R000A_INT_EN1, 0x00},
35 {MAX98927_R000B_INT_EN2, 0x00},
36 {MAX98927_R000C_INT_EN3, 0x00},
37 {MAX98927_R000D_INT_FLAG_CLR1, 0x00},
38 {MAX98927_R000E_INT_FLAG_CLR2, 0x00},
39 {MAX98927_R000F_INT_FLAG_CLR3, 0x00},
40 {MAX98927_R0010_IRQ_CTRL, 0x00},
41 {MAX98927_R0011_CLK_MON, 0x00},
42 {MAX98927_R0012_WDOG_CTRL, 0x00},
43 {MAX98927_R0013_WDOG_RST, 0x00},
44 {MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH, 0x75},
45 {MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH, 0x8c},
46 {MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS, 0x08},
47 {MAX98927_R0017_PIN_CFG, 0x55},
48 {MAX98927_R0018_PCM_RX_EN_A, 0x00},
49 {MAX98927_R0019_PCM_RX_EN_B, 0x00},
50 {MAX98927_R001A_PCM_TX_EN_A, 0x00},
51 {MAX98927_R001B_PCM_TX_EN_B, 0x00},
52 {MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0x00},
53 {MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0x00},
54 {MAX98927_R001E_PCM_TX_CH_SRC_A, 0x00},
55 {MAX98927_R001F_PCM_TX_CH_SRC_B, 0x00},
56 {MAX98927_R0020_PCM_MODE_CFG, 0x40},
57 {MAX98927_R0021_PCM_MASTER_MODE, 0x00},
58 {MAX98927_R0022_PCM_CLK_SETUP, 0x22},
59 {MAX98927_R0023_PCM_SR_SETUP1, 0x00},
60 {MAX98927_R0024_PCM_SR_SETUP2, 0x00},
61 {MAX98927_R0025_PCM_TO_SPK_MONOMIX_A, 0x00},
62 {MAX98927_R0026_PCM_TO_SPK_MONOMIX_B, 0x00},
63 {MAX98927_R0027_ICC_RX_EN_A, 0x00},
64 {MAX98927_R0028_ICC_RX_EN_B, 0x00},
65 {MAX98927_R002B_ICC_TX_EN_A, 0x00},
66 {MAX98927_R002C_ICC_TX_EN_B, 0x00},
67 {MAX98927_R002E_ICC_HIZ_MANUAL_MODE, 0x00},
68 {MAX98927_R002F_ICC_TX_HIZ_EN_A, 0x00},
69 {MAX98927_R0030_ICC_TX_HIZ_EN_B, 0x00},
70 {MAX98927_R0031_ICC_LNK_EN, 0x00},
71 {MAX98927_R0032_PDM_TX_EN, 0x00},
72 {MAX98927_R0033_PDM_TX_HIZ_CTRL, 0x00},
73 {MAX98927_R0034_PDM_TX_CTRL, 0x00},
74 {MAX98927_R0035_PDM_RX_CTRL, 0x00},
75 {MAX98927_R0036_AMP_VOL_CTRL, 0x00},
76 {MAX98927_R0037_AMP_DSP_CFG, 0x02},
77 {MAX98927_R0038_TONE_GEN_DC_CFG, 0x00},
78 {MAX98927_R0039_DRE_CTRL, 0x01},
79 {MAX98927_R003A_AMP_EN, 0x00},
80 {MAX98927_R003B_SPK_SRC_SEL, 0x00},
81 {MAX98927_R003C_SPK_GAIN, 0x00},
82 {MAX98927_R003D_SSM_CFG, 0x04},
83 {MAX98927_R003E_MEAS_EN, 0x00},
84 {MAX98927_R003F_MEAS_DSP_CFG, 0x04},
85 {MAX98927_R0040_BOOST_CTRL0, 0x00},
86 {MAX98927_R0041_BOOST_CTRL3, 0x00},
87 {MAX98927_R0042_BOOST_CTRL1, 0x00},
88 {MAX98927_R0043_MEAS_ADC_CFG, 0x00},
89 {MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x01},
90 {MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x00},
91 {MAX98927_R0046_ADC_CH0_DIVIDE, 0x00},
92 {MAX98927_R0047_ADC_CH1_DIVIDE, 0x00},
93 {MAX98927_R0048_ADC_CH2_DIVIDE, 0x00},
94 {MAX98927_R0049_ADC_CH0_FILT_CFG, 0x00},
95 {MAX98927_R004A_ADC_CH1_FILT_CFG, 0x00},
96 {MAX98927_R004B_ADC_CH2_FILT_CFG, 0x00},
97 {MAX98927_R004C_MEAS_ADC_CH0_READ, 0x00},
98 {MAX98927_R004D_MEAS_ADC_CH1_READ, 0x00},
99 {MAX98927_R004E_MEAS_ADC_CH2_READ, 0x00},
100 {MAX98927_R0051_BROWNOUT_STATUS, 0x00},
101 {MAX98927_R0052_BROWNOUT_EN, 0x00},
102 {MAX98927_R0053_BROWNOUT_INFINITE_HOLD, 0x00},
103 {MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR, 0x00},
104 {MAX98927_R0055_BROWNOUT_LVL_HOLD, 0x00},
105 {MAX98927_R005A_BROWNOUT_LVL1_THRESH, 0x00},
106 {MAX98927_R005B_BROWNOUT_LVL2_THRESH, 0x00},
107 {MAX98927_R005C_BROWNOUT_LVL3_THRESH, 0x00},
108 {MAX98927_R005D_BROWNOUT_LVL4_THRESH, 0x00},
109 {MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS, 0x00},
110 {MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL, 0x00},
111 {MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL, 0x00},
112 {MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE, 0x00},
113 {MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT, 0x00},
114 {MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1, 0x00},
115 {MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2, 0x00},
116 {MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3, 0x00},
117 {MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT, 0x00},
118 {MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1, 0x00},
119 {MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2, 0x00},
120 {MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3, 0x00},
121 {MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT, 0x00},
122 {MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1, 0x00},
123 {MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2, 0x00},
124 {MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3, 0x00},
125 {MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT, 0x00},
126 {MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1, 0x00},
127 {MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2, 0x00},
128 {MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3, 0x00},
129 {MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM, 0x00},
130 {MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY, 0x00},
131 {MAX98927_R0084_ENV_TRACK_REL_RATE, 0x00},
132 {MAX98927_R0085_ENV_TRACK_HOLD_RATE, 0x00},
133 {MAX98927_R0086_ENV_TRACK_CTRL, 0x00},
134 {MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ, 0x00},
135 {MAX98927_R00FF_GLOBAL_SHDN, 0x00},
136 {MAX98927_R0100_SOFT_RESET, 0x00},
137 {MAX98927_R01FF_REV_ID, 0x40},
138};
139
140static int max98927_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
141{
142 struct snd_soc_component *component = codec_dai->component;
143 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
144 unsigned int mode = 0;
145 unsigned int format = 0;
146 bool use_pdm = false;
147 unsigned int invert = 0;
148
149 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
150
151 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
152 case SND_SOC_DAIFMT_CBC_CFC:
153 max98927->provider = false;
154 mode = MAX98927_PCM_MASTER_MODE_SLAVE;
155 break;
156 case SND_SOC_DAIFMT_CBP_CFP:
157 max98927->provider = true;
158 mode = MAX98927_PCM_MASTER_MODE_MASTER;
159 break;
160 default:
161 dev_err(component->dev, "DAI clock mode unsupported\n");
162 return -EINVAL;
163 }
164
165 regmap_update_bits(max98927->regmap,
166 MAX98927_R0021_PCM_MASTER_MODE,
167 MAX98927_PCM_MASTER_MODE_MASK,
168 mode);
169
170 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
171 case SND_SOC_DAIFMT_NB_NF:
172 break;
173 case SND_SOC_DAIFMT_IB_NF:
174 invert = MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE;
175 break;
176 default:
177 dev_err(component->dev, "DAI invert mode unsupported\n");
178 return -EINVAL;
179 }
180
181 regmap_update_bits(max98927->regmap,
182 MAX98927_R0020_PCM_MODE_CFG,
183 MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE,
184 invert);
185
186 /* interface format */
187 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
188 case SND_SOC_DAIFMT_I2S:
189 format = MAX98927_PCM_FORMAT_I2S;
190 break;
191 case SND_SOC_DAIFMT_LEFT_J:
192 format = MAX98927_PCM_FORMAT_LJ;
193 break;
194 case SND_SOC_DAIFMT_DSP_A:
195 format = MAX98927_PCM_FORMAT_TDM_MODE1;
196 break;
197 case SND_SOC_DAIFMT_DSP_B:
198 format = MAX98927_PCM_FORMAT_TDM_MODE0;
199 break;
200 case SND_SOC_DAIFMT_PDM:
201 use_pdm = true;
202 break;
203 default:
204 return -EINVAL;
205 }
206 max98927->iface = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
207
208 if (!use_pdm) {
209 /* pcm channel configuration */
210 regmap_update_bits(max98927->regmap,
211 MAX98927_R0018_PCM_RX_EN_A,
212 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN,
213 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN);
214
215 regmap_update_bits(max98927->regmap,
216 MAX98927_R0020_PCM_MODE_CFG,
217 MAX98927_PCM_MODE_CFG_FORMAT_MASK,
218 format << MAX98927_PCM_MODE_CFG_FORMAT_SHIFT);
219
220 regmap_update_bits(max98927->regmap,
221 MAX98927_R003B_SPK_SRC_SEL,
222 MAX98927_SPK_SRC_MASK, 0);
223
224 regmap_update_bits(max98927->regmap,
225 MAX98927_R0035_PDM_RX_CTRL,
226 MAX98927_PDM_RX_EN_MASK, 0);
227 } else {
228 /* pdm channel configuration */
229 regmap_update_bits(max98927->regmap,
230 MAX98927_R0035_PDM_RX_CTRL,
231 MAX98927_PDM_RX_EN_MASK, 1);
232
233 regmap_update_bits(max98927->regmap,
234 MAX98927_R003B_SPK_SRC_SEL,
235 MAX98927_SPK_SRC_MASK, 3);
236
237 regmap_update_bits(max98927->regmap,
238 MAX98927_R0018_PCM_RX_EN_A,
239 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN, 0);
240 }
241 return 0;
242}
243
244/* codec MCLK rate in master mode */
245static const int rate_table[] = {
246 5644800, 6000000, 6144000, 6500000,
247 9600000, 11289600, 12000000, 12288000,
248 13000000, 19200000,
249};
250
251/* BCLKs per LRCLK */
252static const int bclk_sel_table[] = {
253 32, 48, 64, 96, 128, 192, 256, 384, 512,
254};
255
256static int max98927_get_bclk_sel(int bclk)
257{
258 int i;
259 /* match BCLKs per LRCLK */
260 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
261 if (bclk_sel_table[i] == bclk)
262 return i + 2;
263 }
264 return 0;
265}
266static int max98927_set_clock(struct max98927_priv *max98927,
267 struct snd_pcm_hw_params *params)
268{
269 struct snd_soc_component *component = max98927->component;
270 /* BCLK/LRCLK ratio calculation */
271 int blr_clk_ratio = params_channels(params) * max98927->ch_size;
272 int value;
273
274 if (max98927->provider) {
275 int i;
276 /* match rate to closest value */
277 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
278 if (rate_table[i] >= max98927->sysclk)
279 break;
280 }
281 if (i == ARRAY_SIZE(rate_table)) {
282 dev_err(component->dev, "failed to find proper clock rate.\n");
283 return -EINVAL;
284 }
285 regmap_update_bits(max98927->regmap,
286 MAX98927_R0021_PCM_MASTER_MODE,
287 MAX98927_PCM_MASTER_MODE_MCLK_MASK,
288 i << MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT);
289 }
290
291 if (!max98927->tdm_mode) {
292 /* BCLK configuration */
293 value = max98927_get_bclk_sel(blr_clk_ratio);
294 if (!value) {
295 dev_err(component->dev, "format unsupported %d\n",
296 params_format(params));
297 return -EINVAL;
298 }
299
300 regmap_update_bits(max98927->regmap,
301 MAX98927_R0022_PCM_CLK_SETUP,
302 MAX98927_PCM_CLK_SETUP_BSEL_MASK,
303 value);
304 }
305 return 0;
306}
307
308static int max98927_dai_hw_params(struct snd_pcm_substream *substream,
309 struct snd_pcm_hw_params *params,
310 struct snd_soc_dai *dai)
311{
312 struct snd_soc_component *component = dai->component;
313 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
314 unsigned int sampling_rate = 0;
315 unsigned int chan_sz = 0;
316
317 /* pcm mode configuration */
318 switch (snd_pcm_format_width(params_format(params))) {
319 case 16:
320 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
321 break;
322 case 24:
323 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
324 break;
325 case 32:
326 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
327 break;
328 default:
329 dev_err(component->dev, "format unsupported %d\n",
330 params_format(params));
331 goto err;
332 }
333
334 max98927->ch_size = snd_pcm_format_width(params_format(params));
335
336 regmap_update_bits(max98927->regmap,
337 MAX98927_R0020_PCM_MODE_CFG,
338 MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
339
340 dev_dbg(component->dev, "format supported %d",
341 params_format(params));
342
343 /* sampling rate configuration */
344 switch (params_rate(params)) {
345 case 8000:
346 sampling_rate = MAX98927_PCM_SR_SET1_SR_8000;
347 break;
348 case 11025:
349 sampling_rate = MAX98927_PCM_SR_SET1_SR_11025;
350 break;
351 case 12000:
352 sampling_rate = MAX98927_PCM_SR_SET1_SR_12000;
353 break;
354 case 16000:
355 sampling_rate = MAX98927_PCM_SR_SET1_SR_16000;
356 break;
357 case 22050:
358 sampling_rate = MAX98927_PCM_SR_SET1_SR_22050;
359 break;
360 case 24000:
361 sampling_rate = MAX98927_PCM_SR_SET1_SR_24000;
362 break;
363 case 32000:
364 sampling_rate = MAX98927_PCM_SR_SET1_SR_32000;
365 break;
366 case 44100:
367 sampling_rate = MAX98927_PCM_SR_SET1_SR_44100;
368 break;
369 case 48000:
370 sampling_rate = MAX98927_PCM_SR_SET1_SR_48000;
371 break;
372 default:
373 dev_err(component->dev, "rate %d not supported\n",
374 params_rate(params));
375 goto err;
376 }
377 /* set DAI_SR to correct LRCLK frequency */
378 regmap_update_bits(max98927->regmap,
379 MAX98927_R0023_PCM_SR_SETUP1,
380 MAX98927_PCM_SR_SET1_SR_MASK,
381 sampling_rate);
382 regmap_update_bits(max98927->regmap,
383 MAX98927_R0024_PCM_SR_SETUP2,
384 MAX98927_PCM_SR_SET2_SR_MASK,
385 sampling_rate << MAX98927_PCM_SR_SET2_SR_SHIFT);
386
387 /* set sampling rate of IV */
388 if (max98927->interleave_mode &&
389 sampling_rate > MAX98927_PCM_SR_SET1_SR_16000)
390 regmap_update_bits(max98927->regmap,
391 MAX98927_R0024_PCM_SR_SETUP2,
392 MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
393 sampling_rate - 3);
394 else
395 regmap_update_bits(max98927->regmap,
396 MAX98927_R0024_PCM_SR_SETUP2,
397 MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
398 sampling_rate);
399 return max98927_set_clock(max98927, params);
400err:
401 return -EINVAL;
402}
403
404static int max98927_dai_tdm_slot(struct snd_soc_dai *dai,
405 unsigned int tx_mask, unsigned int rx_mask,
406 int slots, int slot_width)
407{
408 struct snd_soc_component *component = dai->component;
409 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
410 int bsel = 0;
411 unsigned int chan_sz = 0;
412
413 max98927->tdm_mode = true;
414
415 /* BCLK configuration */
416 bsel = max98927_get_bclk_sel(slots * slot_width);
417 if (bsel == 0) {
418 dev_err(component->dev, "BCLK %d not supported\n",
419 slots * slot_width);
420 return -EINVAL;
421 }
422
423 regmap_update_bits(max98927->regmap,
424 MAX98927_R0022_PCM_CLK_SETUP,
425 MAX98927_PCM_CLK_SETUP_BSEL_MASK,
426 bsel);
427
428 /* Channel size configuration */
429 switch (slot_width) {
430 case 16:
431 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
432 break;
433 case 24:
434 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
435 break;
436 case 32:
437 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
438 break;
439 default:
440 dev_err(component->dev, "format unsupported %d\n",
441 slot_width);
442 return -EINVAL;
443 }
444
445 regmap_update_bits(max98927->regmap,
446 MAX98927_R0020_PCM_MODE_CFG,
447 MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
448
449 /* Rx slot configuration */
450 regmap_write(max98927->regmap,
451 MAX98927_R0018_PCM_RX_EN_A,
452 rx_mask & 0xFF);
453 regmap_write(max98927->regmap,
454 MAX98927_R0019_PCM_RX_EN_B,
455 (rx_mask & 0xFF00) >> 8);
456
457 /* Tx slot configuration */
458 regmap_write(max98927->regmap,
459 MAX98927_R001A_PCM_TX_EN_A,
460 tx_mask & 0xFF);
461 regmap_write(max98927->regmap,
462 MAX98927_R001B_PCM_TX_EN_B,
463 (tx_mask & 0xFF00) >> 8);
464
465 /* Tx slot Hi-Z configuration */
466 regmap_write(max98927->regmap,
467 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
468 ~tx_mask & 0xFF);
469 regmap_write(max98927->regmap,
470 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
471 (~tx_mask & 0xFF00) >> 8);
472
473 return 0;
474}
475
476#define MAX98927_RATES SNDRV_PCM_RATE_8000_48000
477
478#define MAX98927_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
479 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
480
481static int max98927_dai_set_sysclk(struct snd_soc_dai *dai,
482 int clk_id, unsigned int freq, int dir)
483{
484 struct snd_soc_component *component = dai->component;
485 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
486
487 max98927->sysclk = freq;
488 return 0;
489}
490
491static const struct snd_soc_dai_ops max98927_dai_ops = {
492 .set_sysclk = max98927_dai_set_sysclk,
493 .set_fmt = max98927_dai_set_fmt,
494 .hw_params = max98927_dai_hw_params,
495 .set_tdm_slot = max98927_dai_tdm_slot,
496};
497
498static int max98927_dac_event(struct snd_soc_dapm_widget *w,
499 struct snd_kcontrol *kcontrol, int event)
500{
501 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
502 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
503
504 switch (event) {
505 case SND_SOC_DAPM_PRE_PMU:
506 max98927->tdm_mode = false;
507 break;
508 case SND_SOC_DAPM_POST_PMU:
509 regmap_update_bits(max98927->regmap,
510 MAX98927_R003A_AMP_EN,
511 MAX98927_AMP_EN_MASK, 1);
512 regmap_update_bits(max98927->regmap,
513 MAX98927_R00FF_GLOBAL_SHDN,
514 MAX98927_GLOBAL_EN_MASK, 1);
515 break;
516 case SND_SOC_DAPM_POST_PMD:
517 regmap_update_bits(max98927->regmap,
518 MAX98927_R00FF_GLOBAL_SHDN,
519 MAX98927_GLOBAL_EN_MASK, 0);
520 regmap_update_bits(max98927->regmap,
521 MAX98927_R003A_AMP_EN,
522 MAX98927_AMP_EN_MASK, 0);
523 break;
524 default:
525 return 0;
526 }
527 return 0;
528}
529
530static const char * const max98927_switch_text[] = {
531 "Left", "Right", "LeftRight"};
532
533static const struct soc_enum dai_sel_enum =
534 SOC_ENUM_SINGLE(MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
535 MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
536 3, max98927_switch_text);
537
538static const struct snd_kcontrol_new max98927_dai_controls =
539 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
540
541static const struct snd_kcontrol_new max98927_vi_control =
542 SOC_DAPM_SINGLE("Switch", MAX98927_R003F_MEAS_DSP_CFG, 2, 1, 0);
543
544static const struct snd_soc_dapm_widget max98927_dapm_widgets[] = {
545 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", MAX98927_R003A_AMP_EN,
546 0, 0, max98927_dac_event,
547 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
548 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
549 &max98927_dai_controls),
550 SND_SOC_DAPM_OUTPUT("BE_OUT"),
551 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
552 MAX98927_R003E_MEAS_EN, 0, 0),
553 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
554 MAX98927_R003E_MEAS_EN, 1, 0),
555 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
556 &max98927_vi_control),
557 SND_SOC_DAPM_SIGGEN("VMON"),
558 SND_SOC_DAPM_SIGGEN("IMON"),
559};
560
561static DECLARE_TLV_DB_SCALE(max98927_spk_tlv, 300, 300, 0);
562static DECLARE_TLV_DB_SCALE(max98927_digital_tlv, -1600, 25, 0);
563
564static bool max98927_readable_register(struct device *dev, unsigned int reg)
565{
566 switch (reg) {
567 case MAX98927_R0001_INT_RAW1 ... MAX98927_R0028_ICC_RX_EN_B:
568 case MAX98927_R002B_ICC_TX_EN_A ... MAX98927_R002C_ICC_TX_EN_B:
569 case MAX98927_R002E_ICC_HIZ_MANUAL_MODE
570 ... MAX98927_R004E_MEAS_ADC_CH2_READ:
571 case MAX98927_R0051_BROWNOUT_STATUS
572 ... MAX98927_R0055_BROWNOUT_LVL_HOLD:
573 case MAX98927_R005A_BROWNOUT_LVL1_THRESH
574 ... MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE:
575 case MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT
576 ... MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
577 case MAX98927_R00FF_GLOBAL_SHDN:
578 case MAX98927_R0100_SOFT_RESET:
579 case MAX98927_R01FF_REV_ID:
580 return true;
581 default:
582 return false;
583 }
584};
585
586static bool max98927_volatile_reg(struct device *dev, unsigned int reg)
587{
588 switch (reg) {
589 case MAX98927_R0001_INT_RAW1 ... MAX98927_R0009_INT_FLAG3:
590 case MAX98927_R004C_MEAS_ADC_CH0_READ:
591 case MAX98927_R004D_MEAS_ADC_CH1_READ:
592 case MAX98927_R004E_MEAS_ADC_CH2_READ:
593 case MAX98927_R0051_BROWNOUT_STATUS:
594 case MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
595 case MAX98927_R01FF_REV_ID:
596 case MAX98927_R0100_SOFT_RESET:
597 return true;
598 default:
599 return false;
600 }
601}
602
603static const char * const max98927_boost_voltage_text[] = {
604 "6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V",
605 "7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V",
606 "8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V",
607 "9.5V", "9.625V", "9.75V", "9.875V", "10V"
608};
609
610static SOC_ENUM_SINGLE_DECL(max98927_boost_voltage,
611 MAX98927_R0040_BOOST_CTRL0, 0,
612 max98927_boost_voltage_text);
613
614static const char * const max98927_current_limit_text[] = {
615 "1.00A", "1.10A", "1.20A", "1.30A", "1.40A", "1.50A", "1.60A", "1.70A",
616 "1.80A", "1.90A", "2.00A", "2.10A", "2.20A", "2.30A", "2.40A", "2.50A",
617 "2.60A", "2.70A", "2.80A", "2.90A", "3.00A", "3.10A", "3.20A", "3.30A",
618 "3.40A", "3.50A", "3.60A", "3.70A", "3.80A", "3.90A", "4.00A", "4.10A"
619};
620
621static SOC_ENUM_SINGLE_DECL(max98927_current_limit,
622 MAX98927_R0042_BOOST_CTRL1, 1,
623 max98927_current_limit_text);
624
625static const struct snd_kcontrol_new max98927_snd_controls[] = {
626 SOC_SINGLE_TLV("Speaker Volume", MAX98927_R003C_SPK_GAIN,
627 0, 6, 0,
628 max98927_spk_tlv),
629 SOC_SINGLE_TLV("Digital Volume", MAX98927_R0036_AMP_VOL_CTRL,
630 0, (1<<MAX98927_AMP_VOL_WIDTH)-1, 0,
631 max98927_digital_tlv),
632 SOC_SINGLE("Amp DSP Switch", MAX98927_R0052_BROWNOUT_EN,
633 MAX98927_BROWNOUT_DSP_SHIFT, 1, 0),
634 SOC_SINGLE("Ramp Switch", MAX98927_R0037_AMP_DSP_CFG,
635 MAX98927_AMP_DSP_CFG_RMP_SHIFT, 1, 0),
636 SOC_SINGLE("DRE Switch", MAX98927_R0039_DRE_CTRL,
637 MAX98927_DRE_EN_SHIFT, 1, 0),
638 SOC_SINGLE("Volume Location Switch", MAX98927_R0036_AMP_VOL_CTRL,
639 MAX98927_AMP_VOL_SEL_SHIFT, 1, 0),
640 SOC_ENUM("Boost Output Voltage", max98927_boost_voltage),
641 SOC_ENUM("Current Limit", max98927_current_limit),
642};
643
644static const struct snd_soc_dapm_route max98927_audio_map[] = {
645 /* Plabyack */
646 {"DAI Sel Mux", "Left", "Amp Enable"},
647 {"DAI Sel Mux", "Right", "Amp Enable"},
648 {"DAI Sel Mux", "LeftRight", "Amp Enable"},
649 {"BE_OUT", NULL, "DAI Sel Mux"},
650 /* Capture */
651 { "VI Sense", "Switch", "VMON" },
652 { "VI Sense", "Switch", "IMON" },
653 { "Voltage Sense", NULL, "VI Sense" },
654 { "Current Sense", NULL, "VI Sense" },
655};
656
657static struct snd_soc_dai_driver max98927_dai[] = {
658 {
659 .name = "max98927-aif1",
660 .playback = {
661 .stream_name = "HiFi Playback",
662 .channels_min = 1,
663 .channels_max = 2,
664 .rates = MAX98927_RATES,
665 .formats = MAX98927_FORMATS,
666 },
667 .capture = {
668 .stream_name = "HiFi Capture",
669 .channels_min = 1,
670 .channels_max = 2,
671 .rates = MAX98927_RATES,
672 .formats = MAX98927_FORMATS,
673 },
674 .ops = &max98927_dai_ops,
675 }
676};
677
678static int max98927_probe(struct snd_soc_component *component)
679{
680 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
681
682 max98927->component = component;
683
684 /* Software Reset */
685 regmap_write(max98927->regmap,
686 MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET);
687
688 /* IV default slot configuration */
689 regmap_write(max98927->regmap,
690 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
691 0xFF);
692 regmap_write(max98927->regmap,
693 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
694 0xFF);
695 regmap_write(max98927->regmap,
696 MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
697 0x80);
698 regmap_write(max98927->regmap,
699 MAX98927_R0026_PCM_TO_SPK_MONOMIX_B,
700 0x1);
701 /* Set inital volume (+13dB) */
702 regmap_write(max98927->regmap,
703 MAX98927_R0036_AMP_VOL_CTRL,
704 0x38);
705 regmap_write(max98927->regmap,
706 MAX98927_R003C_SPK_GAIN,
707 0x05);
708 /* Enable DC blocker */
709 regmap_write(max98927->regmap,
710 MAX98927_R0037_AMP_DSP_CFG,
711 0x03);
712 /* Enable IMON VMON DC blocker */
713 regmap_write(max98927->regmap,
714 MAX98927_R003F_MEAS_DSP_CFG,
715 0xF7);
716 /* Boost Output Voltage & Current limit */
717 regmap_write(max98927->regmap,
718 MAX98927_R0040_BOOST_CTRL0,
719 0x1C);
720 regmap_write(max98927->regmap,
721 MAX98927_R0042_BOOST_CTRL1,
722 0x3E);
723 /* Measurement ADC config */
724 regmap_write(max98927->regmap,
725 MAX98927_R0043_MEAS_ADC_CFG,
726 0x04);
727 regmap_write(max98927->regmap,
728 MAX98927_R0044_MEAS_ADC_BASE_MSB,
729 0x00);
730 regmap_write(max98927->regmap,
731 MAX98927_R0045_MEAS_ADC_BASE_LSB,
732 0x24);
733 /* Brownout Level */
734 regmap_write(max98927->regmap,
735 MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1,
736 0x06);
737 /* Envelope Tracking configuration */
738 regmap_write(max98927->regmap,
739 MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM,
740 0x08);
741 regmap_write(max98927->regmap,
742 MAX98927_R0086_ENV_TRACK_CTRL,
743 0x01);
744 regmap_write(max98927->regmap,
745 MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ,
746 0x10);
747
748 /* voltage, current slot configuration */
749 regmap_write(max98927->regmap,
750 MAX98927_R001E_PCM_TX_CH_SRC_A,
751 (max98927->i_l_slot<<MAX98927_PCM_TX_CH_SRC_A_I_SHIFT|
752 max98927->v_l_slot)&0xFF);
753
754 if (max98927->v_l_slot < 8) {
755 regmap_update_bits(max98927->regmap,
756 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
757 1 << max98927->v_l_slot, 0);
758 regmap_update_bits(max98927->regmap,
759 MAX98927_R001A_PCM_TX_EN_A,
760 1 << max98927->v_l_slot,
761 1 << max98927->v_l_slot);
762 } else {
763 regmap_update_bits(max98927->regmap,
764 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
765 1 << (max98927->v_l_slot - 8), 0);
766 regmap_update_bits(max98927->regmap,
767 MAX98927_R001B_PCM_TX_EN_B,
768 1 << (max98927->v_l_slot - 8),
769 1 << (max98927->v_l_slot - 8));
770 }
771
772 if (max98927->i_l_slot < 8) {
773 regmap_update_bits(max98927->regmap,
774 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
775 1 << max98927->i_l_slot, 0);
776 regmap_update_bits(max98927->regmap,
777 MAX98927_R001A_PCM_TX_EN_A,
778 1 << max98927->i_l_slot,
779 1 << max98927->i_l_slot);
780 } else {
781 regmap_update_bits(max98927->regmap,
782 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
783 1 << (max98927->i_l_slot - 8), 0);
784 regmap_update_bits(max98927->regmap,
785 MAX98927_R001B_PCM_TX_EN_B,
786 1 << (max98927->i_l_slot - 8),
787 1 << (max98927->i_l_slot - 8));
788 }
789
790 /* Set interleave mode */
791 if (max98927->interleave_mode)
792 regmap_update_bits(max98927->regmap,
793 MAX98927_R001F_PCM_TX_CH_SRC_B,
794 MAX98927_PCM_TX_CH_INTERLEAVE_MASK,
795 MAX98927_PCM_TX_CH_INTERLEAVE_MASK);
796 return 0;
797}
798
799#ifdef CONFIG_PM_SLEEP
800static int max98927_suspend(struct device *dev)
801{
802 struct max98927_priv *max98927 = dev_get_drvdata(dev);
803
804 regcache_cache_only(max98927->regmap, true);
805 regcache_mark_dirty(max98927->regmap);
806 return 0;
807}
808static int max98927_resume(struct device *dev)
809{
810 struct max98927_priv *max98927 = dev_get_drvdata(dev);
811
812 regmap_write(max98927->regmap,
813 MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET);
814 regcache_cache_only(max98927->regmap, false);
815 regcache_sync(max98927->regmap);
816 return 0;
817}
818#endif
819
820static const struct dev_pm_ops max98927_pm = {
821 SET_SYSTEM_SLEEP_PM_OPS(max98927_suspend, max98927_resume)
822};
823
824static const struct snd_soc_component_driver soc_component_dev_max98927 = {
825 .probe = max98927_probe,
826 .controls = max98927_snd_controls,
827 .num_controls = ARRAY_SIZE(max98927_snd_controls),
828 .dapm_widgets = max98927_dapm_widgets,
829 .num_dapm_widgets = ARRAY_SIZE(max98927_dapm_widgets),
830 .dapm_routes = max98927_audio_map,
831 .num_dapm_routes = ARRAY_SIZE(max98927_audio_map),
832 .idle_bias_on = 1,
833 .use_pmdown_time = 1,
834 .endianness = 1,
835};
836
837static const struct regmap_config max98927_regmap = {
838 .reg_bits = 16,
839 .val_bits = 8,
840 .max_register = MAX98927_R01FF_REV_ID,
841 .reg_defaults = max98927_reg,
842 .num_reg_defaults = ARRAY_SIZE(max98927_reg),
843 .readable_reg = max98927_readable_register,
844 .volatile_reg = max98927_volatile_reg,
845 .cache_type = REGCACHE_RBTREE,
846};
847
848static void max98927_slot_config(struct i2c_client *i2c,
849 struct max98927_priv *max98927)
850{
851 int value;
852 struct device *dev = &i2c->dev;
853
854 if (!device_property_read_u32(dev, "vmon-slot-no", &value))
855 max98927->v_l_slot = value & 0xF;
856 else
857 max98927->v_l_slot = 0;
858
859 if (!device_property_read_u32(dev, "imon-slot-no", &value))
860 max98927->i_l_slot = value & 0xF;
861 else
862 max98927->i_l_slot = 1;
863}
864
865static int max98927_i2c_probe(struct i2c_client *i2c)
866{
867
868 int ret = 0, value;
869 int reg = 0;
870 struct max98927_priv *max98927 = NULL;
871
872 max98927 = devm_kzalloc(&i2c->dev,
873 sizeof(*max98927), GFP_KERNEL);
874
875 if (!max98927) {
876 ret = -ENOMEM;
877 return ret;
878 }
879 i2c_set_clientdata(i2c, max98927);
880
881 /* update interleave mode info */
882 if (!of_property_read_u32(i2c->dev.of_node,
883 "interleave_mode", &value)) {
884 if (value > 0)
885 max98927->interleave_mode = true;
886 else
887 max98927->interleave_mode = false;
888 } else
889 max98927->interleave_mode = false;
890
891 /* regmap initialization */
892 max98927->regmap
893 = devm_regmap_init_i2c(i2c, &max98927_regmap);
894 if (IS_ERR(max98927->regmap)) {
895 ret = PTR_ERR(max98927->regmap);
896 dev_err(&i2c->dev,
897 "Failed to allocate regmap: %d\n", ret);
898 return ret;
899 }
900
901 max98927->reset_gpio
902 = devm_gpiod_get_optional(&i2c->dev, "reset", GPIOD_OUT_HIGH);
903 if (IS_ERR(max98927->reset_gpio)) {
904 ret = PTR_ERR(max98927->reset_gpio);
905 return dev_err_probe(&i2c->dev, ret, "failed to request GPIO reset pin");
906 }
907
908 if (max98927->reset_gpio) {
909 gpiod_set_value_cansleep(max98927->reset_gpio, 0);
910 /* Wait for i2c port to be ready */
911 usleep_range(5000, 6000);
912 }
913
914 /* Check Revision ID */
915 ret = regmap_read(max98927->regmap,
916 MAX98927_R01FF_REV_ID, ®);
917 if (ret < 0) {
918 dev_err(&i2c->dev,
919 "Failed to read: 0x%02X\n", MAX98927_R01FF_REV_ID);
920 return ret;
921 }
922 dev_info(&i2c->dev, "MAX98927 revisionID: 0x%02X\n", reg);
923
924 /* voltage/current slot configuration */
925 max98927_slot_config(i2c, max98927);
926
927 /* codec registeration */
928 ret = devm_snd_soc_register_component(&i2c->dev,
929 &soc_component_dev_max98927,
930 max98927_dai, ARRAY_SIZE(max98927_dai));
931 if (ret < 0)
932 dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
933
934 return ret;
935}
936
937static void max98927_i2c_remove(struct i2c_client *i2c)
938{
939 struct max98927_priv *max98927 = i2c_get_clientdata(i2c);
940
941 if (max98927->reset_gpio) {
942 gpiod_set_value_cansleep(max98927->reset_gpio, 1);
943 }
944}
945
946static const struct i2c_device_id max98927_i2c_id[] = {
947 { "max98927", 0},
948 { },
949};
950
951MODULE_DEVICE_TABLE(i2c, max98927_i2c_id);
952
953#if defined(CONFIG_OF)
954static const struct of_device_id max98927_of_match[] = {
955 { .compatible = "maxim,max98927", },
956 { }
957};
958MODULE_DEVICE_TABLE(of, max98927_of_match);
959#endif
960
961#ifdef CONFIG_ACPI
962static const struct acpi_device_id max98927_acpi_match[] = {
963 { "MX98927", 0 },
964 {},
965};
966MODULE_DEVICE_TABLE(acpi, max98927_acpi_match);
967#endif
968
969static struct i2c_driver max98927_i2c_driver = {
970 .driver = {
971 .name = "max98927",
972 .of_match_table = of_match_ptr(max98927_of_match),
973 .acpi_match_table = ACPI_PTR(max98927_acpi_match),
974 .pm = &max98927_pm,
975 },
976 .probe_new = max98927_i2c_probe,
977 .remove = max98927_i2c_remove,
978 .id_table = max98927_i2c_id,
979};
980
981module_i2c_driver(max98927_i2c_driver)
982
983MODULE_DESCRIPTION("ALSA SoC MAX98927 driver");
984MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
985MODULE_LICENSE("GPL");