Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Analog Devices ADAU1372 Audio Codec driver
4 *
5 * Copyright 2016 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio/consumer.h>
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/mod_devicetable.h>
15#include <linux/pm.h>
16#include <linux/slab.h>
17
18#include <sound/core.h>
19#include <sound/pcm.h>
20#include <sound/pcm_params.h>
21#include <sound/tlv.h>
22#include <sound/soc.h>
23
24#include "adau1372.h"
25#include "adau-utils.h"
26
27struct adau1372 {
28 struct regmap *regmap;
29 void (*switch_mode)(struct device *dev);
30 bool use_pll;
31 bool enabled;
32 bool clock_provider;
33
34 struct snd_pcm_hw_constraint_list rate_constraints;
35 unsigned int slot_width;
36
37 struct clk *mclk;
38 struct gpio_desc *pd_gpio;
39 struct device *dev;
40};
41
42#define ADAU1372_REG_CLK_CTRL 0x00
43#define ADAU1372_REG_PLL(x) (0x01 + (x))
44#define ADAU1372_REG_DAC_SOURCE 0x11
45#define ADAU1372_REG_SOUT_SOURCE_0_1 0x13
46#define ADAU1372_REG_SOUT_SOURCE_2_3 0x14
47#define ADAU1372_REG_SOUT_SOURCE_4_5 0x15
48#define ADAU1372_REG_SOUT_SOURCE_6_7 0x16
49#define ADAU1372_REG_ADC_SDATA_CH 0x17
50#define ADAU1372_REG_ASRCO_SOURCE_0_1 0x18
51#define ADAU1372_REG_ASRCO_SOURCE_2_3 0x19
52#define ADAU1372_REG_ASRC_MODE 0x1a
53#define ADAU1372_REG_ADC_CTRL0 0x1b
54#define ADAU1372_REG_ADC_CTRL1 0x1c
55#define ADAU1372_REG_ADC_CTRL2 0x1d
56#define ADAU1372_REG_ADC_CTRL3 0x1e
57#define ADAU1372_REG_ADC_VOL(x) (0x1f + (x))
58#define ADAU1372_REG_PGA_CTRL(x) (0x23 + (x))
59#define ADAU1372_REG_PGA_BOOST 0x28
60#define ADAU1372_REG_MICBIAS 0x2d
61#define ADAU1372_REG_DAC_CTRL 0x2e
62#define ADAU1372_REG_DAC_VOL(x) (0x2f + (x))
63#define ADAU1372_REG_OP_STAGE_MUTE 0x31
64#define ADAU1372_REG_SAI0 0x32
65#define ADAU1372_REG_SAI1 0x33
66#define ADAU1372_REG_SOUT_CTRL 0x34
67#define ADAU1372_REG_MODE_MP(x) (0x38 + (x))
68#define ADAU1372_REG_OP_STAGE_CTRL 0x43
69#define ADAU1372_REG_DECIM_PWR 0x44
70#define ADAU1372_REG_INTERP_PWR 0x45
71#define ADAU1372_REG_BIAS_CTRL0 0x46
72#define ADAU1372_REG_BIAS_CTRL1 0x47
73
74#define ADAU1372_CLK_CTRL_PLL_EN BIT(7)
75#define ADAU1372_CLK_CTRL_XTAL_DIS BIT(4)
76#define ADAU1372_CLK_CTRL_CLKSRC BIT(3)
77#define ADAU1372_CLK_CTRL_CC_MDIV BIT(1)
78#define ADAU1372_CLK_CTRL_MCLK_EN BIT(0)
79
80#define ADAU1372_SAI0_DELAY1 (0x0 << 6)
81#define ADAU1372_SAI0_DELAY0 (0x1 << 6)
82#define ADAU1372_SAI0_DELAY_MASK (0x3 << 6)
83#define ADAU1372_SAI0_SAI_I2S (0x0 << 4)
84#define ADAU1372_SAI0_SAI_TDM2 (0x1 << 4)
85#define ADAU1372_SAI0_SAI_TDM4 (0x2 << 4)
86#define ADAU1372_SAI0_SAI_TDM8 (0x3 << 4)
87#define ADAU1372_SAI0_SAI_MASK (0x3 << 4)
88#define ADAU1372_SAI0_FS_48 0x0
89#define ADAU1372_SAI0_FS_8 0x1
90#define ADAU1372_SAI0_FS_12 0x2
91#define ADAU1372_SAI0_FS_16 0x3
92#define ADAU1372_SAI0_FS_24 0x4
93#define ADAU1372_SAI0_FS_32 0x5
94#define ADAU1372_SAI0_FS_96 0x6
95#define ADAU1372_SAI0_FS_192 0x7
96#define ADAU1372_SAI0_FS_MASK 0xf
97
98#define ADAU1372_SAI1_TDM_TS BIT(7)
99#define ADAU1372_SAI1_BCLK_TDMC BIT(6)
100#define ADAU1372_SAI1_LR_MODE BIT(5)
101#define ADAU1372_SAI1_LR_POL BIT(4)
102#define ADAU1372_SAI1_BCLKRATE BIT(2)
103#define ADAU1372_SAI1_BCLKEDGE BIT(1)
104#define ADAU1372_SAI1_MS BIT(0)
105
106static const unsigned int adau1372_rates[] = {
107 [ADAU1372_SAI0_FS_8] = 8000,
108 [ADAU1372_SAI0_FS_12] = 12000,
109 [ADAU1372_SAI0_FS_16] = 16000,
110 [ADAU1372_SAI0_FS_24] = 24000,
111 [ADAU1372_SAI0_FS_32] = 32000,
112 [ADAU1372_SAI0_FS_48] = 48000,
113 [ADAU1372_SAI0_FS_96] = 96000,
114 [ADAU1372_SAI0_FS_192] = 192000,
115};
116
117/* 8k, 12k, 24k, 48k */
118#define ADAU1372_RATE_MASK_TDM8 0x17
119/* + 16k, 96k */
120#define ADAU1372_RATE_MASK_TDM4_MASTER (ADAU1372_RATE_MASK_TDM8 | 0x48 | 0x20)
121/* +32k */
122#define ADAU1372_RATE_MASK_TDM4 (ADAU1372_RATE_MASK_TDM4_MASTER | 0x20)
123/* + 192k */
124#define ADAU1372_RATE_MASK_TDM2 (ADAU1372_RATE_MASK_TDM4 | 0x80)
125
126static const DECLARE_TLV_DB_MINMAX(adau1372_digital_tlv, -9563, 0);
127static const DECLARE_TLV_DB_SCALE(adau1372_pga_tlv, -1200, 75, 0);
128static const DECLARE_TLV_DB_SCALE(adau1372_pga_boost_tlv, 0, 1000, 0);
129
130static const char * const adau1372_bias_text[] = {
131 "Normal operation", "Extreme power saving", "Enhanced performance",
132 "Power saving",
133};
134
135static const unsigned int adau1372_bias_adc_values[] = {
136 0, 2, 3,
137};
138
139static const char * const adau1372_bias_adc_text[] = {
140 "Normal operation", "Enhanced performance", "Power saving",
141};
142
143static const char * const adau1372_bias_dac_text[] = {
144 "Normal operation", "Power saving", "Superior performance",
145 "Enhanced performance",
146};
147
148static SOC_ENUM_SINGLE_DECL(adau1372_bias_hp_enum,
149 ADAU1372_REG_BIAS_CTRL0, 6, adau1372_bias_text);
150static SOC_ENUM_SINGLE_DECL(adau1372_bias_afe0_1_enum,
151 ADAU1372_REG_BIAS_CTRL0, 4, adau1372_bias_text);
152static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_bias_adc2_3_enum,
153 ADAU1372_REG_BIAS_CTRL0, 2, 0x3, adau1372_bias_adc_text,
154 adau1372_bias_adc_values);
155static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_bias_adc0_1_enum,
156 ADAU1372_REG_BIAS_CTRL0, 0, 0x3, adau1372_bias_adc_text,
157 adau1372_bias_adc_values);
158static SOC_ENUM_SINGLE_DECL(adau1372_bias_afe2_3_enum,
159 ADAU1372_REG_BIAS_CTRL1, 4, adau1372_bias_text);
160static SOC_ENUM_SINGLE_DECL(adau1372_bias_mic_enum,
161 ADAU1372_REG_BIAS_CTRL1, 2, adau1372_bias_text);
162static SOC_ENUM_SINGLE_DECL(adau1372_bias_dac_enum,
163 ADAU1372_REG_BIAS_CTRL1, 0, adau1372_bias_dac_text);
164
165static const char * const adau1372_hpf_text[] = {
166 "Off",
167 "1 Hz",
168 "4 Hz",
169 "8 Hz",
170};
171
172static SOC_ENUM_SINGLE_DECL(adau1372_hpf0_1_enum, ADAU1372_REG_ADC_CTRL2, 5,
173 adau1372_hpf_text);
174static SOC_ENUM_SINGLE_DECL(adau1372_hpf2_3_enum, ADAU1372_REG_ADC_CTRL3, 5,
175 adau1372_hpf_text);
176static const struct snd_kcontrol_new adau1372_controls[] = {
177 SOC_SINGLE_TLV("ADC 0 Capture Volume", ADAU1372_REG_ADC_VOL(0),
178 0, 0xff, 1, adau1372_digital_tlv),
179 SOC_SINGLE_TLV("ADC 1 Capture Volume", ADAU1372_REG_ADC_VOL(1),
180 0, 0xff, 1, adau1372_digital_tlv),
181 SOC_SINGLE_TLV("ADC 2 Capture Volume", ADAU1372_REG_ADC_VOL(2),
182 0, 0xff, 1, adau1372_digital_tlv),
183 SOC_SINGLE_TLV("ADC 3 Capture Volume", ADAU1372_REG_ADC_VOL(3),
184 0, 0xff, 1, adau1372_digital_tlv),
185 SOC_SINGLE("ADC 0 Capture Switch", ADAU1372_REG_ADC_CTRL0, 3, 1, 1),
186 SOC_SINGLE("ADC 1 Capture Switch", ADAU1372_REG_ADC_CTRL0, 4, 1, 1),
187 SOC_SINGLE("ADC 2 Capture Switch", ADAU1372_REG_ADC_CTRL1, 3, 1, 1),
188 SOC_SINGLE("ADC 3 Capture Switch", ADAU1372_REG_ADC_CTRL1, 4, 1, 1),
189
190 SOC_ENUM("ADC 0+1 High-Pass-Filter", adau1372_hpf0_1_enum),
191 SOC_ENUM("ADC 2+3 High-Pass-Filter", adau1372_hpf2_3_enum),
192
193 SOC_SINGLE_TLV("PGA 0 Capture Volume", ADAU1372_REG_PGA_CTRL(0),
194 0, 0x3f, 0, adau1372_pga_tlv),
195 SOC_SINGLE_TLV("PGA 1 Capture Volume", ADAU1372_REG_PGA_CTRL(1),
196 0, 0x3f, 0, adau1372_pga_tlv),
197 SOC_SINGLE_TLV("PGA 2 Capture Volume", ADAU1372_REG_PGA_CTRL(2),
198 0, 0x3f, 0, adau1372_pga_tlv),
199 SOC_SINGLE_TLV("PGA 3 Capture Volume", ADAU1372_REG_PGA_CTRL(3),
200 0, 0x3f, 0, adau1372_pga_tlv),
201 SOC_SINGLE_TLV("PGA 0 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
202 0, 1, 0, adau1372_pga_boost_tlv),
203 SOC_SINGLE_TLV("PGA 1 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
204 1, 1, 0, adau1372_pga_boost_tlv),
205 SOC_SINGLE_TLV("PGA 2 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
206 2, 1, 0, adau1372_pga_boost_tlv),
207 SOC_SINGLE_TLV("PGA 3 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
208 3, 1, 0, adau1372_pga_boost_tlv),
209 SOC_SINGLE("PGA 0 Capture Switch", ADAU1372_REG_PGA_CTRL(0), 7, 1, 0),
210 SOC_SINGLE("PGA 1 Capture Switch", ADAU1372_REG_PGA_CTRL(1), 7, 1, 0),
211 SOC_SINGLE("PGA 2 Capture Switch", ADAU1372_REG_PGA_CTRL(2), 7, 1, 0),
212 SOC_SINGLE("PGA 3 Capture Switch", ADAU1372_REG_PGA_CTRL(3), 7, 1, 0),
213
214 SOC_SINGLE_TLV("DAC 0 Playback Volume", ADAU1372_REG_DAC_VOL(0),
215 0, 0xff, 1, adau1372_digital_tlv),
216 SOC_SINGLE_TLV("DAC 1 Playback Volume", ADAU1372_REG_DAC_VOL(1),
217 0, 0xff, 1, adau1372_digital_tlv),
218 SOC_SINGLE("DAC 0 Playback Switch", ADAU1372_REG_DAC_CTRL, 3, 1, 1),
219 SOC_SINGLE("DAC 1 Playback Switch", ADAU1372_REG_DAC_CTRL, 4, 1, 1),
220
221 SOC_ENUM("Headphone Bias", adau1372_bias_hp_enum),
222 SOC_ENUM("Microphone Bias", adau1372_bias_mic_enum),
223 SOC_ENUM("AFE 0+1 Bias", adau1372_bias_afe0_1_enum),
224 SOC_ENUM("AFE 2+3 Bias", adau1372_bias_afe2_3_enum),
225 SOC_ENUM("ADC 0+1 Bias", adau1372_bias_adc0_1_enum),
226 SOC_ENUM("ADC 2+3 Bias", adau1372_bias_adc2_3_enum),
227 SOC_ENUM("DAC 0+1 Bias", adau1372_bias_dac_enum),
228};
229
230static const char * const adau1372_decimator_mux_text[] = {
231 "ADC",
232 "DMIC",
233};
234
235static SOC_ENUM_SINGLE_DECL(adau1372_decimator0_1_mux_enum, ADAU1372_REG_ADC_CTRL2,
236 2, adau1372_decimator_mux_text);
237
238static const struct snd_kcontrol_new adau1372_decimator0_1_mux_control =
239 SOC_DAPM_ENUM("Decimator 0+1 Capture Mux", adau1372_decimator0_1_mux_enum);
240
241static SOC_ENUM_SINGLE_DECL(adau1372_decimator2_3_mux_enum, ADAU1372_REG_ADC_CTRL3,
242 2, adau1372_decimator_mux_text);
243
244static const struct snd_kcontrol_new adau1372_decimator2_3_mux_control =
245 SOC_DAPM_ENUM("Decimator 2+3 Capture Mux", adau1372_decimator2_3_mux_enum);
246
247static const unsigned int adau1372_asrco_mux_values[] = {
248 4, 5, 6, 7,
249};
250
251static const char * const adau1372_asrco_mux_text[] = {
252 "Decimator0",
253 "Decimator1",
254 "Decimator2",
255 "Decimator3",
256};
257
258static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco0_mux_enum, ADAU1372_REG_ASRCO_SOURCE_0_1,
259 0, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
260static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco1_mux_enum, ADAU1372_REG_ASRCO_SOURCE_0_1,
261 4, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
262static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco2_mux_enum, ADAU1372_REG_ASRCO_SOURCE_2_3,
263 0, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
264static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco3_mux_enum, ADAU1372_REG_ASRCO_SOURCE_2_3,
265 4, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
266
267static const struct snd_kcontrol_new adau1372_asrco0_mux_control =
268 SOC_DAPM_ENUM("Output ASRC0 Capture Mux", adau1372_asrco0_mux_enum);
269static const struct snd_kcontrol_new adau1372_asrco1_mux_control =
270 SOC_DAPM_ENUM("Output ASRC1 Capture Mux", adau1372_asrco1_mux_enum);
271static const struct snd_kcontrol_new adau1372_asrco2_mux_control =
272 SOC_DAPM_ENUM("Output ASRC2 Capture Mux", adau1372_asrco2_mux_enum);
273static const struct snd_kcontrol_new adau1372_asrco3_mux_control =
274 SOC_DAPM_ENUM("Output ASRC3 Capture Mux", adau1372_asrco3_mux_enum);
275
276static const unsigned int adau1372_sout_mux_values[] = {
277 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
278};
279
280static const char * const adau1372_sout_mux_text[] = {
281 "Output ASRC0",
282 "Output ASRC1",
283 "Output ASRC2",
284 "Output ASRC3",
285 "Serial Input 0",
286 "Serial Input 1",
287 "Serial Input 2",
288 "Serial Input 3",
289 "Serial Input 4",
290 "Serial Input 5",
291 "Serial Input 6",
292 "Serial Input 7",
293};
294
295static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout0_mux_enum, ADAU1372_REG_SOUT_SOURCE_0_1,
296 0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
297static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout1_mux_enum, ADAU1372_REG_SOUT_SOURCE_0_1,
298 4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
299static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout2_mux_enum, ADAU1372_REG_SOUT_SOURCE_2_3,
300 0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
301static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout3_mux_enum, ADAU1372_REG_SOUT_SOURCE_2_3,
302 4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
303static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout4_mux_enum, ADAU1372_REG_SOUT_SOURCE_4_5,
304 0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
305static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout5_mux_enum, ADAU1372_REG_SOUT_SOURCE_4_5,
306 4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
307static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout6_mux_enum, ADAU1372_REG_SOUT_SOURCE_6_7,
308 0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
309static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout7_mux_enum, ADAU1372_REG_SOUT_SOURCE_6_7,
310 4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
311
312static const struct snd_kcontrol_new adau1372_sout0_mux_control =
313 SOC_DAPM_ENUM("Serial Output 0 Capture Mux", adau1372_sout0_mux_enum);
314static const struct snd_kcontrol_new adau1372_sout1_mux_control =
315 SOC_DAPM_ENUM("Serial Output 1 Capture Mux", adau1372_sout1_mux_enum);
316static const struct snd_kcontrol_new adau1372_sout2_mux_control =
317 SOC_DAPM_ENUM("Serial Output 2 Capture Mux", adau1372_sout2_mux_enum);
318static const struct snd_kcontrol_new adau1372_sout3_mux_control =
319 SOC_DAPM_ENUM("Serial Output 3 Capture Mux", adau1372_sout3_mux_enum);
320static const struct snd_kcontrol_new adau1372_sout4_mux_control =
321 SOC_DAPM_ENUM("Serial Output 4 Capture Mux", adau1372_sout4_mux_enum);
322static const struct snd_kcontrol_new adau1372_sout5_mux_control =
323 SOC_DAPM_ENUM("Serial Output 5 Capture Mux", adau1372_sout5_mux_enum);
324static const struct snd_kcontrol_new adau1372_sout6_mux_control =
325 SOC_DAPM_ENUM("Serial Output 6 Capture Mux", adau1372_sout6_mux_enum);
326static const struct snd_kcontrol_new adau1372_sout7_mux_control =
327 SOC_DAPM_ENUM("Serial Output 7 Capture Mux", adau1372_sout7_mux_enum);
328
329static const char * const adau1372_asrci_mux_text[] = {
330 "Serial Input 0+1",
331 "Serial Input 2+3",
332 "Serial Input 4+5",
333 "Serial Input 6+7",
334};
335
336static SOC_ENUM_SINGLE_DECL(adau1372_asrci_mux_enum,
337 ADAU1372_REG_ASRC_MODE, 2, adau1372_asrci_mux_text);
338
339static const struct snd_kcontrol_new adau1372_asrci_mux_control =
340 SOC_DAPM_ENUM("Input ASRC Playback Mux", adau1372_asrci_mux_enum);
341
342static const unsigned int adau1372_dac_mux_values[] = {
343 12, 13
344};
345
346static const char * const adau1372_dac_mux_text[] = {
347 "Input ASRC0",
348 "Input ASRC1",
349};
350
351static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_dac0_mux_enum, ADAU1372_REG_DAC_SOURCE,
352 0, 0xf, adau1372_dac_mux_text, adau1372_dac_mux_values);
353static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_dac1_mux_enum, ADAU1372_REG_DAC_SOURCE,
354 4, 0xf, adau1372_dac_mux_text, adau1372_dac_mux_values);
355
356static const struct snd_kcontrol_new adau1372_dac0_mux_control =
357 SOC_DAPM_ENUM("DAC 0 Playback Mux", adau1372_dac0_mux_enum);
358static const struct snd_kcontrol_new adau1372_dac1_mux_control =
359 SOC_DAPM_ENUM("DAC 1 Playback Mux", adau1372_dac1_mux_enum);
360
361static const struct snd_soc_dapm_widget adau1372_dapm_widgets[] = {
362 SND_SOC_DAPM_INPUT("AIN0"),
363 SND_SOC_DAPM_INPUT("AIN1"),
364 SND_SOC_DAPM_INPUT("AIN2"),
365 SND_SOC_DAPM_INPUT("AIN3"),
366 SND_SOC_DAPM_INPUT("DMIC0_1"),
367 SND_SOC_DAPM_INPUT("DMIC2_3"),
368
369 SND_SOC_DAPM_SUPPLY("MICBIAS0", ADAU1372_REG_MICBIAS, 4, 0, NULL, 0),
370 SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1372_REG_MICBIAS, 5, 0, NULL, 0),
371
372 SND_SOC_DAPM_PGA("PGA0", ADAU1372_REG_PGA_CTRL(0), 6, 1, NULL, 0),
373 SND_SOC_DAPM_PGA("PGA1", ADAU1372_REG_PGA_CTRL(1), 6, 1, NULL, 0),
374 SND_SOC_DAPM_PGA("PGA2", ADAU1372_REG_PGA_CTRL(2), 6, 1, NULL, 0),
375 SND_SOC_DAPM_PGA("PGA3", ADAU1372_REG_PGA_CTRL(3), 6, 1, NULL, 0),
376 SND_SOC_DAPM_ADC("ADC0", NULL, ADAU1372_REG_ADC_CTRL2, 0, 0),
377 SND_SOC_DAPM_ADC("ADC1", NULL, ADAU1372_REG_ADC_CTRL2, 1, 0),
378 SND_SOC_DAPM_ADC("ADC2", NULL, ADAU1372_REG_ADC_CTRL3, 0, 0),
379 SND_SOC_DAPM_ADC("ADC3", NULL, ADAU1372_REG_ADC_CTRL3, 1, 0),
380
381 SND_SOC_DAPM_SUPPLY("ADC0 Filter", ADAU1372_REG_DECIM_PWR, 0, 0, NULL, 0),
382 SND_SOC_DAPM_SUPPLY("ADC1 Filter", ADAU1372_REG_DECIM_PWR, 1, 0, NULL, 0),
383 SND_SOC_DAPM_SUPPLY("ADC2 Filter", ADAU1372_REG_DECIM_PWR, 2, 0, NULL, 0),
384 SND_SOC_DAPM_SUPPLY("ADC3 Filter", ADAU1372_REG_DECIM_PWR, 3, 0, NULL, 0),
385 SND_SOC_DAPM_SUPPLY("Output ASRC0 Decimator", ADAU1372_REG_DECIM_PWR, 4, 0, NULL, 0),
386 SND_SOC_DAPM_SUPPLY("Output ASRC1 Decimator", ADAU1372_REG_DECIM_PWR, 5, 0, NULL, 0),
387 SND_SOC_DAPM_SUPPLY("Output ASRC2 Decimator", ADAU1372_REG_DECIM_PWR, 6, 0, NULL, 0),
388 SND_SOC_DAPM_SUPPLY("Output ASRC3 Decimator", ADAU1372_REG_DECIM_PWR, 7, 0, NULL, 0),
389
390 SND_SOC_DAPM_MUX("Decimator0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator0_1_mux_control),
391 SND_SOC_DAPM_MUX("Decimator1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator0_1_mux_control),
392 SND_SOC_DAPM_MUX("Decimator2 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator2_3_mux_control),
393 SND_SOC_DAPM_MUX("Decimator3 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator2_3_mux_control),
394
395 SND_SOC_DAPM_MUX("Output ASRC0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco0_mux_control),
396 SND_SOC_DAPM_MUX("Output ASRC1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco1_mux_control),
397 SND_SOC_DAPM_MUX("Output ASRC2 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco2_mux_control),
398 SND_SOC_DAPM_MUX("Output ASRC3 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco3_mux_control),
399 SND_SOC_DAPM_MUX("Serial Output 0 Capture Mux", SND_SOC_NOPM, 0, 0,
400 &adau1372_sout0_mux_control),
401 SND_SOC_DAPM_MUX("Serial Output 1 Capture Mux", SND_SOC_NOPM, 0, 0,
402 &adau1372_sout1_mux_control),
403 SND_SOC_DAPM_MUX("Serial Output 2 Capture Mux", SND_SOC_NOPM, 0, 0,
404 &adau1372_sout2_mux_control),
405 SND_SOC_DAPM_MUX("Serial Output 3 Capture Mux", SND_SOC_NOPM, 0, 0,
406 &adau1372_sout3_mux_control),
407 SND_SOC_DAPM_MUX("Serial Output 4 Capture Mux", SND_SOC_NOPM, 0, 0,
408 &adau1372_sout4_mux_control),
409 SND_SOC_DAPM_MUX("Serial Output 5 Capture Mux", SND_SOC_NOPM, 0, 0,
410 &adau1372_sout5_mux_control),
411 SND_SOC_DAPM_MUX("Serial Output 6 Capture Mux", SND_SOC_NOPM, 0, 0,
412 &adau1372_sout6_mux_control),
413 SND_SOC_DAPM_MUX("Serial Output 7 Capture Mux", SND_SOC_NOPM, 0, 0,
414 &adau1372_sout7_mux_control),
415
416 SND_SOC_DAPM_AIF_IN("Serial Input 0", NULL, 0, SND_SOC_NOPM, 0, 0),
417 SND_SOC_DAPM_AIF_IN("Serial Input 1", NULL, 1, SND_SOC_NOPM, 0, 0),
418 SND_SOC_DAPM_AIF_IN("Serial Input 2", NULL, 2, SND_SOC_NOPM, 0, 0),
419 SND_SOC_DAPM_AIF_IN("Serial Input 3", NULL, 3, SND_SOC_NOPM, 0, 0),
420 SND_SOC_DAPM_AIF_IN("Serial Input 4", NULL, 4, SND_SOC_NOPM, 0, 0),
421 SND_SOC_DAPM_AIF_IN("Serial Input 5", NULL, 5, SND_SOC_NOPM, 0, 0),
422 SND_SOC_DAPM_AIF_IN("Serial Input 6", NULL, 6, SND_SOC_NOPM, 0, 0),
423 SND_SOC_DAPM_AIF_IN("Serial Input 7", NULL, 7, SND_SOC_NOPM, 0, 0),
424
425 SND_SOC_DAPM_AIF_OUT("Serial Output 0", NULL, 0, SND_SOC_NOPM, 0, 0),
426 SND_SOC_DAPM_AIF_OUT("Serial Output 1", NULL, 1, SND_SOC_NOPM, 0, 0),
427 SND_SOC_DAPM_AIF_OUT("Serial Output 2", NULL, 2, SND_SOC_NOPM, 0, 0),
428 SND_SOC_DAPM_AIF_OUT("Serial Output 3", NULL, 3, SND_SOC_NOPM, 0, 0),
429 SND_SOC_DAPM_AIF_OUT("Serial Output 4", NULL, 4, SND_SOC_NOPM, 0, 0),
430 SND_SOC_DAPM_AIF_OUT("Serial Output 5", NULL, 5, SND_SOC_NOPM, 0, 0),
431 SND_SOC_DAPM_AIF_OUT("Serial Output 6", NULL, 6, SND_SOC_NOPM, 0, 0),
432 SND_SOC_DAPM_AIF_OUT("Serial Output 7", NULL, 7, SND_SOC_NOPM, 0, 0),
433
434 SND_SOC_DAPM_SUPPLY("Output ASRC Supply", ADAU1372_REG_ASRC_MODE, 1, 0, NULL, 0),
435 SND_SOC_DAPM_SUPPLY("Input ASRC Supply", ADAU1372_REG_ASRC_MODE, 0, 0, NULL, 0),
436
437 SND_SOC_DAPM_SUPPLY("DAC1 Modulator", ADAU1372_REG_INTERP_PWR, 3, 0, NULL, 0),
438 SND_SOC_DAPM_SUPPLY("DAC0 Modulator", ADAU1372_REG_INTERP_PWR, 2, 0, NULL, 0),
439 SND_SOC_DAPM_SUPPLY("Input ASRC1 Interpolator", ADAU1372_REG_INTERP_PWR, 1, 0, NULL, 0),
440 SND_SOC_DAPM_SUPPLY("Input ASRC0 Interpolator", ADAU1372_REG_INTERP_PWR, 0, 0, NULL, 0),
441
442 SND_SOC_DAPM_MUX("Input ASRC0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrci_mux_control),
443 SND_SOC_DAPM_MUX("Input ASRC1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrci_mux_control),
444
445 SND_SOC_DAPM_MUX("DAC 0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_dac0_mux_control),
446 SND_SOC_DAPM_MUX("DAC 1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_dac1_mux_control),
447
448 SND_SOC_DAPM_DAC("DAC0", NULL, ADAU1372_REG_DAC_CTRL, 0, 0),
449 SND_SOC_DAPM_DAC("DAC1", NULL, ADAU1372_REG_DAC_CTRL, 1, 0),
450
451 SND_SOC_DAPM_OUT_DRV("OP_STAGE_LP", ADAU1372_REG_OP_STAGE_CTRL, 0, 1, NULL, 0),
452 SND_SOC_DAPM_OUT_DRV("OP_STAGE_LN", ADAU1372_REG_OP_STAGE_CTRL, 1, 1, NULL, 0),
453 SND_SOC_DAPM_OUT_DRV("OP_STAGE_RP", ADAU1372_REG_OP_STAGE_CTRL, 2, 1, NULL, 0),
454 SND_SOC_DAPM_OUT_DRV("OP_STAGE_RN", ADAU1372_REG_OP_STAGE_CTRL, 3, 1, NULL, 0),
455
456 SND_SOC_DAPM_OUTPUT("HPOUTL"),
457 SND_SOC_DAPM_OUTPUT("HPOUTR"),
458};
459
460#define ADAU1372_SOUT_ROUTES(x) \
461 { "Serial Output " #x " Capture Mux", "Output ASRC0", "Output ASRC0 Mux" }, \
462 { "Serial Output " #x " Capture Mux", "Output ASRC1", "Output ASRC1 Mux" }, \
463 { "Serial Output " #x " Capture Mux", "Output ASRC2", "Output ASRC2 Mux" }, \
464 { "Serial Output " #x " Capture Mux", "Output ASRC3", "Output ASRC3 Mux" }, \
465 { "Serial Output " #x " Capture Mux", "Serial Input 0", "Serial Input 0" }, \
466 { "Serial Output " #x " Capture Mux", "Serial Input 1", "Serial Input 1" }, \
467 { "Serial Output " #x " Capture Mux", "Serial Input 2", "Serial Input 2" }, \
468 { "Serial Output " #x " Capture Mux", "Serial Input 3", "Serial Input 3" }, \
469 { "Serial Output " #x " Capture Mux", "Serial Input 4", "Serial Input 4" }, \
470 { "Serial Output " #x " Capture Mux", "Serial Input 5", "Serial Input 5" }, \
471 { "Serial Output " #x " Capture Mux", "Serial Input 6", "Serial Input 6" }, \
472 { "Serial Output " #x " Capture Mux", "Serial Input 7", "Serial Input 7" }, \
473 { "Serial Output " #x, NULL, "Serial Output " #x " Capture Mux" }, \
474 { "Capture", NULL, "Serial Output " #x }
475
476#define ADAU1372_ASRCO_ROUTES(x) \
477 { "Output ASRC" #x " Mux", "Decimator0", "Decimator0 Mux" }, \
478 { "Output ASRC" #x " Mux", "Decimator1", "Decimator1 Mux" }, \
479 { "Output ASRC" #x " Mux", "Decimator2", "Decimator2 Mux" }, \
480 { "Output ASRC" #x " Mux", "Decimator3", "Decimator3 Mux" }
481
482static const struct snd_soc_dapm_route adau1372_dapm_routes[] = {
483 { "PGA0", NULL, "AIN0" },
484 { "PGA1", NULL, "AIN1" },
485 { "PGA2", NULL, "AIN2" },
486 { "PGA3", NULL, "AIN3" },
487
488 { "ADC0", NULL, "PGA0" },
489 { "ADC1", NULL, "PGA1" },
490 { "ADC2", NULL, "PGA2" },
491 { "ADC3", NULL, "PGA3" },
492
493 { "Decimator0 Mux", "ADC", "ADC0" },
494 { "Decimator1 Mux", "ADC", "ADC1" },
495 { "Decimator2 Mux", "ADC", "ADC2" },
496 { "Decimator3 Mux", "ADC", "ADC3" },
497
498 { "Decimator0 Mux", "DMIC", "DMIC0_1" },
499 { "Decimator1 Mux", "DMIC", "DMIC0_1" },
500 { "Decimator2 Mux", "DMIC", "DMIC2_3" },
501 { "Decimator3 Mux", "DMIC", "DMIC2_3" },
502
503 { "Decimator0 Mux", NULL, "ADC0 Filter" },
504 { "Decimator1 Mux", NULL, "ADC1 Filter" },
505 { "Decimator2 Mux", NULL, "ADC2 Filter" },
506 { "Decimator3 Mux", NULL, "ADC3 Filter" },
507
508 { "Output ASRC0 Mux", NULL, "Output ASRC Supply" },
509 { "Output ASRC1 Mux", NULL, "Output ASRC Supply" },
510 { "Output ASRC2 Mux", NULL, "Output ASRC Supply" },
511 { "Output ASRC3 Mux", NULL, "Output ASRC Supply" },
512 { "Output ASRC0 Mux", NULL, "Output ASRC0 Decimator" },
513 { "Output ASRC1 Mux", NULL, "Output ASRC1 Decimator" },
514 { "Output ASRC2 Mux", NULL, "Output ASRC2 Decimator" },
515 { "Output ASRC3 Mux", NULL, "Output ASRC3 Decimator" },
516
517 ADAU1372_ASRCO_ROUTES(0),
518 ADAU1372_ASRCO_ROUTES(1),
519 ADAU1372_ASRCO_ROUTES(2),
520 ADAU1372_ASRCO_ROUTES(3),
521
522 ADAU1372_SOUT_ROUTES(0),
523 ADAU1372_SOUT_ROUTES(1),
524 ADAU1372_SOUT_ROUTES(2),
525 ADAU1372_SOUT_ROUTES(3),
526 ADAU1372_SOUT_ROUTES(4),
527 ADAU1372_SOUT_ROUTES(5),
528 ADAU1372_SOUT_ROUTES(6),
529 ADAU1372_SOUT_ROUTES(7),
530
531 { "Serial Input 0", NULL, "Playback" },
532 { "Serial Input 1", NULL, "Playback" },
533 { "Serial Input 2", NULL, "Playback" },
534 { "Serial Input 3", NULL, "Playback" },
535 { "Serial Input 4", NULL, "Playback" },
536 { "Serial Input 5", NULL, "Playback" },
537 { "Serial Input 6", NULL, "Playback" },
538 { "Serial Input 7", NULL, "Playback" },
539
540 { "Input ASRC0 Mux", "Serial Input 0+1", "Serial Input 0" },
541 { "Input ASRC1 Mux", "Serial Input 0+1", "Serial Input 1" },
542 { "Input ASRC0 Mux", "Serial Input 2+3", "Serial Input 2" },
543 { "Input ASRC1 Mux", "Serial Input 2+3", "Serial Input 3" },
544 { "Input ASRC0 Mux", "Serial Input 4+5", "Serial Input 4" },
545 { "Input ASRC1 Mux", "Serial Input 4+5", "Serial Input 5" },
546 { "Input ASRC0 Mux", "Serial Input 6+7", "Serial Input 6" },
547 { "Input ASRC1 Mux", "Serial Input 6+7", "Serial Input 7" },
548 { "Input ASRC0 Mux", NULL, "Input ASRC Supply" },
549 { "Input ASRC1 Mux", NULL, "Input ASRC Supply" },
550 { "Input ASRC0 Mux", NULL, "Input ASRC0 Interpolator" },
551 { "Input ASRC1 Mux", NULL, "Input ASRC1 Interpolator" },
552
553 { "DAC 0 Mux", "Input ASRC0", "Input ASRC0 Mux" },
554 { "DAC 0 Mux", "Input ASRC1", "Input ASRC1 Mux" },
555 { "DAC 1 Mux", "Input ASRC0", "Input ASRC0 Mux" },
556 { "DAC 1 Mux", "Input ASRC1", "Input ASRC1 Mux" },
557
558 { "DAC0", NULL, "DAC 0 Mux" },
559 { "DAC1", NULL, "DAC 1 Mux" },
560 { "DAC0", NULL, "DAC0 Modulator" },
561 { "DAC1", NULL, "DAC1 Modulator" },
562
563 { "OP_STAGE_LP", NULL, "DAC0" },
564 { "OP_STAGE_LN", NULL, "DAC0" },
565 { "OP_STAGE_RP", NULL, "DAC1" },
566 { "OP_STAGE_RN", NULL, "DAC1" },
567
568 { "HPOUTL", NULL, "OP_STAGE_LP" },
569 { "HPOUTL", NULL, "OP_STAGE_LN" },
570 { "HPOUTR", NULL, "OP_STAGE_RP" },
571 { "HPOUTR", NULL, "OP_STAGE_RN" },
572};
573
574static int adau1372_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
575{
576 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
577 unsigned int sai0 = 0, sai1 = 0;
578 bool invert_lrclk = false;
579
580 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
581 case SND_SOC_DAIFMT_CBP_CFP:
582 adau1372->clock_provider = true;
583 sai1 |= ADAU1372_SAI1_MS;
584 break;
585 case SND_SOC_DAIFMT_CBC_CFC:
586 adau1372->clock_provider = false;
587 break;
588 default:
589 return -EINVAL;
590 }
591
592 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
593 case SND_SOC_DAIFMT_NB_NF:
594 invert_lrclk = false;
595 break;
596 case SND_SOC_DAIFMT_NB_IF:
597 invert_lrclk = true;
598 break;
599 case SND_SOC_DAIFMT_IB_NF:
600 invert_lrclk = false;
601 sai1 |= ADAU1372_SAI1_BCLKEDGE;
602 break;
603 case SND_SOC_DAIFMT_IB_IF:
604 invert_lrclk = true;
605 sai1 |= ADAU1372_SAI1_BCLKEDGE;
606 break;
607 }
608
609 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
610 case SND_SOC_DAIFMT_I2S:
611 sai0 |= ADAU1372_SAI0_DELAY1;
612 break;
613 case SND_SOC_DAIFMT_LEFT_J:
614 sai0 |= ADAU1372_SAI0_DELAY0;
615 invert_lrclk = !invert_lrclk;
616 break;
617 case SND_SOC_DAIFMT_DSP_A:
618 sai0 |= ADAU1372_SAI0_DELAY1;
619 sai1 |= ADAU1372_SAI1_LR_MODE;
620 break;
621 case SND_SOC_DAIFMT_DSP_B:
622 sai0 |= ADAU1372_SAI0_DELAY0;
623 sai1 |= ADAU1372_SAI1_LR_MODE;
624 break;
625 }
626
627 if (invert_lrclk)
628 sai1 |= ADAU1372_SAI1_LR_POL;
629
630 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_DELAY_MASK, sai0);
631 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1,
632 ADAU1372_SAI1_MS | ADAU1372_SAI1_BCLKEDGE |
633 ADAU1372_SAI1_LR_MODE | ADAU1372_SAI1_LR_POL, sai1);
634
635 return 0;
636}
637
638static int adau1372_hw_params(struct snd_pcm_substream *substream,
639 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
640{
641 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
642 unsigned int rate = params_rate(params);
643 unsigned int slot_width;
644 unsigned int sai0, sai1;
645 unsigned int i;
646
647 for (i = 0; i < ARRAY_SIZE(adau1372_rates); i++) {
648 if (rate == adau1372_rates[i])
649 break;
650 }
651
652 if (i == ARRAY_SIZE(adau1372_rates))
653 return -EINVAL;
654
655 sai0 = i;
656
657 slot_width = adau1372->slot_width;
658 if (slot_width == 0)
659 slot_width = params_width(params);
660
661 switch (slot_width) {
662 case 16:
663 sai1 = ADAU1372_SAI1_BCLKRATE;
664 break;
665 case 24:
666 case 32:
667 sai1 = 0;
668 break;
669 default:
670 return -EINVAL;
671 }
672
673 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_FS_MASK, sai0);
674 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLKRATE, sai1);
675
676 return 0;
677}
678
679static int adau1372_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
680 unsigned int rx_mask, int slots, int width)
681{
682 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
683 unsigned int sai0, sai1;
684
685 /* I2S mode */
686 if (slots == 0) {
687 /* The other settings dont matter in I2S mode */
688 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0,
689 ADAU1372_SAI0_SAI_MASK, ADAU1372_SAI0_SAI_I2S);
690 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
691 adau1372->slot_width = 0;
692 return 0;
693 }
694
695 /* We have 8 channels anything outside that is not supported */
696 if ((tx_mask & ~0xff) != 0 || (rx_mask & ~0xff) != 0)
697 return -EINVAL;
698
699 switch (width) {
700 case 16:
701 sai1 = ADAU1372_SAI1_BCLK_TDMC;
702 break;
703 case 24:
704 case 32:
705 sai1 = 0;
706 break;
707 default:
708 return -EINVAL;
709 }
710
711 switch (slots) {
712 case 2:
713 sai0 = ADAU1372_SAI0_SAI_TDM2;
714 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
715 break;
716 case 4:
717 sai0 = ADAU1372_SAI0_SAI_TDM4;
718 if (adau1372->clock_provider)
719 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4_MASTER;
720 else
721 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4;
722 break;
723 case 8:
724 sai0 = ADAU1372_SAI0_SAI_TDM8;
725 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM8;
726 break;
727 default:
728 return -EINVAL;
729 }
730
731 adau1372->slot_width = width;
732
733 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_SAI_MASK, sai0);
734 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLK_TDMC, sai1);
735
736 /* Mask is inverted in hardware */
737 regmap_write(adau1372->regmap, ADAU1372_REG_SOUT_CTRL, ~tx_mask);
738
739 return 0;
740}
741
742static int adau1372_set_tristate(struct snd_soc_dai *dai, int tristate)
743{
744 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
745 unsigned int sai1;
746
747 if (tristate)
748 sai1 = ADAU1372_SAI1_TDM_TS;
749 else
750 sai1 = 0;
751
752 return regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_TDM_TS, sai1);
753}
754
755static int adau1372_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
756{
757 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
758
759 snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
760 &adau1372->rate_constraints);
761
762 return 0;
763}
764
765static void adau1372_enable_pll(struct adau1372 *adau1372)
766{
767 unsigned int val, timeout = 0;
768 int ret;
769
770 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
771 ADAU1372_CLK_CTRL_PLL_EN, ADAU1372_CLK_CTRL_PLL_EN);
772 do {
773 /* Takes about 1ms to lock */
774 usleep_range(1000, 2000);
775 ret = regmap_read(adau1372->regmap, ADAU1372_REG_PLL(5), &val);
776 if (ret)
777 break;
778 timeout++;
779 } while (!(val & 1) && timeout < 3);
780
781 if (ret < 0 || !(val & 1))
782 dev_err(adau1372->dev, "Failed to lock PLL\n");
783}
784
785static void adau1372_set_power(struct adau1372 *adau1372, bool enable)
786{
787 if (adau1372->enabled == enable)
788 return;
789
790 if (enable) {
791 unsigned int clk_ctrl = ADAU1372_CLK_CTRL_MCLK_EN;
792
793 clk_prepare_enable(adau1372->mclk);
794 if (adau1372->pd_gpio)
795 gpiod_set_value(adau1372->pd_gpio, 0);
796
797 if (adau1372->switch_mode)
798 adau1372->switch_mode(adau1372->dev);
799
800 regcache_cache_only(adau1372->regmap, false);
801
802 /*
803 * Clocks needs to be enabled before any other register can be
804 * accessed.
805 */
806 if (adau1372->use_pll) {
807 adau1372_enable_pll(adau1372);
808 clk_ctrl |= ADAU1372_CLK_CTRL_CLKSRC;
809 }
810
811 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
812 ADAU1372_CLK_CTRL_MCLK_EN | ADAU1372_CLK_CTRL_CLKSRC, clk_ctrl);
813 regcache_sync(adau1372->regmap);
814 } else {
815 if (adau1372->pd_gpio) {
816 /*
817 * This will turn everything off and reset the register
818 * map. No need to do any register writes to manually
819 * turn things off.
820 */
821 gpiod_set_value(adau1372->pd_gpio, 1);
822 regcache_mark_dirty(adau1372->regmap);
823 } else {
824 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
825 ADAU1372_CLK_CTRL_MCLK_EN | ADAU1372_CLK_CTRL_PLL_EN, 0);
826 }
827 clk_disable_unprepare(adau1372->mclk);
828 regcache_cache_only(adau1372->regmap, true);
829 }
830
831 adau1372->enabled = enable;
832}
833
834static int adau1372_set_bias_level(struct snd_soc_component *component,
835 enum snd_soc_bias_level level)
836{
837 struct adau1372 *adau1372 = snd_soc_component_get_drvdata(component);
838
839 switch (level) {
840 case SND_SOC_BIAS_ON:
841 break;
842 case SND_SOC_BIAS_PREPARE:
843 break;
844 case SND_SOC_BIAS_STANDBY:
845 adau1372_set_power(adau1372, true);
846 break;
847 case SND_SOC_BIAS_OFF:
848 adau1372_set_power(adau1372, false);
849 break;
850 }
851
852 return 0;
853}
854
855static const struct snd_soc_component_driver adau1372_driver = {
856 .set_bias_level = adau1372_set_bias_level,
857 .controls = adau1372_controls,
858 .num_controls = ARRAY_SIZE(adau1372_controls),
859 .dapm_widgets = adau1372_dapm_widgets,
860 .num_dapm_widgets = ARRAY_SIZE(adau1372_dapm_widgets),
861 .dapm_routes = adau1372_dapm_routes,
862 .num_dapm_routes = ARRAY_SIZE(adau1372_dapm_routes),
863 .endianness = 1,
864};
865
866static const struct snd_soc_dai_ops adau1372_dai_ops = {
867 .set_fmt = adau1372_set_dai_fmt,
868 .set_tdm_slot = adau1372_set_tdm_slot,
869 .set_tristate = adau1372_set_tristate,
870 .hw_params = adau1372_hw_params,
871 .startup = adau1372_startup,
872};
873
874#define ADAU1372_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
875 SNDRV_PCM_FMTBIT_S24_LE | \
876 SNDRV_PCM_FMTBIT_S32_LE)
877
878static struct snd_soc_dai_driver adau1372_dai_driver = {
879 .name = "adau1372",
880 .playback = {
881 .stream_name = "Playback",
882 .channels_min = 2,
883 .channels_max = 8,
884 .rates = SNDRV_PCM_RATE_KNOT,
885 .formats = ADAU1372_FORMATS,
886 .sig_bits = 24,
887 },
888 .capture = {
889 .stream_name = "Capture",
890 .channels_min = 2,
891 .channels_max = 8,
892 .rates = SNDRV_PCM_RATE_KNOT,
893 .formats = ADAU1372_FORMATS,
894 .sig_bits = 24,
895 },
896 .ops = &adau1372_dai_ops,
897 .symmetric_rate = 1,
898};
899
900static int adau1372_setup_pll(struct adau1372 *adau1372, unsigned int rate)
901{
902 u8 regs[5];
903 unsigned int i;
904 int ret;
905
906 ret = adau_calc_pll_cfg(rate, 49152000, regs);
907 if (ret < 0)
908 return ret;
909
910 for (i = 0; i < ARRAY_SIZE(regs); i++)
911 regmap_write(adau1372->regmap, ADAU1372_REG_PLL(i), regs[i]);
912
913 return 0;
914}
915
916int adau1372_probe(struct device *dev, struct regmap *regmap,
917 void (*switch_mode)(struct device *dev))
918{
919 struct adau1372 *adau1372;
920 unsigned int clk_ctrl;
921 unsigned long rate;
922 int ret;
923
924 if (IS_ERR(regmap))
925 return PTR_ERR(regmap);
926
927 adau1372 = devm_kzalloc(dev, sizeof(*adau1372), GFP_KERNEL);
928 if (!adau1372)
929 return -ENOMEM;
930
931 adau1372->mclk = devm_clk_get(dev, "mclk");
932 if (IS_ERR(adau1372->mclk))
933 return PTR_ERR(adau1372->mclk);
934
935 adau1372->pd_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
936 if (IS_ERR(adau1372->pd_gpio))
937 return PTR_ERR(adau1372->pd_gpio);
938
939 adau1372->regmap = regmap;
940 adau1372->switch_mode = switch_mode;
941 adau1372->dev = dev;
942 adau1372->rate_constraints.list = adau1372_rates;
943 adau1372->rate_constraints.count = ARRAY_SIZE(adau1372_rates);
944 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
945
946 dev_set_drvdata(dev, adau1372);
947
948 /*
949 * The datasheet says that the internal MCLK always needs to run at
950 * 12.288MHz. Automatically choose a valid configuration from the
951 * external clock.
952 */
953 rate = clk_get_rate(adau1372->mclk);
954
955 switch (rate) {
956 case 12288000:
957 clk_ctrl = ADAU1372_CLK_CTRL_CC_MDIV;
958 break;
959 case 24576000:
960 clk_ctrl = 0;
961 break;
962 default:
963 clk_ctrl = 0;
964 ret = adau1372_setup_pll(adau1372, rate);
965 if (ret < 0)
966 return ret;
967 adau1372->use_pll = true;
968 break;
969 }
970
971 /*
972 * Most of the registers are inaccessible unless the internal clock is
973 * enabled.
974 */
975 regcache_cache_only(regmap, true);
976
977 regmap_update_bits(regmap, ADAU1372_REG_CLK_CTRL, ADAU1372_CLK_CTRL_CC_MDIV, clk_ctrl);
978
979 /*
980 * No pinctrl support yet, put the multi-purpose pins in the most
981 * sensible mode for general purpose CODEC operation.
982 */
983 regmap_write(regmap, ADAU1372_REG_MODE_MP(1), 0x00); /* SDATA OUT */
984 regmap_write(regmap, ADAU1372_REG_MODE_MP(6), 0x12); /* CLOCKOUT */
985
986 regmap_write(regmap, ADAU1372_REG_OP_STAGE_MUTE, 0x0);
987
988 regmap_write(regmap, 0x7, 0x01); /* CLOCK OUT */
989
990 return devm_snd_soc_register_component(dev, &adau1372_driver, &adau1372_dai_driver, 1);
991}
992EXPORT_SYMBOL(adau1372_probe);
993
994static const struct reg_default adau1372_reg_defaults[] = {
995 { ADAU1372_REG_CLK_CTRL, 0x00 },
996 { ADAU1372_REG_PLL(0), 0x00 },
997 { ADAU1372_REG_PLL(1), 0x00 },
998 { ADAU1372_REG_PLL(2), 0x00 },
999 { ADAU1372_REG_PLL(3), 0x00 },
1000 { ADAU1372_REG_PLL(4), 0x00 },
1001 { ADAU1372_REG_PLL(5), 0x00 },
1002 { ADAU1372_REG_DAC_SOURCE, 0x10 },
1003 { ADAU1372_REG_SOUT_SOURCE_0_1, 0x54 },
1004 { ADAU1372_REG_SOUT_SOURCE_2_3, 0x76 },
1005 { ADAU1372_REG_SOUT_SOURCE_4_5, 0x54 },
1006 { ADAU1372_REG_SOUT_SOURCE_6_7, 0x76 },
1007 { ADAU1372_REG_ADC_SDATA_CH, 0x04 },
1008 { ADAU1372_REG_ASRCO_SOURCE_0_1, 0x10 },
1009 { ADAU1372_REG_ASRCO_SOURCE_2_3, 0x32 },
1010 { ADAU1372_REG_ASRC_MODE, 0x00 },
1011 { ADAU1372_REG_ADC_CTRL0, 0x19 },
1012 { ADAU1372_REG_ADC_CTRL1, 0x19 },
1013 { ADAU1372_REG_ADC_CTRL2, 0x00 },
1014 { ADAU1372_REG_ADC_CTRL3, 0x00 },
1015 { ADAU1372_REG_ADC_VOL(0), 0x00 },
1016 { ADAU1372_REG_ADC_VOL(1), 0x00 },
1017 { ADAU1372_REG_ADC_VOL(2), 0x00 },
1018 { ADAU1372_REG_ADC_VOL(3), 0x00 },
1019 { ADAU1372_REG_PGA_CTRL(0), 0x40 },
1020 { ADAU1372_REG_PGA_CTRL(1), 0x40 },
1021 { ADAU1372_REG_PGA_CTRL(2), 0x40 },
1022 { ADAU1372_REG_PGA_CTRL(3), 0x40 },
1023 { ADAU1372_REG_PGA_BOOST, 0x00 },
1024 { ADAU1372_REG_MICBIAS, 0x00 },
1025 { ADAU1372_REG_DAC_CTRL, 0x18 },
1026 { ADAU1372_REG_DAC_VOL(0), 0x00 },
1027 { ADAU1372_REG_DAC_VOL(1), 0x00 },
1028 { ADAU1372_REG_OP_STAGE_MUTE, 0x0f },
1029 { ADAU1372_REG_SAI0, 0x00 },
1030 { ADAU1372_REG_SAI1, 0x00 },
1031 { ADAU1372_REG_SOUT_CTRL, 0x00 },
1032 { ADAU1372_REG_MODE_MP(0), 0x00 },
1033 { ADAU1372_REG_MODE_MP(1), 0x10 },
1034 { ADAU1372_REG_MODE_MP(4), 0x00 },
1035 { ADAU1372_REG_MODE_MP(5), 0x00 },
1036 { ADAU1372_REG_MODE_MP(6), 0x11 },
1037 { ADAU1372_REG_OP_STAGE_CTRL, 0x0f },
1038 { ADAU1372_REG_DECIM_PWR, 0x00 },
1039 { ADAU1372_REG_INTERP_PWR, 0x00 },
1040 { ADAU1372_REG_BIAS_CTRL0, 0x00 },
1041 { ADAU1372_REG_BIAS_CTRL1, 0x00 },
1042};
1043
1044static bool adau1372_volatile_register(struct device *dev, unsigned int reg)
1045{
1046 if (reg == ADAU1372_REG_PLL(5))
1047 return true;
1048
1049 return false;
1050}
1051
1052const struct regmap_config adau1372_regmap_config = {
1053 .val_bits = 8,
1054 .reg_bits = 16,
1055 .max_register = 0x4d,
1056
1057 .reg_defaults = adau1372_reg_defaults,
1058 .num_reg_defaults = ARRAY_SIZE(adau1372_reg_defaults),
1059 .volatile_reg = adau1372_volatile_register,
1060 .cache_type = REGCACHE_MAPLE,
1061};
1062EXPORT_SYMBOL_GPL(adau1372_regmap_config);
1063
1064const struct of_device_id adau1372_of_match[] = {
1065 { .compatible = "adi,adau1372" },
1066 { }
1067};
1068EXPORT_SYMBOL_GPL(adau1372_of_match);
1069MODULE_DEVICE_TABLE(of, adau1372_of_match);
1070
1071MODULE_DESCRIPTION("ASoC ADAU1372 CODEC driver");
1072MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1073MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Analog Devices ADAU1372 Audio Codec driver
4 *
5 * Copyright 2016 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio/consumer.h>
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/pm.h>
15#include <linux/slab.h>
16
17#include <sound/core.h>
18#include <sound/pcm.h>
19#include <sound/pcm_params.h>
20#include <sound/tlv.h>
21#include <sound/soc.h>
22
23#include "adau1372.h"
24#include "adau-utils.h"
25
26struct adau1372 {
27 struct regmap *regmap;
28 void (*switch_mode)(struct device *dev);
29 bool use_pll;
30 bool enabled;
31 bool clock_provider;
32
33 struct snd_pcm_hw_constraint_list rate_constraints;
34 unsigned int slot_width;
35
36 struct clk *mclk;
37 struct gpio_desc *pd_gpio;
38 struct device *dev;
39};
40
41#define ADAU1372_REG_CLK_CTRL 0x00
42#define ADAU1372_REG_PLL(x) (0x01 + (x))
43#define ADAU1372_REG_DAC_SOURCE 0x11
44#define ADAU1372_REG_SOUT_SOURCE_0_1 0x13
45#define ADAU1372_REG_SOUT_SOURCE_2_3 0x14
46#define ADAU1372_REG_SOUT_SOURCE_4_5 0x15
47#define ADAU1372_REG_SOUT_SOURCE_6_7 0x16
48#define ADAU1372_REG_ADC_SDATA_CH 0x17
49#define ADAU1372_REG_ASRCO_SOURCE_0_1 0x18
50#define ADAU1372_REG_ASRCO_SOURCE_2_3 0x19
51#define ADAU1372_REG_ASRC_MODE 0x1a
52#define ADAU1372_REG_ADC_CTRL0 0x1b
53#define ADAU1372_REG_ADC_CTRL1 0x1c
54#define ADAU1372_REG_ADC_CTRL2 0x1d
55#define ADAU1372_REG_ADC_CTRL3 0x1e
56#define ADAU1372_REG_ADC_VOL(x) (0x1f + (x))
57#define ADAU1372_REG_PGA_CTRL(x) (0x23 + (x))
58#define ADAU1372_REG_PGA_BOOST 0x28
59#define ADAU1372_REG_MICBIAS 0x2d
60#define ADAU1372_REG_DAC_CTRL 0x2e
61#define ADAU1372_REG_DAC_VOL(x) (0x2f + (x))
62#define ADAU1372_REG_OP_STAGE_MUTE 0x31
63#define ADAU1372_REG_SAI0 0x32
64#define ADAU1372_REG_SAI1 0x33
65#define ADAU1372_REG_SOUT_CTRL 0x34
66#define ADAU1372_REG_MODE_MP(x) (0x38 + (x))
67#define ADAU1372_REG_OP_STAGE_CTRL 0x43
68#define ADAU1372_REG_DECIM_PWR 0x44
69#define ADAU1372_REG_INTERP_PWR 0x45
70#define ADAU1372_REG_BIAS_CTRL0 0x46
71#define ADAU1372_REG_BIAS_CTRL1 0x47
72
73#define ADAU1372_CLK_CTRL_PLL_EN BIT(7)
74#define ADAU1372_CLK_CTRL_XTAL_DIS BIT(4)
75#define ADAU1372_CLK_CTRL_CLKSRC BIT(3)
76#define ADAU1372_CLK_CTRL_CC_MDIV BIT(1)
77#define ADAU1372_CLK_CTRL_MCLK_EN BIT(0)
78
79#define ADAU1372_SAI0_DELAY1 (0x0 << 6)
80#define ADAU1372_SAI0_DELAY0 (0x1 << 6)
81#define ADAU1372_SAI0_DELAY_MASK (0x3 << 6)
82#define ADAU1372_SAI0_SAI_I2S (0x0 << 4)
83#define ADAU1372_SAI0_SAI_TDM2 (0x1 << 4)
84#define ADAU1372_SAI0_SAI_TDM4 (0x2 << 4)
85#define ADAU1372_SAI0_SAI_TDM8 (0x3 << 4)
86#define ADAU1372_SAI0_SAI_MASK (0x3 << 4)
87#define ADAU1372_SAI0_FS_48 0x0
88#define ADAU1372_SAI0_FS_8 0x1
89#define ADAU1372_SAI0_FS_12 0x2
90#define ADAU1372_SAI0_FS_16 0x3
91#define ADAU1372_SAI0_FS_24 0x4
92#define ADAU1372_SAI0_FS_32 0x5
93#define ADAU1372_SAI0_FS_96 0x6
94#define ADAU1372_SAI0_FS_192 0x7
95#define ADAU1372_SAI0_FS_MASK 0xf
96
97#define ADAU1372_SAI1_TDM_TS BIT(7)
98#define ADAU1372_SAI1_BCLK_TDMC BIT(6)
99#define ADAU1372_SAI1_LR_MODE BIT(5)
100#define ADAU1372_SAI1_LR_POL BIT(4)
101#define ADAU1372_SAI1_BCLKRATE BIT(2)
102#define ADAU1372_SAI1_BCLKEDGE BIT(1)
103#define ADAU1372_SAI1_MS BIT(0)
104
105static const unsigned int adau1372_rates[] = {
106 [ADAU1372_SAI0_FS_8] = 8000,
107 [ADAU1372_SAI0_FS_12] = 12000,
108 [ADAU1372_SAI0_FS_16] = 16000,
109 [ADAU1372_SAI0_FS_24] = 24000,
110 [ADAU1372_SAI0_FS_32] = 32000,
111 [ADAU1372_SAI0_FS_48] = 48000,
112 [ADAU1372_SAI0_FS_96] = 96000,
113 [ADAU1372_SAI0_FS_192] = 192000,
114};
115
116/* 8k, 12k, 24k, 48k */
117#define ADAU1372_RATE_MASK_TDM8 0x17
118/* + 16k, 96k */
119#define ADAU1372_RATE_MASK_TDM4_MASTER (ADAU1372_RATE_MASK_TDM8 | 0x48 | 0x20)
120/* +32k */
121#define ADAU1372_RATE_MASK_TDM4 (ADAU1372_RATE_MASK_TDM4_MASTER | 0x20)
122/* + 192k */
123#define ADAU1372_RATE_MASK_TDM2 (ADAU1372_RATE_MASK_TDM4 | 0x80)
124
125static const DECLARE_TLV_DB_MINMAX(adau1372_digital_tlv, -9563, 0);
126static const DECLARE_TLV_DB_SCALE(adau1372_pga_tlv, -1200, 75, 0);
127static const DECLARE_TLV_DB_SCALE(adau1372_pga_boost_tlv, 0, 1000, 0);
128
129static const char * const adau1372_bias_text[] = {
130 "Normal operation", "Extreme power saving", "Enhanced performance",
131 "Power saving",
132};
133
134static const unsigned int adau1372_bias_adc_values[] = {
135 0, 2, 3,
136};
137
138static const char * const adau1372_bias_adc_text[] = {
139 "Normal operation", "Enhanced performance", "Power saving",
140};
141
142static const char * const adau1372_bias_dac_text[] = {
143 "Normal operation", "Power saving", "Superior performance",
144 "Enhanced performance",
145};
146
147static SOC_ENUM_SINGLE_DECL(adau1372_bias_hp_enum,
148 ADAU1372_REG_BIAS_CTRL0, 6, adau1372_bias_text);
149static SOC_ENUM_SINGLE_DECL(adau1372_bias_afe0_1_enum,
150 ADAU1372_REG_BIAS_CTRL0, 4, adau1372_bias_text);
151static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_bias_adc2_3_enum,
152 ADAU1372_REG_BIAS_CTRL0, 2, 0x3, adau1372_bias_adc_text,
153 adau1372_bias_adc_values);
154static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_bias_adc0_1_enum,
155 ADAU1372_REG_BIAS_CTRL0, 0, 0x3, adau1372_bias_adc_text,
156 adau1372_bias_adc_values);
157static SOC_ENUM_SINGLE_DECL(adau1372_bias_afe2_3_enum,
158 ADAU1372_REG_BIAS_CTRL1, 4, adau1372_bias_text);
159static SOC_ENUM_SINGLE_DECL(adau1372_bias_mic_enum,
160 ADAU1372_REG_BIAS_CTRL1, 2, adau1372_bias_text);
161static SOC_ENUM_SINGLE_DECL(adau1372_bias_dac_enum,
162 ADAU1372_REG_BIAS_CTRL1, 0, adau1372_bias_dac_text);
163
164static const char * const adau1372_hpf_text[] = {
165 "Off",
166 "1 Hz",
167 "4 Hz",
168 "8 Hz",
169};
170
171static SOC_ENUM_SINGLE_DECL(adau1372_hpf0_1_enum, ADAU1372_REG_ADC_CTRL2, 5,
172 adau1372_hpf_text);
173static SOC_ENUM_SINGLE_DECL(adau1372_hpf2_3_enum, ADAU1372_REG_ADC_CTRL3, 5,
174 adau1372_hpf_text);
175static const struct snd_kcontrol_new adau1372_controls[] = {
176 SOC_SINGLE_TLV("ADC 0 Capture Volume", ADAU1372_REG_ADC_VOL(0),
177 0, 0xff, 1, adau1372_digital_tlv),
178 SOC_SINGLE_TLV("ADC 1 Capture Volume", ADAU1372_REG_ADC_VOL(1),
179 0, 0xff, 1, adau1372_digital_tlv),
180 SOC_SINGLE_TLV("ADC 2 Capture Volume", ADAU1372_REG_ADC_VOL(2),
181 0, 0xff, 1, adau1372_digital_tlv),
182 SOC_SINGLE_TLV("ADC 3 Capture Volume", ADAU1372_REG_ADC_VOL(3),
183 0, 0xff, 1, adau1372_digital_tlv),
184 SOC_SINGLE("ADC 0 Capture Switch", ADAU1372_REG_ADC_CTRL0, 3, 1, 1),
185 SOC_SINGLE("ADC 1 Capture Switch", ADAU1372_REG_ADC_CTRL0, 4, 1, 1),
186 SOC_SINGLE("ADC 2 Capture Switch", ADAU1372_REG_ADC_CTRL1, 3, 1, 1),
187 SOC_SINGLE("ADC 3 Capture Switch", ADAU1372_REG_ADC_CTRL1, 4, 1, 1),
188
189 SOC_ENUM("ADC 0+1 High-Pass-Filter", adau1372_hpf0_1_enum),
190 SOC_ENUM("ADC 2+3 High-Pass-Filter", adau1372_hpf2_3_enum),
191
192 SOC_SINGLE_TLV("PGA 0 Capture Volume", ADAU1372_REG_PGA_CTRL(0),
193 0, 0x3f, 0, adau1372_pga_tlv),
194 SOC_SINGLE_TLV("PGA 1 Capture Volume", ADAU1372_REG_PGA_CTRL(1),
195 0, 0x3f, 0, adau1372_pga_tlv),
196 SOC_SINGLE_TLV("PGA 2 Capture Volume", ADAU1372_REG_PGA_CTRL(2),
197 0, 0x3f, 0, adau1372_pga_tlv),
198 SOC_SINGLE_TLV("PGA 3 Capture Volume", ADAU1372_REG_PGA_CTRL(3),
199 0, 0x3f, 0, adau1372_pga_tlv),
200 SOC_SINGLE_TLV("PGA 0 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
201 0, 1, 0, adau1372_pga_boost_tlv),
202 SOC_SINGLE_TLV("PGA 1 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
203 1, 1, 0, adau1372_pga_boost_tlv),
204 SOC_SINGLE_TLV("PGA 2 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
205 2, 1, 0, adau1372_pga_boost_tlv),
206 SOC_SINGLE_TLV("PGA 3 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
207 3, 1, 0, adau1372_pga_boost_tlv),
208 SOC_SINGLE("PGA 0 Capture Switch", ADAU1372_REG_PGA_CTRL(0), 7, 1, 0),
209 SOC_SINGLE("PGA 1 Capture Switch", ADAU1372_REG_PGA_CTRL(1), 7, 1, 0),
210 SOC_SINGLE("PGA 2 Capture Switch", ADAU1372_REG_PGA_CTRL(2), 7, 1, 0),
211 SOC_SINGLE("PGA 3 Capture Switch", ADAU1372_REG_PGA_CTRL(3), 7, 1, 0),
212
213 SOC_SINGLE_TLV("DAC 0 Playback Volume", ADAU1372_REG_DAC_VOL(0),
214 0, 0xff, 1, adau1372_digital_tlv),
215 SOC_SINGLE_TLV("DAC 1 Playback Volume", ADAU1372_REG_DAC_VOL(1),
216 0, 0xff, 1, adau1372_digital_tlv),
217 SOC_SINGLE("DAC 0 Playback Switch", ADAU1372_REG_DAC_CTRL, 3, 1, 1),
218 SOC_SINGLE("DAC 1 Playback Switch", ADAU1372_REG_DAC_CTRL, 4, 1, 1),
219
220 SOC_ENUM("Headphone Bias", adau1372_bias_hp_enum),
221 SOC_ENUM("Microphone Bias", adau1372_bias_mic_enum),
222 SOC_ENUM("AFE 0+1 Bias", adau1372_bias_afe0_1_enum),
223 SOC_ENUM("AFE 2+3 Bias", adau1372_bias_afe2_3_enum),
224 SOC_ENUM("ADC 0+1 Bias", adau1372_bias_adc0_1_enum),
225 SOC_ENUM("ADC 2+3 Bias", adau1372_bias_adc2_3_enum),
226 SOC_ENUM("DAC 0+1 Bias", adau1372_bias_dac_enum),
227};
228
229static const char * const adau1372_decimator_mux_text[] = {
230 "ADC",
231 "DMIC",
232};
233
234static SOC_ENUM_SINGLE_DECL(adau1372_decimator0_1_mux_enum, ADAU1372_REG_ADC_CTRL2,
235 2, adau1372_decimator_mux_text);
236
237static const struct snd_kcontrol_new adau1372_decimator0_1_mux_control =
238 SOC_DAPM_ENUM("Decimator 0+1 Capture Mux", adau1372_decimator0_1_mux_enum);
239
240static SOC_ENUM_SINGLE_DECL(adau1372_decimator2_3_mux_enum, ADAU1372_REG_ADC_CTRL3,
241 2, adau1372_decimator_mux_text);
242
243static const struct snd_kcontrol_new adau1372_decimator2_3_mux_control =
244 SOC_DAPM_ENUM("Decimator 2+3 Capture Mux", adau1372_decimator2_3_mux_enum);
245
246static const unsigned int adau1372_asrco_mux_values[] = {
247 4, 5, 6, 7,
248};
249
250static const char * const adau1372_asrco_mux_text[] = {
251 "Decimator0",
252 "Decimator1",
253 "Decimator2",
254 "Decimator3",
255};
256
257static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco0_mux_enum, ADAU1372_REG_ASRCO_SOURCE_0_1,
258 0, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
259static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco1_mux_enum, ADAU1372_REG_ASRCO_SOURCE_0_1,
260 4, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
261static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco2_mux_enum, ADAU1372_REG_ASRCO_SOURCE_2_3,
262 0, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
263static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco3_mux_enum, ADAU1372_REG_ASRCO_SOURCE_2_3,
264 4, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
265
266static const struct snd_kcontrol_new adau1372_asrco0_mux_control =
267 SOC_DAPM_ENUM("Output ASRC0 Capture Mux", adau1372_asrco0_mux_enum);
268static const struct snd_kcontrol_new adau1372_asrco1_mux_control =
269 SOC_DAPM_ENUM("Output ASRC1 Capture Mux", adau1372_asrco1_mux_enum);
270static const struct snd_kcontrol_new adau1372_asrco2_mux_control =
271 SOC_DAPM_ENUM("Output ASRC2 Capture Mux", adau1372_asrco2_mux_enum);
272static const struct snd_kcontrol_new adau1372_asrco3_mux_control =
273 SOC_DAPM_ENUM("Output ASRC3 Capture Mux", adau1372_asrco3_mux_enum);
274
275static const unsigned int adau1372_sout_mux_values[] = {
276 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
277};
278
279static const char * const adau1372_sout_mux_text[] = {
280 "Output ASRC0",
281 "Output ASRC1",
282 "Output ASRC2",
283 "Output ASRC3",
284 "Serial Input 0",
285 "Serial Input 1",
286 "Serial Input 2",
287 "Serial Input 3",
288 "Serial Input 4",
289 "Serial Input 5",
290 "Serial Input 6",
291 "Serial Input 7",
292};
293
294static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout0_mux_enum, ADAU1372_REG_SOUT_SOURCE_0_1,
295 0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
296static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout1_mux_enum, ADAU1372_REG_SOUT_SOURCE_0_1,
297 4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
298static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout2_mux_enum, ADAU1372_REG_SOUT_SOURCE_2_3,
299 0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
300static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout3_mux_enum, ADAU1372_REG_SOUT_SOURCE_2_3,
301 4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
302static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout4_mux_enum, ADAU1372_REG_SOUT_SOURCE_4_5,
303 0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
304static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout5_mux_enum, ADAU1372_REG_SOUT_SOURCE_4_5,
305 4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
306static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout6_mux_enum, ADAU1372_REG_SOUT_SOURCE_6_7,
307 0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
308static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout7_mux_enum, ADAU1372_REG_SOUT_SOURCE_6_7,
309 4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
310
311static const struct snd_kcontrol_new adau1372_sout0_mux_control =
312 SOC_DAPM_ENUM("Serial Output 0 Capture Mux", adau1372_sout0_mux_enum);
313static const struct snd_kcontrol_new adau1372_sout1_mux_control =
314 SOC_DAPM_ENUM("Serial Output 1 Capture Mux", adau1372_sout1_mux_enum);
315static const struct snd_kcontrol_new adau1372_sout2_mux_control =
316 SOC_DAPM_ENUM("Serial Output 2 Capture Mux", adau1372_sout2_mux_enum);
317static const struct snd_kcontrol_new adau1372_sout3_mux_control =
318 SOC_DAPM_ENUM("Serial Output 3 Capture Mux", adau1372_sout3_mux_enum);
319static const struct snd_kcontrol_new adau1372_sout4_mux_control =
320 SOC_DAPM_ENUM("Serial Output 4 Capture Mux", adau1372_sout4_mux_enum);
321static const struct snd_kcontrol_new adau1372_sout5_mux_control =
322 SOC_DAPM_ENUM("Serial Output 5 Capture Mux", adau1372_sout5_mux_enum);
323static const struct snd_kcontrol_new adau1372_sout6_mux_control =
324 SOC_DAPM_ENUM("Serial Output 6 Capture Mux", adau1372_sout6_mux_enum);
325static const struct snd_kcontrol_new adau1372_sout7_mux_control =
326 SOC_DAPM_ENUM("Serial Output 7 Capture Mux", adau1372_sout7_mux_enum);
327
328static const char * const adau1372_asrci_mux_text[] = {
329 "Serial Input 0+1",
330 "Serial Input 2+3",
331 "Serial Input 4+5",
332 "Serial Input 6+7",
333};
334
335static SOC_ENUM_SINGLE_DECL(adau1372_asrci_mux_enum,
336 ADAU1372_REG_ASRC_MODE, 2, adau1372_asrci_mux_text);
337
338static const struct snd_kcontrol_new adau1372_asrci_mux_control =
339 SOC_DAPM_ENUM("Input ASRC Playback Mux", adau1372_asrci_mux_enum);
340
341static const unsigned int adau1372_dac_mux_values[] = {
342 12, 13
343};
344
345static const char * const adau1372_dac_mux_text[] = {
346 "Input ASRC0",
347 "Input ASRC1",
348};
349
350static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_dac0_mux_enum, ADAU1372_REG_DAC_SOURCE,
351 0, 0xf, adau1372_dac_mux_text, adau1372_dac_mux_values);
352static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_dac1_mux_enum, ADAU1372_REG_DAC_SOURCE,
353 4, 0xf, adau1372_dac_mux_text, adau1372_dac_mux_values);
354
355static const struct snd_kcontrol_new adau1372_dac0_mux_control =
356 SOC_DAPM_ENUM("DAC 0 Playback Mux", adau1372_dac0_mux_enum);
357static const struct snd_kcontrol_new adau1372_dac1_mux_control =
358 SOC_DAPM_ENUM("DAC 1 Playback Mux", adau1372_dac1_mux_enum);
359
360static const struct snd_soc_dapm_widget adau1372_dapm_widgets[] = {
361 SND_SOC_DAPM_INPUT("AIN0"),
362 SND_SOC_DAPM_INPUT("AIN1"),
363 SND_SOC_DAPM_INPUT("AIN2"),
364 SND_SOC_DAPM_INPUT("AIN3"),
365 SND_SOC_DAPM_INPUT("DMIC0_1"),
366 SND_SOC_DAPM_INPUT("DMIC2_3"),
367
368 SND_SOC_DAPM_SUPPLY("MICBIAS0", ADAU1372_REG_MICBIAS, 4, 0, NULL, 0),
369 SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1372_REG_MICBIAS, 5, 0, NULL, 0),
370
371 SND_SOC_DAPM_PGA("PGA0", ADAU1372_REG_PGA_CTRL(0), 6, 1, NULL, 0),
372 SND_SOC_DAPM_PGA("PGA1", ADAU1372_REG_PGA_CTRL(1), 6, 1, NULL, 0),
373 SND_SOC_DAPM_PGA("PGA2", ADAU1372_REG_PGA_CTRL(2), 6, 1, NULL, 0),
374 SND_SOC_DAPM_PGA("PGA3", ADAU1372_REG_PGA_CTRL(3), 6, 1, NULL, 0),
375 SND_SOC_DAPM_ADC("ADC0", NULL, ADAU1372_REG_ADC_CTRL2, 0, 0),
376 SND_SOC_DAPM_ADC("ADC1", NULL, ADAU1372_REG_ADC_CTRL2, 1, 0),
377 SND_SOC_DAPM_ADC("ADC2", NULL, ADAU1372_REG_ADC_CTRL3, 0, 0),
378 SND_SOC_DAPM_ADC("ADC3", NULL, ADAU1372_REG_ADC_CTRL3, 1, 0),
379
380 SND_SOC_DAPM_SUPPLY("ADC0 Filter", ADAU1372_REG_DECIM_PWR, 0, 0, NULL, 0),
381 SND_SOC_DAPM_SUPPLY("ADC1 Filter", ADAU1372_REG_DECIM_PWR, 1, 0, NULL, 0),
382 SND_SOC_DAPM_SUPPLY("ADC2 Filter", ADAU1372_REG_DECIM_PWR, 2, 0, NULL, 0),
383 SND_SOC_DAPM_SUPPLY("ADC3 Filter", ADAU1372_REG_DECIM_PWR, 3, 0, NULL, 0),
384 SND_SOC_DAPM_SUPPLY("Output ASRC0 Decimator", ADAU1372_REG_DECIM_PWR, 4, 0, NULL, 0),
385 SND_SOC_DAPM_SUPPLY("Output ASRC1 Decimator", ADAU1372_REG_DECIM_PWR, 5, 0, NULL, 0),
386 SND_SOC_DAPM_SUPPLY("Output ASRC2 Decimator", ADAU1372_REG_DECIM_PWR, 6, 0, NULL, 0),
387 SND_SOC_DAPM_SUPPLY("Output ASRC3 Decimator", ADAU1372_REG_DECIM_PWR, 7, 0, NULL, 0),
388
389 SND_SOC_DAPM_MUX("Decimator0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator0_1_mux_control),
390 SND_SOC_DAPM_MUX("Decimator1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator0_1_mux_control),
391 SND_SOC_DAPM_MUX("Decimator2 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator2_3_mux_control),
392 SND_SOC_DAPM_MUX("Decimator3 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator2_3_mux_control),
393
394 SND_SOC_DAPM_MUX("Output ASRC0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco0_mux_control),
395 SND_SOC_DAPM_MUX("Output ASRC1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco1_mux_control),
396 SND_SOC_DAPM_MUX("Output ASRC2 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco2_mux_control),
397 SND_SOC_DAPM_MUX("Output ASRC3 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco3_mux_control),
398 SND_SOC_DAPM_MUX("Serial Output 0 Capture Mux", SND_SOC_NOPM, 0, 0,
399 &adau1372_sout0_mux_control),
400 SND_SOC_DAPM_MUX("Serial Output 1 Capture Mux", SND_SOC_NOPM, 0, 0,
401 &adau1372_sout1_mux_control),
402 SND_SOC_DAPM_MUX("Serial Output 2 Capture Mux", SND_SOC_NOPM, 0, 0,
403 &adau1372_sout2_mux_control),
404 SND_SOC_DAPM_MUX("Serial Output 3 Capture Mux", SND_SOC_NOPM, 0, 0,
405 &adau1372_sout3_mux_control),
406 SND_SOC_DAPM_MUX("Serial Output 4 Capture Mux", SND_SOC_NOPM, 0, 0,
407 &adau1372_sout4_mux_control),
408 SND_SOC_DAPM_MUX("Serial Output 5 Capture Mux", SND_SOC_NOPM, 0, 0,
409 &adau1372_sout5_mux_control),
410 SND_SOC_DAPM_MUX("Serial Output 6 Capture Mux", SND_SOC_NOPM, 0, 0,
411 &adau1372_sout6_mux_control),
412 SND_SOC_DAPM_MUX("Serial Output 7 Capture Mux", SND_SOC_NOPM, 0, 0,
413 &adau1372_sout7_mux_control),
414
415 SND_SOC_DAPM_AIF_IN("Serial Input 0", NULL, 0, SND_SOC_NOPM, 0, 0),
416 SND_SOC_DAPM_AIF_IN("Serial Input 1", NULL, 1, SND_SOC_NOPM, 0, 0),
417 SND_SOC_DAPM_AIF_IN("Serial Input 2", NULL, 2, SND_SOC_NOPM, 0, 0),
418 SND_SOC_DAPM_AIF_IN("Serial Input 3", NULL, 3, SND_SOC_NOPM, 0, 0),
419 SND_SOC_DAPM_AIF_IN("Serial Input 4", NULL, 4, SND_SOC_NOPM, 0, 0),
420 SND_SOC_DAPM_AIF_IN("Serial Input 5", NULL, 5, SND_SOC_NOPM, 0, 0),
421 SND_SOC_DAPM_AIF_IN("Serial Input 6", NULL, 6, SND_SOC_NOPM, 0, 0),
422 SND_SOC_DAPM_AIF_IN("Serial Input 7", NULL, 7, SND_SOC_NOPM, 0, 0),
423
424 SND_SOC_DAPM_AIF_OUT("Serial Output 0", NULL, 0, SND_SOC_NOPM, 0, 0),
425 SND_SOC_DAPM_AIF_OUT("Serial Output 1", NULL, 1, SND_SOC_NOPM, 0, 0),
426 SND_SOC_DAPM_AIF_OUT("Serial Output 2", NULL, 2, SND_SOC_NOPM, 0, 0),
427 SND_SOC_DAPM_AIF_OUT("Serial Output 3", NULL, 3, SND_SOC_NOPM, 0, 0),
428 SND_SOC_DAPM_AIF_OUT("Serial Output 4", NULL, 4, SND_SOC_NOPM, 0, 0),
429 SND_SOC_DAPM_AIF_OUT("Serial Output 5", NULL, 5, SND_SOC_NOPM, 0, 0),
430 SND_SOC_DAPM_AIF_OUT("Serial Output 6", NULL, 6, SND_SOC_NOPM, 0, 0),
431 SND_SOC_DAPM_AIF_OUT("Serial Output 7", NULL, 7, SND_SOC_NOPM, 0, 0),
432
433 SND_SOC_DAPM_SUPPLY("Output ASRC Supply", ADAU1372_REG_ASRC_MODE, 1, 0, NULL, 0),
434 SND_SOC_DAPM_SUPPLY("Input ASRC Supply", ADAU1372_REG_ASRC_MODE, 0, 0, NULL, 0),
435
436 SND_SOC_DAPM_SUPPLY("DAC1 Modulator", ADAU1372_REG_INTERP_PWR, 3, 0, NULL, 0),
437 SND_SOC_DAPM_SUPPLY("DAC0 Modulator", ADAU1372_REG_INTERP_PWR, 2, 0, NULL, 0),
438 SND_SOC_DAPM_SUPPLY("Input ASRC1 Interpolator", ADAU1372_REG_INTERP_PWR, 1, 0, NULL, 0),
439 SND_SOC_DAPM_SUPPLY("Input ASRC0 Interpolator", ADAU1372_REG_INTERP_PWR, 0, 0, NULL, 0),
440
441 SND_SOC_DAPM_MUX("Input ASRC0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrci_mux_control),
442 SND_SOC_DAPM_MUX("Input ASRC1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrci_mux_control),
443
444 SND_SOC_DAPM_MUX("DAC 0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_dac0_mux_control),
445 SND_SOC_DAPM_MUX("DAC 1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_dac1_mux_control),
446
447 SND_SOC_DAPM_DAC("DAC0", NULL, ADAU1372_REG_DAC_CTRL, 0, 0),
448 SND_SOC_DAPM_DAC("DAC1", NULL, ADAU1372_REG_DAC_CTRL, 1, 0),
449
450 SND_SOC_DAPM_OUT_DRV("OP_STAGE_LP", ADAU1372_REG_OP_STAGE_CTRL, 0, 1, NULL, 0),
451 SND_SOC_DAPM_OUT_DRV("OP_STAGE_LN", ADAU1372_REG_OP_STAGE_CTRL, 1, 1, NULL, 0),
452 SND_SOC_DAPM_OUT_DRV("OP_STAGE_RP", ADAU1372_REG_OP_STAGE_CTRL, 2, 1, NULL, 0),
453 SND_SOC_DAPM_OUT_DRV("OP_STAGE_RN", ADAU1372_REG_OP_STAGE_CTRL, 3, 1, NULL, 0),
454
455 SND_SOC_DAPM_OUTPUT("HPOUTL"),
456 SND_SOC_DAPM_OUTPUT("HPOUTR"),
457};
458
459#define ADAU1372_SOUT_ROUTES(x) \
460 { "Serial Output " #x " Capture Mux", "Output ASRC0", "Output ASRC0 Mux" }, \
461 { "Serial Output " #x " Capture Mux", "Output ASRC1", "Output ASRC1 Mux" }, \
462 { "Serial Output " #x " Capture Mux", "Output ASRC2", "Output ASRC2 Mux" }, \
463 { "Serial Output " #x " Capture Mux", "Output ASRC3", "Output ASRC3 Mux" }, \
464 { "Serial Output " #x " Capture Mux", "Serial Input 0", "Serial Input 0" }, \
465 { "Serial Output " #x " Capture Mux", "Serial Input 1", "Serial Input 1" }, \
466 { "Serial Output " #x " Capture Mux", "Serial Input 2", "Serial Input 2" }, \
467 { "Serial Output " #x " Capture Mux", "Serial Input 3", "Serial Input 3" }, \
468 { "Serial Output " #x " Capture Mux", "Serial Input 4", "Serial Input 4" }, \
469 { "Serial Output " #x " Capture Mux", "Serial Input 5", "Serial Input 5" }, \
470 { "Serial Output " #x " Capture Mux", "Serial Input 6", "Serial Input 6" }, \
471 { "Serial Output " #x " Capture Mux", "Serial Input 7", "Serial Input 7" }, \
472 { "Serial Output " #x, NULL, "Serial Output " #x " Capture Mux" }, \
473 { "Capture", NULL, "Serial Output " #x }
474
475#define ADAU1372_ASRCO_ROUTES(x) \
476 { "Output ASRC" #x " Mux", "Decimator0", "Decimator0 Mux" }, \
477 { "Output ASRC" #x " Mux", "Decimator1", "Decimator1 Mux" }, \
478 { "Output ASRC" #x " Mux", "Decimator2", "Decimator2 Mux" }, \
479 { "Output ASRC" #x " Mux", "Decimator3", "Decimator3 Mux" }
480
481static const struct snd_soc_dapm_route adau1372_dapm_routes[] = {
482 { "PGA0", NULL, "AIN0" },
483 { "PGA1", NULL, "AIN1" },
484 { "PGA2", NULL, "AIN2" },
485 { "PGA3", NULL, "AIN3" },
486
487 { "ADC0", NULL, "PGA0" },
488 { "ADC1", NULL, "PGA1" },
489 { "ADC2", NULL, "PGA2" },
490 { "ADC3", NULL, "PGA3" },
491
492 { "Decimator0 Mux", "ADC", "ADC0" },
493 { "Decimator1 Mux", "ADC", "ADC1" },
494 { "Decimator2 Mux", "ADC", "ADC2" },
495 { "Decimator3 Mux", "ADC", "ADC3" },
496
497 { "Decimator0 Mux", "DMIC", "DMIC0_1" },
498 { "Decimator1 Mux", "DMIC", "DMIC0_1" },
499 { "Decimator2 Mux", "DMIC", "DMIC2_3" },
500 { "Decimator3 Mux", "DMIC", "DMIC2_3" },
501
502 { "Decimator0 Mux", NULL, "ADC0 Filter" },
503 { "Decimator1 Mux", NULL, "ADC1 Filter" },
504 { "Decimator2 Mux", NULL, "ADC2 Filter" },
505 { "Decimator3 Mux", NULL, "ADC3 Filter" },
506
507 { "Output ASRC0 Mux", NULL, "Output ASRC Supply" },
508 { "Output ASRC1 Mux", NULL, "Output ASRC Supply" },
509 { "Output ASRC2 Mux", NULL, "Output ASRC Supply" },
510 { "Output ASRC3 Mux", NULL, "Output ASRC Supply" },
511 { "Output ASRC0 Mux", NULL, "Output ASRC0 Decimator" },
512 { "Output ASRC1 Mux", NULL, "Output ASRC1 Decimator" },
513 { "Output ASRC2 Mux", NULL, "Output ASRC2 Decimator" },
514 { "Output ASRC3 Mux", NULL, "Output ASRC3 Decimator" },
515
516 ADAU1372_ASRCO_ROUTES(0),
517 ADAU1372_ASRCO_ROUTES(1),
518 ADAU1372_ASRCO_ROUTES(2),
519 ADAU1372_ASRCO_ROUTES(3),
520
521 ADAU1372_SOUT_ROUTES(0),
522 ADAU1372_SOUT_ROUTES(1),
523 ADAU1372_SOUT_ROUTES(2),
524 ADAU1372_SOUT_ROUTES(3),
525 ADAU1372_SOUT_ROUTES(4),
526 ADAU1372_SOUT_ROUTES(5),
527 ADAU1372_SOUT_ROUTES(6),
528 ADAU1372_SOUT_ROUTES(7),
529
530 { "Serial Input 0", NULL, "Playback" },
531 { "Serial Input 1", NULL, "Playback" },
532 { "Serial Input 2", NULL, "Playback" },
533 { "Serial Input 3", NULL, "Playback" },
534 { "Serial Input 4", NULL, "Playback" },
535 { "Serial Input 5", NULL, "Playback" },
536 { "Serial Input 6", NULL, "Playback" },
537 { "Serial Input 7", NULL, "Playback" },
538
539 { "Input ASRC0 Mux", "Serial Input 0+1", "Serial Input 0" },
540 { "Input ASRC1 Mux", "Serial Input 0+1", "Serial Input 1" },
541 { "Input ASRC0 Mux", "Serial Input 2+3", "Serial Input 2" },
542 { "Input ASRC1 Mux", "Serial Input 2+3", "Serial Input 3" },
543 { "Input ASRC0 Mux", "Serial Input 4+5", "Serial Input 4" },
544 { "Input ASRC1 Mux", "Serial Input 4+5", "Serial Input 5" },
545 { "Input ASRC0 Mux", "Serial Input 6+7", "Serial Input 6" },
546 { "Input ASRC1 Mux", "Serial Input 6+7", "Serial Input 7" },
547 { "Input ASRC0 Mux", NULL, "Input ASRC Supply" },
548 { "Input ASRC1 Mux", NULL, "Input ASRC Supply" },
549 { "Input ASRC0 Mux", NULL, "Input ASRC0 Interpolator" },
550 { "Input ASRC1 Mux", NULL, "Input ASRC1 Interpolator" },
551
552 { "DAC 0 Mux", "Input ASRC0", "Input ASRC0 Mux" },
553 { "DAC 0 Mux", "Input ASRC1", "Input ASRC1 Mux" },
554 { "DAC 1 Mux", "Input ASRC0", "Input ASRC0 Mux" },
555 { "DAC 1 Mux", "Input ASRC1", "Input ASRC1 Mux" },
556
557 { "DAC0", NULL, "DAC 0 Mux" },
558 { "DAC1", NULL, "DAC 1 Mux" },
559 { "DAC0", NULL, "DAC0 Modulator" },
560 { "DAC1", NULL, "DAC1 Modulator" },
561
562 { "OP_STAGE_LP", NULL, "DAC0" },
563 { "OP_STAGE_LN", NULL, "DAC0" },
564 { "OP_STAGE_RP", NULL, "DAC1" },
565 { "OP_STAGE_RN", NULL, "DAC1" },
566
567 { "HPOUTL", NULL, "OP_STAGE_LP" },
568 { "HPOUTL", NULL, "OP_STAGE_LN" },
569 { "HPOUTR", NULL, "OP_STAGE_RP" },
570 { "HPOUTR", NULL, "OP_STAGE_RN" },
571};
572
573static int adau1372_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
574{
575 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
576 unsigned int sai0 = 0, sai1 = 0;
577 bool invert_lrclk = false;
578
579 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
580 case SND_SOC_DAIFMT_CBP_CFP:
581 adau1372->clock_provider = true;
582 sai1 |= ADAU1372_SAI1_MS;
583 break;
584 case SND_SOC_DAIFMT_CBC_CFC:
585 adau1372->clock_provider = false;
586 break;
587 default:
588 return -EINVAL;
589 }
590
591 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
592 case SND_SOC_DAIFMT_NB_NF:
593 invert_lrclk = false;
594 break;
595 case SND_SOC_DAIFMT_NB_IF:
596 invert_lrclk = true;
597 break;
598 case SND_SOC_DAIFMT_IB_NF:
599 invert_lrclk = false;
600 sai1 |= ADAU1372_SAI1_BCLKEDGE;
601 break;
602 case SND_SOC_DAIFMT_IB_IF:
603 invert_lrclk = true;
604 sai1 |= ADAU1372_SAI1_BCLKEDGE;
605 break;
606 }
607
608 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
609 case SND_SOC_DAIFMT_I2S:
610 sai0 |= ADAU1372_SAI0_DELAY1;
611 break;
612 case SND_SOC_DAIFMT_LEFT_J:
613 sai0 |= ADAU1372_SAI0_DELAY0;
614 invert_lrclk = !invert_lrclk;
615 break;
616 case SND_SOC_DAIFMT_DSP_A:
617 sai0 |= ADAU1372_SAI0_DELAY1;
618 sai1 |= ADAU1372_SAI1_LR_MODE;
619 break;
620 case SND_SOC_DAIFMT_DSP_B:
621 sai0 |= ADAU1372_SAI0_DELAY0;
622 sai1 |= ADAU1372_SAI1_LR_MODE;
623 break;
624 }
625
626 if (invert_lrclk)
627 sai1 |= ADAU1372_SAI1_LR_POL;
628
629 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_DELAY_MASK, sai0);
630 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1,
631 ADAU1372_SAI1_MS | ADAU1372_SAI1_BCLKEDGE |
632 ADAU1372_SAI1_LR_MODE | ADAU1372_SAI1_LR_POL, sai1);
633
634 return 0;
635}
636
637static int adau1372_hw_params(struct snd_pcm_substream *substream,
638 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
639{
640 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
641 unsigned int rate = params_rate(params);
642 unsigned int slot_width;
643 unsigned int sai0, sai1;
644 unsigned int i;
645
646 for (i = 0; i < ARRAY_SIZE(adau1372_rates); i++) {
647 if (rate == adau1372_rates[i])
648 break;
649 }
650
651 if (i == ARRAY_SIZE(adau1372_rates))
652 return -EINVAL;
653
654 sai0 = i;
655
656 slot_width = adau1372->slot_width;
657 if (slot_width == 0)
658 slot_width = params_width(params);
659
660 switch (slot_width) {
661 case 16:
662 sai1 = ADAU1372_SAI1_BCLKRATE;
663 break;
664 case 24:
665 case 32:
666 sai1 = 0;
667 break;
668 default:
669 return -EINVAL;
670 }
671
672 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_FS_MASK, sai0);
673 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLKRATE, sai1);
674
675 return 0;
676}
677
678static int adau1372_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
679 unsigned int rx_mask, int slots, int width)
680{
681 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
682 unsigned int sai0, sai1;
683
684 /* I2S mode */
685 if (slots == 0) {
686 /* The other settings dont matter in I2S mode */
687 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0,
688 ADAU1372_SAI0_SAI_MASK, ADAU1372_SAI0_SAI_I2S);
689 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
690 adau1372->slot_width = 0;
691 return 0;
692 }
693
694 /* We have 8 channels anything outside that is not supported */
695 if ((tx_mask & ~0xff) != 0 || (rx_mask & ~0xff) != 0)
696 return -EINVAL;
697
698 switch (width) {
699 case 16:
700 sai1 = ADAU1372_SAI1_BCLK_TDMC;
701 break;
702 case 24:
703 case 32:
704 sai1 = 0;
705 break;
706 default:
707 return -EINVAL;
708 }
709
710 switch (slots) {
711 case 2:
712 sai0 = ADAU1372_SAI0_SAI_TDM2;
713 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
714 break;
715 case 4:
716 sai0 = ADAU1372_SAI0_SAI_TDM4;
717 if (adau1372->clock_provider)
718 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4_MASTER;
719 else
720 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4;
721 break;
722 case 8:
723 sai0 = ADAU1372_SAI0_SAI_TDM8;
724 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM8;
725 break;
726 default:
727 return -EINVAL;
728 }
729
730 adau1372->slot_width = width;
731
732 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_SAI_MASK, sai0);
733 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLK_TDMC, sai1);
734
735 /* Mask is inverted in hardware */
736 regmap_write(adau1372->regmap, ADAU1372_REG_SOUT_CTRL, ~tx_mask);
737
738 return 0;
739}
740
741static int adau1372_set_tristate(struct snd_soc_dai *dai, int tristate)
742{
743 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
744 unsigned int sai1;
745
746 if (tristate)
747 sai1 = ADAU1372_SAI1_TDM_TS;
748 else
749 sai1 = 0;
750
751 return regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_TDM_TS, sai1);
752}
753
754static int adau1372_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
755{
756 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
757
758 snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
759 &adau1372->rate_constraints);
760
761 return 0;
762}
763
764static void adau1372_enable_pll(struct adau1372 *adau1372)
765{
766 unsigned int val, timeout = 0;
767 int ret;
768
769 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
770 ADAU1372_CLK_CTRL_PLL_EN, ADAU1372_CLK_CTRL_PLL_EN);
771 do {
772 /* Takes about 1ms to lock */
773 usleep_range(1000, 2000);
774 ret = regmap_read(adau1372->regmap, ADAU1372_REG_PLL(5), &val);
775 if (ret)
776 break;
777 timeout++;
778 } while (!(val & 1) && timeout < 3);
779
780 if (ret < 0 || !(val & 1))
781 dev_err(adau1372->dev, "Failed to lock PLL\n");
782}
783
784static void adau1372_set_power(struct adau1372 *adau1372, bool enable)
785{
786 if (adau1372->enabled == enable)
787 return;
788
789 if (enable) {
790 unsigned int clk_ctrl = ADAU1372_CLK_CTRL_MCLK_EN;
791
792 clk_prepare_enable(adau1372->mclk);
793 if (adau1372->pd_gpio)
794 gpiod_set_value(adau1372->pd_gpio, 0);
795
796 if (adau1372->switch_mode)
797 adau1372->switch_mode(adau1372->dev);
798
799 regcache_cache_only(adau1372->regmap, false);
800
801 /*
802 * Clocks needs to be enabled before any other register can be
803 * accessed.
804 */
805 if (adau1372->use_pll) {
806 adau1372_enable_pll(adau1372);
807 clk_ctrl |= ADAU1372_CLK_CTRL_CLKSRC;
808 }
809
810 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
811 ADAU1372_CLK_CTRL_MCLK_EN | ADAU1372_CLK_CTRL_CLKSRC, clk_ctrl);
812 regcache_sync(adau1372->regmap);
813 } else {
814 if (adau1372->pd_gpio) {
815 /*
816 * This will turn everything off and reset the register
817 * map. No need to do any register writes to manually
818 * turn things off.
819 */
820 gpiod_set_value(adau1372->pd_gpio, 1);
821 regcache_mark_dirty(adau1372->regmap);
822 } else {
823 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
824 ADAU1372_CLK_CTRL_MCLK_EN | ADAU1372_CLK_CTRL_PLL_EN, 0);
825 }
826 clk_disable_unprepare(adau1372->mclk);
827 regcache_cache_only(adau1372->regmap, true);
828 }
829
830 adau1372->enabled = enable;
831}
832
833static int adau1372_set_bias_level(struct snd_soc_component *component,
834 enum snd_soc_bias_level level)
835{
836 struct adau1372 *adau1372 = snd_soc_component_get_drvdata(component);
837
838 switch (level) {
839 case SND_SOC_BIAS_ON:
840 break;
841 case SND_SOC_BIAS_PREPARE:
842 break;
843 case SND_SOC_BIAS_STANDBY:
844 adau1372_set_power(adau1372, true);
845 break;
846 case SND_SOC_BIAS_OFF:
847 adau1372_set_power(adau1372, false);
848 break;
849 }
850
851 return 0;
852}
853
854static const struct snd_soc_component_driver adau1372_driver = {
855 .set_bias_level = adau1372_set_bias_level,
856 .controls = adau1372_controls,
857 .num_controls = ARRAY_SIZE(adau1372_controls),
858 .dapm_widgets = adau1372_dapm_widgets,
859 .num_dapm_widgets = ARRAY_SIZE(adau1372_dapm_widgets),
860 .dapm_routes = adau1372_dapm_routes,
861 .num_dapm_routes = ARRAY_SIZE(adau1372_dapm_routes),
862 .endianness = 1,
863};
864
865static const struct snd_soc_dai_ops adau1372_dai_ops = {
866 .set_fmt = adau1372_set_dai_fmt,
867 .set_tdm_slot = adau1372_set_tdm_slot,
868 .set_tristate = adau1372_set_tristate,
869 .hw_params = adau1372_hw_params,
870 .startup = adau1372_startup,
871};
872
873#define ADAU1372_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
874 SNDRV_PCM_FMTBIT_S24_LE | \
875 SNDRV_PCM_FMTBIT_S32_LE)
876
877static struct snd_soc_dai_driver adau1372_dai_driver = {
878 .name = "adau1372",
879 .playback = {
880 .stream_name = "Playback",
881 .channels_min = 2,
882 .channels_max = 8,
883 .rates = SNDRV_PCM_RATE_KNOT,
884 .formats = ADAU1372_FORMATS,
885 .sig_bits = 24,
886 },
887 .capture = {
888 .stream_name = "Capture",
889 .channels_min = 2,
890 .channels_max = 8,
891 .rates = SNDRV_PCM_RATE_KNOT,
892 .formats = ADAU1372_FORMATS,
893 .sig_bits = 24,
894 },
895 .ops = &adau1372_dai_ops,
896 .symmetric_rate = 1,
897};
898
899static int adau1372_setup_pll(struct adau1372 *adau1372, unsigned int rate)
900{
901 u8 regs[5];
902 unsigned int i;
903 int ret;
904
905 ret = adau_calc_pll_cfg(rate, 49152000, regs);
906 if (ret < 0)
907 return ret;
908
909 for (i = 0; i < ARRAY_SIZE(regs); i++)
910 regmap_write(adau1372->regmap, ADAU1372_REG_PLL(i), regs[i]);
911
912 return 0;
913}
914
915int adau1372_probe(struct device *dev, struct regmap *regmap,
916 void (*switch_mode)(struct device *dev))
917{
918 struct adau1372 *adau1372;
919 unsigned int clk_ctrl;
920 unsigned long rate;
921 int ret;
922
923 if (IS_ERR(regmap))
924 return PTR_ERR(regmap);
925
926 adau1372 = devm_kzalloc(dev, sizeof(*adau1372), GFP_KERNEL);
927 if (!adau1372)
928 return -ENOMEM;
929
930 adau1372->mclk = devm_clk_get(dev, "mclk");
931 if (IS_ERR(adau1372->mclk))
932 return PTR_ERR(adau1372->mclk);
933
934 adau1372->pd_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
935 if (IS_ERR(adau1372->pd_gpio))
936 return PTR_ERR(adau1372->pd_gpio);
937
938 adau1372->regmap = regmap;
939 adau1372->switch_mode = switch_mode;
940 adau1372->dev = dev;
941 adau1372->rate_constraints.list = adau1372_rates;
942 adau1372->rate_constraints.count = ARRAY_SIZE(adau1372_rates);
943 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
944
945 dev_set_drvdata(dev, adau1372);
946
947 /*
948 * The datasheet says that the internal MCLK always needs to run at
949 * 12.288MHz. Automatically choose a valid configuration from the
950 * external clock.
951 */
952 rate = clk_get_rate(adau1372->mclk);
953
954 switch (rate) {
955 case 12288000:
956 clk_ctrl = ADAU1372_CLK_CTRL_CC_MDIV;
957 break;
958 case 24576000:
959 clk_ctrl = 0;
960 break;
961 default:
962 clk_ctrl = 0;
963 ret = adau1372_setup_pll(adau1372, rate);
964 if (ret < 0)
965 return ret;
966 adau1372->use_pll = true;
967 break;
968 }
969
970 /*
971 * Most of the registers are inaccessible unless the internal clock is
972 * enabled.
973 */
974 regcache_cache_only(regmap, true);
975
976 regmap_update_bits(regmap, ADAU1372_REG_CLK_CTRL, ADAU1372_CLK_CTRL_CC_MDIV, clk_ctrl);
977
978 /*
979 * No pinctrl support yet, put the multi-purpose pins in the most
980 * sensible mode for general purpose CODEC operation.
981 */
982 regmap_write(regmap, ADAU1372_REG_MODE_MP(1), 0x00); /* SDATA OUT */
983 regmap_write(regmap, ADAU1372_REG_MODE_MP(6), 0x12); /* CLOCKOUT */
984
985 regmap_write(regmap, ADAU1372_REG_OP_STAGE_MUTE, 0x0);
986
987 regmap_write(regmap, 0x7, 0x01); /* CLOCK OUT */
988
989 return devm_snd_soc_register_component(dev, &adau1372_driver, &adau1372_dai_driver, 1);
990}
991EXPORT_SYMBOL(adau1372_probe);
992
993static const struct reg_default adau1372_reg_defaults[] = {
994 { ADAU1372_REG_CLK_CTRL, 0x00 },
995 { ADAU1372_REG_PLL(0), 0x00 },
996 { ADAU1372_REG_PLL(1), 0x00 },
997 { ADAU1372_REG_PLL(2), 0x00 },
998 { ADAU1372_REG_PLL(3), 0x00 },
999 { ADAU1372_REG_PLL(4), 0x00 },
1000 { ADAU1372_REG_PLL(5), 0x00 },
1001 { ADAU1372_REG_DAC_SOURCE, 0x10 },
1002 { ADAU1372_REG_SOUT_SOURCE_0_1, 0x54 },
1003 { ADAU1372_REG_SOUT_SOURCE_2_3, 0x76 },
1004 { ADAU1372_REG_SOUT_SOURCE_4_5, 0x54 },
1005 { ADAU1372_REG_SOUT_SOURCE_6_7, 0x76 },
1006 { ADAU1372_REG_ADC_SDATA_CH, 0x04 },
1007 { ADAU1372_REG_ASRCO_SOURCE_0_1, 0x10 },
1008 { ADAU1372_REG_ASRCO_SOURCE_2_3, 0x32 },
1009 { ADAU1372_REG_ASRC_MODE, 0x00 },
1010 { ADAU1372_REG_ADC_CTRL0, 0x19 },
1011 { ADAU1372_REG_ADC_CTRL1, 0x19 },
1012 { ADAU1372_REG_ADC_CTRL2, 0x00 },
1013 { ADAU1372_REG_ADC_CTRL3, 0x00 },
1014 { ADAU1372_REG_ADC_VOL(0), 0x00 },
1015 { ADAU1372_REG_ADC_VOL(1), 0x00 },
1016 { ADAU1372_REG_ADC_VOL(2), 0x00 },
1017 { ADAU1372_REG_ADC_VOL(3), 0x00 },
1018 { ADAU1372_REG_PGA_CTRL(0), 0x40 },
1019 { ADAU1372_REG_PGA_CTRL(1), 0x40 },
1020 { ADAU1372_REG_PGA_CTRL(2), 0x40 },
1021 { ADAU1372_REG_PGA_CTRL(3), 0x40 },
1022 { ADAU1372_REG_PGA_BOOST, 0x00 },
1023 { ADAU1372_REG_MICBIAS, 0x00 },
1024 { ADAU1372_REG_DAC_CTRL, 0x18 },
1025 { ADAU1372_REG_DAC_VOL(0), 0x00 },
1026 { ADAU1372_REG_DAC_VOL(1), 0x00 },
1027 { ADAU1372_REG_OP_STAGE_MUTE, 0x0f },
1028 { ADAU1372_REG_SAI0, 0x00 },
1029 { ADAU1372_REG_SAI1, 0x00 },
1030 { ADAU1372_REG_SOUT_CTRL, 0x00 },
1031 { ADAU1372_REG_MODE_MP(0), 0x00 },
1032 { ADAU1372_REG_MODE_MP(1), 0x10 },
1033 { ADAU1372_REG_MODE_MP(4), 0x00 },
1034 { ADAU1372_REG_MODE_MP(5), 0x00 },
1035 { ADAU1372_REG_MODE_MP(6), 0x11 },
1036 { ADAU1372_REG_OP_STAGE_CTRL, 0x0f },
1037 { ADAU1372_REG_DECIM_PWR, 0x00 },
1038 { ADAU1372_REG_INTERP_PWR, 0x00 },
1039 { ADAU1372_REG_BIAS_CTRL0, 0x00 },
1040 { ADAU1372_REG_BIAS_CTRL1, 0x00 },
1041};
1042
1043static bool adau1372_volatile_register(struct device *dev, unsigned int reg)
1044{
1045 if (reg == ADAU1372_REG_PLL(5))
1046 return true;
1047
1048 return false;
1049}
1050
1051const struct regmap_config adau1372_regmap_config = {
1052 .val_bits = 8,
1053 .reg_bits = 16,
1054 .max_register = 0x4d,
1055
1056 .reg_defaults = adau1372_reg_defaults,
1057 .num_reg_defaults = ARRAY_SIZE(adau1372_reg_defaults),
1058 .volatile_reg = adau1372_volatile_register,
1059 .cache_type = REGCACHE_RBTREE,
1060};
1061EXPORT_SYMBOL_GPL(adau1372_regmap_config);
1062
1063MODULE_DESCRIPTION("ASoC ADAU1372 CODEC driver");
1064MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1065MODULE_LICENSE("GPL v2");