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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright (c) 2021, Microsoft Corporation. */
3
4#ifndef _GDMA_H
5#define _GDMA_H
6
7#include <linux/dma-mapping.h>
8#include <linux/netdevice.h>
9
10#include "shm_channel.h"
11
12#define GDMA_STATUS_MORE_ENTRIES 0x00000105
13
14/* Structures labeled with "HW DATA" are exchanged with the hardware. All of
15 * them are naturally aligned and hence don't need __packed.
16 */
17
18enum gdma_request_type {
19 GDMA_VERIFY_VF_DRIVER_VERSION = 1,
20 GDMA_QUERY_MAX_RESOURCES = 2,
21 GDMA_LIST_DEVICES = 3,
22 GDMA_REGISTER_DEVICE = 4,
23 GDMA_DEREGISTER_DEVICE = 5,
24 GDMA_GENERATE_TEST_EQE = 10,
25 GDMA_CREATE_QUEUE = 12,
26 GDMA_DISABLE_QUEUE = 13,
27 GDMA_ALLOCATE_RESOURCE_RANGE = 22,
28 GDMA_DESTROY_RESOURCE_RANGE = 24,
29 GDMA_CREATE_DMA_REGION = 25,
30 GDMA_DMA_REGION_ADD_PAGES = 26,
31 GDMA_DESTROY_DMA_REGION = 27,
32 GDMA_CREATE_PD = 29,
33 GDMA_DESTROY_PD = 30,
34 GDMA_CREATE_MR = 31,
35 GDMA_DESTROY_MR = 32,
36 GDMA_QUERY_HWC_TIMEOUT = 84, /* 0x54 */
37};
38
39#define GDMA_RESOURCE_DOORBELL_PAGE 27
40
41enum gdma_queue_type {
42 GDMA_INVALID_QUEUE,
43 GDMA_SQ,
44 GDMA_RQ,
45 GDMA_CQ,
46 GDMA_EQ,
47};
48
49enum gdma_work_request_flags {
50 GDMA_WR_NONE = 0,
51 GDMA_WR_OOB_IN_SGL = BIT(0),
52 GDMA_WR_PAD_BY_SGE0 = BIT(1),
53};
54
55enum gdma_eqe_type {
56 GDMA_EQE_COMPLETION = 3,
57 GDMA_EQE_TEST_EVENT = 64,
58 GDMA_EQE_HWC_INIT_EQ_ID_DB = 129,
59 GDMA_EQE_HWC_INIT_DATA = 130,
60 GDMA_EQE_HWC_INIT_DONE = 131,
61 GDMA_EQE_HWC_SOC_RECONFIG = 132,
62 GDMA_EQE_HWC_SOC_RECONFIG_DATA = 133,
63 GDMA_EQE_RNIC_QP_FATAL = 176,
64};
65
66enum {
67 GDMA_DEVICE_NONE = 0,
68 GDMA_DEVICE_HWC = 1,
69 GDMA_DEVICE_MANA = 2,
70 GDMA_DEVICE_MANA_IB = 3,
71};
72
73struct gdma_resource {
74 /* Protect the bitmap */
75 spinlock_t lock;
76
77 /* The bitmap size in bits. */
78 u32 size;
79
80 /* The bitmap tracks the resources. */
81 unsigned long *map;
82};
83
84union gdma_doorbell_entry {
85 u64 as_uint64;
86
87 struct {
88 u64 id : 24;
89 u64 reserved : 8;
90 u64 tail_ptr : 31;
91 u64 arm : 1;
92 } cq;
93
94 struct {
95 u64 id : 24;
96 u64 wqe_cnt : 8;
97 u64 tail_ptr : 32;
98 } rq;
99
100 struct {
101 u64 id : 24;
102 u64 reserved : 8;
103 u64 tail_ptr : 32;
104 } sq;
105
106 struct {
107 u64 id : 16;
108 u64 reserved : 16;
109 u64 tail_ptr : 31;
110 u64 arm : 1;
111 } eq;
112}; /* HW DATA */
113
114struct gdma_msg_hdr {
115 u32 hdr_type;
116 u32 msg_type;
117 u16 msg_version;
118 u16 hwc_msg_id;
119 u32 msg_size;
120}; /* HW DATA */
121
122struct gdma_dev_id {
123 union {
124 struct {
125 u16 type;
126 u16 instance;
127 };
128
129 u32 as_uint32;
130 };
131}; /* HW DATA */
132
133struct gdma_req_hdr {
134 struct gdma_msg_hdr req;
135 struct gdma_msg_hdr resp; /* The expected response */
136 struct gdma_dev_id dev_id;
137 u32 activity_id;
138}; /* HW DATA */
139
140struct gdma_resp_hdr {
141 struct gdma_msg_hdr response;
142 struct gdma_dev_id dev_id;
143 u32 activity_id;
144 u32 status;
145 u32 reserved;
146}; /* HW DATA */
147
148struct gdma_general_req {
149 struct gdma_req_hdr hdr;
150}; /* HW DATA */
151
152#define GDMA_MESSAGE_V1 1
153#define GDMA_MESSAGE_V2 2
154#define GDMA_MESSAGE_V3 3
155
156struct gdma_general_resp {
157 struct gdma_resp_hdr hdr;
158}; /* HW DATA */
159
160#define GDMA_STANDARD_HEADER_TYPE 0
161
162static inline void mana_gd_init_req_hdr(struct gdma_req_hdr *hdr, u32 code,
163 u32 req_size, u32 resp_size)
164{
165 hdr->req.hdr_type = GDMA_STANDARD_HEADER_TYPE;
166 hdr->req.msg_type = code;
167 hdr->req.msg_version = GDMA_MESSAGE_V1;
168 hdr->req.msg_size = req_size;
169
170 hdr->resp.hdr_type = GDMA_STANDARD_HEADER_TYPE;
171 hdr->resp.msg_type = code;
172 hdr->resp.msg_version = GDMA_MESSAGE_V1;
173 hdr->resp.msg_size = resp_size;
174}
175
176/* The 16-byte struct is part of the GDMA work queue entry (WQE). */
177struct gdma_sge {
178 u64 address;
179 u32 mem_key;
180 u32 size;
181}; /* HW DATA */
182
183struct gdma_wqe_request {
184 struct gdma_sge *sgl;
185 u32 num_sge;
186
187 u32 inline_oob_size;
188 const void *inline_oob_data;
189
190 u32 flags;
191 u32 client_data_unit;
192};
193
194enum gdma_page_type {
195 GDMA_PAGE_TYPE_4K,
196};
197
198#define GDMA_INVALID_DMA_REGION 0
199
200struct gdma_mem_info {
201 struct device *dev;
202
203 dma_addr_t dma_handle;
204 void *virt_addr;
205 u64 length;
206
207 /* Allocated by the PF driver */
208 u64 dma_region_handle;
209};
210
211#define REGISTER_ATB_MST_MKEY_LOWER_SIZE 8
212
213struct gdma_dev {
214 struct gdma_context *gdma_context;
215
216 struct gdma_dev_id dev_id;
217
218 u32 pdid;
219 u32 doorbell;
220 u32 gpa_mkey;
221
222 /* GDMA driver specific pointer */
223 void *driver_data;
224
225 struct auxiliary_device *adev;
226};
227
228/* MANA_PAGE_SIZE is the DMA unit */
229#define MANA_PAGE_SHIFT 12
230#define MANA_PAGE_SIZE BIT(MANA_PAGE_SHIFT)
231#define MANA_PAGE_ALIGN(x) ALIGN((x), MANA_PAGE_SIZE)
232#define MANA_PAGE_ALIGNED(addr) IS_ALIGNED((unsigned long)(addr), MANA_PAGE_SIZE)
233#define MANA_PFN(a) ((a) >> MANA_PAGE_SHIFT)
234
235/* Required by HW */
236#define MANA_MIN_QSIZE MANA_PAGE_SIZE
237
238#define GDMA_CQE_SIZE 64
239#define GDMA_EQE_SIZE 16
240#define GDMA_MAX_SQE_SIZE 512
241#define GDMA_MAX_RQE_SIZE 256
242
243#define GDMA_COMP_DATA_SIZE 0x3C
244
245#define GDMA_EVENT_DATA_SIZE 0xC
246
247/* The WQE size must be a multiple of the Basic Unit, which is 32 bytes. */
248#define GDMA_WQE_BU_SIZE 32
249
250#define INVALID_PDID UINT_MAX
251#define INVALID_DOORBELL UINT_MAX
252#define INVALID_MEM_KEY UINT_MAX
253#define INVALID_QUEUE_ID UINT_MAX
254#define INVALID_PCI_MSIX_INDEX UINT_MAX
255
256struct gdma_comp {
257 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4];
258 u32 wq_num;
259 bool is_sq;
260};
261
262struct gdma_event {
263 u32 details[GDMA_EVENT_DATA_SIZE / 4];
264 u8 type;
265};
266
267struct gdma_queue;
268
269struct mana_eq {
270 struct gdma_queue *eq;
271 struct dentry *mana_eq_debugfs;
272};
273
274typedef void gdma_eq_callback(void *context, struct gdma_queue *q,
275 struct gdma_event *e);
276
277typedef void gdma_cq_callback(void *context, struct gdma_queue *q);
278
279/* The 'head' is the producer index. For SQ/RQ, when the driver posts a WQE
280 * (Note: the WQE size must be a multiple of the 32-byte Basic Unit), the
281 * driver increases the 'head' in BUs rather than in bytes, and notifies
282 * the HW of the updated head. For EQ/CQ, the driver uses the 'head' to track
283 * the HW head, and increases the 'head' by 1 for every processed EQE/CQE.
284 *
285 * The 'tail' is the consumer index for SQ/RQ. After the CQE of the SQ/RQ is
286 * processed, the driver increases the 'tail' to indicate that WQEs have
287 * been consumed by the HW, so the driver can post new WQEs into the SQ/RQ.
288 *
289 * The driver doesn't use the 'tail' for EQ/CQ, because the driver ensures
290 * that the EQ/CQ is big enough so they can't overflow, and the driver uses
291 * the owner bits mechanism to detect if the queue has become empty.
292 */
293struct gdma_queue {
294 struct gdma_dev *gdma_dev;
295
296 enum gdma_queue_type type;
297 u32 id;
298
299 struct gdma_mem_info mem_info;
300
301 void *queue_mem_ptr;
302 u32 queue_size;
303
304 bool monitor_avl_buf;
305
306 u32 head;
307 u32 tail;
308 struct list_head entry;
309
310 /* Extra fields specific to EQ/CQ. */
311 union {
312 struct {
313 bool disable_needed;
314
315 gdma_eq_callback *callback;
316 void *context;
317
318 unsigned int msix_index;
319
320 u32 log2_throttle_limit;
321 } eq;
322
323 struct {
324 gdma_cq_callback *callback;
325 void *context;
326
327 struct gdma_queue *parent; /* For CQ/EQ relationship */
328 } cq;
329 };
330};
331
332struct gdma_queue_spec {
333 enum gdma_queue_type type;
334 bool monitor_avl_buf;
335 unsigned int queue_size;
336
337 /* Extra fields specific to EQ/CQ. */
338 union {
339 struct {
340 gdma_eq_callback *callback;
341 void *context;
342
343 unsigned long log2_throttle_limit;
344 unsigned int msix_index;
345 } eq;
346
347 struct {
348 gdma_cq_callback *callback;
349 void *context;
350
351 struct gdma_queue *parent_eq;
352
353 } cq;
354 };
355};
356
357#define MANA_IRQ_NAME_SZ 32
358
359struct gdma_irq_context {
360 void (*handler)(void *arg);
361 /* Protect the eq_list */
362 spinlock_t lock;
363 struct list_head eq_list;
364 char name[MANA_IRQ_NAME_SZ];
365};
366
367struct gdma_context {
368 struct device *dev;
369 struct dentry *mana_pci_debugfs;
370
371 /* Per-vPort max number of queues */
372 unsigned int max_num_queues;
373 unsigned int max_num_msix;
374 unsigned int num_msix_usable;
375 struct gdma_irq_context *irq_contexts;
376
377 /* L2 MTU */
378 u16 adapter_mtu;
379
380 /* This maps a CQ index to the queue structure. */
381 unsigned int max_num_cqs;
382 struct gdma_queue **cq_table;
383
384 /* Protect eq_test_event and test_event_eq_id */
385 struct mutex eq_test_event_mutex;
386 struct completion eq_test_event;
387 u32 test_event_eq_id;
388
389 bool is_pf;
390 phys_addr_t bar0_pa;
391 void __iomem *bar0_va;
392 void __iomem *shm_base;
393 void __iomem *db_page_base;
394 phys_addr_t phys_db_page_base;
395 u32 db_page_size;
396 int numa_node;
397
398 /* Shared memory chanenl (used to bootstrap HWC) */
399 struct shm_channel shm_channel;
400
401 /* Hardware communication channel (HWC) */
402 struct gdma_dev hwc;
403
404 /* Azure network adapter */
405 struct gdma_dev mana;
406
407 /* Azure RDMA adapter */
408 struct gdma_dev mana_ib;
409};
410
411#define MAX_NUM_GDMA_DEVICES 4
412
413static inline bool mana_gd_is_mana(struct gdma_dev *gd)
414{
415 return gd->dev_id.type == GDMA_DEVICE_MANA;
416}
417
418static inline bool mana_gd_is_hwc(struct gdma_dev *gd)
419{
420 return gd->dev_id.type == GDMA_DEVICE_HWC;
421}
422
423u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset);
424u32 mana_gd_wq_avail_space(struct gdma_queue *wq);
425
426int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq);
427
428int mana_gd_create_hwc_queue(struct gdma_dev *gd,
429 const struct gdma_queue_spec *spec,
430 struct gdma_queue **queue_ptr);
431
432int mana_gd_create_mana_eq(struct gdma_dev *gd,
433 const struct gdma_queue_spec *spec,
434 struct gdma_queue **queue_ptr);
435
436int mana_gd_create_mana_wq_cq(struct gdma_dev *gd,
437 const struct gdma_queue_spec *spec,
438 struct gdma_queue **queue_ptr);
439
440void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue);
441
442int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe);
443
444void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit);
445
446struct gdma_wqe {
447 u32 reserved :24;
448 u32 last_vbytes :8;
449
450 union {
451 u32 flags;
452
453 struct {
454 u32 num_sge :8;
455 u32 inline_oob_size_div4:3;
456 u32 client_oob_in_sgl :1;
457 u32 reserved1 :4;
458 u32 client_data_unit :14;
459 u32 reserved2 :2;
460 };
461 };
462}; /* HW DATA */
463
464#define INLINE_OOB_SMALL_SIZE 8
465#define INLINE_OOB_LARGE_SIZE 24
466
467#define MAX_TX_WQE_SIZE 512
468#define MAX_RX_WQE_SIZE 256
469
470#define MAX_TX_WQE_SGL_ENTRIES ((GDMA_MAX_SQE_SIZE - \
471 sizeof(struct gdma_sge) - INLINE_OOB_SMALL_SIZE) / \
472 sizeof(struct gdma_sge))
473
474#define MAX_RX_WQE_SGL_ENTRIES ((GDMA_MAX_RQE_SIZE - \
475 sizeof(struct gdma_sge)) / sizeof(struct gdma_sge))
476
477struct gdma_cqe {
478 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4];
479
480 union {
481 u32 as_uint32;
482
483 struct {
484 u32 wq_num : 24;
485 u32 is_sq : 1;
486 u32 reserved : 4;
487 u32 owner_bits : 3;
488 };
489 } cqe_info;
490}; /* HW DATA */
491
492#define GDMA_CQE_OWNER_BITS 3
493
494#define GDMA_CQE_OWNER_MASK ((1 << GDMA_CQE_OWNER_BITS) - 1)
495
496#define SET_ARM_BIT 1
497
498#define GDMA_EQE_OWNER_BITS 3
499
500union gdma_eqe_info {
501 u32 as_uint32;
502
503 struct {
504 u32 type : 8;
505 u32 reserved1 : 8;
506 u32 client_id : 2;
507 u32 reserved2 : 11;
508 u32 owner_bits : 3;
509 };
510}; /* HW DATA */
511
512#define GDMA_EQE_OWNER_MASK ((1 << GDMA_EQE_OWNER_BITS) - 1)
513#define INITIALIZED_OWNER_BIT(log2_num_entries) (1UL << (log2_num_entries))
514
515struct gdma_eqe {
516 u32 details[GDMA_EVENT_DATA_SIZE / 4];
517 u32 eqe_info;
518}; /* HW DATA */
519
520#define GDMA_REG_DB_PAGE_OFFSET 8
521#define GDMA_REG_DB_PAGE_SIZE 0x10
522#define GDMA_REG_SHM_OFFSET 0x18
523
524#define GDMA_PF_REG_DB_PAGE_SIZE 0xD0
525#define GDMA_PF_REG_DB_PAGE_OFF 0xC8
526#define GDMA_PF_REG_SHM_OFF 0x70
527
528#define GDMA_SRIOV_REG_CFG_BASE_OFF 0x108
529
530#define MANA_PF_DEVICE_ID 0x00B9
531#define MANA_VF_DEVICE_ID 0x00BA
532
533struct gdma_posted_wqe_info {
534 u32 wqe_size_in_bu;
535};
536
537/* GDMA_GENERATE_TEST_EQE */
538struct gdma_generate_test_event_req {
539 struct gdma_req_hdr hdr;
540 u32 queue_index;
541}; /* HW DATA */
542
543/* GDMA_VERIFY_VF_DRIVER_VERSION */
544enum {
545 GDMA_PROTOCOL_V1 = 1,
546 GDMA_PROTOCOL_FIRST = GDMA_PROTOCOL_V1,
547 GDMA_PROTOCOL_LAST = GDMA_PROTOCOL_V1,
548};
549
550#define GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT BIT(0)
551
552/* Advertise to the NIC firmware: the NAPI work_done variable race is fixed,
553 * so the driver is able to reliably support features like busy_poll.
554 */
555#define GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX BIT(2)
556#define GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG BIT(3)
557#define GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT BIT(5)
558
559#define GDMA_DRV_CAP_FLAGS1 \
560 (GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT | \
561 GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX | \
562 GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG | \
563 GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT)
564
565#define GDMA_DRV_CAP_FLAGS2 0
566
567#define GDMA_DRV_CAP_FLAGS3 0
568
569#define GDMA_DRV_CAP_FLAGS4 0
570
571struct gdma_verify_ver_req {
572 struct gdma_req_hdr hdr;
573
574 /* Mandatory fields required for protocol establishment */
575 u64 protocol_ver_min;
576 u64 protocol_ver_max;
577
578 /* Gdma Driver Capability Flags */
579 u64 gd_drv_cap_flags1;
580 u64 gd_drv_cap_flags2;
581 u64 gd_drv_cap_flags3;
582 u64 gd_drv_cap_flags4;
583
584 /* Advisory fields */
585 u64 drv_ver;
586 u32 os_type; /* Linux = 0x10; Windows = 0x20; Other = 0x30 */
587 u32 reserved;
588 u32 os_ver_major;
589 u32 os_ver_minor;
590 u32 os_ver_build;
591 u32 os_ver_platform;
592 u64 reserved_2;
593 u8 os_ver_str1[128];
594 u8 os_ver_str2[128];
595 u8 os_ver_str3[128];
596 u8 os_ver_str4[128];
597}; /* HW DATA */
598
599struct gdma_verify_ver_resp {
600 struct gdma_resp_hdr hdr;
601 u64 gdma_protocol_ver;
602 u64 pf_cap_flags1;
603 u64 pf_cap_flags2;
604 u64 pf_cap_flags3;
605 u64 pf_cap_flags4;
606}; /* HW DATA */
607
608/* GDMA_QUERY_MAX_RESOURCES */
609struct gdma_query_max_resources_resp {
610 struct gdma_resp_hdr hdr;
611 u32 status;
612 u32 max_sq;
613 u32 max_rq;
614 u32 max_cq;
615 u32 max_eq;
616 u32 max_db;
617 u32 max_mst;
618 u32 max_cq_mod_ctx;
619 u32 max_mod_cq;
620 u32 max_msix;
621}; /* HW DATA */
622
623/* GDMA_LIST_DEVICES */
624struct gdma_list_devices_resp {
625 struct gdma_resp_hdr hdr;
626 u32 num_of_devs;
627 u32 reserved;
628 struct gdma_dev_id devs[64];
629}; /* HW DATA */
630
631/* GDMA_REGISTER_DEVICE */
632struct gdma_register_device_resp {
633 struct gdma_resp_hdr hdr;
634 u32 pdid;
635 u32 gpa_mkey;
636 u32 db_id;
637}; /* HW DATA */
638
639struct gdma_allocate_resource_range_req {
640 struct gdma_req_hdr hdr;
641 u32 resource_type;
642 u32 num_resources;
643 u32 alignment;
644 u32 allocated_resources;
645};
646
647struct gdma_allocate_resource_range_resp {
648 struct gdma_resp_hdr hdr;
649 u32 allocated_resources;
650};
651
652struct gdma_destroy_resource_range_req {
653 struct gdma_req_hdr hdr;
654 u32 resource_type;
655 u32 num_resources;
656 u32 allocated_resources;
657};
658
659/* GDMA_CREATE_QUEUE */
660struct gdma_create_queue_req {
661 struct gdma_req_hdr hdr;
662 u32 type;
663 u32 reserved1;
664 u32 pdid;
665 u32 doolbell_id;
666 u64 gdma_region;
667 u32 reserved2;
668 u32 queue_size;
669 u32 log2_throttle_limit;
670 u32 eq_pci_msix_index;
671 u32 cq_mod_ctx_id;
672 u32 cq_parent_eq_id;
673 u8 rq_drop_on_overrun;
674 u8 rq_err_on_wqe_overflow;
675 u8 rq_chain_rec_wqes;
676 u8 sq_hw_db;
677 u32 reserved3;
678}; /* HW DATA */
679
680struct gdma_create_queue_resp {
681 struct gdma_resp_hdr hdr;
682 u32 queue_index;
683}; /* HW DATA */
684
685/* GDMA_DISABLE_QUEUE */
686struct gdma_disable_queue_req {
687 struct gdma_req_hdr hdr;
688 u32 type;
689 u32 queue_index;
690 u32 alloc_res_id_on_creation;
691}; /* HW DATA */
692
693/* GDMA_QUERY_HWC_TIMEOUT */
694struct gdma_query_hwc_timeout_req {
695 struct gdma_req_hdr hdr;
696 u32 timeout_ms;
697 u32 reserved;
698};
699
700struct gdma_query_hwc_timeout_resp {
701 struct gdma_resp_hdr hdr;
702 u32 timeout_ms;
703 u32 reserved;
704};
705
706enum atb_page_size {
707 ATB_PAGE_SIZE_4K,
708 ATB_PAGE_SIZE_8K,
709 ATB_PAGE_SIZE_16K,
710 ATB_PAGE_SIZE_32K,
711 ATB_PAGE_SIZE_64K,
712 ATB_PAGE_SIZE_128K,
713 ATB_PAGE_SIZE_256K,
714 ATB_PAGE_SIZE_512K,
715 ATB_PAGE_SIZE_1M,
716 ATB_PAGE_SIZE_2M,
717 ATB_PAGE_SIZE_MAX,
718};
719
720enum gdma_mr_access_flags {
721 GDMA_ACCESS_FLAG_LOCAL_READ = BIT_ULL(0),
722 GDMA_ACCESS_FLAG_LOCAL_WRITE = BIT_ULL(1),
723 GDMA_ACCESS_FLAG_REMOTE_READ = BIT_ULL(2),
724 GDMA_ACCESS_FLAG_REMOTE_WRITE = BIT_ULL(3),
725 GDMA_ACCESS_FLAG_REMOTE_ATOMIC = BIT_ULL(4),
726};
727
728/* GDMA_CREATE_DMA_REGION */
729struct gdma_create_dma_region_req {
730 struct gdma_req_hdr hdr;
731
732 /* The total size of the DMA region */
733 u64 length;
734
735 /* The offset in the first page */
736 u32 offset_in_page;
737
738 /* enum gdma_page_type */
739 u32 gdma_page_type;
740
741 /* The total number of pages */
742 u32 page_count;
743
744 /* If page_addr_list_len is smaller than page_count,
745 * the remaining page addresses will be added via the
746 * message GDMA_DMA_REGION_ADD_PAGES.
747 */
748 u32 page_addr_list_len;
749 u64 page_addr_list[];
750}; /* HW DATA */
751
752struct gdma_create_dma_region_resp {
753 struct gdma_resp_hdr hdr;
754 u64 dma_region_handle;
755}; /* HW DATA */
756
757/* GDMA_DMA_REGION_ADD_PAGES */
758struct gdma_dma_region_add_pages_req {
759 struct gdma_req_hdr hdr;
760
761 u64 dma_region_handle;
762
763 u32 page_addr_list_len;
764 u32 reserved3;
765
766 u64 page_addr_list[];
767}; /* HW DATA */
768
769/* GDMA_DESTROY_DMA_REGION */
770struct gdma_destroy_dma_region_req {
771 struct gdma_req_hdr hdr;
772
773 u64 dma_region_handle;
774}; /* HW DATA */
775
776enum gdma_pd_flags {
777 GDMA_PD_FLAG_INVALID = 0,
778};
779
780struct gdma_create_pd_req {
781 struct gdma_req_hdr hdr;
782 enum gdma_pd_flags flags;
783 u32 reserved;
784};/* HW DATA */
785
786struct gdma_create_pd_resp {
787 struct gdma_resp_hdr hdr;
788 u64 pd_handle;
789 u32 pd_id;
790 u32 reserved;
791};/* HW DATA */
792
793struct gdma_destroy_pd_req {
794 struct gdma_req_hdr hdr;
795 u64 pd_handle;
796};/* HW DATA */
797
798struct gdma_destory_pd_resp {
799 struct gdma_resp_hdr hdr;
800};/* HW DATA */
801
802enum gdma_mr_type {
803 /* Guest Virtual Address - MRs of this type allow access
804 * to memory mapped by PTEs associated with this MR using a virtual
805 * address that is set up in the MST
806 */
807 GDMA_MR_TYPE_GVA = 2,
808};
809
810struct gdma_create_mr_params {
811 u64 pd_handle;
812 enum gdma_mr_type mr_type;
813 union {
814 struct {
815 u64 dma_region_handle;
816 u64 virtual_address;
817 enum gdma_mr_access_flags access_flags;
818 } gva;
819 };
820};
821
822struct gdma_create_mr_request {
823 struct gdma_req_hdr hdr;
824 u64 pd_handle;
825 enum gdma_mr_type mr_type;
826 u32 reserved_1;
827
828 union {
829 struct {
830 u64 dma_region_handle;
831 u64 virtual_address;
832 enum gdma_mr_access_flags access_flags;
833 } gva;
834
835 };
836 u32 reserved_2;
837};/* HW DATA */
838
839struct gdma_create_mr_response {
840 struct gdma_resp_hdr hdr;
841 u64 mr_handle;
842 u32 lkey;
843 u32 rkey;
844};/* HW DATA */
845
846struct gdma_destroy_mr_request {
847 struct gdma_req_hdr hdr;
848 u64 mr_handle;
849};/* HW DATA */
850
851struct gdma_destroy_mr_response {
852 struct gdma_resp_hdr hdr;
853};/* HW DATA */
854
855int mana_gd_verify_vf_version(struct pci_dev *pdev);
856
857int mana_gd_register_device(struct gdma_dev *gd);
858int mana_gd_deregister_device(struct gdma_dev *gd);
859
860int mana_gd_post_work_request(struct gdma_queue *wq,
861 const struct gdma_wqe_request *wqe_req,
862 struct gdma_posted_wqe_info *wqe_info);
863
864int mana_gd_post_and_ring(struct gdma_queue *queue,
865 const struct gdma_wqe_request *wqe,
866 struct gdma_posted_wqe_info *wqe_info);
867
868int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r);
869void mana_gd_free_res_map(struct gdma_resource *r);
870
871void mana_gd_wq_ring_doorbell(struct gdma_context *gc,
872 struct gdma_queue *queue);
873
874int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length,
875 struct gdma_mem_info *gmi);
876
877void mana_gd_free_memory(struct gdma_mem_info *gmi);
878
879int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req,
880 u32 resp_len, void *resp);
881
882int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle);
883void mana_register_debugfs(void);
884void mana_unregister_debugfs(void);
885
886#endif /* _GDMA_H */
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright (c) 2021, Microsoft Corporation. */
3
4#ifndef _GDMA_H
5#define _GDMA_H
6
7#include <linux/dma-mapping.h>
8#include <linux/netdevice.h>
9
10#include "shm_channel.h"
11
12#define GDMA_STATUS_MORE_ENTRIES 0x00000105
13
14/* Structures labeled with "HW DATA" are exchanged with the hardware. All of
15 * them are naturally aligned and hence don't need __packed.
16 */
17
18enum gdma_request_type {
19 GDMA_VERIFY_VF_DRIVER_VERSION = 1,
20 GDMA_QUERY_MAX_RESOURCES = 2,
21 GDMA_LIST_DEVICES = 3,
22 GDMA_REGISTER_DEVICE = 4,
23 GDMA_DEREGISTER_DEVICE = 5,
24 GDMA_GENERATE_TEST_EQE = 10,
25 GDMA_CREATE_QUEUE = 12,
26 GDMA_DISABLE_QUEUE = 13,
27 GDMA_ALLOCATE_RESOURCE_RANGE = 22,
28 GDMA_DESTROY_RESOURCE_RANGE = 24,
29 GDMA_CREATE_DMA_REGION = 25,
30 GDMA_DMA_REGION_ADD_PAGES = 26,
31 GDMA_DESTROY_DMA_REGION = 27,
32 GDMA_CREATE_PD = 29,
33 GDMA_DESTROY_PD = 30,
34 GDMA_CREATE_MR = 31,
35 GDMA_DESTROY_MR = 32,
36};
37
38#define GDMA_RESOURCE_DOORBELL_PAGE 27
39
40enum gdma_queue_type {
41 GDMA_INVALID_QUEUE,
42 GDMA_SQ,
43 GDMA_RQ,
44 GDMA_CQ,
45 GDMA_EQ,
46};
47
48enum gdma_work_request_flags {
49 GDMA_WR_NONE = 0,
50 GDMA_WR_OOB_IN_SGL = BIT(0),
51 GDMA_WR_PAD_BY_SGE0 = BIT(1),
52};
53
54enum gdma_eqe_type {
55 GDMA_EQE_COMPLETION = 3,
56 GDMA_EQE_TEST_EVENT = 64,
57 GDMA_EQE_HWC_INIT_EQ_ID_DB = 129,
58 GDMA_EQE_HWC_INIT_DATA = 130,
59 GDMA_EQE_HWC_INIT_DONE = 131,
60};
61
62enum {
63 GDMA_DEVICE_NONE = 0,
64 GDMA_DEVICE_HWC = 1,
65 GDMA_DEVICE_MANA = 2,
66};
67
68struct gdma_resource {
69 /* Protect the bitmap */
70 spinlock_t lock;
71
72 /* The bitmap size in bits. */
73 u32 size;
74
75 /* The bitmap tracks the resources. */
76 unsigned long *map;
77};
78
79union gdma_doorbell_entry {
80 u64 as_uint64;
81
82 struct {
83 u64 id : 24;
84 u64 reserved : 8;
85 u64 tail_ptr : 31;
86 u64 arm : 1;
87 } cq;
88
89 struct {
90 u64 id : 24;
91 u64 wqe_cnt : 8;
92 u64 tail_ptr : 32;
93 } rq;
94
95 struct {
96 u64 id : 24;
97 u64 reserved : 8;
98 u64 tail_ptr : 32;
99 } sq;
100
101 struct {
102 u64 id : 16;
103 u64 reserved : 16;
104 u64 tail_ptr : 31;
105 u64 arm : 1;
106 } eq;
107}; /* HW DATA */
108
109struct gdma_msg_hdr {
110 u32 hdr_type;
111 u32 msg_type;
112 u16 msg_version;
113 u16 hwc_msg_id;
114 u32 msg_size;
115}; /* HW DATA */
116
117struct gdma_dev_id {
118 union {
119 struct {
120 u16 type;
121 u16 instance;
122 };
123
124 u32 as_uint32;
125 };
126}; /* HW DATA */
127
128struct gdma_req_hdr {
129 struct gdma_msg_hdr req;
130 struct gdma_msg_hdr resp; /* The expected response */
131 struct gdma_dev_id dev_id;
132 u32 activity_id;
133}; /* HW DATA */
134
135struct gdma_resp_hdr {
136 struct gdma_msg_hdr response;
137 struct gdma_dev_id dev_id;
138 u32 activity_id;
139 u32 status;
140 u32 reserved;
141}; /* HW DATA */
142
143struct gdma_general_req {
144 struct gdma_req_hdr hdr;
145}; /* HW DATA */
146
147#define GDMA_MESSAGE_V1 1
148
149struct gdma_general_resp {
150 struct gdma_resp_hdr hdr;
151}; /* HW DATA */
152
153#define GDMA_STANDARD_HEADER_TYPE 0
154
155static inline void mana_gd_init_req_hdr(struct gdma_req_hdr *hdr, u32 code,
156 u32 req_size, u32 resp_size)
157{
158 hdr->req.hdr_type = GDMA_STANDARD_HEADER_TYPE;
159 hdr->req.msg_type = code;
160 hdr->req.msg_version = GDMA_MESSAGE_V1;
161 hdr->req.msg_size = req_size;
162
163 hdr->resp.hdr_type = GDMA_STANDARD_HEADER_TYPE;
164 hdr->resp.msg_type = code;
165 hdr->resp.msg_version = GDMA_MESSAGE_V1;
166 hdr->resp.msg_size = resp_size;
167}
168
169/* The 16-byte struct is part of the GDMA work queue entry (WQE). */
170struct gdma_sge {
171 u64 address;
172 u32 mem_key;
173 u32 size;
174}; /* HW DATA */
175
176struct gdma_wqe_request {
177 struct gdma_sge *sgl;
178 u32 num_sge;
179
180 u32 inline_oob_size;
181 const void *inline_oob_data;
182
183 u32 flags;
184 u32 client_data_unit;
185};
186
187enum gdma_page_type {
188 GDMA_PAGE_TYPE_4K,
189};
190
191#define GDMA_INVALID_DMA_REGION 0
192
193struct gdma_mem_info {
194 struct device *dev;
195
196 dma_addr_t dma_handle;
197 void *virt_addr;
198 u64 length;
199
200 /* Allocated by the PF driver */
201 u64 dma_region_handle;
202};
203
204#define REGISTER_ATB_MST_MKEY_LOWER_SIZE 8
205
206struct gdma_dev {
207 struct gdma_context *gdma_context;
208
209 struct gdma_dev_id dev_id;
210
211 u32 pdid;
212 u32 doorbell;
213 u32 gpa_mkey;
214
215 /* GDMA driver specific pointer */
216 void *driver_data;
217
218 struct auxiliary_device *adev;
219};
220
221#define MINIMUM_SUPPORTED_PAGE_SIZE PAGE_SIZE
222
223#define GDMA_CQE_SIZE 64
224#define GDMA_EQE_SIZE 16
225#define GDMA_MAX_SQE_SIZE 512
226#define GDMA_MAX_RQE_SIZE 256
227
228#define GDMA_COMP_DATA_SIZE 0x3C
229
230#define GDMA_EVENT_DATA_SIZE 0xC
231
232/* The WQE size must be a multiple of the Basic Unit, which is 32 bytes. */
233#define GDMA_WQE_BU_SIZE 32
234
235#define INVALID_PDID UINT_MAX
236#define INVALID_DOORBELL UINT_MAX
237#define INVALID_MEM_KEY UINT_MAX
238#define INVALID_QUEUE_ID UINT_MAX
239#define INVALID_PCI_MSIX_INDEX UINT_MAX
240
241struct gdma_comp {
242 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4];
243 u32 wq_num;
244 bool is_sq;
245};
246
247struct gdma_event {
248 u32 details[GDMA_EVENT_DATA_SIZE / 4];
249 u8 type;
250};
251
252struct gdma_queue;
253
254struct mana_eq {
255 struct gdma_queue *eq;
256};
257
258typedef void gdma_eq_callback(void *context, struct gdma_queue *q,
259 struct gdma_event *e);
260
261typedef void gdma_cq_callback(void *context, struct gdma_queue *q);
262
263/* The 'head' is the producer index. For SQ/RQ, when the driver posts a WQE
264 * (Note: the WQE size must be a multiple of the 32-byte Basic Unit), the
265 * driver increases the 'head' in BUs rather than in bytes, and notifies
266 * the HW of the updated head. For EQ/CQ, the driver uses the 'head' to track
267 * the HW head, and increases the 'head' by 1 for every processed EQE/CQE.
268 *
269 * The 'tail' is the consumer index for SQ/RQ. After the CQE of the SQ/RQ is
270 * processed, the driver increases the 'tail' to indicate that WQEs have
271 * been consumed by the HW, so the driver can post new WQEs into the SQ/RQ.
272 *
273 * The driver doesn't use the 'tail' for EQ/CQ, because the driver ensures
274 * that the EQ/CQ is big enough so they can't overflow, and the driver uses
275 * the owner bits mechanism to detect if the queue has become empty.
276 */
277struct gdma_queue {
278 struct gdma_dev *gdma_dev;
279
280 enum gdma_queue_type type;
281 u32 id;
282
283 struct gdma_mem_info mem_info;
284
285 void *queue_mem_ptr;
286 u32 queue_size;
287
288 bool monitor_avl_buf;
289
290 u32 head;
291 u32 tail;
292
293 /* Extra fields specific to EQ/CQ. */
294 union {
295 struct {
296 bool disable_needed;
297
298 gdma_eq_callback *callback;
299 void *context;
300
301 unsigned int msix_index;
302
303 u32 log2_throttle_limit;
304 } eq;
305
306 struct {
307 gdma_cq_callback *callback;
308 void *context;
309
310 struct gdma_queue *parent; /* For CQ/EQ relationship */
311 } cq;
312 };
313};
314
315struct gdma_queue_spec {
316 enum gdma_queue_type type;
317 bool monitor_avl_buf;
318 unsigned int queue_size;
319
320 /* Extra fields specific to EQ/CQ. */
321 union {
322 struct {
323 gdma_eq_callback *callback;
324 void *context;
325
326 unsigned long log2_throttle_limit;
327 } eq;
328
329 struct {
330 gdma_cq_callback *callback;
331 void *context;
332
333 struct gdma_queue *parent_eq;
334
335 } cq;
336 };
337};
338
339#define MANA_IRQ_NAME_SZ 32
340
341struct gdma_irq_context {
342 void (*handler)(void *arg);
343 void *arg;
344 char name[MANA_IRQ_NAME_SZ];
345};
346
347struct gdma_context {
348 struct device *dev;
349
350 /* Per-vPort max number of queues */
351 unsigned int max_num_queues;
352 unsigned int max_num_msix;
353 unsigned int num_msix_usable;
354 struct gdma_resource msix_resource;
355 struct gdma_irq_context *irq_contexts;
356
357 /* This maps a CQ index to the queue structure. */
358 unsigned int max_num_cqs;
359 struct gdma_queue **cq_table;
360
361 /* Protect eq_test_event and test_event_eq_id */
362 struct mutex eq_test_event_mutex;
363 struct completion eq_test_event;
364 u32 test_event_eq_id;
365
366 bool is_pf;
367 phys_addr_t bar0_pa;
368 void __iomem *bar0_va;
369 void __iomem *shm_base;
370 void __iomem *db_page_base;
371 phys_addr_t phys_db_page_base;
372 u32 db_page_size;
373 int numa_node;
374
375 /* Shared memory chanenl (used to bootstrap HWC) */
376 struct shm_channel shm_channel;
377
378 /* Hardware communication channel (HWC) */
379 struct gdma_dev hwc;
380
381 /* Azure network adapter */
382 struct gdma_dev mana;
383};
384
385#define MAX_NUM_GDMA_DEVICES 4
386
387static inline bool mana_gd_is_mana(struct gdma_dev *gd)
388{
389 return gd->dev_id.type == GDMA_DEVICE_MANA;
390}
391
392static inline bool mana_gd_is_hwc(struct gdma_dev *gd)
393{
394 return gd->dev_id.type == GDMA_DEVICE_HWC;
395}
396
397u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset);
398u32 mana_gd_wq_avail_space(struct gdma_queue *wq);
399
400int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq);
401
402int mana_gd_create_hwc_queue(struct gdma_dev *gd,
403 const struct gdma_queue_spec *spec,
404 struct gdma_queue **queue_ptr);
405
406int mana_gd_create_mana_eq(struct gdma_dev *gd,
407 const struct gdma_queue_spec *spec,
408 struct gdma_queue **queue_ptr);
409
410int mana_gd_create_mana_wq_cq(struct gdma_dev *gd,
411 const struct gdma_queue_spec *spec,
412 struct gdma_queue **queue_ptr);
413
414void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue);
415
416int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe);
417
418void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit);
419
420struct gdma_wqe {
421 u32 reserved :24;
422 u32 last_vbytes :8;
423
424 union {
425 u32 flags;
426
427 struct {
428 u32 num_sge :8;
429 u32 inline_oob_size_div4:3;
430 u32 client_oob_in_sgl :1;
431 u32 reserved1 :4;
432 u32 client_data_unit :14;
433 u32 reserved2 :2;
434 };
435 };
436}; /* HW DATA */
437
438#define INLINE_OOB_SMALL_SIZE 8
439#define INLINE_OOB_LARGE_SIZE 24
440
441#define MAX_TX_WQE_SIZE 512
442#define MAX_RX_WQE_SIZE 256
443
444#define MAX_TX_WQE_SGL_ENTRIES ((GDMA_MAX_SQE_SIZE - \
445 sizeof(struct gdma_sge) - INLINE_OOB_SMALL_SIZE) / \
446 sizeof(struct gdma_sge))
447
448#define MAX_RX_WQE_SGL_ENTRIES ((GDMA_MAX_RQE_SIZE - \
449 sizeof(struct gdma_sge)) / sizeof(struct gdma_sge))
450
451struct gdma_cqe {
452 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4];
453
454 union {
455 u32 as_uint32;
456
457 struct {
458 u32 wq_num : 24;
459 u32 is_sq : 1;
460 u32 reserved : 4;
461 u32 owner_bits : 3;
462 };
463 } cqe_info;
464}; /* HW DATA */
465
466#define GDMA_CQE_OWNER_BITS 3
467
468#define GDMA_CQE_OWNER_MASK ((1 << GDMA_CQE_OWNER_BITS) - 1)
469
470#define SET_ARM_BIT 1
471
472#define GDMA_EQE_OWNER_BITS 3
473
474union gdma_eqe_info {
475 u32 as_uint32;
476
477 struct {
478 u32 type : 8;
479 u32 reserved1 : 8;
480 u32 client_id : 2;
481 u32 reserved2 : 11;
482 u32 owner_bits : 3;
483 };
484}; /* HW DATA */
485
486#define GDMA_EQE_OWNER_MASK ((1 << GDMA_EQE_OWNER_BITS) - 1)
487#define INITIALIZED_OWNER_BIT(log2_num_entries) (1UL << (log2_num_entries))
488
489struct gdma_eqe {
490 u32 details[GDMA_EVENT_DATA_SIZE / 4];
491 u32 eqe_info;
492}; /* HW DATA */
493
494#define GDMA_REG_DB_PAGE_OFFSET 8
495#define GDMA_REG_DB_PAGE_SIZE 0x10
496#define GDMA_REG_SHM_OFFSET 0x18
497
498#define GDMA_PF_REG_DB_PAGE_SIZE 0xD0
499#define GDMA_PF_REG_DB_PAGE_OFF 0xC8
500#define GDMA_PF_REG_SHM_OFF 0x70
501
502#define GDMA_SRIOV_REG_CFG_BASE_OFF 0x108
503
504#define MANA_PF_DEVICE_ID 0x00B9
505#define MANA_VF_DEVICE_ID 0x00BA
506
507struct gdma_posted_wqe_info {
508 u32 wqe_size_in_bu;
509};
510
511/* GDMA_GENERATE_TEST_EQE */
512struct gdma_generate_test_event_req {
513 struct gdma_req_hdr hdr;
514 u32 queue_index;
515}; /* HW DATA */
516
517/* GDMA_VERIFY_VF_DRIVER_VERSION */
518enum {
519 GDMA_PROTOCOL_V1 = 1,
520 GDMA_PROTOCOL_FIRST = GDMA_PROTOCOL_V1,
521 GDMA_PROTOCOL_LAST = GDMA_PROTOCOL_V1,
522};
523
524#define GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT BIT(0)
525
526/* Advertise to the NIC firmware: the NAPI work_done variable race is fixed,
527 * so the driver is able to reliably support features like busy_poll.
528 */
529#define GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX BIT(2)
530
531#define GDMA_DRV_CAP_FLAGS1 \
532 (GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT | \
533 GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX)
534
535#define GDMA_DRV_CAP_FLAGS2 0
536
537#define GDMA_DRV_CAP_FLAGS3 0
538
539#define GDMA_DRV_CAP_FLAGS4 0
540
541struct gdma_verify_ver_req {
542 struct gdma_req_hdr hdr;
543
544 /* Mandatory fields required for protocol establishment */
545 u64 protocol_ver_min;
546 u64 protocol_ver_max;
547
548 /* Gdma Driver Capability Flags */
549 u64 gd_drv_cap_flags1;
550 u64 gd_drv_cap_flags2;
551 u64 gd_drv_cap_flags3;
552 u64 gd_drv_cap_flags4;
553
554 /* Advisory fields */
555 u64 drv_ver;
556 u32 os_type; /* Linux = 0x10; Windows = 0x20; Other = 0x30 */
557 u32 reserved;
558 u32 os_ver_major;
559 u32 os_ver_minor;
560 u32 os_ver_build;
561 u32 os_ver_platform;
562 u64 reserved_2;
563 u8 os_ver_str1[128];
564 u8 os_ver_str2[128];
565 u8 os_ver_str3[128];
566 u8 os_ver_str4[128];
567}; /* HW DATA */
568
569struct gdma_verify_ver_resp {
570 struct gdma_resp_hdr hdr;
571 u64 gdma_protocol_ver;
572 u64 pf_cap_flags1;
573 u64 pf_cap_flags2;
574 u64 pf_cap_flags3;
575 u64 pf_cap_flags4;
576}; /* HW DATA */
577
578/* GDMA_QUERY_MAX_RESOURCES */
579struct gdma_query_max_resources_resp {
580 struct gdma_resp_hdr hdr;
581 u32 status;
582 u32 max_sq;
583 u32 max_rq;
584 u32 max_cq;
585 u32 max_eq;
586 u32 max_db;
587 u32 max_mst;
588 u32 max_cq_mod_ctx;
589 u32 max_mod_cq;
590 u32 max_msix;
591}; /* HW DATA */
592
593/* GDMA_LIST_DEVICES */
594struct gdma_list_devices_resp {
595 struct gdma_resp_hdr hdr;
596 u32 num_of_devs;
597 u32 reserved;
598 struct gdma_dev_id devs[64];
599}; /* HW DATA */
600
601/* GDMA_REGISTER_DEVICE */
602struct gdma_register_device_resp {
603 struct gdma_resp_hdr hdr;
604 u32 pdid;
605 u32 gpa_mkey;
606 u32 db_id;
607}; /* HW DATA */
608
609struct gdma_allocate_resource_range_req {
610 struct gdma_req_hdr hdr;
611 u32 resource_type;
612 u32 num_resources;
613 u32 alignment;
614 u32 allocated_resources;
615};
616
617struct gdma_allocate_resource_range_resp {
618 struct gdma_resp_hdr hdr;
619 u32 allocated_resources;
620};
621
622struct gdma_destroy_resource_range_req {
623 struct gdma_req_hdr hdr;
624 u32 resource_type;
625 u32 num_resources;
626 u32 allocated_resources;
627};
628
629/* GDMA_CREATE_QUEUE */
630struct gdma_create_queue_req {
631 struct gdma_req_hdr hdr;
632 u32 type;
633 u32 reserved1;
634 u32 pdid;
635 u32 doolbell_id;
636 u64 gdma_region;
637 u32 reserved2;
638 u32 queue_size;
639 u32 log2_throttle_limit;
640 u32 eq_pci_msix_index;
641 u32 cq_mod_ctx_id;
642 u32 cq_parent_eq_id;
643 u8 rq_drop_on_overrun;
644 u8 rq_err_on_wqe_overflow;
645 u8 rq_chain_rec_wqes;
646 u8 sq_hw_db;
647 u32 reserved3;
648}; /* HW DATA */
649
650struct gdma_create_queue_resp {
651 struct gdma_resp_hdr hdr;
652 u32 queue_index;
653}; /* HW DATA */
654
655/* GDMA_DISABLE_QUEUE */
656struct gdma_disable_queue_req {
657 struct gdma_req_hdr hdr;
658 u32 type;
659 u32 queue_index;
660 u32 alloc_res_id_on_creation;
661}; /* HW DATA */
662
663enum atb_page_size {
664 ATB_PAGE_SIZE_4K,
665 ATB_PAGE_SIZE_8K,
666 ATB_PAGE_SIZE_16K,
667 ATB_PAGE_SIZE_32K,
668 ATB_PAGE_SIZE_64K,
669 ATB_PAGE_SIZE_128K,
670 ATB_PAGE_SIZE_256K,
671 ATB_PAGE_SIZE_512K,
672 ATB_PAGE_SIZE_1M,
673 ATB_PAGE_SIZE_2M,
674 ATB_PAGE_SIZE_MAX,
675};
676
677enum gdma_mr_access_flags {
678 GDMA_ACCESS_FLAG_LOCAL_READ = BIT_ULL(0),
679 GDMA_ACCESS_FLAG_LOCAL_WRITE = BIT_ULL(1),
680 GDMA_ACCESS_FLAG_REMOTE_READ = BIT_ULL(2),
681 GDMA_ACCESS_FLAG_REMOTE_WRITE = BIT_ULL(3),
682 GDMA_ACCESS_FLAG_REMOTE_ATOMIC = BIT_ULL(4),
683};
684
685/* GDMA_CREATE_DMA_REGION */
686struct gdma_create_dma_region_req {
687 struct gdma_req_hdr hdr;
688
689 /* The total size of the DMA region */
690 u64 length;
691
692 /* The offset in the first page */
693 u32 offset_in_page;
694
695 /* enum gdma_page_type */
696 u32 gdma_page_type;
697
698 /* The total number of pages */
699 u32 page_count;
700
701 /* If page_addr_list_len is smaller than page_count,
702 * the remaining page addresses will be added via the
703 * message GDMA_DMA_REGION_ADD_PAGES.
704 */
705 u32 page_addr_list_len;
706 u64 page_addr_list[];
707}; /* HW DATA */
708
709struct gdma_create_dma_region_resp {
710 struct gdma_resp_hdr hdr;
711 u64 dma_region_handle;
712}; /* HW DATA */
713
714/* GDMA_DMA_REGION_ADD_PAGES */
715struct gdma_dma_region_add_pages_req {
716 struct gdma_req_hdr hdr;
717
718 u64 dma_region_handle;
719
720 u32 page_addr_list_len;
721 u32 reserved3;
722
723 u64 page_addr_list[];
724}; /* HW DATA */
725
726/* GDMA_DESTROY_DMA_REGION */
727struct gdma_destroy_dma_region_req {
728 struct gdma_req_hdr hdr;
729
730 u64 dma_region_handle;
731}; /* HW DATA */
732
733enum gdma_pd_flags {
734 GDMA_PD_FLAG_INVALID = 0,
735};
736
737struct gdma_create_pd_req {
738 struct gdma_req_hdr hdr;
739 enum gdma_pd_flags flags;
740 u32 reserved;
741};/* HW DATA */
742
743struct gdma_create_pd_resp {
744 struct gdma_resp_hdr hdr;
745 u64 pd_handle;
746 u32 pd_id;
747 u32 reserved;
748};/* HW DATA */
749
750struct gdma_destroy_pd_req {
751 struct gdma_req_hdr hdr;
752 u64 pd_handle;
753};/* HW DATA */
754
755struct gdma_destory_pd_resp {
756 struct gdma_resp_hdr hdr;
757};/* HW DATA */
758
759enum gdma_mr_type {
760 /* Guest Virtual Address - MRs of this type allow access
761 * to memory mapped by PTEs associated with this MR using a virtual
762 * address that is set up in the MST
763 */
764 GDMA_MR_TYPE_GVA = 2,
765};
766
767struct gdma_create_mr_params {
768 u64 pd_handle;
769 enum gdma_mr_type mr_type;
770 union {
771 struct {
772 u64 dma_region_handle;
773 u64 virtual_address;
774 enum gdma_mr_access_flags access_flags;
775 } gva;
776 };
777};
778
779struct gdma_create_mr_request {
780 struct gdma_req_hdr hdr;
781 u64 pd_handle;
782 enum gdma_mr_type mr_type;
783 u32 reserved_1;
784
785 union {
786 struct {
787 u64 dma_region_handle;
788 u64 virtual_address;
789 enum gdma_mr_access_flags access_flags;
790 } gva;
791
792 };
793 u32 reserved_2;
794};/* HW DATA */
795
796struct gdma_create_mr_response {
797 struct gdma_resp_hdr hdr;
798 u64 mr_handle;
799 u32 lkey;
800 u32 rkey;
801};/* HW DATA */
802
803struct gdma_destroy_mr_request {
804 struct gdma_req_hdr hdr;
805 u64 mr_handle;
806};/* HW DATA */
807
808struct gdma_destroy_mr_response {
809 struct gdma_resp_hdr hdr;
810};/* HW DATA */
811
812int mana_gd_verify_vf_version(struct pci_dev *pdev);
813
814int mana_gd_register_device(struct gdma_dev *gd);
815int mana_gd_deregister_device(struct gdma_dev *gd);
816
817int mana_gd_post_work_request(struct gdma_queue *wq,
818 const struct gdma_wqe_request *wqe_req,
819 struct gdma_posted_wqe_info *wqe_info);
820
821int mana_gd_post_and_ring(struct gdma_queue *queue,
822 const struct gdma_wqe_request *wqe,
823 struct gdma_posted_wqe_info *wqe_info);
824
825int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r);
826void mana_gd_free_res_map(struct gdma_resource *r);
827
828void mana_gd_wq_ring_doorbell(struct gdma_context *gc,
829 struct gdma_queue *queue);
830
831int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length,
832 struct gdma_mem_info *gmi);
833
834void mana_gd_free_memory(struct gdma_mem_info *gmi);
835
836int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req,
837 u32 resp_len, void *resp);
838
839int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle);
840
841#endif /* _GDMA_H */