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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11#include <linux/circ_buf.h>
12#include <linux/module.h>
13#include <linux/ioport.h>
14#include <linux/init.h>
15#include <linux/console.h>
16#include <linux/sysrq.h>
17#include <linux/platform_device.h>
18#include <linux/tty.h>
19#include <linux/tty_flip.h>
20#include <linux/serial_core.h>
21#include <linux/serial.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/ktime.h>
25#include <linux/pinctrl/consumer.h>
26#include <linux/rational.h>
27#include <linux/slab.h>
28#include <linux/of.h>
29#include <linux/io.h>
30#include <linux/iopoll.h>
31#include <linux/dma-mapping.h>
32
33#include <asm/irq.h>
34#include <linux/dma/imx-dma.h>
35
36#include "serial_mctrl_gpio.h"
37
38/* Register definitions */
39#define URXD0 0x0 /* Receiver Register */
40#define URTX0 0x40 /* Transmitter Register */
41#define UCR1 0x80 /* Control Register 1 */
42#define UCR2 0x84 /* Control Register 2 */
43#define UCR3 0x88 /* Control Register 3 */
44#define UCR4 0x8c /* Control Register 4 */
45#define UFCR 0x90 /* FIFO Control Register */
46#define USR1 0x94 /* Status Register 1 */
47#define USR2 0x98 /* Status Register 2 */
48#define UESC 0x9c /* Escape Character Register */
49#define UTIM 0xa0 /* Escape Timer Register */
50#define UBIR 0xa4 /* BRM Incremental Register */
51#define UBMR 0xa8 /* BRM Modulator Register */
52#define UBRC 0xac /* Baud Rate Count Register */
53#define IMX21_ONEMS 0xb0 /* One Millisecond register */
54#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
55#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
56
57/* UART Control Register Bit Fields.*/
58#define URXD_DUMMY_READ (1<<16)
59#define URXD_CHARRDY (1<<15)
60#define URXD_ERR (1<<14)
61#define URXD_OVRRUN (1<<13)
62#define URXD_FRMERR (1<<12)
63#define URXD_BRK (1<<11)
64#define URXD_PRERR (1<<10)
65#define URXD_RX_DATA (0xFF<<0)
66#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
67#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
68#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
69#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
70#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
71#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
72#define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
73#define UCR1_IREN (1<<7) /* Infrared interface enable */
74#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
75#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
76#define UCR1_SNDBRK (1<<4) /* Send break */
77#define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
78#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
79#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
80#define UCR1_DOZE (1<<1) /* Doze */
81#define UCR1_UARTEN (1<<0) /* UART enabled */
82#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
83#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
84#define UCR2_CTSC (1<<13) /* CTS pin control */
85#define UCR2_CTS (1<<12) /* Clear to send */
86#define UCR2_ESCEN (1<<11) /* Escape enable */
87#define UCR2_PREN (1<<8) /* Parity enable */
88#define UCR2_PROE (1<<7) /* Parity odd/even */
89#define UCR2_STPB (1<<6) /* Stop */
90#define UCR2_WS (1<<5) /* Word size */
91#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
92#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
93#define UCR2_TXEN (1<<2) /* Transmitter enabled */
94#define UCR2_RXEN (1<<1) /* Receiver enabled */
95#define UCR2_SRST (1<<0) /* SW reset */
96#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
97#define UCR3_PARERREN (1<<12) /* Parity enable */
98#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
99#define UCR3_DSR (1<<10) /* Data set ready */
100#define UCR3_DCD (1<<9) /* Data carrier detect */
101#define UCR3_RI (1<<8) /* Ring indicator */
102#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
103#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
104#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
105#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
106#define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
107#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
108#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
109#define UCR3_BPEN (1<<0) /* Preset registers enable */
110#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
111#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
112#define UCR4_INVR (1<<9) /* Inverted infrared reception */
113#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
114#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
115#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
116#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
117#define UCR4_IRSC (1<<5) /* IR special case */
118#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
119#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
120#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
121#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
122#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
123#define UFCR_RXTL_MASK 0x3F /* Receiver trigger 6 bits wide */
124#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
125#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
126#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
127#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
128#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
129#define USR1_RTSS (1<<14) /* RTS pin status */
130#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
131#define USR1_RTSD (1<<12) /* RTS delta */
132#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
133#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
134#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
135#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
136#define USR1_DTRD (1<<7) /* DTR Delta */
137#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
138#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
139#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
140#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
141#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
142#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
143#define USR2_IDLE (1<<12) /* Idle condition */
144#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
145#define USR2_RIIN (1<<9) /* Ring Indicator Input */
146#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
147#define USR2_WAKE (1<<7) /* Wake */
148#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
149#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
150#define USR2_TXDC (1<<3) /* Transmitter complete */
151#define USR2_BRCD (1<<2) /* Break condition */
152#define USR2_ORE (1<<1) /* Overrun error */
153#define USR2_RDR (1<<0) /* Recv data ready */
154#define UTS_FRCPERR (1<<13) /* Force parity error */
155#define UTS_LOOP (1<<12) /* Loop tx and rx */
156#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
157#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
158#define UTS_TXFULL (1<<4) /* TxFIFO full */
159#define UTS_RXFULL (1<<3) /* RxFIFO full */
160#define UTS_SOFTRST (1<<0) /* Software reset */
161
162/* We've been assigned a range on the "Low-density serial ports" major */
163#define SERIAL_IMX_MAJOR 207
164#define MINOR_START 16
165#define DEV_NAME "ttymxc"
166
167/*
168 * This determines how often we check the modem status signals
169 * for any change. They generally aren't connected to an IRQ
170 * so we have to poll them. We also check immediately before
171 * filling the TX fifo incase CTS has been dropped.
172 */
173#define MCTRL_TIMEOUT (250*HZ/1000)
174
175#define DRIVER_NAME "IMX-uart"
176
177#define UART_NR 8
178
179/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
180enum imx_uart_type {
181 IMX1_UART,
182 IMX21_UART,
183};
184
185/* device type dependent stuff */
186struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189};
190
191enum imx_tx_state {
192 OFF,
193 WAIT_AFTER_RTS,
194 SEND,
195 WAIT_AFTER_SEND,
196};
197
198struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 unsigned int have_rtscts:1;
203 unsigned int have_rtsgpio:1;
204 unsigned int dte_mode:1;
205 unsigned int inverted_tx:1;
206 unsigned int inverted_rx:1;
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 const struct imx_uart_data *devdata;
210
211 struct mctrl_gpios *gpios;
212
213 /* counter to stop 0xff flood */
214 int idle_counter;
215
216 /* DMA fields */
217 unsigned int dma_is_enabled:1;
218 unsigned int dma_is_rxing:1;
219 unsigned int dma_is_txing:1;
220 struct dma_chan *dma_chan_rx, *dma_chan_tx;
221 struct scatterlist rx_sgl, tx_sgl[2];
222 void *rx_buf;
223 struct circ_buf rx_ring;
224 unsigned int rx_buf_size;
225 unsigned int rx_period_length;
226 unsigned int rx_periods;
227 dma_cookie_t rx_cookie;
228 unsigned int tx_bytes;
229 unsigned int dma_tx_nents;
230 unsigned int saved_reg[10];
231 bool context_saved;
232
233 bool last_putchar_was_newline;
234
235 enum imx_tx_state tx_state;
236 struct hrtimer trigger_start_tx;
237 struct hrtimer trigger_stop_tx;
238};
239
240struct imx_port_ucrs {
241 unsigned int ucr1;
242 unsigned int ucr2;
243 unsigned int ucr3;
244};
245
246static const struct imx_uart_data imx_uart_imx1_devdata = {
247 .uts_reg = IMX1_UTS,
248 .devtype = IMX1_UART,
249};
250
251static const struct imx_uart_data imx_uart_imx21_devdata = {
252 .uts_reg = IMX21_UTS,
253 .devtype = IMX21_UART,
254};
255
256static const struct of_device_id imx_uart_dt_ids[] = {
257 /*
258 * For reasons unknown to me, some UART devices (e.g. imx6ul's) are
259 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
260 * original imx6q's UART is compatible to fsl,imx21-uart. This driver
261 * doesn't make any distinction between these two variants.
262 */
263 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
264 { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, },
265 { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, },
266 { /* sentinel */ }
267};
268MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
269
270static inline struct imx_port *to_imx_port(struct uart_port *port)
271{
272 return container_of(port, struct imx_port, port);
273}
274
275static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
276{
277 writel(val, sport->port.membase + offset);
278}
279
280static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
281{
282 return readl(sport->port.membase + offset);
283}
284
285static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
286{
287 return sport->devdata->uts_reg;
288}
289
290static inline int imx_uart_is_imx1(struct imx_port *sport)
291{
292 return sport->devdata->devtype == IMX1_UART;
293}
294
295/*
296 * Save and restore functions for UCR1, UCR2 and UCR3 registers
297 */
298#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
299static void imx_uart_ucrs_save(struct imx_port *sport,
300 struct imx_port_ucrs *ucr)
301{
302 /* save control registers */
303 ucr->ucr1 = imx_uart_readl(sport, UCR1);
304 ucr->ucr2 = imx_uart_readl(sport, UCR2);
305 ucr->ucr3 = imx_uart_readl(sport, UCR3);
306}
307
308static void imx_uart_ucrs_restore(struct imx_port *sport,
309 struct imx_port_ucrs *ucr)
310{
311 /* restore control registers */
312 imx_uart_writel(sport, ucr->ucr1, UCR1);
313 imx_uart_writel(sport, ucr->ucr2, UCR2);
314 imx_uart_writel(sport, ucr->ucr3, UCR3);
315}
316#endif
317
318/* called with port.lock taken and irqs caller dependent */
319static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
320{
321 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
322
323 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
324}
325
326/* called with port.lock taken and irqs caller dependent */
327static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
328{
329 *ucr2 &= ~UCR2_CTSC;
330 *ucr2 |= UCR2_CTS;
331
332 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
333}
334
335static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
336{
337 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
338}
339
340/* called with port.lock taken and irqs off */
341static void imx_uart_soft_reset(struct imx_port *sport)
342{
343 int i = 10;
344 u32 ucr2, ubir, ubmr, uts;
345
346 /*
347 * According to the Reference Manual description of the UART SRST bit:
348 *
349 * "Reset the transmit and receive state machines,
350 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
351 * and UTS[6-3]".
352 *
353 * We don't need to restore the old values from USR1, USR2, URXD and
354 * UTXD. UBRC is read only, so only save/restore the other three
355 * registers.
356 */
357 ubir = imx_uart_readl(sport, UBIR);
358 ubmr = imx_uart_readl(sport, UBMR);
359 uts = imx_uart_readl(sport, IMX21_UTS);
360
361 ucr2 = imx_uart_readl(sport, UCR2);
362 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
363
364 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
365 udelay(1);
366
367 /* Restore the registers */
368 imx_uart_writel(sport, ubir, UBIR);
369 imx_uart_writel(sport, ubmr, UBMR);
370 imx_uart_writel(sport, uts, IMX21_UTS);
371
372 sport->idle_counter = 0;
373}
374
375/* called with port.lock taken and irqs off */
376static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
377{
378 unsigned int uts;
379
380 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
381 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
382 uts &= ~UTS_LOOP;
383 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
384}
385
386/* called with port.lock taken and irqs off */
387static void imx_uart_start_rx(struct uart_port *port)
388{
389 struct imx_port *sport = to_imx_port(port);
390 unsigned int ucr1, ucr2;
391
392 ucr1 = imx_uart_readl(sport, UCR1);
393 ucr2 = imx_uart_readl(sport, UCR2);
394
395 ucr2 |= UCR2_RXEN;
396
397 if (sport->dma_is_enabled) {
398 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
399 } else {
400 ucr1 |= UCR1_RRDYEN;
401 ucr2 |= UCR2_ATEN;
402 }
403
404 /* Write UCR2 first as it includes RXEN */
405 imx_uart_writel(sport, ucr2, UCR2);
406 imx_uart_writel(sport, ucr1, UCR1);
407 imx_uart_disable_loopback_rs485(sport);
408}
409
410/* called with port.lock taken and irqs off */
411static void imx_uart_stop_tx(struct uart_port *port)
412{
413 struct imx_port *sport = to_imx_port(port);
414 u32 ucr1, ucr4, usr2;
415
416 if (sport->tx_state == OFF)
417 return;
418
419 /*
420 * We are maybe in the SMP context, so if the DMA TX thread is running
421 * on other cpu, we have to wait for it to finish.
422 */
423 if (sport->dma_is_txing)
424 return;
425
426 ucr1 = imx_uart_readl(sport, UCR1);
427 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
428
429 ucr4 = imx_uart_readl(sport, UCR4);
430 usr2 = imx_uart_readl(sport, USR2);
431 if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) {
432 /* The shifter is still busy, so retry once TC triggers */
433 return;
434 }
435
436 ucr4 &= ~UCR4_TCEN;
437 imx_uart_writel(sport, ucr4, UCR4);
438
439 /* in rs485 mode disable transmitter */
440 if (port->rs485.flags & SER_RS485_ENABLED) {
441 if (sport->tx_state == SEND) {
442 sport->tx_state = WAIT_AFTER_SEND;
443
444 if (port->rs485.delay_rts_after_send > 0) {
445 start_hrtimer_ms(&sport->trigger_stop_tx,
446 port->rs485.delay_rts_after_send);
447 return;
448 }
449
450 /* continue without any delay */
451 }
452
453 if (sport->tx_state == WAIT_AFTER_RTS ||
454 sport->tx_state == WAIT_AFTER_SEND) {
455 u32 ucr2;
456
457 hrtimer_try_to_cancel(&sport->trigger_start_tx);
458
459 ucr2 = imx_uart_readl(sport, UCR2);
460 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
461 imx_uart_rts_active(sport, &ucr2);
462 else
463 imx_uart_rts_inactive(sport, &ucr2);
464 imx_uart_writel(sport, ucr2, UCR2);
465
466 if (!port->rs485_rx_during_tx_gpio)
467 imx_uart_start_rx(port);
468
469 sport->tx_state = OFF;
470 }
471 } else {
472 sport->tx_state = OFF;
473 }
474}
475
476/* called with port.lock taken and irqs off */
477static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback)
478{
479 struct imx_port *sport = to_imx_port(port);
480 u32 ucr1, ucr2, ucr4, uts;
481
482 ucr1 = imx_uart_readl(sport, UCR1);
483 ucr2 = imx_uart_readl(sport, UCR2);
484 ucr4 = imx_uart_readl(sport, UCR4);
485
486 if (sport->dma_is_enabled) {
487 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
488 } else {
489 ucr1 &= ~UCR1_RRDYEN;
490 ucr2 &= ~UCR2_ATEN;
491 ucr4 &= ~UCR4_OREN;
492 }
493 imx_uart_writel(sport, ucr1, UCR1);
494 imx_uart_writel(sport, ucr4, UCR4);
495
496 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
497 if (port->rs485.flags & SER_RS485_ENABLED &&
498 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
499 sport->have_rtscts && !sport->have_rtsgpio && loopback) {
500 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
501 uts |= UTS_LOOP;
502 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
503 ucr2 |= UCR2_RXEN;
504 } else {
505 ucr2 &= ~UCR2_RXEN;
506 }
507
508 imx_uart_writel(sport, ucr2, UCR2);
509}
510
511/* called with port.lock taken and irqs off */
512static void imx_uart_stop_rx(struct uart_port *port)
513{
514 /*
515 * Stop RX and enable loopback in order to make sure RS485 bus
516 * is not blocked. Se comment in imx_uart_probe().
517 */
518 imx_uart_stop_rx_with_loopback_ctrl(port, true);
519}
520
521/* called with port.lock taken and irqs off */
522static void imx_uart_enable_ms(struct uart_port *port)
523{
524 struct imx_port *sport = to_imx_port(port);
525
526 mod_timer(&sport->timer, jiffies);
527
528 mctrl_gpio_enable_ms(sport->gpios);
529}
530
531static void imx_uart_dma_tx(struct imx_port *sport);
532
533/* called with port.lock taken and irqs off */
534static inline void imx_uart_transmit_buffer(struct imx_port *sport)
535{
536 struct tty_port *tport = &sport->port.state->port;
537 unsigned char c;
538
539 if (sport->port.x_char) {
540 /* Send next char */
541 imx_uart_writel(sport, sport->port.x_char, URTX0);
542 sport->port.icount.tx++;
543 sport->port.x_char = 0;
544 return;
545 }
546
547 if (kfifo_is_empty(&tport->xmit_fifo) ||
548 uart_tx_stopped(&sport->port)) {
549 imx_uart_stop_tx(&sport->port);
550 return;
551 }
552
553 if (sport->dma_is_enabled) {
554 u32 ucr1;
555 /*
556 * We've just sent a X-char Ensure the TX DMA is enabled
557 * and the TX IRQ is disabled.
558 **/
559 ucr1 = imx_uart_readl(sport, UCR1);
560 ucr1 &= ~UCR1_TRDYEN;
561 if (sport->dma_is_txing) {
562 ucr1 |= UCR1_TXDMAEN;
563 imx_uart_writel(sport, ucr1, UCR1);
564 } else {
565 imx_uart_writel(sport, ucr1, UCR1);
566 imx_uart_dma_tx(sport);
567 }
568
569 return;
570 }
571
572 while (!(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) &&
573 uart_fifo_get(&sport->port, &c))
574 imx_uart_writel(sport, c, URTX0);
575
576 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
577 uart_write_wakeup(&sport->port);
578
579 if (kfifo_is_empty(&tport->xmit_fifo))
580 imx_uart_stop_tx(&sport->port);
581}
582
583static void imx_uart_dma_tx_callback(void *data)
584{
585 struct imx_port *sport = data;
586 struct tty_port *tport = &sport->port.state->port;
587 struct scatterlist *sgl = &sport->tx_sgl[0];
588 unsigned long flags;
589 u32 ucr1;
590
591 uart_port_lock_irqsave(&sport->port, &flags);
592
593 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
594
595 ucr1 = imx_uart_readl(sport, UCR1);
596 ucr1 &= ~UCR1_TXDMAEN;
597 imx_uart_writel(sport, ucr1, UCR1);
598
599 uart_xmit_advance(&sport->port, sport->tx_bytes);
600
601 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
602
603 sport->dma_is_txing = 0;
604
605 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
606 uart_write_wakeup(&sport->port);
607
608 if (!kfifo_is_empty(&tport->xmit_fifo) &&
609 !uart_tx_stopped(&sport->port))
610 imx_uart_dma_tx(sport);
611 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
612 u32 ucr4 = imx_uart_readl(sport, UCR4);
613 ucr4 |= UCR4_TCEN;
614 imx_uart_writel(sport, ucr4, UCR4);
615 }
616
617 uart_port_unlock_irqrestore(&sport->port, flags);
618}
619
620/* called with port.lock taken and irqs off */
621static void imx_uart_dma_tx(struct imx_port *sport)
622{
623 struct tty_port *tport = &sport->port.state->port;
624 struct scatterlist *sgl = sport->tx_sgl;
625 struct dma_async_tx_descriptor *desc;
626 struct dma_chan *chan = sport->dma_chan_tx;
627 struct device *dev = sport->port.dev;
628 u32 ucr1, ucr4;
629 int ret;
630
631 if (sport->dma_is_txing)
632 return;
633
634 ucr4 = imx_uart_readl(sport, UCR4);
635 ucr4 &= ~UCR4_TCEN;
636 imx_uart_writel(sport, ucr4, UCR4);
637
638 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl));
639 sport->tx_bytes = kfifo_len(&tport->xmit_fifo);
640 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl,
641 ARRAY_SIZE(sport->tx_sgl), sport->tx_bytes);
642
643 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
644 if (ret == 0) {
645 dev_err(dev, "DMA mapping error for TX.\n");
646 return;
647 }
648 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
649 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
650 if (!desc) {
651 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
652 DMA_TO_DEVICE);
653 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
654 return;
655 }
656 desc->callback = imx_uart_dma_tx_callback;
657 desc->callback_param = sport;
658
659 dev_dbg(dev, "TX: prepare to send %u bytes by DMA.\n", sport->tx_bytes);
660
661 ucr1 = imx_uart_readl(sport, UCR1);
662 ucr1 |= UCR1_TXDMAEN;
663 imx_uart_writel(sport, ucr1, UCR1);
664
665 /* fire it */
666 sport->dma_is_txing = 1;
667 dmaengine_submit(desc);
668 dma_async_issue_pending(chan);
669 return;
670}
671
672/* called with port.lock taken and irqs off */
673static void imx_uart_start_tx(struct uart_port *port)
674{
675 struct imx_port *sport = to_imx_port(port);
676 struct tty_port *tport = &sport->port.state->port;
677 u32 ucr1;
678
679 if (!sport->port.x_char && kfifo_is_empty(&tport->xmit_fifo))
680 return;
681
682 /*
683 * We cannot simply do nothing here if sport->tx_state == SEND already
684 * because UCR1_TXMPTYEN might already have been cleared in
685 * imx_uart_stop_tx(), but tx_state is still SEND.
686 */
687
688 if (port->rs485.flags & SER_RS485_ENABLED) {
689 if (sport->tx_state == OFF) {
690 u32 ucr2 = imx_uart_readl(sport, UCR2);
691 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
692 imx_uart_rts_active(sport, &ucr2);
693 else
694 imx_uart_rts_inactive(sport, &ucr2);
695 imx_uart_writel(sport, ucr2, UCR2);
696
697 /*
698 * Since we are about to transmit we can not stop RX
699 * with loopback enabled because that will make our
700 * transmitted data being just looped to RX.
701 */
702 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
703 !port->rs485_rx_during_tx_gpio)
704 imx_uart_stop_rx_with_loopback_ctrl(port, false);
705
706 sport->tx_state = WAIT_AFTER_RTS;
707
708 if (port->rs485.delay_rts_before_send > 0) {
709 start_hrtimer_ms(&sport->trigger_start_tx,
710 port->rs485.delay_rts_before_send);
711 return;
712 }
713
714 /* continue without any delay */
715 }
716
717 if (sport->tx_state == WAIT_AFTER_SEND
718 || sport->tx_state == WAIT_AFTER_RTS) {
719
720 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
721
722 /*
723 * Enable transmitter and shifter empty irq only if DMA
724 * is off. In the DMA case this is done in the
725 * tx-callback.
726 */
727 if (!sport->dma_is_enabled) {
728 u32 ucr4 = imx_uart_readl(sport, UCR4);
729 ucr4 |= UCR4_TCEN;
730 imx_uart_writel(sport, ucr4, UCR4);
731 }
732
733 sport->tx_state = SEND;
734 }
735 } else {
736 sport->tx_state = SEND;
737 }
738
739 if (!sport->dma_is_enabled) {
740 ucr1 = imx_uart_readl(sport, UCR1);
741 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
742 }
743
744 if (sport->dma_is_enabled) {
745 if (sport->port.x_char) {
746 /* We have X-char to send, so enable TX IRQ and
747 * disable TX DMA to let TX interrupt to send X-char */
748 ucr1 = imx_uart_readl(sport, UCR1);
749 ucr1 &= ~UCR1_TXDMAEN;
750 ucr1 |= UCR1_TRDYEN;
751 imx_uart_writel(sport, ucr1, UCR1);
752 return;
753 }
754
755 if (!kfifo_is_empty(&tport->xmit_fifo) &&
756 !uart_tx_stopped(port))
757 imx_uart_dma_tx(sport);
758 return;
759 }
760}
761
762static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
763{
764 struct imx_port *sport = dev_id;
765 u32 usr1;
766
767 imx_uart_writel(sport, USR1_RTSD, USR1);
768 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
769 /*
770 * Update sport->old_status here, so any follow-up calls to
771 * imx_uart_mctrl_check() will be able to recognize that RTS
772 * state changed since last imx_uart_mctrl_check() call.
773 *
774 * In case RTS has been detected as asserted here and later on
775 * deasserted by the time imx_uart_mctrl_check() was called,
776 * imx_uart_mctrl_check() can detect the RTS state change and
777 * trigger uart_handle_cts_change() to unblock the port for
778 * further TX transfers.
779 */
780 if (usr1 & USR1_RTSS)
781 sport->old_status |= TIOCM_CTS;
782 else
783 sport->old_status &= ~TIOCM_CTS;
784 uart_handle_cts_change(&sport->port, usr1);
785 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
786
787 return IRQ_HANDLED;
788}
789
790static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
791{
792 struct imx_port *sport = dev_id;
793 irqreturn_t ret;
794
795 uart_port_lock(&sport->port);
796
797 ret = __imx_uart_rtsint(irq, dev_id);
798
799 uart_port_unlock(&sport->port);
800
801 return ret;
802}
803
804static irqreturn_t imx_uart_txint(int irq, void *dev_id)
805{
806 struct imx_port *sport = dev_id;
807
808 uart_port_lock(&sport->port);
809 imx_uart_transmit_buffer(sport);
810 uart_port_unlock(&sport->port);
811 return IRQ_HANDLED;
812}
813
814/* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
815 * This is to be called from Rx ISRs only when some bytes were actually
816 * received.
817 *
818 * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
819 * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
820 * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
821 * that is terminated by any activity on RxD line, or could be stopped by
822 * issuing soft reset to the UART (just stop/start of RX does not help). Note
823 * that what we do here is sending isolated start bit about 2.4 times shorter
824 * than it is to be on UART configured baud rate.
825 *
826 * Called with port.lock taken and irqs off.
827 */
828static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
829{
830 /* To detect hardware 0xff flood we monitor RxD line between RX
831 * interrupts to isolate "receiving" of char(s) with no activity
832 * on RxD line, that'd never happen on actual data transfers.
833 *
834 * We use USR2_WAKE bit to check for activity on RxD line, but we have a
835 * race here if we clear USR2_WAKE when receiving of a char is in
836 * progress, so we might get RX interrupt later with USR2_WAKE bit
837 * cleared. Note though that as we don't try to clear USR2_WAKE when we
838 * detected no activity, this race may hide actual activity only once.
839 *
840 * Yet another case where receive interrupt may occur without RxD
841 * activity is expiration of aging timer, so we consider this as well.
842 *
843 * We use 'idle_counter' to ensure that we got at least so many RX
844 * interrupts without any detected activity on RxD line. 2 cases
845 * described plus 1 to be on the safe side gives us a margin of 3,
846 * below. In practice I was not able to produce a false positive to
847 * induce soft reset at regular data transfers even using 1 as the
848 * margin, so 3 is actually very strong.
849 *
850 * We count interrupts, not chars in 'idle-counter' for simplicity.
851 */
852
853 if (usr2 & USR2_WAKE) {
854 imx_uart_writel(sport, USR2_WAKE, USR2);
855 sport->idle_counter = 0;
856 } else if (++sport->idle_counter > 3) {
857 dev_warn(sport->port.dev, "RX flood detected: soft reset.");
858 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
859 }
860}
861
862/* called with port.lock taken and irqs off */
863static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
864{
865 struct imx_port *sport = dev_id;
866 struct tty_port *port = &sport->port.state->port;
867 u32 usr2, rx;
868
869 /* If we received something, check for 0xff flood */
870 usr2 = imx_uart_readl(sport, USR2);
871 if (usr2 & USR2_RDR)
872 imx_uart_check_flood(sport, usr2);
873
874 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
875 unsigned int flg = TTY_NORMAL;
876 sport->port.icount.rx++;
877
878 if (unlikely(rx & URXD_ERR)) {
879 if (rx & URXD_BRK) {
880 sport->port.icount.brk++;
881 if (uart_handle_break(&sport->port))
882 continue;
883 }
884 else if (rx & URXD_PRERR)
885 sport->port.icount.parity++;
886 else if (rx & URXD_FRMERR)
887 sport->port.icount.frame++;
888 if (rx & URXD_OVRRUN)
889 sport->port.icount.overrun++;
890
891 if (rx & sport->port.ignore_status_mask)
892 continue;
893
894 rx &= (sport->port.read_status_mask | 0xFF);
895
896 if (rx & URXD_BRK)
897 flg = TTY_BREAK;
898 else if (rx & URXD_PRERR)
899 flg = TTY_PARITY;
900 else if (rx & URXD_FRMERR)
901 flg = TTY_FRAME;
902 if (rx & URXD_OVRRUN)
903 flg = TTY_OVERRUN;
904
905 sport->port.sysrq = 0;
906 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
907 continue;
908 }
909
910 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
911 continue;
912
913 if (tty_insert_flip_char(port, rx, flg) == 0)
914 sport->port.icount.buf_overrun++;
915 }
916
917 tty_flip_buffer_push(port);
918
919 return IRQ_HANDLED;
920}
921
922static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
923{
924 struct imx_port *sport = dev_id;
925 irqreturn_t ret;
926
927 uart_port_lock(&sport->port);
928
929 ret = __imx_uart_rxint(irq, dev_id);
930
931 uart_port_unlock(&sport->port);
932
933 return ret;
934}
935
936static void imx_uart_clear_rx_errors(struct imx_port *sport);
937
938/*
939 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
940 */
941/* called with port.lock taken and irqs off */
942static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
943{
944 unsigned int tmp = TIOCM_DSR;
945 unsigned usr1 = imx_uart_readl(sport, USR1);
946 unsigned usr2 = imx_uart_readl(sport, USR2);
947
948 if (usr1 & USR1_RTSS)
949 tmp |= TIOCM_CTS;
950
951 /* in DCE mode DCDIN is always 0 */
952 if (!(usr2 & USR2_DCDIN))
953 tmp |= TIOCM_CAR;
954
955 if (sport->dte_mode)
956 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
957 tmp |= TIOCM_RI;
958
959 return tmp;
960}
961
962/*
963 * Handle any change of modem status signal since we were last called.
964 *
965 * Called with port.lock taken and irqs off.
966 */
967static void imx_uart_mctrl_check(struct imx_port *sport)
968{
969 unsigned int status, changed;
970
971 status = imx_uart_get_hwmctrl(sport);
972 changed = status ^ sport->old_status;
973
974 if (changed == 0)
975 return;
976
977 sport->old_status = status;
978
979 if (changed & TIOCM_RI && status & TIOCM_RI)
980 sport->port.icount.rng++;
981 if (changed & TIOCM_DSR)
982 sport->port.icount.dsr++;
983 if (changed & TIOCM_CAR)
984 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
985 if (changed & TIOCM_CTS)
986 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
987
988 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
989}
990
991static irqreturn_t imx_uart_int(int irq, void *dev_id)
992{
993 struct imx_port *sport = dev_id;
994 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
995 irqreturn_t ret = IRQ_NONE;
996
997 uart_port_lock(&sport->port);
998
999 usr1 = imx_uart_readl(sport, USR1);
1000 usr2 = imx_uart_readl(sport, USR2);
1001 ucr1 = imx_uart_readl(sport, UCR1);
1002 ucr2 = imx_uart_readl(sport, UCR2);
1003 ucr3 = imx_uart_readl(sport, UCR3);
1004 ucr4 = imx_uart_readl(sport, UCR4);
1005
1006 /*
1007 * Even if a condition is true that can trigger an irq only handle it if
1008 * the respective irq source is enabled. This prevents some undesired
1009 * actions, for example if a character that sits in the RX FIFO and that
1010 * should be fetched via DMA is tried to be fetched using PIO. Or the
1011 * receiver is currently off and so reading from URXD0 results in an
1012 * exception. So just mask the (raw) status bits for disabled irqs.
1013 */
1014 if ((ucr1 & UCR1_RRDYEN) == 0)
1015 usr1 &= ~USR1_RRDY;
1016 if ((ucr2 & UCR2_ATEN) == 0)
1017 usr1 &= ~USR1_AGTIM;
1018 if ((ucr1 & UCR1_TRDYEN) == 0)
1019 usr1 &= ~USR1_TRDY;
1020 if ((ucr4 & UCR4_TCEN) == 0)
1021 usr2 &= ~USR2_TXDC;
1022 if ((ucr3 & UCR3_DTRDEN) == 0)
1023 usr1 &= ~USR1_DTRD;
1024 if ((ucr1 & UCR1_RTSDEN) == 0)
1025 usr1 &= ~USR1_RTSD;
1026 if ((ucr3 & UCR3_AWAKEN) == 0)
1027 usr1 &= ~USR1_AWAKE;
1028 if ((ucr4 & UCR4_OREN) == 0)
1029 usr2 &= ~USR2_ORE;
1030
1031 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1032 imx_uart_writel(sport, USR1_AGTIM, USR1);
1033
1034 __imx_uart_rxint(irq, dev_id);
1035 ret = IRQ_HANDLED;
1036 }
1037
1038 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1039 imx_uart_transmit_buffer(sport);
1040 ret = IRQ_HANDLED;
1041 }
1042
1043 if (usr1 & USR1_DTRD) {
1044 imx_uart_writel(sport, USR1_DTRD, USR1);
1045
1046 imx_uart_mctrl_check(sport);
1047
1048 ret = IRQ_HANDLED;
1049 }
1050
1051 if (usr1 & USR1_RTSD) {
1052 __imx_uart_rtsint(irq, dev_id);
1053 ret = IRQ_HANDLED;
1054 }
1055
1056 if (usr1 & USR1_AWAKE) {
1057 imx_uart_writel(sport, USR1_AWAKE, USR1);
1058 ret = IRQ_HANDLED;
1059 }
1060
1061 if (usr2 & USR2_ORE) {
1062 sport->port.icount.overrun++;
1063 imx_uart_writel(sport, USR2_ORE, USR2);
1064 ret = IRQ_HANDLED;
1065 }
1066
1067 uart_port_unlock(&sport->port);
1068
1069 return ret;
1070}
1071
1072/*
1073 * Return TIOCSER_TEMT when transmitter is not busy.
1074 */
1075static unsigned int imx_uart_tx_empty(struct uart_port *port)
1076{
1077 struct imx_port *sport = to_imx_port(port);
1078 unsigned int ret;
1079
1080 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1081
1082 /* If the TX DMA is working, return 0. */
1083 if (sport->dma_is_txing)
1084 ret = 0;
1085
1086 return ret;
1087}
1088
1089/* called with port.lock taken and irqs off */
1090static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1091{
1092 struct imx_port *sport = to_imx_port(port);
1093 unsigned int ret = imx_uart_get_hwmctrl(sport);
1094
1095 mctrl_gpio_get(sport->gpios, &ret);
1096
1097 return ret;
1098}
1099
1100/* called with port.lock taken and irqs off */
1101static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1102{
1103 struct imx_port *sport = to_imx_port(port);
1104 u32 ucr3, uts;
1105
1106 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1107 u32 ucr2;
1108
1109 /*
1110 * Turn off autoRTS if RTS is lowered and restore autoRTS
1111 * setting if RTS is raised.
1112 */
1113 ucr2 = imx_uart_readl(sport, UCR2);
1114 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1115 if (mctrl & TIOCM_RTS) {
1116 ucr2 |= UCR2_CTS;
1117 /*
1118 * UCR2_IRTS is unset if and only if the port is
1119 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1120 * to get the state to restore to.
1121 */
1122 if (!(ucr2 & UCR2_IRTS))
1123 ucr2 |= UCR2_CTSC;
1124 }
1125 imx_uart_writel(sport, ucr2, UCR2);
1126 }
1127
1128 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1129 if (!(mctrl & TIOCM_DTR))
1130 ucr3 |= UCR3_DSR;
1131 imx_uart_writel(sport, ucr3, UCR3);
1132
1133 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1134 if (mctrl & TIOCM_LOOP)
1135 uts |= UTS_LOOP;
1136 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1137
1138 mctrl_gpio_set(sport->gpios, mctrl);
1139}
1140
1141/*
1142 * Interrupts always disabled.
1143 */
1144static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1145{
1146 struct imx_port *sport = to_imx_port(port);
1147 unsigned long flags;
1148 u32 ucr1;
1149
1150 uart_port_lock_irqsave(&sport->port, &flags);
1151
1152 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1153
1154 if (break_state != 0)
1155 ucr1 |= UCR1_SNDBRK;
1156
1157 imx_uart_writel(sport, ucr1, UCR1);
1158
1159 uart_port_unlock_irqrestore(&sport->port, flags);
1160}
1161
1162/*
1163 * This is our per-port timeout handler, for checking the
1164 * modem status signals.
1165 */
1166static void imx_uart_timeout(struct timer_list *t)
1167{
1168 struct imx_port *sport = from_timer(sport, t, timer);
1169 unsigned long flags;
1170
1171 if (sport->port.state) {
1172 uart_port_lock_irqsave(&sport->port, &flags);
1173 imx_uart_mctrl_check(sport);
1174 uart_port_unlock_irqrestore(&sport->port, flags);
1175
1176 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1177 }
1178}
1179
1180/*
1181 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1182 * [1] the RX DMA buffer is full.
1183 * [2] the aging timer expires
1184 *
1185 * Condition [2] is triggered when a character has been sitting in the FIFO
1186 * for at least 8 byte durations.
1187 */
1188static void imx_uart_dma_rx_callback(void *data)
1189{
1190 struct imx_port *sport = data;
1191 struct dma_chan *chan = sport->dma_chan_rx;
1192 struct scatterlist *sgl = &sport->rx_sgl;
1193 struct tty_port *port = &sport->port.state->port;
1194 struct dma_tx_state state;
1195 struct circ_buf *rx_ring = &sport->rx_ring;
1196 enum dma_status status;
1197 unsigned int w_bytes = 0;
1198 unsigned int r_bytes;
1199 unsigned int bd_size;
1200
1201 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1202
1203 if (status == DMA_ERROR) {
1204 uart_port_lock(&sport->port);
1205 imx_uart_clear_rx_errors(sport);
1206 uart_port_unlock(&sport->port);
1207 return;
1208 }
1209
1210 /*
1211 * The state-residue variable represents the empty space
1212 * relative to the entire buffer. Taking this in consideration
1213 * the head is always calculated base on the buffer total
1214 * length - DMA transaction residue. The UART script from the
1215 * SDMA firmware will jump to the next buffer descriptor,
1216 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1217 * Taking this in consideration the tail is always at the
1218 * beginning of the buffer descriptor that contains the head.
1219 */
1220
1221 /* Calculate the head */
1222 rx_ring->head = sg_dma_len(sgl) - state.residue;
1223
1224 /* Calculate the tail. */
1225 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1226 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1227
1228 if (rx_ring->head <= sg_dma_len(sgl) &&
1229 rx_ring->head > rx_ring->tail) {
1230
1231 /* Move data from tail to head */
1232 r_bytes = rx_ring->head - rx_ring->tail;
1233
1234 /* If we received something, check for 0xff flood */
1235 uart_port_lock(&sport->port);
1236 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1237 uart_port_unlock(&sport->port);
1238
1239 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1240
1241 /* CPU claims ownership of RX DMA buffer */
1242 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1243 DMA_FROM_DEVICE);
1244
1245 w_bytes = tty_insert_flip_string(port,
1246 sport->rx_buf + rx_ring->tail, r_bytes);
1247
1248 /* UART retrieves ownership of RX DMA buffer */
1249 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1250 DMA_FROM_DEVICE);
1251
1252 if (w_bytes != r_bytes)
1253 sport->port.icount.buf_overrun++;
1254
1255 sport->port.icount.rx += w_bytes;
1256 }
1257 } else {
1258 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1259 WARN_ON(rx_ring->head <= rx_ring->tail);
1260 }
1261
1262 if (w_bytes) {
1263 tty_flip_buffer_push(port);
1264 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1265 }
1266}
1267
1268static int imx_uart_start_rx_dma(struct imx_port *sport)
1269{
1270 struct scatterlist *sgl = &sport->rx_sgl;
1271 struct dma_chan *chan = sport->dma_chan_rx;
1272 struct device *dev = sport->port.dev;
1273 struct dma_async_tx_descriptor *desc;
1274 int ret;
1275
1276 sport->rx_ring.head = 0;
1277 sport->rx_ring.tail = 0;
1278
1279 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1280 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1281 if (ret == 0) {
1282 dev_err(dev, "DMA mapping error for RX.\n");
1283 return -EINVAL;
1284 }
1285
1286 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1287 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1288 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1289
1290 if (!desc) {
1291 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1292 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1293 return -EINVAL;
1294 }
1295 desc->callback = imx_uart_dma_rx_callback;
1296 desc->callback_param = sport;
1297
1298 dev_dbg(dev, "RX: prepare for the DMA.\n");
1299 sport->dma_is_rxing = 1;
1300 sport->rx_cookie = dmaengine_submit(desc);
1301 dma_async_issue_pending(chan);
1302 return 0;
1303}
1304
1305/* called with port.lock taken and irqs off */
1306static void imx_uart_clear_rx_errors(struct imx_port *sport)
1307{
1308 struct tty_port *port = &sport->port.state->port;
1309 u32 usr1, usr2;
1310
1311 usr1 = imx_uart_readl(sport, USR1);
1312 usr2 = imx_uart_readl(sport, USR2);
1313
1314 if (usr2 & USR2_BRCD) {
1315 sport->port.icount.brk++;
1316 imx_uart_writel(sport, USR2_BRCD, USR2);
1317 uart_handle_break(&sport->port);
1318 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1319 sport->port.icount.buf_overrun++;
1320 tty_flip_buffer_push(port);
1321 } else {
1322 if (usr1 & USR1_FRAMERR) {
1323 sport->port.icount.frame++;
1324 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1325 } else if (usr1 & USR1_PARITYERR) {
1326 sport->port.icount.parity++;
1327 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1328 }
1329 }
1330
1331 if (usr2 & USR2_ORE) {
1332 sport->port.icount.overrun++;
1333 imx_uart_writel(sport, USR2_ORE, USR2);
1334 }
1335
1336 sport->idle_counter = 0;
1337
1338}
1339
1340#define TXTL_DEFAULT 8
1341#define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1342#define TXTL_DMA 8 /* DMA burst setting */
1343#define RXTL_DMA 9 /* DMA burst setting */
1344
1345static void imx_uart_setup_ufcr(struct imx_port *sport,
1346 unsigned char txwl, unsigned char rxwl)
1347{
1348 unsigned int val;
1349
1350 /* set receiver / transmitter trigger level */
1351 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1352 val |= txwl << UFCR_TXTL_SHF | rxwl;
1353 imx_uart_writel(sport, val, UFCR);
1354}
1355
1356static void imx_uart_dma_exit(struct imx_port *sport)
1357{
1358 if (sport->dma_chan_rx) {
1359 dmaengine_terminate_sync(sport->dma_chan_rx);
1360 dma_release_channel(sport->dma_chan_rx);
1361 sport->dma_chan_rx = NULL;
1362 sport->rx_cookie = -EINVAL;
1363 kfree(sport->rx_buf);
1364 sport->rx_buf = NULL;
1365 }
1366
1367 if (sport->dma_chan_tx) {
1368 dmaengine_terminate_sync(sport->dma_chan_tx);
1369 dma_release_channel(sport->dma_chan_tx);
1370 sport->dma_chan_tx = NULL;
1371 }
1372}
1373
1374static int imx_uart_dma_init(struct imx_port *sport)
1375{
1376 struct dma_slave_config slave_config = {};
1377 struct device *dev = sport->port.dev;
1378 struct dma_chan *chan;
1379 int ret;
1380
1381 /* Prepare for RX : */
1382 chan = dma_request_chan(dev, "rx");
1383 if (IS_ERR(chan)) {
1384 dev_dbg(dev, "cannot get the DMA channel.\n");
1385 sport->dma_chan_rx = NULL;
1386 ret = PTR_ERR(chan);
1387 goto err;
1388 }
1389 sport->dma_chan_rx = chan;
1390
1391 slave_config.direction = DMA_DEV_TO_MEM;
1392 slave_config.src_addr = sport->port.mapbase + URXD0;
1393 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1394 /* one byte less than the watermark level to enable the aging timer */
1395 slave_config.src_maxburst = RXTL_DMA - 1;
1396 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1397 if (ret) {
1398 dev_err(dev, "error in RX dma configuration.\n");
1399 goto err;
1400 }
1401
1402 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1403 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1404 if (!sport->rx_buf) {
1405 ret = -ENOMEM;
1406 goto err;
1407 }
1408 sport->rx_ring.buf = sport->rx_buf;
1409
1410 /* Prepare for TX : */
1411 chan = dma_request_chan(dev, "tx");
1412 if (IS_ERR(chan)) {
1413 dev_err(dev, "cannot get the TX DMA channel!\n");
1414 sport->dma_chan_tx = NULL;
1415 ret = PTR_ERR(chan);
1416 goto err;
1417 }
1418 sport->dma_chan_tx = chan;
1419
1420 slave_config.direction = DMA_MEM_TO_DEV;
1421 slave_config.dst_addr = sport->port.mapbase + URTX0;
1422 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1423 slave_config.dst_maxburst = TXTL_DMA;
1424 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1425 if (ret) {
1426 dev_err(dev, "error in TX dma configuration.");
1427 goto err;
1428 }
1429
1430 return 0;
1431err:
1432 imx_uart_dma_exit(sport);
1433 return ret;
1434}
1435
1436/* called with port.lock taken and irqs off */
1437static void imx_uart_enable_dma(struct imx_port *sport)
1438{
1439 u32 ucr1;
1440
1441 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1442
1443 /* set UCR1 */
1444 ucr1 = imx_uart_readl(sport, UCR1);
1445 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1446 imx_uart_writel(sport, ucr1, UCR1);
1447
1448 sport->dma_is_enabled = 1;
1449}
1450
1451static void imx_uart_disable_dma(struct imx_port *sport)
1452{
1453 u32 ucr1;
1454
1455 /* clear UCR1 */
1456 ucr1 = imx_uart_readl(sport, UCR1);
1457 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1458 imx_uart_writel(sport, ucr1, UCR1);
1459
1460 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1461
1462 sport->dma_is_enabled = 0;
1463}
1464
1465/* half the RX buffer size */
1466#define CTSTL 16
1467
1468static int imx_uart_startup(struct uart_port *port)
1469{
1470 struct imx_port *sport = to_imx_port(port);
1471 int retval;
1472 unsigned long flags;
1473 int dma_is_inited = 0;
1474 u32 ucr1, ucr2, ucr3, ucr4;
1475
1476 retval = clk_prepare_enable(sport->clk_per);
1477 if (retval)
1478 return retval;
1479 retval = clk_prepare_enable(sport->clk_ipg);
1480 if (retval) {
1481 clk_disable_unprepare(sport->clk_per);
1482 return retval;
1483 }
1484
1485 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1486
1487 /* disable the DREN bit (Data Ready interrupt enable) before
1488 * requesting IRQs
1489 */
1490 ucr4 = imx_uart_readl(sport, UCR4);
1491
1492 /* set the trigger level for CTS */
1493 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1494 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1495
1496 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1497
1498 /* Can we enable the DMA support? */
1499 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) {
1500 lockdep_set_subclass(&port->lock, 1);
1501 dma_is_inited = 1;
1502 }
1503
1504 uart_port_lock_irqsave(&sport->port, &flags);
1505
1506 /* Reset fifo's and state machines */
1507 imx_uart_soft_reset(sport);
1508
1509 /*
1510 * Finally, clear and enable interrupts
1511 */
1512 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1513 imx_uart_writel(sport, USR2_ORE, USR2);
1514
1515 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1516 ucr1 |= UCR1_UARTEN;
1517 if (sport->have_rtscts)
1518 ucr1 |= UCR1_RTSDEN;
1519
1520 imx_uart_writel(sport, ucr1, UCR1);
1521
1522 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1523 if (!dma_is_inited)
1524 ucr4 |= UCR4_OREN;
1525 if (sport->inverted_rx)
1526 ucr4 |= UCR4_INVR;
1527 imx_uart_writel(sport, ucr4, UCR4);
1528
1529 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1530 /*
1531 * configure tx polarity before enabling tx
1532 */
1533 if (sport->inverted_tx)
1534 ucr3 |= UCR3_INVT;
1535
1536 if (!imx_uart_is_imx1(sport)) {
1537 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1538
1539 if (sport->dte_mode)
1540 /* disable broken interrupts */
1541 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1542 }
1543 imx_uart_writel(sport, ucr3, UCR3);
1544
1545 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1546 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1547 if (!sport->have_rtscts)
1548 ucr2 |= UCR2_IRTS;
1549 /*
1550 * make sure the edge sensitive RTS-irq is disabled,
1551 * we're using RTSD instead.
1552 */
1553 if (!imx_uart_is_imx1(sport))
1554 ucr2 &= ~UCR2_RTSEN;
1555 imx_uart_writel(sport, ucr2, UCR2);
1556
1557 /*
1558 * Enable modem status interrupts
1559 */
1560 imx_uart_enable_ms(&sport->port);
1561
1562 if (dma_is_inited) {
1563 imx_uart_enable_dma(sport);
1564 imx_uart_start_rx_dma(sport);
1565 } else {
1566 ucr1 = imx_uart_readl(sport, UCR1);
1567 ucr1 |= UCR1_RRDYEN;
1568 imx_uart_writel(sport, ucr1, UCR1);
1569
1570 ucr2 = imx_uart_readl(sport, UCR2);
1571 ucr2 |= UCR2_ATEN;
1572 imx_uart_writel(sport, ucr2, UCR2);
1573 }
1574
1575 imx_uart_disable_loopback_rs485(sport);
1576
1577 uart_port_unlock_irqrestore(&sport->port, flags);
1578
1579 return 0;
1580}
1581
1582static void imx_uart_shutdown(struct uart_port *port)
1583{
1584 struct imx_port *sport = to_imx_port(port);
1585 unsigned long flags;
1586 u32 ucr1, ucr2, ucr4, uts;
1587 int loops;
1588
1589 if (sport->dma_is_enabled) {
1590 dmaengine_terminate_sync(sport->dma_chan_tx);
1591 if (sport->dma_is_txing) {
1592 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1593 sport->dma_tx_nents, DMA_TO_DEVICE);
1594 sport->dma_is_txing = 0;
1595 }
1596 dmaengine_terminate_sync(sport->dma_chan_rx);
1597 if (sport->dma_is_rxing) {
1598 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1599 1, DMA_FROM_DEVICE);
1600 sport->dma_is_rxing = 0;
1601 }
1602
1603 uart_port_lock_irqsave(&sport->port, &flags);
1604 imx_uart_stop_tx(port);
1605 imx_uart_stop_rx(port);
1606 imx_uart_disable_dma(sport);
1607 uart_port_unlock_irqrestore(&sport->port, flags);
1608 imx_uart_dma_exit(sport);
1609 }
1610
1611 mctrl_gpio_disable_ms(sport->gpios);
1612
1613 uart_port_lock_irqsave(&sport->port, &flags);
1614 ucr2 = imx_uart_readl(sport, UCR2);
1615 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1616 imx_uart_writel(sport, ucr2, UCR2);
1617 uart_port_unlock_irqrestore(&sport->port, flags);
1618
1619 /*
1620 * Stop our timer.
1621 */
1622 del_timer_sync(&sport->timer);
1623
1624 /*
1625 * Disable all interrupts, port and break condition.
1626 */
1627
1628 uart_port_lock_irqsave(&sport->port, &flags);
1629
1630 ucr1 = imx_uart_readl(sport, UCR1);
1631 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1632 UCR1_ATDMAEN | UCR1_SNDBRK);
1633 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1634 if (port->rs485.flags & SER_RS485_ENABLED &&
1635 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1636 sport->have_rtscts && !sport->have_rtsgpio) {
1637 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1638 uts |= UTS_LOOP;
1639 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1640 ucr1 |= UCR1_UARTEN;
1641 } else {
1642 ucr1 &= ~UCR1_UARTEN;
1643 }
1644 imx_uart_writel(sport, ucr1, UCR1);
1645
1646 ucr4 = imx_uart_readl(sport, UCR4);
1647 ucr4 &= ~UCR4_TCEN;
1648 imx_uart_writel(sport, ucr4, UCR4);
1649
1650 /*
1651 * We have to ensure the tx state machine ends up in OFF. This
1652 * is especially important for rs485 where we must not leave
1653 * the RTS signal high, blocking the bus indefinitely.
1654 *
1655 * All interrupts are now disabled, so imx_uart_stop_tx() will
1656 * no longer be called from imx_uart_transmit_buffer(). It may
1657 * still be called via the hrtimers, and if those are in play,
1658 * we have to honour the delays.
1659 */
1660 if (sport->tx_state == WAIT_AFTER_RTS || sport->tx_state == SEND)
1661 imx_uart_stop_tx(port);
1662
1663 /*
1664 * In many cases (rs232 mode, or if tx_state was
1665 * WAIT_AFTER_RTS, or if tx_state was SEND and there is no
1666 * delay_rts_after_send), this will have moved directly to
1667 * OFF. In rs485 mode, tx_state might already have been
1668 * WAIT_AFTER_SEND and the hrtimer thus already started, or
1669 * the above imx_uart_stop_tx() call could have started it. In
1670 * those cases, we have to wait for the hrtimer to fire and
1671 * complete the transition to OFF.
1672 */
1673 loops = port->rs485.flags & SER_RS485_ENABLED ?
1674 port->rs485.delay_rts_after_send : 0;
1675 while (sport->tx_state != OFF && loops--) {
1676 uart_port_unlock_irqrestore(&sport->port, flags);
1677 msleep(1);
1678 uart_port_lock_irqsave(&sport->port, &flags);
1679 }
1680
1681 if (sport->tx_state != OFF) {
1682 dev_warn(sport->port.dev, "unexpected tx_state %d\n",
1683 sport->tx_state);
1684 /*
1685 * This machine may be busted, but ensure the RTS
1686 * signal is inactive in order not to block other
1687 * devices.
1688 */
1689 if (port->rs485.flags & SER_RS485_ENABLED) {
1690 ucr2 = imx_uart_readl(sport, UCR2);
1691 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1692 imx_uart_rts_active(sport, &ucr2);
1693 else
1694 imx_uart_rts_inactive(sport, &ucr2);
1695 imx_uart_writel(sport, ucr2, UCR2);
1696 }
1697 sport->tx_state = OFF;
1698 }
1699
1700 uart_port_unlock_irqrestore(&sport->port, flags);
1701
1702 clk_disable_unprepare(sport->clk_per);
1703 clk_disable_unprepare(sport->clk_ipg);
1704}
1705
1706/* called with port.lock taken and irqs off */
1707static void imx_uart_flush_buffer(struct uart_port *port)
1708{
1709 struct imx_port *sport = to_imx_port(port);
1710 struct scatterlist *sgl = &sport->tx_sgl[0];
1711
1712 if (!sport->dma_chan_tx)
1713 return;
1714
1715 sport->tx_bytes = 0;
1716 dmaengine_terminate_all(sport->dma_chan_tx);
1717 if (sport->dma_is_txing) {
1718 u32 ucr1;
1719
1720 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1721 DMA_TO_DEVICE);
1722 ucr1 = imx_uart_readl(sport, UCR1);
1723 ucr1 &= ~UCR1_TXDMAEN;
1724 imx_uart_writel(sport, ucr1, UCR1);
1725 sport->dma_is_txing = 0;
1726 }
1727
1728 imx_uart_soft_reset(sport);
1729
1730}
1731
1732static void
1733imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1734 const struct ktermios *old)
1735{
1736 struct imx_port *sport = to_imx_port(port);
1737 unsigned long flags;
1738 u32 ucr2, old_ucr2, ufcr;
1739 unsigned int baud, quot;
1740 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1741 unsigned long div;
1742 unsigned long num, denom, old_ubir, old_ubmr;
1743 uint64_t tdiv64;
1744
1745 /*
1746 * We only support CS7 and CS8.
1747 */
1748 while ((termios->c_cflag & CSIZE) != CS7 &&
1749 (termios->c_cflag & CSIZE) != CS8) {
1750 termios->c_cflag &= ~CSIZE;
1751 termios->c_cflag |= old_csize;
1752 old_csize = CS8;
1753 }
1754
1755 del_timer_sync(&sport->timer);
1756
1757 /*
1758 * Ask the core to calculate the divisor for us.
1759 */
1760 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1761 quot = uart_get_divisor(port, baud);
1762
1763 uart_port_lock_irqsave(&sport->port, &flags);
1764
1765 /*
1766 * Read current UCR2 and save it for future use, then clear all the bits
1767 * except those we will or may need to preserve.
1768 */
1769 old_ucr2 = imx_uart_readl(sport, UCR2);
1770 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1771
1772 ucr2 |= UCR2_SRST | UCR2_IRTS;
1773 if ((termios->c_cflag & CSIZE) == CS8)
1774 ucr2 |= UCR2_WS;
1775
1776 if (!sport->have_rtscts)
1777 termios->c_cflag &= ~CRTSCTS;
1778
1779 if (port->rs485.flags & SER_RS485_ENABLED) {
1780 /*
1781 * RTS is mandatory for rs485 operation, so keep
1782 * it under manual control and keep transmitter
1783 * disabled.
1784 */
1785 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1786 imx_uart_rts_active(sport, &ucr2);
1787 else
1788 imx_uart_rts_inactive(sport, &ucr2);
1789
1790 } else if (termios->c_cflag & CRTSCTS) {
1791 /*
1792 * Only let receiver control RTS output if we were not requested
1793 * to have RTS inactive (which then should take precedence).
1794 */
1795 if (ucr2 & UCR2_CTS)
1796 ucr2 |= UCR2_CTSC;
1797 }
1798
1799 if (termios->c_cflag & CRTSCTS)
1800 ucr2 &= ~UCR2_IRTS;
1801 if (termios->c_cflag & CSTOPB)
1802 ucr2 |= UCR2_STPB;
1803 if (termios->c_cflag & PARENB) {
1804 ucr2 |= UCR2_PREN;
1805 if (termios->c_cflag & PARODD)
1806 ucr2 |= UCR2_PROE;
1807 }
1808
1809 sport->port.read_status_mask = 0;
1810 if (termios->c_iflag & INPCK)
1811 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1812 if (termios->c_iflag & (BRKINT | PARMRK))
1813 sport->port.read_status_mask |= URXD_BRK;
1814
1815 /*
1816 * Characters to ignore
1817 */
1818 sport->port.ignore_status_mask = 0;
1819 if (termios->c_iflag & IGNPAR)
1820 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1821 if (termios->c_iflag & IGNBRK) {
1822 sport->port.ignore_status_mask |= URXD_BRK;
1823 /*
1824 * If we're ignoring parity and break indicators,
1825 * ignore overruns too (for real raw support).
1826 */
1827 if (termios->c_iflag & IGNPAR)
1828 sport->port.ignore_status_mask |= URXD_OVRRUN;
1829 }
1830
1831 if ((termios->c_cflag & CREAD) == 0)
1832 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1833
1834 /*
1835 * Update the per-port timeout.
1836 */
1837 uart_update_timeout(port, termios->c_cflag, baud);
1838
1839 /* custom-baudrate handling */
1840 div = sport->port.uartclk / (baud * 16);
1841 if (baud == 38400 && quot != div)
1842 baud = sport->port.uartclk / (quot * 16);
1843
1844 div = sport->port.uartclk / (baud * 16);
1845 if (div > 7)
1846 div = 7;
1847 if (!div)
1848 div = 1;
1849
1850 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1851 1 << 16, 1 << 16, &num, &denom);
1852
1853 tdiv64 = sport->port.uartclk;
1854 tdiv64 *= num;
1855 do_div(tdiv64, denom * 16 * div);
1856 tty_termios_encode_baud_rate(termios,
1857 (speed_t)tdiv64, (speed_t)tdiv64);
1858
1859 num -= 1;
1860 denom -= 1;
1861
1862 ufcr = imx_uart_readl(sport, UFCR);
1863 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1864 imx_uart_writel(sport, ufcr, UFCR);
1865
1866 /*
1867 * Two registers below should always be written both and in this
1868 * particular order. One consequence is that we need to check if any of
1869 * them changes and then update both. We do need the check for change
1870 * as even writing the same values seem to "restart"
1871 * transmission/receiving logic in the hardware, that leads to data
1872 * breakage even when rate doesn't in fact change. E.g., user switches
1873 * RTS/CTS handshake and suddenly gets broken bytes.
1874 */
1875 old_ubir = imx_uart_readl(sport, UBIR);
1876 old_ubmr = imx_uart_readl(sport, UBMR);
1877 if (old_ubir != num || old_ubmr != denom) {
1878 imx_uart_writel(sport, num, UBIR);
1879 imx_uart_writel(sport, denom, UBMR);
1880 }
1881
1882 if (!imx_uart_is_imx1(sport))
1883 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1884 IMX21_ONEMS);
1885
1886 imx_uart_writel(sport, ucr2, UCR2);
1887
1888 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1889 imx_uart_enable_ms(&sport->port);
1890
1891 uart_port_unlock_irqrestore(&sport->port, flags);
1892}
1893
1894static const char *imx_uart_type(struct uart_port *port)
1895{
1896 return port->type == PORT_IMX ? "IMX" : NULL;
1897}
1898
1899/*
1900 * Configure/autoconfigure the port.
1901 */
1902static void imx_uart_config_port(struct uart_port *port, int flags)
1903{
1904 if (flags & UART_CONFIG_TYPE)
1905 port->type = PORT_IMX;
1906}
1907
1908/*
1909 * Verify the new serial_struct (for TIOCSSERIAL).
1910 * The only change we allow are to the flags and type, and
1911 * even then only between PORT_IMX and PORT_UNKNOWN
1912 */
1913static int
1914imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1915{
1916 int ret = 0;
1917
1918 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1919 ret = -EINVAL;
1920 if (port->irq != ser->irq)
1921 ret = -EINVAL;
1922 if (ser->io_type != UPIO_MEM)
1923 ret = -EINVAL;
1924 if (port->uartclk / 16 != ser->baud_base)
1925 ret = -EINVAL;
1926 if (port->mapbase != (unsigned long)ser->iomem_base)
1927 ret = -EINVAL;
1928 if (port->iobase != ser->port)
1929 ret = -EINVAL;
1930 if (ser->hub6 != 0)
1931 ret = -EINVAL;
1932 return ret;
1933}
1934
1935#if defined(CONFIG_CONSOLE_POLL)
1936
1937static int imx_uart_poll_init(struct uart_port *port)
1938{
1939 struct imx_port *sport = to_imx_port(port);
1940 unsigned long flags;
1941 u32 ucr1, ucr2;
1942 int retval;
1943
1944 retval = clk_prepare_enable(sport->clk_ipg);
1945 if (retval)
1946 return retval;
1947 retval = clk_prepare_enable(sport->clk_per);
1948 if (retval)
1949 clk_disable_unprepare(sport->clk_ipg);
1950
1951 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1952
1953 uart_port_lock_irqsave(&sport->port, &flags);
1954
1955 /*
1956 * Be careful about the order of enabling bits here. First enable the
1957 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1958 * This prevents that a character that already sits in the RX fifo is
1959 * triggering an irq but the try to fetch it from there results in an
1960 * exception because UARTEN or RXEN is still off.
1961 */
1962 ucr1 = imx_uart_readl(sport, UCR1);
1963 ucr2 = imx_uart_readl(sport, UCR2);
1964
1965 if (imx_uart_is_imx1(sport))
1966 ucr1 |= IMX1_UCR1_UARTCLKEN;
1967
1968 ucr1 |= UCR1_UARTEN;
1969 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1970
1971 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1972 ucr2 &= ~UCR2_ATEN;
1973
1974 imx_uart_writel(sport, ucr1, UCR1);
1975 imx_uart_writel(sport, ucr2, UCR2);
1976
1977 /* now enable irqs */
1978 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1979 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1980
1981 uart_port_unlock_irqrestore(&sport->port, flags);
1982
1983 return 0;
1984}
1985
1986static int imx_uart_poll_get_char(struct uart_port *port)
1987{
1988 struct imx_port *sport = to_imx_port(port);
1989 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1990 return NO_POLL_CHAR;
1991
1992 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1993}
1994
1995static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1996{
1997 struct imx_port *sport = to_imx_port(port);
1998 unsigned int status;
1999
2000 /* drain */
2001 do {
2002 status = imx_uart_readl(sport, USR1);
2003 } while (~status & USR1_TRDY);
2004
2005 /* write */
2006 imx_uart_writel(sport, c, URTX0);
2007
2008 /* flush */
2009 do {
2010 status = imx_uart_readl(sport, USR2);
2011 } while (~status & USR2_TXDC);
2012}
2013#endif
2014
2015/* called with port.lock taken and irqs off or from .probe without locking */
2016static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
2017 struct serial_rs485 *rs485conf)
2018{
2019 struct imx_port *sport = to_imx_port(port);
2020 u32 ucr2, ufcr;
2021
2022 if (rs485conf->flags & SER_RS485_ENABLED) {
2023 /* Enable receiver if low-active RTS signal is requested */
2024 if (sport->have_rtscts && !sport->have_rtsgpio &&
2025 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
2026 rs485conf->flags |= SER_RS485_RX_DURING_TX;
2027
2028 /* disable transmitter */
2029 ucr2 = imx_uart_readl(sport, UCR2);
2030 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
2031 imx_uart_rts_active(sport, &ucr2);
2032 else
2033 imx_uart_rts_inactive(sport, &ucr2);
2034 imx_uart_writel(sport, ucr2, UCR2);
2035 }
2036
2037 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
2038 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
2039 rs485conf->flags & SER_RS485_RX_DURING_TX) {
2040 /* If the receiver trigger is 0, set it to a default value */
2041 ufcr = imx_uart_readl(sport, UFCR);
2042 if ((ufcr & UFCR_RXTL_MASK) == 0)
2043 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2044 imx_uart_start_rx(port);
2045 }
2046
2047 return 0;
2048}
2049
2050static const struct uart_ops imx_uart_pops = {
2051 .tx_empty = imx_uart_tx_empty,
2052 .set_mctrl = imx_uart_set_mctrl,
2053 .get_mctrl = imx_uart_get_mctrl,
2054 .stop_tx = imx_uart_stop_tx,
2055 .start_tx = imx_uart_start_tx,
2056 .stop_rx = imx_uart_stop_rx,
2057 .enable_ms = imx_uart_enable_ms,
2058 .break_ctl = imx_uart_break_ctl,
2059 .startup = imx_uart_startup,
2060 .shutdown = imx_uart_shutdown,
2061 .flush_buffer = imx_uart_flush_buffer,
2062 .set_termios = imx_uart_set_termios,
2063 .type = imx_uart_type,
2064 .config_port = imx_uart_config_port,
2065 .verify_port = imx_uart_verify_port,
2066#if defined(CONFIG_CONSOLE_POLL)
2067 .poll_init = imx_uart_poll_init,
2068 .poll_get_char = imx_uart_poll_get_char,
2069 .poll_put_char = imx_uart_poll_put_char,
2070#endif
2071};
2072
2073static struct imx_port *imx_uart_ports[UART_NR];
2074
2075#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
2076static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
2077{
2078 struct imx_port *sport = to_imx_port(port);
2079
2080 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
2081 barrier();
2082
2083 imx_uart_writel(sport, ch, URTX0);
2084
2085 sport->last_putchar_was_newline = (ch == '\n');
2086}
2087
2088static void imx_uart_console_device_lock(struct console *co, unsigned long *flags)
2089{
2090 struct uart_port *up = &imx_uart_ports[co->index]->port;
2091
2092 return __uart_port_lock_irqsave(up, flags);
2093}
2094
2095static void imx_uart_console_device_unlock(struct console *co, unsigned long flags)
2096{
2097 struct uart_port *up = &imx_uart_ports[co->index]->port;
2098
2099 return __uart_port_unlock_irqrestore(up, flags);
2100}
2101
2102static void imx_uart_console_write_atomic(struct console *co,
2103 struct nbcon_write_context *wctxt)
2104{
2105 struct imx_port *sport = imx_uart_ports[co->index];
2106 struct uart_port *port = &sport->port;
2107 struct imx_port_ucrs old_ucr;
2108 unsigned int ucr1, usr2;
2109
2110 if (!nbcon_enter_unsafe(wctxt))
2111 return;
2112
2113 /*
2114 * First, save UCR1/2/3 and then disable interrupts
2115 */
2116 imx_uart_ucrs_save(sport, &old_ucr);
2117 ucr1 = old_ucr.ucr1;
2118
2119 if (imx_uart_is_imx1(sport))
2120 ucr1 |= IMX1_UCR1_UARTCLKEN;
2121 ucr1 |= UCR1_UARTEN;
2122 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2123
2124 imx_uart_writel(sport, ucr1, UCR1);
2125 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2126
2127 if (!sport->last_putchar_was_newline)
2128 uart_console_write(port, "\n", 1, imx_uart_console_putchar);
2129 uart_console_write(port, wctxt->outbuf, wctxt->len,
2130 imx_uart_console_putchar);
2131
2132 /*
2133 * Finally, wait for transmitter to become empty
2134 * and restore UCR1/2/3
2135 */
2136 read_poll_timeout_atomic(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2137 0, USEC_PER_SEC, false, sport, USR2);
2138 imx_uart_ucrs_restore(sport, &old_ucr);
2139
2140 nbcon_exit_unsafe(wctxt);
2141}
2142
2143static void imx_uart_console_write_thread(struct console *co,
2144 struct nbcon_write_context *wctxt)
2145{
2146 struct imx_port *sport = imx_uart_ports[co->index];
2147 struct uart_port *port = &sport->port;
2148 struct imx_port_ucrs old_ucr;
2149 unsigned int ucr1, usr2;
2150
2151 if (!nbcon_enter_unsafe(wctxt))
2152 return;
2153
2154 /*
2155 * First, save UCR1/2/3 and then disable interrupts
2156 */
2157 imx_uart_ucrs_save(sport, &old_ucr);
2158 ucr1 = old_ucr.ucr1;
2159
2160 if (imx_uart_is_imx1(sport))
2161 ucr1 |= IMX1_UCR1_UARTCLKEN;
2162 ucr1 |= UCR1_UARTEN;
2163 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2164
2165 imx_uart_writel(sport, ucr1, UCR1);
2166 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2167
2168 if (nbcon_exit_unsafe(wctxt)) {
2169 int len = READ_ONCE(wctxt->len);
2170 int i;
2171
2172 /*
2173 * Write out the message. Toggle unsafe for each byte in order
2174 * to give another (higher priority) context the opportunity
2175 * for a friendly takeover. If such a takeover occurs, this
2176 * context must reacquire ownership in order to perform final
2177 * actions (such as re-enabling the interrupts).
2178 *
2179 * IMPORTANT: wctxt->outbuf and wctxt->len are no longer valid
2180 * after a reacquire so writing the message must be
2181 * aborted.
2182 */
2183 for (i = 0; i < len; i++) {
2184 if (!nbcon_enter_unsafe(wctxt))
2185 break;
2186
2187 uart_console_write(port, wctxt->outbuf + i, 1,
2188 imx_uart_console_putchar);
2189
2190 if (!nbcon_exit_unsafe(wctxt))
2191 break;
2192 }
2193 }
2194
2195 while (!nbcon_enter_unsafe(wctxt))
2196 nbcon_reacquire_nobuf(wctxt);
2197
2198 /*
2199 * Finally, wait for transmitter to become empty
2200 * and restore UCR1/2/3
2201 */
2202 read_poll_timeout(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2203 0, USEC_PER_SEC, false, sport, USR2);
2204 imx_uart_ucrs_restore(sport, &old_ucr);
2205
2206 nbcon_exit_unsafe(wctxt);
2207}
2208
2209/*
2210 * If the port was already initialised (eg, by a boot loader),
2211 * try to determine the current setup.
2212 */
2213static void
2214imx_uart_console_get_options(struct imx_port *sport, int *baud,
2215 int *parity, int *bits)
2216{
2217
2218 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2219 /* ok, the port was enabled */
2220 unsigned int ucr2, ubir, ubmr, uartclk;
2221 unsigned int baud_raw;
2222 unsigned int ucfr_rfdiv;
2223
2224 ucr2 = imx_uart_readl(sport, UCR2);
2225
2226 *parity = 'n';
2227 if (ucr2 & UCR2_PREN) {
2228 if (ucr2 & UCR2_PROE)
2229 *parity = 'o';
2230 else
2231 *parity = 'e';
2232 }
2233
2234 if (ucr2 & UCR2_WS)
2235 *bits = 8;
2236 else
2237 *bits = 7;
2238
2239 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2240 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2241
2242 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2243 if (ucfr_rfdiv == 6)
2244 ucfr_rfdiv = 7;
2245 else
2246 ucfr_rfdiv = 6 - ucfr_rfdiv;
2247
2248 uartclk = clk_get_rate(sport->clk_per);
2249 uartclk /= ucfr_rfdiv;
2250
2251 { /*
2252 * The next code provides exact computation of
2253 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2254 * without need of float support or long long division,
2255 * which would be required to prevent 32bit arithmetic overflow
2256 */
2257 unsigned int mul = ubir + 1;
2258 unsigned int div = 16 * (ubmr + 1);
2259 unsigned int rem = uartclk % div;
2260
2261 baud_raw = (uartclk / div) * mul;
2262 baud_raw += (rem * mul + div / 2) / div;
2263 *baud = (baud_raw + 50) / 100 * 100;
2264 }
2265
2266 if (*baud != baud_raw)
2267 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2268 baud_raw, *baud);
2269 }
2270}
2271
2272static int
2273imx_uart_console_setup(struct console *co, char *options)
2274{
2275 struct imx_port *sport;
2276 int baud = 9600;
2277 int bits = 8;
2278 int parity = 'n';
2279 int flow = 'n';
2280 int retval;
2281
2282 /*
2283 * Check whether an invalid uart number has been specified, and
2284 * if so, search for the first available port that does have
2285 * console support.
2286 */
2287 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2288 co->index = 0;
2289 sport = imx_uart_ports[co->index];
2290 if (sport == NULL)
2291 return -ENODEV;
2292
2293 /* For setting the registers, we only need to enable the ipg clock. */
2294 retval = clk_prepare_enable(sport->clk_ipg);
2295 if (retval)
2296 goto error_console;
2297
2298 sport->last_putchar_was_newline = true;
2299
2300 if (options)
2301 uart_parse_options(options, &baud, &parity, &bits, &flow);
2302 else
2303 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2304
2305 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2306
2307 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2308
2309 if (retval) {
2310 clk_disable_unprepare(sport->clk_ipg);
2311 goto error_console;
2312 }
2313
2314 retval = clk_prepare_enable(sport->clk_per);
2315 if (retval)
2316 clk_disable_unprepare(sport->clk_ipg);
2317
2318error_console:
2319 return retval;
2320}
2321
2322static int
2323imx_uart_console_exit(struct console *co)
2324{
2325 struct imx_port *sport = imx_uart_ports[co->index];
2326
2327 clk_disable_unprepare(sport->clk_per);
2328 clk_disable_unprepare(sport->clk_ipg);
2329
2330 return 0;
2331}
2332
2333static struct uart_driver imx_uart_uart_driver;
2334static struct console imx_uart_console = {
2335 .name = DEV_NAME,
2336 .write_atomic = imx_uart_console_write_atomic,
2337 .write_thread = imx_uart_console_write_thread,
2338 .device_lock = imx_uart_console_device_lock,
2339 .device_unlock = imx_uart_console_device_unlock,
2340 .flags = CON_PRINTBUFFER | CON_NBCON,
2341 .device = uart_console_device,
2342 .setup = imx_uart_console_setup,
2343 .exit = imx_uart_console_exit,
2344 .index = -1,
2345 .data = &imx_uart_uart_driver,
2346};
2347
2348#define IMX_CONSOLE &imx_uart_console
2349
2350#else
2351#define IMX_CONSOLE NULL
2352#endif
2353
2354static struct uart_driver imx_uart_uart_driver = {
2355 .owner = THIS_MODULE,
2356 .driver_name = DRIVER_NAME,
2357 .dev_name = DEV_NAME,
2358 .major = SERIAL_IMX_MAJOR,
2359 .minor = MINOR_START,
2360 .nr = ARRAY_SIZE(imx_uart_ports),
2361 .cons = IMX_CONSOLE,
2362};
2363
2364static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2365{
2366 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2367 unsigned long flags;
2368
2369 uart_port_lock_irqsave(&sport->port, &flags);
2370 if (sport->tx_state == WAIT_AFTER_RTS)
2371 imx_uart_start_tx(&sport->port);
2372 uart_port_unlock_irqrestore(&sport->port, flags);
2373
2374 return HRTIMER_NORESTART;
2375}
2376
2377static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2378{
2379 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2380 unsigned long flags;
2381
2382 uart_port_lock_irqsave(&sport->port, &flags);
2383 if (sport->tx_state == WAIT_AFTER_SEND)
2384 imx_uart_stop_tx(&sport->port);
2385 uart_port_unlock_irqrestore(&sport->port, flags);
2386
2387 return HRTIMER_NORESTART;
2388}
2389
2390static const struct serial_rs485 imx_rs485_supported = {
2391 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2392 SER_RS485_RX_DURING_TX,
2393 .delay_rts_before_send = 1,
2394 .delay_rts_after_send = 1,
2395};
2396
2397/* Default RX DMA buffer configuration */
2398#define RX_DMA_PERIODS 16
2399#define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2400
2401static int imx_uart_probe(struct platform_device *pdev)
2402{
2403 struct device_node *np = pdev->dev.of_node;
2404 struct imx_port *sport;
2405 void __iomem *base;
2406 u32 dma_buf_conf[2];
2407 int ret = 0;
2408 u32 ucr1, ucr2, uts;
2409 struct resource *res;
2410 int txirq, rxirq, rtsirq;
2411
2412 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2413 if (!sport)
2414 return -ENOMEM;
2415
2416 sport->devdata = of_device_get_match_data(&pdev->dev);
2417
2418 ret = of_alias_get_id(np, "serial");
2419 if (ret < 0) {
2420 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2421 return ret;
2422 }
2423 sport->port.line = ret;
2424
2425 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2426 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
2427
2428 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
2429
2430 sport->have_rtsgpio = of_property_present(np, "rts-gpios");
2431
2432 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
2433
2434 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
2435
2436 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2437 sport->rx_period_length = dma_buf_conf[0];
2438 sport->rx_periods = dma_buf_conf[1];
2439 } else {
2440 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2441 sport->rx_periods = RX_DMA_PERIODS;
2442 }
2443
2444 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2445 dev_err(&pdev->dev, "serial%d out of range\n",
2446 sport->port.line);
2447 return -EINVAL;
2448 }
2449
2450 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2451 if (IS_ERR(base))
2452 return PTR_ERR(base);
2453
2454 rxirq = platform_get_irq(pdev, 0);
2455 if (rxirq < 0)
2456 return rxirq;
2457 txirq = platform_get_irq_optional(pdev, 1);
2458 rtsirq = platform_get_irq_optional(pdev, 2);
2459
2460 sport->port.dev = &pdev->dev;
2461 sport->port.mapbase = res->start;
2462 sport->port.membase = base;
2463 sport->port.type = PORT_IMX;
2464 sport->port.iotype = UPIO_MEM;
2465 sport->port.irq = rxirq;
2466 sport->port.fifosize = 32;
2467 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2468 sport->port.ops = &imx_uart_pops;
2469 sport->port.rs485_config = imx_uart_rs485_config;
2470 /* RTS is required to control the RS485 transmitter */
2471 if (sport->have_rtscts || sport->have_rtsgpio)
2472 sport->port.rs485_supported = imx_rs485_supported;
2473 sport->port.flags = UPF_BOOT_AUTOCONF;
2474 timer_setup(&sport->timer, imx_uart_timeout, 0);
2475
2476 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2477 if (IS_ERR(sport->gpios))
2478 return PTR_ERR(sport->gpios);
2479
2480 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2481 if (IS_ERR(sport->clk_ipg)) {
2482 ret = PTR_ERR(sport->clk_ipg);
2483 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2484 return ret;
2485 }
2486
2487 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2488 if (IS_ERR(sport->clk_per)) {
2489 ret = PTR_ERR(sport->clk_per);
2490 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2491 return ret;
2492 }
2493
2494 sport->port.uartclk = clk_get_rate(sport->clk_per);
2495
2496 /* For register access, we only need to enable the ipg clock. */
2497 ret = clk_prepare_enable(sport->clk_ipg);
2498 if (ret) {
2499 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2500 return ret;
2501 }
2502
2503 ret = uart_get_rs485_mode(&sport->port);
2504 if (ret)
2505 goto err_clk;
2506
2507 /*
2508 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2509 * signal cannot be set low during transmission in case the
2510 * receiver is off (limitation of the i.MX UART IP).
2511 */
2512 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2513 sport->have_rtscts && !sport->have_rtsgpio &&
2514 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2515 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2516 dev_err(&pdev->dev,
2517 "low-active RTS not possible when receiver is off, enabling receiver\n");
2518
2519 /* Disable interrupts before requesting them */
2520 ucr1 = imx_uart_readl(sport, UCR1);
2521 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2522 imx_uart_writel(sport, ucr1, UCR1);
2523
2524 /* Disable Ageing Timer interrupt */
2525 ucr2 = imx_uart_readl(sport, UCR2);
2526 ucr2 &= ~UCR2_ATEN;
2527 imx_uart_writel(sport, ucr2, UCR2);
2528
2529 /*
2530 * In case RS485 is enabled without GPIO RTS control, the UART IP
2531 * is used to control CTS signal. Keep both the UART and Receiver
2532 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2533 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2534 * data from being fed into the RX FIFO, enable loopback mode in
2535 * UTS register, which disconnects the RX path from external RXD
2536 * pin and connects it to the Transceiver, which is disabled, so
2537 * no data can be fed to the RX FIFO that way.
2538 */
2539 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2540 sport->have_rtscts && !sport->have_rtsgpio) {
2541 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2542 uts |= UTS_LOOP;
2543 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2544
2545 ucr1 = imx_uart_readl(sport, UCR1);
2546 ucr1 |= UCR1_UARTEN;
2547 imx_uart_writel(sport, ucr1, UCR1);
2548
2549 ucr2 = imx_uart_readl(sport, UCR2);
2550 ucr2 |= UCR2_RXEN;
2551 imx_uart_writel(sport, ucr2, UCR2);
2552 }
2553
2554 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2555 /*
2556 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2557 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2558 * and DCD (when they are outputs) or enables the respective
2559 * irqs. So set this bit early, i.e. before requesting irqs.
2560 */
2561 u32 ufcr = imx_uart_readl(sport, UFCR);
2562 if (!(ufcr & UFCR_DCEDTE))
2563 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2564
2565 /*
2566 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2567 * enabled later because they cannot be cleared
2568 * (confirmed on i.MX25) which makes them unusable.
2569 */
2570 imx_uart_writel(sport,
2571 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2572 UCR3);
2573
2574 } else {
2575 u32 ucr3 = UCR3_DSR;
2576 u32 ufcr = imx_uart_readl(sport, UFCR);
2577 if (ufcr & UFCR_DCEDTE)
2578 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2579
2580 if (!imx_uart_is_imx1(sport))
2581 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2582 imx_uart_writel(sport, ucr3, UCR3);
2583 }
2584
2585 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2586 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2587 sport->trigger_start_tx.function = imx_trigger_start_tx;
2588 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2589
2590 /*
2591 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2592 * chips only have one interrupt.
2593 */
2594 if (txirq > 0) {
2595 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2596 dev_name(&pdev->dev), sport);
2597 if (ret) {
2598 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2599 ret);
2600 goto err_clk;
2601 }
2602
2603 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2604 dev_name(&pdev->dev), sport);
2605 if (ret) {
2606 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2607 ret);
2608 goto err_clk;
2609 }
2610
2611 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2612 dev_name(&pdev->dev), sport);
2613 if (ret) {
2614 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2615 ret);
2616 goto err_clk;
2617 }
2618 } else {
2619 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2620 dev_name(&pdev->dev), sport);
2621 if (ret) {
2622 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2623 goto err_clk;
2624 }
2625 }
2626
2627 imx_uart_ports[sport->port.line] = sport;
2628
2629 platform_set_drvdata(pdev, sport);
2630
2631 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2632
2633err_clk:
2634 clk_disable_unprepare(sport->clk_ipg);
2635
2636 return ret;
2637}
2638
2639static void imx_uart_remove(struct platform_device *pdev)
2640{
2641 struct imx_port *sport = platform_get_drvdata(pdev);
2642
2643 uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2644}
2645
2646static void imx_uart_restore_context(struct imx_port *sport)
2647{
2648 unsigned long flags;
2649
2650 uart_port_lock_irqsave(&sport->port, &flags);
2651 if (!sport->context_saved) {
2652 uart_port_unlock_irqrestore(&sport->port, flags);
2653 return;
2654 }
2655
2656 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2657 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2658 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2659 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2660 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2661 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2662 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2663 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2664 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2665 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2666 sport->context_saved = false;
2667 uart_port_unlock_irqrestore(&sport->port, flags);
2668}
2669
2670static void imx_uart_save_context(struct imx_port *sport)
2671{
2672 unsigned long flags;
2673
2674 /* Save necessary regs */
2675 uart_port_lock_irqsave(&sport->port, &flags);
2676 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2677 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2678 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2679 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2680 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2681 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2682 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2683 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2684 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2685 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2686 sport->context_saved = true;
2687 uart_port_unlock_irqrestore(&sport->port, flags);
2688}
2689
2690/* called with irq off */
2691static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2692{
2693 u32 ucr3;
2694
2695 uart_port_lock_irq(&sport->port);
2696
2697 ucr3 = imx_uart_readl(sport, UCR3);
2698 if (on) {
2699 imx_uart_writel(sport, USR1_AWAKE, USR1);
2700 ucr3 |= UCR3_AWAKEN;
2701 } else {
2702 ucr3 &= ~UCR3_AWAKEN;
2703 }
2704 imx_uart_writel(sport, ucr3, UCR3);
2705
2706 if (sport->have_rtscts) {
2707 u32 ucr1 = imx_uart_readl(sport, UCR1);
2708 if (on) {
2709 imx_uart_writel(sport, USR1_RTSD, USR1);
2710 ucr1 |= UCR1_RTSDEN;
2711 } else {
2712 ucr1 &= ~UCR1_RTSDEN;
2713 }
2714 imx_uart_writel(sport, ucr1, UCR1);
2715 }
2716
2717 uart_port_unlock_irq(&sport->port);
2718}
2719
2720static int imx_uart_suspend_noirq(struct device *dev)
2721{
2722 struct imx_port *sport = dev_get_drvdata(dev);
2723
2724 imx_uart_save_context(sport);
2725
2726 clk_disable(sport->clk_ipg);
2727
2728 pinctrl_pm_select_sleep_state(dev);
2729
2730 return 0;
2731}
2732
2733static int imx_uart_resume_noirq(struct device *dev)
2734{
2735 struct imx_port *sport = dev_get_drvdata(dev);
2736 int ret;
2737
2738 pinctrl_pm_select_default_state(dev);
2739
2740 ret = clk_enable(sport->clk_ipg);
2741 if (ret)
2742 return ret;
2743
2744 imx_uart_restore_context(sport);
2745
2746 return 0;
2747}
2748
2749static int imx_uart_suspend(struct device *dev)
2750{
2751 struct imx_port *sport = dev_get_drvdata(dev);
2752 int ret;
2753
2754 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2755 disable_irq(sport->port.irq);
2756
2757 ret = clk_prepare_enable(sport->clk_ipg);
2758 if (ret)
2759 return ret;
2760
2761 /* enable wakeup from i.MX UART */
2762 imx_uart_enable_wakeup(sport, true);
2763
2764 return 0;
2765}
2766
2767static int imx_uart_resume(struct device *dev)
2768{
2769 struct imx_port *sport = dev_get_drvdata(dev);
2770
2771 /* disable wakeup from i.MX UART */
2772 imx_uart_enable_wakeup(sport, false);
2773
2774 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2775 enable_irq(sport->port.irq);
2776
2777 clk_disable_unprepare(sport->clk_ipg);
2778
2779 return 0;
2780}
2781
2782static int imx_uart_freeze(struct device *dev)
2783{
2784 struct imx_port *sport = dev_get_drvdata(dev);
2785
2786 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2787
2788 return clk_prepare_enable(sport->clk_ipg);
2789}
2790
2791static int imx_uart_thaw(struct device *dev)
2792{
2793 struct imx_port *sport = dev_get_drvdata(dev);
2794
2795 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2796
2797 clk_disable_unprepare(sport->clk_ipg);
2798
2799 return 0;
2800}
2801
2802static const struct dev_pm_ops imx_uart_pm_ops = {
2803 .suspend_noirq = imx_uart_suspend_noirq,
2804 .resume_noirq = imx_uart_resume_noirq,
2805 .freeze_noirq = imx_uart_suspend_noirq,
2806 .thaw_noirq = imx_uart_resume_noirq,
2807 .restore_noirq = imx_uart_resume_noirq,
2808 .suspend = imx_uart_suspend,
2809 .resume = imx_uart_resume,
2810 .freeze = imx_uart_freeze,
2811 .thaw = imx_uart_thaw,
2812 .restore = imx_uart_thaw,
2813};
2814
2815static struct platform_driver imx_uart_platform_driver = {
2816 .probe = imx_uart_probe,
2817 .remove = imx_uart_remove,
2818
2819 .driver = {
2820 .name = "imx-uart",
2821 .of_match_table = imx_uart_dt_ids,
2822 .pm = &imx_uart_pm_ops,
2823 },
2824};
2825
2826static int __init imx_uart_init(void)
2827{
2828 int ret = uart_register_driver(&imx_uart_uart_driver);
2829
2830 if (ret)
2831 return ret;
2832
2833 ret = platform_driver_register(&imx_uart_platform_driver);
2834 if (ret != 0)
2835 uart_unregister_driver(&imx_uart_uart_driver);
2836
2837 return ret;
2838}
2839
2840static void __exit imx_uart_exit(void)
2841{
2842 platform_driver_unregister(&imx_uart_platform_driver);
2843 uart_unregister_driver(&imx_uart_uart_driver);
2844}
2845
2846module_init(imx_uart_init);
2847module_exit(imx_uart_exit);
2848
2849MODULE_AUTHOR("Sascha Hauer");
2850MODULE_DESCRIPTION("IMX generic serial port driver");
2851MODULE_LICENSE("GPL");
2852MODULE_ALIAS("platform:imx-uart");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11#include <linux/module.h>
12#include <linux/ioport.h>
13#include <linux/init.h>
14#include <linux/console.h>
15#include <linux/sysrq.h>
16#include <linux/platform_device.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/serial_core.h>
20#include <linux/serial.h>
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/ktime.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/rational.h>
26#include <linux/slab.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/io.h>
30#include <linux/dma-mapping.h>
31
32#include <asm/irq.h>
33#include <linux/dma/imx-dma.h>
34
35#include "serial_mctrl_gpio.h"
36
37/* Register definitions */
38#define URXD0 0x0 /* Receiver Register */
39#define URTX0 0x40 /* Transmitter Register */
40#define UCR1 0x80 /* Control Register 1 */
41#define UCR2 0x84 /* Control Register 2 */
42#define UCR3 0x88 /* Control Register 3 */
43#define UCR4 0x8c /* Control Register 4 */
44#define UFCR 0x90 /* FIFO Control Register */
45#define USR1 0x94 /* Status Register 1 */
46#define USR2 0x98 /* Status Register 2 */
47#define UESC 0x9c /* Escape Character Register */
48#define UTIM 0xa0 /* Escape Timer Register */
49#define UBIR 0xa4 /* BRM Incremental Register */
50#define UBMR 0xa8 /* BRM Modulator Register */
51#define UBRC 0xac /* Baud Rate Count Register */
52#define IMX21_ONEMS 0xb0 /* One Millisecond register */
53#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55
56/* UART Control Register Bit Fields.*/
57#define URXD_DUMMY_READ (1<<16)
58#define URXD_CHARRDY (1<<15)
59#define URXD_ERR (1<<14)
60#define URXD_OVRRUN (1<<13)
61#define URXD_FRMERR (1<<12)
62#define URXD_BRK (1<<11)
63#define URXD_PRERR (1<<10)
64#define URXD_RX_DATA (0xFF<<0)
65#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
66#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
67#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
68#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
69#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
71#define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
72#define UCR1_IREN (1<<7) /* Infrared interface enable */
73#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
74#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
75#define UCR1_SNDBRK (1<<4) /* Send break */
76#define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
77#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
79#define UCR1_DOZE (1<<1) /* Doze */
80#define UCR1_UARTEN (1<<0) /* UART enabled */
81#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
82#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
83#define UCR2_CTSC (1<<13) /* CTS pin control */
84#define UCR2_CTS (1<<12) /* Clear to send */
85#define UCR2_ESCEN (1<<11) /* Escape enable */
86#define UCR2_PREN (1<<8) /* Parity enable */
87#define UCR2_PROE (1<<7) /* Parity odd/even */
88#define UCR2_STPB (1<<6) /* Stop */
89#define UCR2_WS (1<<5) /* Word size */
90#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
91#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
92#define UCR2_TXEN (1<<2) /* Transmitter enabled */
93#define UCR2_RXEN (1<<1) /* Receiver enabled */
94#define UCR2_SRST (1<<0) /* SW reset */
95#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
96#define UCR3_PARERREN (1<<12) /* Parity enable */
97#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
98#define UCR3_DSR (1<<10) /* Data set ready */
99#define UCR3_DCD (1<<9) /* Data carrier detect */
100#define UCR3_RI (1<<8) /* Ring indicator */
101#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
102#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
103#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
104#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
105#define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
106#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
107#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
108#define UCR3_BPEN (1<<0) /* Preset registers enable */
109#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
110#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
111#define UCR4_INVR (1<<9) /* Inverted infrared reception */
112#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
113#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
114#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
115#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
116#define UCR4_IRSC (1<<5) /* IR special case */
117#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
118#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
119#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
120#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
121#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
122#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
123#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
124#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
125#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
126#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
127#define USR1_RTSS (1<<14) /* RTS pin status */
128#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
129#define USR1_RTSD (1<<12) /* RTS delta */
130#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
131#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
132#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
133#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
134#define USR1_DTRD (1<<7) /* DTR Delta */
135#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
136#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
137#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
138#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
139#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
140#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
141#define USR2_IDLE (1<<12) /* Idle condition */
142#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
143#define USR2_RIIN (1<<9) /* Ring Indicator Input */
144#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
145#define USR2_WAKE (1<<7) /* Wake */
146#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
147#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
148#define USR2_TXDC (1<<3) /* Transmitter complete */
149#define USR2_BRCD (1<<2) /* Break condition */
150#define USR2_ORE (1<<1) /* Overrun error */
151#define USR2_RDR (1<<0) /* Recv data ready */
152#define UTS_FRCPERR (1<<13) /* Force parity error */
153#define UTS_LOOP (1<<12) /* Loop tx and rx */
154#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
155#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
156#define UTS_TXFULL (1<<4) /* TxFIFO full */
157#define UTS_RXFULL (1<<3) /* RxFIFO full */
158#define UTS_SOFTRST (1<<0) /* Software reset */
159
160/* We've been assigned a range on the "Low-density serial ports" major */
161#define SERIAL_IMX_MAJOR 207
162#define MINOR_START 16
163#define DEV_NAME "ttymxc"
164
165/*
166 * This determines how often we check the modem status signals
167 * for any change. They generally aren't connected to an IRQ
168 * so we have to poll them. We also check immediately before
169 * filling the TX fifo incase CTS has been dropped.
170 */
171#define MCTRL_TIMEOUT (250*HZ/1000)
172
173#define DRIVER_NAME "IMX-uart"
174
175#define UART_NR 8
176
177/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
178enum imx_uart_type {
179 IMX1_UART,
180 IMX21_UART,
181 IMX53_UART,
182 IMX6Q_UART,
183};
184
185/* device type dependent stuff */
186struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189};
190
191enum imx_tx_state {
192 OFF,
193 WAIT_AFTER_RTS,
194 SEND,
195 WAIT_AFTER_SEND,
196};
197
198struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 unsigned int have_rtscts:1;
203 unsigned int have_rtsgpio:1;
204 unsigned int dte_mode:1;
205 unsigned int inverted_tx:1;
206 unsigned int inverted_rx:1;
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 const struct imx_uart_data *devdata;
210
211 struct mctrl_gpios *gpios;
212
213 /* shadow registers */
214 unsigned int ucr1;
215 unsigned int ucr2;
216 unsigned int ucr3;
217 unsigned int ucr4;
218 unsigned int ufcr;
219
220 /* DMA fields */
221 unsigned int dma_is_enabled:1;
222 unsigned int dma_is_rxing:1;
223 unsigned int dma_is_txing:1;
224 struct dma_chan *dma_chan_rx, *dma_chan_tx;
225 struct scatterlist rx_sgl, tx_sgl[2];
226 void *rx_buf;
227 struct circ_buf rx_ring;
228 unsigned int rx_buf_size;
229 unsigned int rx_period_length;
230 unsigned int rx_periods;
231 dma_cookie_t rx_cookie;
232 unsigned int tx_bytes;
233 unsigned int dma_tx_nents;
234 unsigned int saved_reg[10];
235 bool context_saved;
236
237 enum imx_tx_state tx_state;
238 struct hrtimer trigger_start_tx;
239 struct hrtimer trigger_stop_tx;
240};
241
242struct imx_port_ucrs {
243 unsigned int ucr1;
244 unsigned int ucr2;
245 unsigned int ucr3;
246};
247
248static struct imx_uart_data imx_uart_devdata[] = {
249 [IMX1_UART] = {
250 .uts_reg = IMX1_UTS,
251 .devtype = IMX1_UART,
252 },
253 [IMX21_UART] = {
254 .uts_reg = IMX21_UTS,
255 .devtype = IMX21_UART,
256 },
257 [IMX53_UART] = {
258 .uts_reg = IMX21_UTS,
259 .devtype = IMX53_UART,
260 },
261 [IMX6Q_UART] = {
262 .uts_reg = IMX21_UTS,
263 .devtype = IMX6Q_UART,
264 },
265};
266
267static const struct of_device_id imx_uart_dt_ids[] = {
268 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
269 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
270 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
271 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
272 { /* sentinel */ }
273};
274MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
275
276static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
277{
278 switch (offset) {
279 case UCR1:
280 sport->ucr1 = val;
281 break;
282 case UCR2:
283 sport->ucr2 = val;
284 break;
285 case UCR3:
286 sport->ucr3 = val;
287 break;
288 case UCR4:
289 sport->ucr4 = val;
290 break;
291 case UFCR:
292 sport->ufcr = val;
293 break;
294 default:
295 break;
296 }
297 writel(val, sport->port.membase + offset);
298}
299
300static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
301{
302 switch (offset) {
303 case UCR1:
304 return sport->ucr1;
305 break;
306 case UCR2:
307 /*
308 * UCR2_SRST is the only bit in the cached registers that might
309 * differ from the value that was last written. As it only
310 * automatically becomes one after being cleared, reread
311 * conditionally.
312 */
313 if (!(sport->ucr2 & UCR2_SRST))
314 sport->ucr2 = readl(sport->port.membase + offset);
315 return sport->ucr2;
316 break;
317 case UCR3:
318 return sport->ucr3;
319 break;
320 case UCR4:
321 return sport->ucr4;
322 break;
323 case UFCR:
324 return sport->ufcr;
325 break;
326 default:
327 return readl(sport->port.membase + offset);
328 }
329}
330
331static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
332{
333 return sport->devdata->uts_reg;
334}
335
336static inline int imx_uart_is_imx1(struct imx_port *sport)
337{
338 return sport->devdata->devtype == IMX1_UART;
339}
340
341static inline int imx_uart_is_imx21(struct imx_port *sport)
342{
343 return sport->devdata->devtype == IMX21_UART;
344}
345
346static inline int imx_uart_is_imx53(struct imx_port *sport)
347{
348 return sport->devdata->devtype == IMX53_UART;
349}
350
351static inline int imx_uart_is_imx6q(struct imx_port *sport)
352{
353 return sport->devdata->devtype == IMX6Q_UART;
354}
355/*
356 * Save and restore functions for UCR1, UCR2 and UCR3 registers
357 */
358#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
359static void imx_uart_ucrs_save(struct imx_port *sport,
360 struct imx_port_ucrs *ucr)
361{
362 /* save control registers */
363 ucr->ucr1 = imx_uart_readl(sport, UCR1);
364 ucr->ucr2 = imx_uart_readl(sport, UCR2);
365 ucr->ucr3 = imx_uart_readl(sport, UCR3);
366}
367
368static void imx_uart_ucrs_restore(struct imx_port *sport,
369 struct imx_port_ucrs *ucr)
370{
371 /* restore control registers */
372 imx_uart_writel(sport, ucr->ucr1, UCR1);
373 imx_uart_writel(sport, ucr->ucr2, UCR2);
374 imx_uart_writel(sport, ucr->ucr3, UCR3);
375}
376#endif
377
378/* called with port.lock taken and irqs caller dependent */
379static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
380{
381 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
382
383 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
384}
385
386/* called with port.lock taken and irqs caller dependent */
387static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
388{
389 *ucr2 &= ~UCR2_CTSC;
390 *ucr2 |= UCR2_CTS;
391
392 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
393}
394
395static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
396{
397 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
398}
399
400/* called with port.lock taken and irqs off */
401static void imx_uart_start_rx(struct uart_port *port)
402{
403 struct imx_port *sport = (struct imx_port *)port;
404 unsigned int ucr1, ucr2;
405
406 ucr1 = imx_uart_readl(sport, UCR1);
407 ucr2 = imx_uart_readl(sport, UCR2);
408
409 ucr2 |= UCR2_RXEN;
410
411 if (sport->dma_is_enabled) {
412 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
413 } else {
414 ucr1 |= UCR1_RRDYEN;
415 ucr2 |= UCR2_ATEN;
416 }
417
418 /* Write UCR2 first as it includes RXEN */
419 imx_uart_writel(sport, ucr2, UCR2);
420 imx_uart_writel(sport, ucr1, UCR1);
421}
422
423/* called with port.lock taken and irqs off */
424static void imx_uart_stop_tx(struct uart_port *port)
425{
426 struct imx_port *sport = (struct imx_port *)port;
427 u32 ucr1, ucr4, usr2;
428
429 if (sport->tx_state == OFF)
430 return;
431
432 /*
433 * We are maybe in the SMP context, so if the DMA TX thread is running
434 * on other cpu, we have to wait for it to finish.
435 */
436 if (sport->dma_is_txing)
437 return;
438
439 ucr1 = imx_uart_readl(sport, UCR1);
440 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
441
442 usr2 = imx_uart_readl(sport, USR2);
443 if (!(usr2 & USR2_TXDC)) {
444 /* The shifter is still busy, so retry once TC triggers */
445 return;
446 }
447
448 ucr4 = imx_uart_readl(sport, UCR4);
449 ucr4 &= ~UCR4_TCEN;
450 imx_uart_writel(sport, ucr4, UCR4);
451
452 /* in rs485 mode disable transmitter */
453 if (port->rs485.flags & SER_RS485_ENABLED) {
454 if (sport->tx_state == SEND) {
455 sport->tx_state = WAIT_AFTER_SEND;
456
457 if (port->rs485.delay_rts_after_send > 0) {
458 start_hrtimer_ms(&sport->trigger_stop_tx,
459 port->rs485.delay_rts_after_send);
460 return;
461 }
462
463 /* continue without any delay */
464 }
465
466 if (sport->tx_state == WAIT_AFTER_RTS ||
467 sport->tx_state == WAIT_AFTER_SEND) {
468 u32 ucr2;
469
470 hrtimer_try_to_cancel(&sport->trigger_start_tx);
471
472 ucr2 = imx_uart_readl(sport, UCR2);
473 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
474 imx_uart_rts_active(sport, &ucr2);
475 else
476 imx_uart_rts_inactive(sport, &ucr2);
477 imx_uart_writel(sport, ucr2, UCR2);
478
479 imx_uart_start_rx(port);
480
481 sport->tx_state = OFF;
482 }
483 } else {
484 sport->tx_state = OFF;
485 }
486}
487
488/* called with port.lock taken and irqs off */
489static void imx_uart_stop_rx(struct uart_port *port)
490{
491 struct imx_port *sport = (struct imx_port *)port;
492 u32 ucr1, ucr2, ucr4, uts;
493
494 ucr1 = imx_uart_readl(sport, UCR1);
495 ucr2 = imx_uart_readl(sport, UCR2);
496 ucr4 = imx_uart_readl(sport, UCR4);
497
498 if (sport->dma_is_enabled) {
499 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
500 } else {
501 ucr1 &= ~UCR1_RRDYEN;
502 ucr2 &= ~UCR2_ATEN;
503 ucr4 &= ~UCR4_OREN;
504 }
505 imx_uart_writel(sport, ucr1, UCR1);
506 imx_uart_writel(sport, ucr4, UCR4);
507
508 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
509 if (port->rs485.flags & SER_RS485_ENABLED &&
510 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
511 sport->have_rtscts && !sport->have_rtsgpio) {
512 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
513 uts |= UTS_LOOP;
514 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
515 ucr2 |= UCR2_RXEN;
516 } else {
517 ucr2 &= ~UCR2_RXEN;
518 }
519
520 imx_uart_writel(sport, ucr2, UCR2);
521}
522
523/* called with port.lock taken and irqs off */
524static void imx_uart_enable_ms(struct uart_port *port)
525{
526 struct imx_port *sport = (struct imx_port *)port;
527
528 mod_timer(&sport->timer, jiffies);
529
530 mctrl_gpio_enable_ms(sport->gpios);
531}
532
533static void imx_uart_dma_tx(struct imx_port *sport);
534
535/* called with port.lock taken and irqs off */
536static inline void imx_uart_transmit_buffer(struct imx_port *sport)
537{
538 struct circ_buf *xmit = &sport->port.state->xmit;
539
540 if (sport->port.x_char) {
541 /* Send next char */
542 imx_uart_writel(sport, sport->port.x_char, URTX0);
543 sport->port.icount.tx++;
544 sport->port.x_char = 0;
545 return;
546 }
547
548 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
549 imx_uart_stop_tx(&sport->port);
550 return;
551 }
552
553 if (sport->dma_is_enabled) {
554 u32 ucr1;
555 /*
556 * We've just sent a X-char Ensure the TX DMA is enabled
557 * and the TX IRQ is disabled.
558 **/
559 ucr1 = imx_uart_readl(sport, UCR1);
560 ucr1 &= ~UCR1_TRDYEN;
561 if (sport->dma_is_txing) {
562 ucr1 |= UCR1_TXDMAEN;
563 imx_uart_writel(sport, ucr1, UCR1);
564 } else {
565 imx_uart_writel(sport, ucr1, UCR1);
566 imx_uart_dma_tx(sport);
567 }
568
569 return;
570 }
571
572 while (!uart_circ_empty(xmit) &&
573 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
574 /* send xmit->buf[xmit->tail]
575 * out the port here */
576 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
577 uart_xmit_advance(&sport->port, 1);
578 }
579
580 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
581 uart_write_wakeup(&sport->port);
582
583 if (uart_circ_empty(xmit))
584 imx_uart_stop_tx(&sport->port);
585}
586
587static void imx_uart_dma_tx_callback(void *data)
588{
589 struct imx_port *sport = data;
590 struct scatterlist *sgl = &sport->tx_sgl[0];
591 struct circ_buf *xmit = &sport->port.state->xmit;
592 unsigned long flags;
593 u32 ucr1;
594
595 spin_lock_irqsave(&sport->port.lock, flags);
596
597 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
598
599 ucr1 = imx_uart_readl(sport, UCR1);
600 ucr1 &= ~UCR1_TXDMAEN;
601 imx_uart_writel(sport, ucr1, UCR1);
602
603 uart_xmit_advance(&sport->port, sport->tx_bytes);
604
605 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
606
607 sport->dma_is_txing = 0;
608
609 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
610 uart_write_wakeup(&sport->port);
611
612 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
613 imx_uart_dma_tx(sport);
614 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
615 u32 ucr4 = imx_uart_readl(sport, UCR4);
616 ucr4 |= UCR4_TCEN;
617 imx_uart_writel(sport, ucr4, UCR4);
618 }
619
620 spin_unlock_irqrestore(&sport->port.lock, flags);
621}
622
623/* called with port.lock taken and irqs off */
624static void imx_uart_dma_tx(struct imx_port *sport)
625{
626 struct circ_buf *xmit = &sport->port.state->xmit;
627 struct scatterlist *sgl = sport->tx_sgl;
628 struct dma_async_tx_descriptor *desc;
629 struct dma_chan *chan = sport->dma_chan_tx;
630 struct device *dev = sport->port.dev;
631 u32 ucr1, ucr4;
632 int ret;
633
634 if (sport->dma_is_txing)
635 return;
636
637 ucr4 = imx_uart_readl(sport, UCR4);
638 ucr4 &= ~UCR4_TCEN;
639 imx_uart_writel(sport, ucr4, UCR4);
640
641 sport->tx_bytes = uart_circ_chars_pending(xmit);
642
643 if (xmit->tail < xmit->head || xmit->head == 0) {
644 sport->dma_tx_nents = 1;
645 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
646 } else {
647 sport->dma_tx_nents = 2;
648 sg_init_table(sgl, 2);
649 sg_set_buf(sgl, xmit->buf + xmit->tail,
650 UART_XMIT_SIZE - xmit->tail);
651 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
652 }
653
654 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
655 if (ret == 0) {
656 dev_err(dev, "DMA mapping error for TX.\n");
657 return;
658 }
659 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
660 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
661 if (!desc) {
662 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
663 DMA_TO_DEVICE);
664 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
665 return;
666 }
667 desc->callback = imx_uart_dma_tx_callback;
668 desc->callback_param = sport;
669
670 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
671 uart_circ_chars_pending(xmit));
672
673 ucr1 = imx_uart_readl(sport, UCR1);
674 ucr1 |= UCR1_TXDMAEN;
675 imx_uart_writel(sport, ucr1, UCR1);
676
677 /* fire it */
678 sport->dma_is_txing = 1;
679 dmaengine_submit(desc);
680 dma_async_issue_pending(chan);
681 return;
682}
683
684/* called with port.lock taken and irqs off */
685static void imx_uart_start_tx(struct uart_port *port)
686{
687 struct imx_port *sport = (struct imx_port *)port;
688 u32 ucr1;
689
690 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
691 return;
692
693 /*
694 * We cannot simply do nothing here if sport->tx_state == SEND already
695 * because UCR1_TXMPTYEN might already have been cleared in
696 * imx_uart_stop_tx(), but tx_state is still SEND.
697 */
698
699 if (port->rs485.flags & SER_RS485_ENABLED) {
700 if (sport->tx_state == OFF) {
701 u32 ucr2 = imx_uart_readl(sport, UCR2);
702 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
703 imx_uart_rts_active(sport, &ucr2);
704 else
705 imx_uart_rts_inactive(sport, &ucr2);
706 imx_uart_writel(sport, ucr2, UCR2);
707
708 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
709 imx_uart_stop_rx(port);
710
711 sport->tx_state = WAIT_AFTER_RTS;
712
713 if (port->rs485.delay_rts_before_send > 0) {
714 start_hrtimer_ms(&sport->trigger_start_tx,
715 port->rs485.delay_rts_before_send);
716 return;
717 }
718
719 /* continue without any delay */
720 }
721
722 if (sport->tx_state == WAIT_AFTER_SEND
723 || sport->tx_state == WAIT_AFTER_RTS) {
724
725 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
726
727 /*
728 * Enable transmitter and shifter empty irq only if DMA
729 * is off. In the DMA case this is done in the
730 * tx-callback.
731 */
732 if (!sport->dma_is_enabled) {
733 u32 ucr4 = imx_uart_readl(sport, UCR4);
734 ucr4 |= UCR4_TCEN;
735 imx_uart_writel(sport, ucr4, UCR4);
736 }
737
738 sport->tx_state = SEND;
739 }
740 } else {
741 sport->tx_state = SEND;
742 }
743
744 if (!sport->dma_is_enabled) {
745 ucr1 = imx_uart_readl(sport, UCR1);
746 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
747 }
748
749 if (sport->dma_is_enabled) {
750 if (sport->port.x_char) {
751 /* We have X-char to send, so enable TX IRQ and
752 * disable TX DMA to let TX interrupt to send X-char */
753 ucr1 = imx_uart_readl(sport, UCR1);
754 ucr1 &= ~UCR1_TXDMAEN;
755 ucr1 |= UCR1_TRDYEN;
756 imx_uart_writel(sport, ucr1, UCR1);
757 return;
758 }
759
760 if (!uart_circ_empty(&port->state->xmit) &&
761 !uart_tx_stopped(port))
762 imx_uart_dma_tx(sport);
763 return;
764 }
765}
766
767static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
768{
769 struct imx_port *sport = dev_id;
770 u32 usr1;
771
772 imx_uart_writel(sport, USR1_RTSD, USR1);
773 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
774 uart_handle_cts_change(&sport->port, !!usr1);
775 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
776
777 return IRQ_HANDLED;
778}
779
780static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
781{
782 struct imx_port *sport = dev_id;
783 irqreturn_t ret;
784
785 spin_lock(&sport->port.lock);
786
787 ret = __imx_uart_rtsint(irq, dev_id);
788
789 spin_unlock(&sport->port.lock);
790
791 return ret;
792}
793
794static irqreturn_t imx_uart_txint(int irq, void *dev_id)
795{
796 struct imx_port *sport = dev_id;
797
798 spin_lock(&sport->port.lock);
799 imx_uart_transmit_buffer(sport);
800 spin_unlock(&sport->port.lock);
801 return IRQ_HANDLED;
802}
803
804static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
805{
806 struct imx_port *sport = dev_id;
807 unsigned int rx, flg, ignored = 0;
808 struct tty_port *port = &sport->port.state->port;
809
810 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
811 u32 usr2;
812
813 flg = TTY_NORMAL;
814 sport->port.icount.rx++;
815
816 rx = imx_uart_readl(sport, URXD0);
817
818 usr2 = imx_uart_readl(sport, USR2);
819 if (usr2 & USR2_BRCD) {
820 imx_uart_writel(sport, USR2_BRCD, USR2);
821 if (uart_handle_break(&sport->port))
822 continue;
823 }
824
825 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
826 continue;
827
828 if (unlikely(rx & URXD_ERR)) {
829 if (rx & URXD_BRK)
830 sport->port.icount.brk++;
831 else if (rx & URXD_PRERR)
832 sport->port.icount.parity++;
833 else if (rx & URXD_FRMERR)
834 sport->port.icount.frame++;
835 if (rx & URXD_OVRRUN)
836 sport->port.icount.overrun++;
837
838 if (rx & sport->port.ignore_status_mask) {
839 if (++ignored > 100)
840 goto out;
841 continue;
842 }
843
844 rx &= (sport->port.read_status_mask | 0xFF);
845
846 if (rx & URXD_BRK)
847 flg = TTY_BREAK;
848 else if (rx & URXD_PRERR)
849 flg = TTY_PARITY;
850 else if (rx & URXD_FRMERR)
851 flg = TTY_FRAME;
852 if (rx & URXD_OVRRUN)
853 flg = TTY_OVERRUN;
854
855 sport->port.sysrq = 0;
856 }
857
858 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
859 goto out;
860
861 if (tty_insert_flip_char(port, rx, flg) == 0)
862 sport->port.icount.buf_overrun++;
863 }
864
865out:
866 tty_flip_buffer_push(port);
867
868 return IRQ_HANDLED;
869}
870
871static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
872{
873 struct imx_port *sport = dev_id;
874 irqreturn_t ret;
875
876 spin_lock(&sport->port.lock);
877
878 ret = __imx_uart_rxint(irq, dev_id);
879
880 spin_unlock(&sport->port.lock);
881
882 return ret;
883}
884
885static void imx_uart_clear_rx_errors(struct imx_port *sport);
886
887/*
888 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
889 */
890static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
891{
892 unsigned int tmp = TIOCM_DSR;
893 unsigned usr1 = imx_uart_readl(sport, USR1);
894 unsigned usr2 = imx_uart_readl(sport, USR2);
895
896 if (usr1 & USR1_RTSS)
897 tmp |= TIOCM_CTS;
898
899 /* in DCE mode DCDIN is always 0 */
900 if (!(usr2 & USR2_DCDIN))
901 tmp |= TIOCM_CAR;
902
903 if (sport->dte_mode)
904 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
905 tmp |= TIOCM_RI;
906
907 return tmp;
908}
909
910/*
911 * Handle any change of modem status signal since we were last called.
912 */
913static void imx_uart_mctrl_check(struct imx_port *sport)
914{
915 unsigned int status, changed;
916
917 status = imx_uart_get_hwmctrl(sport);
918 changed = status ^ sport->old_status;
919
920 if (changed == 0)
921 return;
922
923 sport->old_status = status;
924
925 if (changed & TIOCM_RI && status & TIOCM_RI)
926 sport->port.icount.rng++;
927 if (changed & TIOCM_DSR)
928 sport->port.icount.dsr++;
929 if (changed & TIOCM_CAR)
930 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
931 if (changed & TIOCM_CTS)
932 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
933
934 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
935}
936
937static irqreturn_t imx_uart_int(int irq, void *dev_id)
938{
939 struct imx_port *sport = dev_id;
940 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
941 irqreturn_t ret = IRQ_NONE;
942
943 spin_lock(&sport->port.lock);
944
945 usr1 = imx_uart_readl(sport, USR1);
946 usr2 = imx_uart_readl(sport, USR2);
947 ucr1 = imx_uart_readl(sport, UCR1);
948 ucr2 = imx_uart_readl(sport, UCR2);
949 ucr3 = imx_uart_readl(sport, UCR3);
950 ucr4 = imx_uart_readl(sport, UCR4);
951
952 /*
953 * Even if a condition is true that can trigger an irq only handle it if
954 * the respective irq source is enabled. This prevents some undesired
955 * actions, for example if a character that sits in the RX FIFO and that
956 * should be fetched via DMA is tried to be fetched using PIO. Or the
957 * receiver is currently off and so reading from URXD0 results in an
958 * exception. So just mask the (raw) status bits for disabled irqs.
959 */
960 if ((ucr1 & UCR1_RRDYEN) == 0)
961 usr1 &= ~USR1_RRDY;
962 if ((ucr2 & UCR2_ATEN) == 0)
963 usr1 &= ~USR1_AGTIM;
964 if ((ucr1 & UCR1_TRDYEN) == 0)
965 usr1 &= ~USR1_TRDY;
966 if ((ucr4 & UCR4_TCEN) == 0)
967 usr2 &= ~USR2_TXDC;
968 if ((ucr3 & UCR3_DTRDEN) == 0)
969 usr1 &= ~USR1_DTRD;
970 if ((ucr1 & UCR1_RTSDEN) == 0)
971 usr1 &= ~USR1_RTSD;
972 if ((ucr3 & UCR3_AWAKEN) == 0)
973 usr1 &= ~USR1_AWAKE;
974 if ((ucr4 & UCR4_OREN) == 0)
975 usr2 &= ~USR2_ORE;
976
977 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
978 imx_uart_writel(sport, USR1_AGTIM, USR1);
979
980 __imx_uart_rxint(irq, dev_id);
981 ret = IRQ_HANDLED;
982 }
983
984 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
985 imx_uart_transmit_buffer(sport);
986 ret = IRQ_HANDLED;
987 }
988
989 if (usr1 & USR1_DTRD) {
990 imx_uart_writel(sport, USR1_DTRD, USR1);
991
992 imx_uart_mctrl_check(sport);
993
994 ret = IRQ_HANDLED;
995 }
996
997 if (usr1 & USR1_RTSD) {
998 __imx_uart_rtsint(irq, dev_id);
999 ret = IRQ_HANDLED;
1000 }
1001
1002 if (usr1 & USR1_AWAKE) {
1003 imx_uart_writel(sport, USR1_AWAKE, USR1);
1004 ret = IRQ_HANDLED;
1005 }
1006
1007 if (usr2 & USR2_ORE) {
1008 sport->port.icount.overrun++;
1009 imx_uart_writel(sport, USR2_ORE, USR2);
1010 ret = IRQ_HANDLED;
1011 }
1012
1013 spin_unlock(&sport->port.lock);
1014
1015 return ret;
1016}
1017
1018/*
1019 * Return TIOCSER_TEMT when transmitter is not busy.
1020 */
1021static unsigned int imx_uart_tx_empty(struct uart_port *port)
1022{
1023 struct imx_port *sport = (struct imx_port *)port;
1024 unsigned int ret;
1025
1026 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1027
1028 /* If the TX DMA is working, return 0. */
1029 if (sport->dma_is_txing)
1030 ret = 0;
1031
1032 return ret;
1033}
1034
1035/* called with port.lock taken and irqs off */
1036static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1037{
1038 struct imx_port *sport = (struct imx_port *)port;
1039 unsigned int ret = imx_uart_get_hwmctrl(sport);
1040
1041 mctrl_gpio_get(sport->gpios, &ret);
1042
1043 return ret;
1044}
1045
1046/* called with port.lock taken and irqs off */
1047static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1048{
1049 struct imx_port *sport = (struct imx_port *)port;
1050 u32 ucr3, uts;
1051
1052 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1053 u32 ucr2;
1054
1055 /*
1056 * Turn off autoRTS if RTS is lowered and restore autoRTS
1057 * setting if RTS is raised.
1058 */
1059 ucr2 = imx_uart_readl(sport, UCR2);
1060 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1061 if (mctrl & TIOCM_RTS) {
1062 ucr2 |= UCR2_CTS;
1063 /*
1064 * UCR2_IRTS is unset if and only if the port is
1065 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1066 * to get the state to restore to.
1067 */
1068 if (!(ucr2 & UCR2_IRTS))
1069 ucr2 |= UCR2_CTSC;
1070 }
1071 imx_uart_writel(sport, ucr2, UCR2);
1072 }
1073
1074 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1075 if (!(mctrl & TIOCM_DTR))
1076 ucr3 |= UCR3_DSR;
1077 imx_uart_writel(sport, ucr3, UCR3);
1078
1079 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1080 if (mctrl & TIOCM_LOOP)
1081 uts |= UTS_LOOP;
1082 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1083
1084 mctrl_gpio_set(sport->gpios, mctrl);
1085}
1086
1087/*
1088 * Interrupts always disabled.
1089 */
1090static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1091{
1092 struct imx_port *sport = (struct imx_port *)port;
1093 unsigned long flags;
1094 u32 ucr1;
1095
1096 spin_lock_irqsave(&sport->port.lock, flags);
1097
1098 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1099
1100 if (break_state != 0)
1101 ucr1 |= UCR1_SNDBRK;
1102
1103 imx_uart_writel(sport, ucr1, UCR1);
1104
1105 spin_unlock_irqrestore(&sport->port.lock, flags);
1106}
1107
1108/*
1109 * This is our per-port timeout handler, for checking the
1110 * modem status signals.
1111 */
1112static void imx_uart_timeout(struct timer_list *t)
1113{
1114 struct imx_port *sport = from_timer(sport, t, timer);
1115 unsigned long flags;
1116
1117 if (sport->port.state) {
1118 spin_lock_irqsave(&sport->port.lock, flags);
1119 imx_uart_mctrl_check(sport);
1120 spin_unlock_irqrestore(&sport->port.lock, flags);
1121
1122 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1123 }
1124}
1125
1126/*
1127 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1128 * [1] the RX DMA buffer is full.
1129 * [2] the aging timer expires
1130 *
1131 * Condition [2] is triggered when a character has been sitting in the FIFO
1132 * for at least 8 byte durations.
1133 */
1134static void imx_uart_dma_rx_callback(void *data)
1135{
1136 struct imx_port *sport = data;
1137 struct dma_chan *chan = sport->dma_chan_rx;
1138 struct scatterlist *sgl = &sport->rx_sgl;
1139 struct tty_port *port = &sport->port.state->port;
1140 struct dma_tx_state state;
1141 struct circ_buf *rx_ring = &sport->rx_ring;
1142 enum dma_status status;
1143 unsigned int w_bytes = 0;
1144 unsigned int r_bytes;
1145 unsigned int bd_size;
1146
1147 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1148
1149 if (status == DMA_ERROR) {
1150 imx_uart_clear_rx_errors(sport);
1151 return;
1152 }
1153
1154 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1155
1156 /*
1157 * The state-residue variable represents the empty space
1158 * relative to the entire buffer. Taking this in consideration
1159 * the head is always calculated base on the buffer total
1160 * length - DMA transaction residue. The UART script from the
1161 * SDMA firmware will jump to the next buffer descriptor,
1162 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1163 * Taking this in consideration the tail is always at the
1164 * beginning of the buffer descriptor that contains the head.
1165 */
1166
1167 /* Calculate the head */
1168 rx_ring->head = sg_dma_len(sgl) - state.residue;
1169
1170 /* Calculate the tail. */
1171 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1172 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1173
1174 if (rx_ring->head <= sg_dma_len(sgl) &&
1175 rx_ring->head > rx_ring->tail) {
1176
1177 /* Move data from tail to head */
1178 r_bytes = rx_ring->head - rx_ring->tail;
1179
1180 /* CPU claims ownership of RX DMA buffer */
1181 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1182 DMA_FROM_DEVICE);
1183
1184 w_bytes = tty_insert_flip_string(port,
1185 sport->rx_buf + rx_ring->tail, r_bytes);
1186
1187 /* UART retrieves ownership of RX DMA buffer */
1188 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1189 DMA_FROM_DEVICE);
1190
1191 if (w_bytes != r_bytes)
1192 sport->port.icount.buf_overrun++;
1193
1194 sport->port.icount.rx += w_bytes;
1195 } else {
1196 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1197 WARN_ON(rx_ring->head <= rx_ring->tail);
1198 }
1199 }
1200
1201 if (w_bytes) {
1202 tty_flip_buffer_push(port);
1203 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1204 }
1205}
1206
1207static int imx_uart_start_rx_dma(struct imx_port *sport)
1208{
1209 struct scatterlist *sgl = &sport->rx_sgl;
1210 struct dma_chan *chan = sport->dma_chan_rx;
1211 struct device *dev = sport->port.dev;
1212 struct dma_async_tx_descriptor *desc;
1213 int ret;
1214
1215 sport->rx_ring.head = 0;
1216 sport->rx_ring.tail = 0;
1217
1218 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1219 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1220 if (ret == 0) {
1221 dev_err(dev, "DMA mapping error for RX.\n");
1222 return -EINVAL;
1223 }
1224
1225 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1226 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1227 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1228
1229 if (!desc) {
1230 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1231 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1232 return -EINVAL;
1233 }
1234 desc->callback = imx_uart_dma_rx_callback;
1235 desc->callback_param = sport;
1236
1237 dev_dbg(dev, "RX: prepare for the DMA.\n");
1238 sport->dma_is_rxing = 1;
1239 sport->rx_cookie = dmaengine_submit(desc);
1240 dma_async_issue_pending(chan);
1241 return 0;
1242}
1243
1244static void imx_uart_clear_rx_errors(struct imx_port *sport)
1245{
1246 struct tty_port *port = &sport->port.state->port;
1247 u32 usr1, usr2;
1248
1249 usr1 = imx_uart_readl(sport, USR1);
1250 usr2 = imx_uart_readl(sport, USR2);
1251
1252 if (usr2 & USR2_BRCD) {
1253 sport->port.icount.brk++;
1254 imx_uart_writel(sport, USR2_BRCD, USR2);
1255 uart_handle_break(&sport->port);
1256 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1257 sport->port.icount.buf_overrun++;
1258 tty_flip_buffer_push(port);
1259 } else {
1260 if (usr1 & USR1_FRAMERR) {
1261 sport->port.icount.frame++;
1262 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1263 } else if (usr1 & USR1_PARITYERR) {
1264 sport->port.icount.parity++;
1265 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1266 }
1267 }
1268
1269 if (usr2 & USR2_ORE) {
1270 sport->port.icount.overrun++;
1271 imx_uart_writel(sport, USR2_ORE, USR2);
1272 }
1273
1274}
1275
1276#define TXTL_DEFAULT 2 /* reset default */
1277#define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1278#define TXTL_DMA 8 /* DMA burst setting */
1279#define RXTL_DMA 9 /* DMA burst setting */
1280
1281static void imx_uart_setup_ufcr(struct imx_port *sport,
1282 unsigned char txwl, unsigned char rxwl)
1283{
1284 unsigned int val;
1285
1286 /* set receiver / transmitter trigger level */
1287 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1288 val |= txwl << UFCR_TXTL_SHF | rxwl;
1289 imx_uart_writel(sport, val, UFCR);
1290}
1291
1292static void imx_uart_dma_exit(struct imx_port *sport)
1293{
1294 if (sport->dma_chan_rx) {
1295 dmaengine_terminate_sync(sport->dma_chan_rx);
1296 dma_release_channel(sport->dma_chan_rx);
1297 sport->dma_chan_rx = NULL;
1298 sport->rx_cookie = -EINVAL;
1299 kfree(sport->rx_buf);
1300 sport->rx_buf = NULL;
1301 }
1302
1303 if (sport->dma_chan_tx) {
1304 dmaengine_terminate_sync(sport->dma_chan_tx);
1305 dma_release_channel(sport->dma_chan_tx);
1306 sport->dma_chan_tx = NULL;
1307 }
1308}
1309
1310static int imx_uart_dma_init(struct imx_port *sport)
1311{
1312 struct dma_slave_config slave_config = {};
1313 struct device *dev = sport->port.dev;
1314 int ret;
1315
1316 /* Prepare for RX : */
1317 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1318 if (!sport->dma_chan_rx) {
1319 dev_dbg(dev, "cannot get the DMA channel.\n");
1320 ret = -EINVAL;
1321 goto err;
1322 }
1323
1324 slave_config.direction = DMA_DEV_TO_MEM;
1325 slave_config.src_addr = sport->port.mapbase + URXD0;
1326 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1327 /* one byte less than the watermark level to enable the aging timer */
1328 slave_config.src_maxburst = RXTL_DMA - 1;
1329 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1330 if (ret) {
1331 dev_err(dev, "error in RX dma configuration.\n");
1332 goto err;
1333 }
1334
1335 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1336 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1337 if (!sport->rx_buf) {
1338 ret = -ENOMEM;
1339 goto err;
1340 }
1341 sport->rx_ring.buf = sport->rx_buf;
1342
1343 /* Prepare for TX : */
1344 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1345 if (!sport->dma_chan_tx) {
1346 dev_err(dev, "cannot get the TX DMA channel!\n");
1347 ret = -EINVAL;
1348 goto err;
1349 }
1350
1351 slave_config.direction = DMA_MEM_TO_DEV;
1352 slave_config.dst_addr = sport->port.mapbase + URTX0;
1353 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1354 slave_config.dst_maxburst = TXTL_DMA;
1355 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1356 if (ret) {
1357 dev_err(dev, "error in TX dma configuration.");
1358 goto err;
1359 }
1360
1361 return 0;
1362err:
1363 imx_uart_dma_exit(sport);
1364 return ret;
1365}
1366
1367static void imx_uart_enable_dma(struct imx_port *sport)
1368{
1369 u32 ucr1;
1370
1371 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1372
1373 /* set UCR1 */
1374 ucr1 = imx_uart_readl(sport, UCR1);
1375 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1376 imx_uart_writel(sport, ucr1, UCR1);
1377
1378 sport->dma_is_enabled = 1;
1379}
1380
1381static void imx_uart_disable_dma(struct imx_port *sport)
1382{
1383 u32 ucr1;
1384
1385 /* clear UCR1 */
1386 ucr1 = imx_uart_readl(sport, UCR1);
1387 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1388 imx_uart_writel(sport, ucr1, UCR1);
1389
1390 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1391
1392 sport->dma_is_enabled = 0;
1393}
1394
1395/* half the RX buffer size */
1396#define CTSTL 16
1397
1398static int imx_uart_startup(struct uart_port *port)
1399{
1400 struct imx_port *sport = (struct imx_port *)port;
1401 int retval, i;
1402 unsigned long flags;
1403 int dma_is_inited = 0;
1404 u32 ucr1, ucr2, ucr3, ucr4, uts;
1405
1406 retval = clk_prepare_enable(sport->clk_per);
1407 if (retval)
1408 return retval;
1409 retval = clk_prepare_enable(sport->clk_ipg);
1410 if (retval) {
1411 clk_disable_unprepare(sport->clk_per);
1412 return retval;
1413 }
1414
1415 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1416
1417 /* disable the DREN bit (Data Ready interrupt enable) before
1418 * requesting IRQs
1419 */
1420 ucr4 = imx_uart_readl(sport, UCR4);
1421
1422 /* set the trigger level for CTS */
1423 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1424 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1425
1426 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1427
1428 /* Can we enable the DMA support? */
1429 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1430 dma_is_inited = 1;
1431
1432 spin_lock_irqsave(&sport->port.lock, flags);
1433 /* Reset fifo's and state machines */
1434 i = 100;
1435
1436 ucr2 = imx_uart_readl(sport, UCR2);
1437 ucr2 &= ~UCR2_SRST;
1438 imx_uart_writel(sport, ucr2, UCR2);
1439
1440 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1441 udelay(1);
1442
1443 /*
1444 * Finally, clear and enable interrupts
1445 */
1446 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1447 imx_uart_writel(sport, USR2_ORE, USR2);
1448
1449 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1450 ucr1 |= UCR1_UARTEN;
1451 if (sport->have_rtscts)
1452 ucr1 |= UCR1_RTSDEN;
1453
1454 imx_uart_writel(sport, ucr1, UCR1);
1455
1456 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1457 if (!dma_is_inited)
1458 ucr4 |= UCR4_OREN;
1459 if (sport->inverted_rx)
1460 ucr4 |= UCR4_INVR;
1461 imx_uart_writel(sport, ucr4, UCR4);
1462
1463 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1464 /*
1465 * configure tx polarity before enabling tx
1466 */
1467 if (sport->inverted_tx)
1468 ucr3 |= UCR3_INVT;
1469
1470 if (!imx_uart_is_imx1(sport)) {
1471 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1472
1473 if (sport->dte_mode)
1474 /* disable broken interrupts */
1475 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1476 }
1477 imx_uart_writel(sport, ucr3, UCR3);
1478
1479 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1480 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1481 if (!sport->have_rtscts)
1482 ucr2 |= UCR2_IRTS;
1483 /*
1484 * make sure the edge sensitive RTS-irq is disabled,
1485 * we're using RTSD instead.
1486 */
1487 if (!imx_uart_is_imx1(sport))
1488 ucr2 &= ~UCR2_RTSEN;
1489 imx_uart_writel(sport, ucr2, UCR2);
1490
1491 /*
1492 * Enable modem status interrupts
1493 */
1494 imx_uart_enable_ms(&sport->port);
1495
1496 if (dma_is_inited) {
1497 imx_uart_enable_dma(sport);
1498 imx_uart_start_rx_dma(sport);
1499 } else {
1500 ucr1 = imx_uart_readl(sport, UCR1);
1501 ucr1 |= UCR1_RRDYEN;
1502 imx_uart_writel(sport, ucr1, UCR1);
1503
1504 ucr2 = imx_uart_readl(sport, UCR2);
1505 ucr2 |= UCR2_ATEN;
1506 imx_uart_writel(sport, ucr2, UCR2);
1507 }
1508
1509 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1510 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1511 uts &= ~UTS_LOOP;
1512 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1513
1514 spin_unlock_irqrestore(&sport->port.lock, flags);
1515
1516 return 0;
1517}
1518
1519static void imx_uart_shutdown(struct uart_port *port)
1520{
1521 struct imx_port *sport = (struct imx_port *)port;
1522 unsigned long flags;
1523 u32 ucr1, ucr2, ucr4, uts;
1524
1525 if (sport->dma_is_enabled) {
1526 dmaengine_terminate_sync(sport->dma_chan_tx);
1527 if (sport->dma_is_txing) {
1528 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1529 sport->dma_tx_nents, DMA_TO_DEVICE);
1530 sport->dma_is_txing = 0;
1531 }
1532 dmaengine_terminate_sync(sport->dma_chan_rx);
1533 if (sport->dma_is_rxing) {
1534 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1535 1, DMA_FROM_DEVICE);
1536 sport->dma_is_rxing = 0;
1537 }
1538
1539 spin_lock_irqsave(&sport->port.lock, flags);
1540 imx_uart_stop_tx(port);
1541 imx_uart_stop_rx(port);
1542 imx_uart_disable_dma(sport);
1543 spin_unlock_irqrestore(&sport->port.lock, flags);
1544 imx_uart_dma_exit(sport);
1545 }
1546
1547 mctrl_gpio_disable_ms(sport->gpios);
1548
1549 spin_lock_irqsave(&sport->port.lock, flags);
1550 ucr2 = imx_uart_readl(sport, UCR2);
1551 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1552 imx_uart_writel(sport, ucr2, UCR2);
1553 spin_unlock_irqrestore(&sport->port.lock, flags);
1554
1555 /*
1556 * Stop our timer.
1557 */
1558 del_timer_sync(&sport->timer);
1559
1560 /*
1561 * Disable all interrupts, port and break condition.
1562 */
1563
1564 spin_lock_irqsave(&sport->port.lock, flags);
1565
1566 ucr1 = imx_uart_readl(sport, UCR1);
1567 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1568 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1569 if (port->rs485.flags & SER_RS485_ENABLED &&
1570 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1571 sport->have_rtscts && !sport->have_rtsgpio) {
1572 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1573 uts |= UTS_LOOP;
1574 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1575 ucr1 |= UCR1_UARTEN;
1576 } else {
1577 ucr1 &= ~UCR1_UARTEN;
1578 }
1579 imx_uart_writel(sport, ucr1, UCR1);
1580
1581 ucr4 = imx_uart_readl(sport, UCR4);
1582 ucr4 &= ~UCR4_TCEN;
1583 imx_uart_writel(sport, ucr4, UCR4);
1584
1585 spin_unlock_irqrestore(&sport->port.lock, flags);
1586
1587 clk_disable_unprepare(sport->clk_per);
1588 clk_disable_unprepare(sport->clk_ipg);
1589}
1590
1591/* called with port.lock taken and irqs off */
1592static void imx_uart_flush_buffer(struct uart_port *port)
1593{
1594 struct imx_port *sport = (struct imx_port *)port;
1595 struct scatterlist *sgl = &sport->tx_sgl[0];
1596 u32 ucr2;
1597 int i = 100, ubir, ubmr, uts;
1598
1599 if (!sport->dma_chan_tx)
1600 return;
1601
1602 sport->tx_bytes = 0;
1603 dmaengine_terminate_all(sport->dma_chan_tx);
1604 if (sport->dma_is_txing) {
1605 u32 ucr1;
1606
1607 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1608 DMA_TO_DEVICE);
1609 ucr1 = imx_uart_readl(sport, UCR1);
1610 ucr1 &= ~UCR1_TXDMAEN;
1611 imx_uart_writel(sport, ucr1, UCR1);
1612 sport->dma_is_txing = 0;
1613 }
1614
1615 /*
1616 * According to the Reference Manual description of the UART SRST bit:
1617 *
1618 * "Reset the transmit and receive state machines,
1619 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1620 * and UTS[6-3]".
1621 *
1622 * We don't need to restore the old values from USR1, USR2, URXD and
1623 * UTXD. UBRC is read only, so only save/restore the other three
1624 * registers.
1625 */
1626 ubir = imx_uart_readl(sport, UBIR);
1627 ubmr = imx_uart_readl(sport, UBMR);
1628 uts = imx_uart_readl(sport, IMX21_UTS);
1629
1630 ucr2 = imx_uart_readl(sport, UCR2);
1631 ucr2 &= ~UCR2_SRST;
1632 imx_uart_writel(sport, ucr2, UCR2);
1633
1634 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1635 udelay(1);
1636
1637 /* Restore the registers */
1638 imx_uart_writel(sport, ubir, UBIR);
1639 imx_uart_writel(sport, ubmr, UBMR);
1640 imx_uart_writel(sport, uts, IMX21_UTS);
1641}
1642
1643static void
1644imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1645 const struct ktermios *old)
1646{
1647 struct imx_port *sport = (struct imx_port *)port;
1648 unsigned long flags;
1649 u32 ucr2, old_ucr2, ufcr;
1650 unsigned int baud, quot;
1651 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1652 unsigned long div;
1653 unsigned long num, denom, old_ubir, old_ubmr;
1654 uint64_t tdiv64;
1655
1656 /*
1657 * We only support CS7 and CS8.
1658 */
1659 while ((termios->c_cflag & CSIZE) != CS7 &&
1660 (termios->c_cflag & CSIZE) != CS8) {
1661 termios->c_cflag &= ~CSIZE;
1662 termios->c_cflag |= old_csize;
1663 old_csize = CS8;
1664 }
1665
1666 del_timer_sync(&sport->timer);
1667
1668 /*
1669 * Ask the core to calculate the divisor for us.
1670 */
1671 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1672 quot = uart_get_divisor(port, baud);
1673
1674 spin_lock_irqsave(&sport->port.lock, flags);
1675
1676 /*
1677 * Read current UCR2 and save it for future use, then clear all the bits
1678 * except those we will or may need to preserve.
1679 */
1680 old_ucr2 = imx_uart_readl(sport, UCR2);
1681 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1682
1683 ucr2 |= UCR2_SRST | UCR2_IRTS;
1684 if ((termios->c_cflag & CSIZE) == CS8)
1685 ucr2 |= UCR2_WS;
1686
1687 if (!sport->have_rtscts)
1688 termios->c_cflag &= ~CRTSCTS;
1689
1690 if (port->rs485.flags & SER_RS485_ENABLED) {
1691 /*
1692 * RTS is mandatory for rs485 operation, so keep
1693 * it under manual control and keep transmitter
1694 * disabled.
1695 */
1696 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1697 imx_uart_rts_active(sport, &ucr2);
1698 else
1699 imx_uart_rts_inactive(sport, &ucr2);
1700
1701 } else if (termios->c_cflag & CRTSCTS) {
1702 /*
1703 * Only let receiver control RTS output if we were not requested
1704 * to have RTS inactive (which then should take precedence).
1705 */
1706 if (ucr2 & UCR2_CTS)
1707 ucr2 |= UCR2_CTSC;
1708 }
1709
1710 if (termios->c_cflag & CRTSCTS)
1711 ucr2 &= ~UCR2_IRTS;
1712 if (termios->c_cflag & CSTOPB)
1713 ucr2 |= UCR2_STPB;
1714 if (termios->c_cflag & PARENB) {
1715 ucr2 |= UCR2_PREN;
1716 if (termios->c_cflag & PARODD)
1717 ucr2 |= UCR2_PROE;
1718 }
1719
1720 sport->port.read_status_mask = 0;
1721 if (termios->c_iflag & INPCK)
1722 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1723 if (termios->c_iflag & (BRKINT | PARMRK))
1724 sport->port.read_status_mask |= URXD_BRK;
1725
1726 /*
1727 * Characters to ignore
1728 */
1729 sport->port.ignore_status_mask = 0;
1730 if (termios->c_iflag & IGNPAR)
1731 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1732 if (termios->c_iflag & IGNBRK) {
1733 sport->port.ignore_status_mask |= URXD_BRK;
1734 /*
1735 * If we're ignoring parity and break indicators,
1736 * ignore overruns too (for real raw support).
1737 */
1738 if (termios->c_iflag & IGNPAR)
1739 sport->port.ignore_status_mask |= URXD_OVRRUN;
1740 }
1741
1742 if ((termios->c_cflag & CREAD) == 0)
1743 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1744
1745 /*
1746 * Update the per-port timeout.
1747 */
1748 uart_update_timeout(port, termios->c_cflag, baud);
1749
1750 /* custom-baudrate handling */
1751 div = sport->port.uartclk / (baud * 16);
1752 if (baud == 38400 && quot != div)
1753 baud = sport->port.uartclk / (quot * 16);
1754
1755 div = sport->port.uartclk / (baud * 16);
1756 if (div > 7)
1757 div = 7;
1758 if (!div)
1759 div = 1;
1760
1761 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1762 1 << 16, 1 << 16, &num, &denom);
1763
1764 tdiv64 = sport->port.uartclk;
1765 tdiv64 *= num;
1766 do_div(tdiv64, denom * 16 * div);
1767 tty_termios_encode_baud_rate(termios,
1768 (speed_t)tdiv64, (speed_t)tdiv64);
1769
1770 num -= 1;
1771 denom -= 1;
1772
1773 ufcr = imx_uart_readl(sport, UFCR);
1774 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1775 imx_uart_writel(sport, ufcr, UFCR);
1776
1777 /*
1778 * Two registers below should always be written both and in this
1779 * particular order. One consequence is that we need to check if any of
1780 * them changes and then update both. We do need the check for change
1781 * as even writing the same values seem to "restart"
1782 * transmission/receiving logic in the hardware, that leads to data
1783 * breakage even when rate doesn't in fact change. E.g., user switches
1784 * RTS/CTS handshake and suddenly gets broken bytes.
1785 */
1786 old_ubir = imx_uart_readl(sport, UBIR);
1787 old_ubmr = imx_uart_readl(sport, UBMR);
1788 if (old_ubir != num || old_ubmr != denom) {
1789 imx_uart_writel(sport, num, UBIR);
1790 imx_uart_writel(sport, denom, UBMR);
1791 }
1792
1793 if (!imx_uart_is_imx1(sport))
1794 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1795 IMX21_ONEMS);
1796
1797 imx_uart_writel(sport, ucr2, UCR2);
1798
1799 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1800 imx_uart_enable_ms(&sport->port);
1801
1802 spin_unlock_irqrestore(&sport->port.lock, flags);
1803}
1804
1805static const char *imx_uart_type(struct uart_port *port)
1806{
1807 struct imx_port *sport = (struct imx_port *)port;
1808
1809 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1810}
1811
1812/*
1813 * Configure/autoconfigure the port.
1814 */
1815static void imx_uart_config_port(struct uart_port *port, int flags)
1816{
1817 struct imx_port *sport = (struct imx_port *)port;
1818
1819 if (flags & UART_CONFIG_TYPE)
1820 sport->port.type = PORT_IMX;
1821}
1822
1823/*
1824 * Verify the new serial_struct (for TIOCSSERIAL).
1825 * The only change we allow are to the flags and type, and
1826 * even then only between PORT_IMX and PORT_UNKNOWN
1827 */
1828static int
1829imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1830{
1831 struct imx_port *sport = (struct imx_port *)port;
1832 int ret = 0;
1833
1834 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1835 ret = -EINVAL;
1836 if (sport->port.irq != ser->irq)
1837 ret = -EINVAL;
1838 if (ser->io_type != UPIO_MEM)
1839 ret = -EINVAL;
1840 if (sport->port.uartclk / 16 != ser->baud_base)
1841 ret = -EINVAL;
1842 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1843 ret = -EINVAL;
1844 if (sport->port.iobase != ser->port)
1845 ret = -EINVAL;
1846 if (ser->hub6 != 0)
1847 ret = -EINVAL;
1848 return ret;
1849}
1850
1851#if defined(CONFIG_CONSOLE_POLL)
1852
1853static int imx_uart_poll_init(struct uart_port *port)
1854{
1855 struct imx_port *sport = (struct imx_port *)port;
1856 unsigned long flags;
1857 u32 ucr1, ucr2;
1858 int retval;
1859
1860 retval = clk_prepare_enable(sport->clk_ipg);
1861 if (retval)
1862 return retval;
1863 retval = clk_prepare_enable(sport->clk_per);
1864 if (retval)
1865 clk_disable_unprepare(sport->clk_ipg);
1866
1867 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1868
1869 spin_lock_irqsave(&sport->port.lock, flags);
1870
1871 /*
1872 * Be careful about the order of enabling bits here. First enable the
1873 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1874 * This prevents that a character that already sits in the RX fifo is
1875 * triggering an irq but the try to fetch it from there results in an
1876 * exception because UARTEN or RXEN is still off.
1877 */
1878 ucr1 = imx_uart_readl(sport, UCR1);
1879 ucr2 = imx_uart_readl(sport, UCR2);
1880
1881 if (imx_uart_is_imx1(sport))
1882 ucr1 |= IMX1_UCR1_UARTCLKEN;
1883
1884 ucr1 |= UCR1_UARTEN;
1885 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1886
1887 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1888 ucr2 &= ~UCR2_ATEN;
1889
1890 imx_uart_writel(sport, ucr1, UCR1);
1891 imx_uart_writel(sport, ucr2, UCR2);
1892
1893 /* now enable irqs */
1894 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1895 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1896
1897 spin_unlock_irqrestore(&sport->port.lock, flags);
1898
1899 return 0;
1900}
1901
1902static int imx_uart_poll_get_char(struct uart_port *port)
1903{
1904 struct imx_port *sport = (struct imx_port *)port;
1905 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1906 return NO_POLL_CHAR;
1907
1908 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1909}
1910
1911static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1912{
1913 struct imx_port *sport = (struct imx_port *)port;
1914 unsigned int status;
1915
1916 /* drain */
1917 do {
1918 status = imx_uart_readl(sport, USR1);
1919 } while (~status & USR1_TRDY);
1920
1921 /* write */
1922 imx_uart_writel(sport, c, URTX0);
1923
1924 /* flush */
1925 do {
1926 status = imx_uart_readl(sport, USR2);
1927 } while (~status & USR2_TXDC);
1928}
1929#endif
1930
1931/* called with port.lock taken and irqs off or from .probe without locking */
1932static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
1933 struct serial_rs485 *rs485conf)
1934{
1935 struct imx_port *sport = (struct imx_port *)port;
1936 u32 ucr2;
1937
1938 if (rs485conf->flags & SER_RS485_ENABLED) {
1939 /* Enable receiver if low-active RTS signal is requested */
1940 if (sport->have_rtscts && !sport->have_rtsgpio &&
1941 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1942 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1943
1944 /* disable transmitter */
1945 ucr2 = imx_uart_readl(sport, UCR2);
1946 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1947 imx_uart_rts_active(sport, &ucr2);
1948 else
1949 imx_uart_rts_inactive(sport, &ucr2);
1950 imx_uart_writel(sport, ucr2, UCR2);
1951 }
1952
1953 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1954 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1955 rs485conf->flags & SER_RS485_RX_DURING_TX)
1956 imx_uart_start_rx(port);
1957
1958 return 0;
1959}
1960
1961static const struct uart_ops imx_uart_pops = {
1962 .tx_empty = imx_uart_tx_empty,
1963 .set_mctrl = imx_uart_set_mctrl,
1964 .get_mctrl = imx_uart_get_mctrl,
1965 .stop_tx = imx_uart_stop_tx,
1966 .start_tx = imx_uart_start_tx,
1967 .stop_rx = imx_uart_stop_rx,
1968 .enable_ms = imx_uart_enable_ms,
1969 .break_ctl = imx_uart_break_ctl,
1970 .startup = imx_uart_startup,
1971 .shutdown = imx_uart_shutdown,
1972 .flush_buffer = imx_uart_flush_buffer,
1973 .set_termios = imx_uart_set_termios,
1974 .type = imx_uart_type,
1975 .config_port = imx_uart_config_port,
1976 .verify_port = imx_uart_verify_port,
1977#if defined(CONFIG_CONSOLE_POLL)
1978 .poll_init = imx_uart_poll_init,
1979 .poll_get_char = imx_uart_poll_get_char,
1980 .poll_put_char = imx_uart_poll_put_char,
1981#endif
1982};
1983
1984static struct imx_port *imx_uart_ports[UART_NR];
1985
1986#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
1987static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
1988{
1989 struct imx_port *sport = (struct imx_port *)port;
1990
1991 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1992 barrier();
1993
1994 imx_uart_writel(sport, ch, URTX0);
1995}
1996
1997/*
1998 * Interrupts are disabled on entering
1999 */
2000static void
2001imx_uart_console_write(struct console *co, const char *s, unsigned int count)
2002{
2003 struct imx_port *sport = imx_uart_ports[co->index];
2004 struct imx_port_ucrs old_ucr;
2005 unsigned long flags;
2006 unsigned int ucr1;
2007 int locked = 1;
2008
2009 if (sport->port.sysrq)
2010 locked = 0;
2011 else if (oops_in_progress)
2012 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2013 else
2014 spin_lock_irqsave(&sport->port.lock, flags);
2015
2016 /*
2017 * First, save UCR1/2/3 and then disable interrupts
2018 */
2019 imx_uart_ucrs_save(sport, &old_ucr);
2020 ucr1 = old_ucr.ucr1;
2021
2022 if (imx_uart_is_imx1(sport))
2023 ucr1 |= IMX1_UCR1_UARTCLKEN;
2024 ucr1 |= UCR1_UARTEN;
2025 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2026
2027 imx_uart_writel(sport, ucr1, UCR1);
2028
2029 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2030
2031 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2032
2033 /*
2034 * Finally, wait for transmitter to become empty
2035 * and restore UCR1/2/3
2036 */
2037 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
2038
2039 imx_uart_ucrs_restore(sport, &old_ucr);
2040
2041 if (locked)
2042 spin_unlock_irqrestore(&sport->port.lock, flags);
2043}
2044
2045/*
2046 * If the port was already initialised (eg, by a boot loader),
2047 * try to determine the current setup.
2048 */
2049static void
2050imx_uart_console_get_options(struct imx_port *sport, int *baud,
2051 int *parity, int *bits)
2052{
2053
2054 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2055 /* ok, the port was enabled */
2056 unsigned int ucr2, ubir, ubmr, uartclk;
2057 unsigned int baud_raw;
2058 unsigned int ucfr_rfdiv;
2059
2060 ucr2 = imx_uart_readl(sport, UCR2);
2061
2062 *parity = 'n';
2063 if (ucr2 & UCR2_PREN) {
2064 if (ucr2 & UCR2_PROE)
2065 *parity = 'o';
2066 else
2067 *parity = 'e';
2068 }
2069
2070 if (ucr2 & UCR2_WS)
2071 *bits = 8;
2072 else
2073 *bits = 7;
2074
2075 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2076 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2077
2078 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2079 if (ucfr_rfdiv == 6)
2080 ucfr_rfdiv = 7;
2081 else
2082 ucfr_rfdiv = 6 - ucfr_rfdiv;
2083
2084 uartclk = clk_get_rate(sport->clk_per);
2085 uartclk /= ucfr_rfdiv;
2086
2087 { /*
2088 * The next code provides exact computation of
2089 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2090 * without need of float support or long long division,
2091 * which would be required to prevent 32bit arithmetic overflow
2092 */
2093 unsigned int mul = ubir + 1;
2094 unsigned int div = 16 * (ubmr + 1);
2095 unsigned int rem = uartclk % div;
2096
2097 baud_raw = (uartclk / div) * mul;
2098 baud_raw += (rem * mul + div / 2) / div;
2099 *baud = (baud_raw + 50) / 100 * 100;
2100 }
2101
2102 if (*baud != baud_raw)
2103 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2104 baud_raw, *baud);
2105 }
2106}
2107
2108static int
2109imx_uart_console_setup(struct console *co, char *options)
2110{
2111 struct imx_port *sport;
2112 int baud = 9600;
2113 int bits = 8;
2114 int parity = 'n';
2115 int flow = 'n';
2116 int retval;
2117
2118 /*
2119 * Check whether an invalid uart number has been specified, and
2120 * if so, search for the first available port that does have
2121 * console support.
2122 */
2123 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2124 co->index = 0;
2125 sport = imx_uart_ports[co->index];
2126 if (sport == NULL)
2127 return -ENODEV;
2128
2129 /* For setting the registers, we only need to enable the ipg clock. */
2130 retval = clk_prepare_enable(sport->clk_ipg);
2131 if (retval)
2132 goto error_console;
2133
2134 if (options)
2135 uart_parse_options(options, &baud, &parity, &bits, &flow);
2136 else
2137 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2138
2139 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2140
2141 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2142
2143 if (retval) {
2144 clk_disable_unprepare(sport->clk_ipg);
2145 goto error_console;
2146 }
2147
2148 retval = clk_prepare_enable(sport->clk_per);
2149 if (retval)
2150 clk_disable_unprepare(sport->clk_ipg);
2151
2152error_console:
2153 return retval;
2154}
2155
2156static int
2157imx_uart_console_exit(struct console *co)
2158{
2159 struct imx_port *sport = imx_uart_ports[co->index];
2160
2161 clk_disable_unprepare(sport->clk_per);
2162 clk_disable_unprepare(sport->clk_ipg);
2163
2164 return 0;
2165}
2166
2167static struct uart_driver imx_uart_uart_driver;
2168static struct console imx_uart_console = {
2169 .name = DEV_NAME,
2170 .write = imx_uart_console_write,
2171 .device = uart_console_device,
2172 .setup = imx_uart_console_setup,
2173 .exit = imx_uart_console_exit,
2174 .flags = CON_PRINTBUFFER,
2175 .index = -1,
2176 .data = &imx_uart_uart_driver,
2177};
2178
2179#define IMX_CONSOLE &imx_uart_console
2180
2181#else
2182#define IMX_CONSOLE NULL
2183#endif
2184
2185static struct uart_driver imx_uart_uart_driver = {
2186 .owner = THIS_MODULE,
2187 .driver_name = DRIVER_NAME,
2188 .dev_name = DEV_NAME,
2189 .major = SERIAL_IMX_MAJOR,
2190 .minor = MINOR_START,
2191 .nr = ARRAY_SIZE(imx_uart_ports),
2192 .cons = IMX_CONSOLE,
2193};
2194
2195static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2196{
2197 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2198 unsigned long flags;
2199
2200 spin_lock_irqsave(&sport->port.lock, flags);
2201 if (sport->tx_state == WAIT_AFTER_RTS)
2202 imx_uart_start_tx(&sport->port);
2203 spin_unlock_irqrestore(&sport->port.lock, flags);
2204
2205 return HRTIMER_NORESTART;
2206}
2207
2208static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2209{
2210 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2211 unsigned long flags;
2212
2213 spin_lock_irqsave(&sport->port.lock, flags);
2214 if (sport->tx_state == WAIT_AFTER_SEND)
2215 imx_uart_stop_tx(&sport->port);
2216 spin_unlock_irqrestore(&sport->port.lock, flags);
2217
2218 return HRTIMER_NORESTART;
2219}
2220
2221static const struct serial_rs485 imx_no_rs485 = {}; /* No RS485 if no RTS */
2222static const struct serial_rs485 imx_rs485_supported = {
2223 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2224 SER_RS485_RX_DURING_TX,
2225 .delay_rts_before_send = 1,
2226 .delay_rts_after_send = 1,
2227};
2228
2229/* Default RX DMA buffer configuration */
2230#define RX_DMA_PERIODS 16
2231#define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2232
2233static int imx_uart_probe(struct platform_device *pdev)
2234{
2235 struct device_node *np = pdev->dev.of_node;
2236 struct imx_port *sport;
2237 void __iomem *base;
2238 u32 dma_buf_conf[2];
2239 int ret = 0;
2240 u32 ucr1, ucr2, uts;
2241 struct resource *res;
2242 int txirq, rxirq, rtsirq;
2243
2244 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2245 if (!sport)
2246 return -ENOMEM;
2247
2248 sport->devdata = of_device_get_match_data(&pdev->dev);
2249
2250 ret = of_alias_get_id(np, "serial");
2251 if (ret < 0) {
2252 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2253 return ret;
2254 }
2255 sport->port.line = ret;
2256
2257 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2258 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2259 sport->have_rtscts = 1;
2260
2261 if (of_get_property(np, "fsl,dte-mode", NULL))
2262 sport->dte_mode = 1;
2263
2264 if (of_get_property(np, "rts-gpios", NULL))
2265 sport->have_rtsgpio = 1;
2266
2267 if (of_get_property(np, "fsl,inverted-tx", NULL))
2268 sport->inverted_tx = 1;
2269
2270 if (of_get_property(np, "fsl,inverted-rx", NULL))
2271 sport->inverted_rx = 1;
2272
2273 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2274 sport->rx_period_length = dma_buf_conf[0];
2275 sport->rx_periods = dma_buf_conf[1];
2276 } else {
2277 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2278 sport->rx_periods = RX_DMA_PERIODS;
2279 }
2280
2281 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2282 dev_err(&pdev->dev, "serial%d out of range\n",
2283 sport->port.line);
2284 return -EINVAL;
2285 }
2286
2287 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2288 base = devm_ioremap_resource(&pdev->dev, res);
2289 if (IS_ERR(base))
2290 return PTR_ERR(base);
2291
2292 rxirq = platform_get_irq(pdev, 0);
2293 if (rxirq < 0)
2294 return rxirq;
2295 txirq = platform_get_irq_optional(pdev, 1);
2296 rtsirq = platform_get_irq_optional(pdev, 2);
2297
2298 sport->port.dev = &pdev->dev;
2299 sport->port.mapbase = res->start;
2300 sport->port.membase = base;
2301 sport->port.type = PORT_IMX;
2302 sport->port.iotype = UPIO_MEM;
2303 sport->port.irq = rxirq;
2304 sport->port.fifosize = 32;
2305 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2306 sport->port.ops = &imx_uart_pops;
2307 sport->port.rs485_config = imx_uart_rs485_config;
2308 /* RTS is required to control the RS485 transmitter */
2309 if (sport->have_rtscts || sport->have_rtsgpio)
2310 sport->port.rs485_supported = imx_rs485_supported;
2311 else
2312 sport->port.rs485_supported = imx_no_rs485;
2313 sport->port.flags = UPF_BOOT_AUTOCONF;
2314 timer_setup(&sport->timer, imx_uart_timeout, 0);
2315
2316 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2317 if (IS_ERR(sport->gpios))
2318 return PTR_ERR(sport->gpios);
2319
2320 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2321 if (IS_ERR(sport->clk_ipg)) {
2322 ret = PTR_ERR(sport->clk_ipg);
2323 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2324 return ret;
2325 }
2326
2327 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2328 if (IS_ERR(sport->clk_per)) {
2329 ret = PTR_ERR(sport->clk_per);
2330 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2331 return ret;
2332 }
2333
2334 sport->port.uartclk = clk_get_rate(sport->clk_per);
2335
2336 /* For register access, we only need to enable the ipg clock. */
2337 ret = clk_prepare_enable(sport->clk_ipg);
2338 if (ret) {
2339 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2340 return ret;
2341 }
2342
2343 /* initialize shadow register values */
2344 sport->ucr1 = readl(sport->port.membase + UCR1);
2345 sport->ucr2 = readl(sport->port.membase + UCR2);
2346 sport->ucr3 = readl(sport->port.membase + UCR3);
2347 sport->ucr4 = readl(sport->port.membase + UCR4);
2348 sport->ufcr = readl(sport->port.membase + UFCR);
2349
2350 ret = uart_get_rs485_mode(&sport->port);
2351 if (ret) {
2352 clk_disable_unprepare(sport->clk_ipg);
2353 return ret;
2354 }
2355
2356 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2357 (!sport->have_rtscts && !sport->have_rtsgpio))
2358 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2359
2360 /*
2361 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2362 * signal cannot be set low during transmission in case the
2363 * receiver is off (limitation of the i.MX UART IP).
2364 */
2365 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2366 sport->have_rtscts && !sport->have_rtsgpio &&
2367 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2368 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2369 dev_err(&pdev->dev,
2370 "low-active RTS not possible when receiver is off, enabling receiver\n");
2371
2372 /* Disable interrupts before requesting them */
2373 ucr1 = imx_uart_readl(sport, UCR1);
2374 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2375 imx_uart_writel(sport, ucr1, UCR1);
2376
2377 /*
2378 * In case RS485 is enabled without GPIO RTS control, the UART IP
2379 * is used to control CTS signal. Keep both the UART and Receiver
2380 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2381 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2382 * data from being fed into the RX FIFO, enable loopback mode in
2383 * UTS register, which disconnects the RX path from external RXD
2384 * pin and connects it to the Transceiver, which is disabled, so
2385 * no data can be fed to the RX FIFO that way.
2386 */
2387 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2388 sport->have_rtscts && !sport->have_rtsgpio) {
2389 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2390 uts |= UTS_LOOP;
2391 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2392
2393 ucr1 = imx_uart_readl(sport, UCR1);
2394 ucr1 |= UCR1_UARTEN;
2395 imx_uart_writel(sport, ucr1, UCR1);
2396
2397 ucr2 = imx_uart_readl(sport, UCR2);
2398 ucr2 |= UCR2_RXEN;
2399 imx_uart_writel(sport, ucr2, UCR2);
2400 }
2401
2402 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2403 /*
2404 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2405 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2406 * and DCD (when they are outputs) or enables the respective
2407 * irqs. So set this bit early, i.e. before requesting irqs.
2408 */
2409 u32 ufcr = imx_uart_readl(sport, UFCR);
2410 if (!(ufcr & UFCR_DCEDTE))
2411 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2412
2413 /*
2414 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2415 * enabled later because they cannot be cleared
2416 * (confirmed on i.MX25) which makes them unusable.
2417 */
2418 imx_uart_writel(sport,
2419 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2420 UCR3);
2421
2422 } else {
2423 u32 ucr3 = UCR3_DSR;
2424 u32 ufcr = imx_uart_readl(sport, UFCR);
2425 if (ufcr & UFCR_DCEDTE)
2426 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2427
2428 if (!imx_uart_is_imx1(sport))
2429 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2430 imx_uart_writel(sport, ucr3, UCR3);
2431 }
2432
2433 clk_disable_unprepare(sport->clk_ipg);
2434
2435 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2436 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2437 sport->trigger_start_tx.function = imx_trigger_start_tx;
2438 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2439
2440 /*
2441 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2442 * chips only have one interrupt.
2443 */
2444 if (txirq > 0) {
2445 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2446 dev_name(&pdev->dev), sport);
2447 if (ret) {
2448 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2449 ret);
2450 return ret;
2451 }
2452
2453 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2454 dev_name(&pdev->dev), sport);
2455 if (ret) {
2456 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2457 ret);
2458 return ret;
2459 }
2460
2461 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2462 dev_name(&pdev->dev), sport);
2463 if (ret) {
2464 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2465 ret);
2466 return ret;
2467 }
2468 } else {
2469 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2470 dev_name(&pdev->dev), sport);
2471 if (ret) {
2472 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2473 return ret;
2474 }
2475 }
2476
2477 imx_uart_ports[sport->port.line] = sport;
2478
2479 platform_set_drvdata(pdev, sport);
2480
2481 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2482}
2483
2484static int imx_uart_remove(struct platform_device *pdev)
2485{
2486 struct imx_port *sport = platform_get_drvdata(pdev);
2487
2488 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2489}
2490
2491static void imx_uart_restore_context(struct imx_port *sport)
2492{
2493 unsigned long flags;
2494
2495 spin_lock_irqsave(&sport->port.lock, flags);
2496 if (!sport->context_saved) {
2497 spin_unlock_irqrestore(&sport->port.lock, flags);
2498 return;
2499 }
2500
2501 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2502 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2503 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2504 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2505 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2506 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2507 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2508 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2509 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2510 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2511 sport->context_saved = false;
2512 spin_unlock_irqrestore(&sport->port.lock, flags);
2513}
2514
2515static void imx_uart_save_context(struct imx_port *sport)
2516{
2517 unsigned long flags;
2518
2519 /* Save necessary regs */
2520 spin_lock_irqsave(&sport->port.lock, flags);
2521 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2522 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2523 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2524 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2525 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2526 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2527 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2528 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2529 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2530 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2531 sport->context_saved = true;
2532 spin_unlock_irqrestore(&sport->port.lock, flags);
2533}
2534
2535static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2536{
2537 u32 ucr3;
2538
2539 ucr3 = imx_uart_readl(sport, UCR3);
2540 if (on) {
2541 imx_uart_writel(sport, USR1_AWAKE, USR1);
2542 ucr3 |= UCR3_AWAKEN;
2543 } else {
2544 ucr3 &= ~UCR3_AWAKEN;
2545 }
2546 imx_uart_writel(sport, ucr3, UCR3);
2547
2548 if (sport->have_rtscts) {
2549 u32 ucr1 = imx_uart_readl(sport, UCR1);
2550 if (on) {
2551 imx_uart_writel(sport, USR1_RTSD, USR1);
2552 ucr1 |= UCR1_RTSDEN;
2553 } else {
2554 ucr1 &= ~UCR1_RTSDEN;
2555 }
2556 imx_uart_writel(sport, ucr1, UCR1);
2557 }
2558}
2559
2560static int imx_uart_suspend_noirq(struct device *dev)
2561{
2562 struct imx_port *sport = dev_get_drvdata(dev);
2563
2564 imx_uart_save_context(sport);
2565
2566 clk_disable(sport->clk_ipg);
2567
2568 pinctrl_pm_select_sleep_state(dev);
2569
2570 return 0;
2571}
2572
2573static int imx_uart_resume_noirq(struct device *dev)
2574{
2575 struct imx_port *sport = dev_get_drvdata(dev);
2576 int ret;
2577
2578 pinctrl_pm_select_default_state(dev);
2579
2580 ret = clk_enable(sport->clk_ipg);
2581 if (ret)
2582 return ret;
2583
2584 imx_uart_restore_context(sport);
2585
2586 return 0;
2587}
2588
2589static int imx_uart_suspend(struct device *dev)
2590{
2591 struct imx_port *sport = dev_get_drvdata(dev);
2592 int ret;
2593
2594 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2595 disable_irq(sport->port.irq);
2596
2597 ret = clk_prepare_enable(sport->clk_ipg);
2598 if (ret)
2599 return ret;
2600
2601 /* enable wakeup from i.MX UART */
2602 imx_uart_enable_wakeup(sport, true);
2603
2604 return 0;
2605}
2606
2607static int imx_uart_resume(struct device *dev)
2608{
2609 struct imx_port *sport = dev_get_drvdata(dev);
2610
2611 /* disable wakeup from i.MX UART */
2612 imx_uart_enable_wakeup(sport, false);
2613
2614 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2615 enable_irq(sport->port.irq);
2616
2617 clk_disable_unprepare(sport->clk_ipg);
2618
2619 return 0;
2620}
2621
2622static int imx_uart_freeze(struct device *dev)
2623{
2624 struct imx_port *sport = dev_get_drvdata(dev);
2625
2626 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2627
2628 return clk_prepare_enable(sport->clk_ipg);
2629}
2630
2631static int imx_uart_thaw(struct device *dev)
2632{
2633 struct imx_port *sport = dev_get_drvdata(dev);
2634
2635 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2636
2637 clk_disable_unprepare(sport->clk_ipg);
2638
2639 return 0;
2640}
2641
2642static const struct dev_pm_ops imx_uart_pm_ops = {
2643 .suspend_noirq = imx_uart_suspend_noirq,
2644 .resume_noirq = imx_uart_resume_noirq,
2645 .freeze_noirq = imx_uart_suspend_noirq,
2646 .thaw_noirq = imx_uart_resume_noirq,
2647 .restore_noirq = imx_uart_resume_noirq,
2648 .suspend = imx_uart_suspend,
2649 .resume = imx_uart_resume,
2650 .freeze = imx_uart_freeze,
2651 .thaw = imx_uart_thaw,
2652 .restore = imx_uart_thaw,
2653};
2654
2655static struct platform_driver imx_uart_platform_driver = {
2656 .probe = imx_uart_probe,
2657 .remove = imx_uart_remove,
2658
2659 .driver = {
2660 .name = "imx-uart",
2661 .of_match_table = imx_uart_dt_ids,
2662 .pm = &imx_uart_pm_ops,
2663 },
2664};
2665
2666static int __init imx_uart_init(void)
2667{
2668 int ret = uart_register_driver(&imx_uart_uart_driver);
2669
2670 if (ret)
2671 return ret;
2672
2673 ret = platform_driver_register(&imx_uart_platform_driver);
2674 if (ret != 0)
2675 uart_unregister_driver(&imx_uart_uart_driver);
2676
2677 return ret;
2678}
2679
2680static void __exit imx_uart_exit(void)
2681{
2682 platform_driver_unregister(&imx_uart_platform_driver);
2683 uart_unregister_driver(&imx_uart_uart_driver);
2684}
2685
2686module_init(imx_uart_init);
2687module_exit(imx_uart_exit);
2688
2689MODULE_AUTHOR("Sascha Hauer");
2690MODULE_DESCRIPTION("IMX generic serial port driver");
2691MODULE_LICENSE("GPL");
2692MODULE_ALIAS("platform:imx-uart");