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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek PCIe host controller driver.
4 *
5 * Copyright (c) 2020 MediaTek Inc.
6 * Author: Jianjun Wang <jianjun.wang@mediatek.com>
7 */
8
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/clk-provider.h>
12#include <linux/delay.h>
13#include <linux/iopoll.h>
14#include <linux/irq.h>
15#include <linux/irqchip/chained_irq.h>
16#include <linux/irqdomain.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/msi.h>
20#include <linux/of_device.h>
21#include <linux/of_pci.h>
22#include <linux/pci.h>
23#include <linux/phy/phy.h>
24#include <linux/platform_device.h>
25#include <linux/pm_domain.h>
26#include <linux/pm_runtime.h>
27#include <linux/reset.h>
28
29#include "../pci.h"
30
31#define PCIE_BASE_CFG_REG 0x14
32#define PCIE_BASE_CFG_SPEED GENMASK(15, 8)
33
34#define PCIE_SETTING_REG 0x80
35#define PCIE_SETTING_LINK_WIDTH GENMASK(11, 8)
36#define PCIE_SETTING_GEN_SUPPORT GENMASK(14, 12)
37#define PCIE_PCI_IDS_1 0x9c
38#define PCI_CLASS(class) (class << 8)
39#define PCIE_RC_MODE BIT(0)
40
41#define PCIE_EQ_PRESET_01_REG 0x100
42#define PCIE_VAL_LN0_DOWNSTREAM GENMASK(6, 0)
43#define PCIE_VAL_LN0_UPSTREAM GENMASK(14, 8)
44#define PCIE_VAL_LN1_DOWNSTREAM GENMASK(22, 16)
45#define PCIE_VAL_LN1_UPSTREAM GENMASK(30, 24)
46
47#define PCIE_CFGNUM_REG 0x140
48#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0))
49#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8))
50#define PCIE_CFG_BYTE_EN(bytes) (((bytes) << 16) & GENMASK(19, 16))
51#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
52#define PCIE_CFG_OFFSET_ADDR 0x1000
53#define PCIE_CFG_HEADER(bus, devfn) \
54 (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
55
56#define PCIE_RST_CTRL_REG 0x148
57#define PCIE_MAC_RSTB BIT(0)
58#define PCIE_PHY_RSTB BIT(1)
59#define PCIE_BRG_RSTB BIT(2)
60#define PCIE_PE_RSTB BIT(3)
61
62#define PCIE_LTSSM_STATUS_REG 0x150
63#define PCIE_LTSSM_STATE_MASK GENMASK(28, 24)
64#define PCIE_LTSSM_STATE(val) ((val & PCIE_LTSSM_STATE_MASK) >> 24)
65#define PCIE_LTSSM_STATE_L2_IDLE 0x14
66
67#define PCIE_LINK_STATUS_REG 0x154
68#define PCIE_PORT_LINKUP BIT(8)
69
70#define PCIE_MSI_SET_NUM 8
71#define PCIE_MSI_IRQS_PER_SET 32
72#define PCIE_MSI_IRQS_NUM \
73 (PCIE_MSI_IRQS_PER_SET * PCIE_MSI_SET_NUM)
74
75#define PCIE_INT_ENABLE_REG 0x180
76#define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
77#define PCIE_MSI_SHIFT 8
78#define PCIE_INTX_SHIFT 24
79#define PCIE_INTX_ENABLE \
80 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
81
82#define PCIE_INT_STATUS_REG 0x184
83#define PCIE_MSI_SET_ENABLE_REG 0x190
84#define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
85
86#define PCIE_PIPE4_PIE8_REG 0x338
87#define PCIE_K_FINETUNE_MAX GENMASK(5, 0)
88#define PCIE_K_FINETUNE_ERR GENMASK(7, 6)
89#define PCIE_K_PRESET_TO_USE GENMASK(18, 8)
90#define PCIE_K_PHYPARAM_QUERY BIT(19)
91#define PCIE_K_QUERY_TIMEOUT BIT(20)
92#define PCIE_K_PRESET_TO_USE_16G GENMASK(31, 21)
93
94#define PCIE_MSI_SET_BASE_REG 0xc00
95#define PCIE_MSI_SET_OFFSET 0x10
96#define PCIE_MSI_SET_STATUS_OFFSET 0x04
97#define PCIE_MSI_SET_ENABLE_OFFSET 0x08
98
99#define PCIE_MSI_SET_ADDR_HI_BASE 0xc80
100#define PCIE_MSI_SET_ADDR_HI_OFFSET 0x04
101
102#define PCIE_ICMD_PM_REG 0x198
103#define PCIE_TURN_OFF_LINK BIT(4)
104
105#define PCIE_MISC_CTRL_REG 0x348
106#define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1)
107
108#define PCIE_TRANS_TABLE_BASE_REG 0x800
109#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4
110#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8
111#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET 0xc
112#define PCIE_ATR_TRSL_PARAM_OFFSET 0x10
113#define PCIE_ATR_TLB_SET_OFFSET 0x20
114
115#define PCIE_MAX_TRANS_TABLES 8
116#define PCIE_ATR_EN BIT(0)
117#define PCIE_ATR_SIZE(size) \
118 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
119#define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0))
120#define PCIE_ATR_TYPE_MEM PCIE_ATR_ID(0)
121#define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1)
122#define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16))
123#define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0)
124#define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2)
125
126#define MAX_NUM_PHY_RESETS 3
127
128/* Time in ms needed to complete PCIe reset on EN7581 SoC */
129#define PCIE_EN7581_RESET_TIME_MS 100
130
131struct mtk_gen3_pcie;
132
133#define PCIE_CONF_LINK2_CTL_STS (PCIE_CFG_OFFSET_ADDR + 0xb0)
134#define PCIE_CONF_LINK2_LCR2_LINK_SPEED GENMASK(3, 0)
135
136enum mtk_gen3_pcie_flags {
137 SKIP_PCIE_RSTB = BIT(0), /* Skip PERST# assertion during device
138 * probing or suspend/resume phase to
139 * avoid hw bugs/issues.
140 */
141};
142
143/**
144 * struct mtk_gen3_pcie_pdata - differentiate between host generations
145 * @power_up: pcie power_up callback
146 * @phy_resets: phy reset lines SoC data.
147 * @flags: pcie device flags.
148 */
149struct mtk_gen3_pcie_pdata {
150 int (*power_up)(struct mtk_gen3_pcie *pcie);
151 struct {
152 const char *id[MAX_NUM_PHY_RESETS];
153 int num_resets;
154 } phy_resets;
155 u32 flags;
156};
157
158/**
159 * struct mtk_msi_set - MSI information for each set
160 * @base: IO mapped register base
161 * @msg_addr: MSI message address
162 * @saved_irq_state: IRQ enable state saved at suspend time
163 */
164struct mtk_msi_set {
165 void __iomem *base;
166 phys_addr_t msg_addr;
167 u32 saved_irq_state;
168};
169
170/**
171 * struct mtk_gen3_pcie - PCIe port information
172 * @dev: pointer to PCIe device
173 * @base: IO mapped register base
174 * @reg_base: physical register base
175 * @mac_reset: MAC reset control
176 * @phy_resets: PHY reset controllers
177 * @phy: PHY controller block
178 * @clks: PCIe clocks
179 * @num_clks: PCIe clocks count for this port
180 * @max_link_speed: Maximum link speed (PCIe Gen) for this port
181 * @num_lanes: Number of PCIe lanes for this port
182 * @irq: PCIe controller interrupt number
183 * @saved_irq_state: IRQ enable state saved at suspend time
184 * @irq_lock: lock protecting IRQ register access
185 * @intx_domain: legacy INTx IRQ domain
186 * @msi_domain: MSI IRQ domain
187 * @msi_bottom_domain: MSI IRQ bottom domain
188 * @msi_sets: MSI sets information
189 * @lock: lock protecting IRQ bit map
190 * @msi_irq_in_use: bit map for assigned MSI IRQ
191 * @soc: pointer to SoC-dependent operations
192 */
193struct mtk_gen3_pcie {
194 struct device *dev;
195 void __iomem *base;
196 phys_addr_t reg_base;
197 struct reset_control *mac_reset;
198 struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RESETS];
199 struct phy *phy;
200 struct clk_bulk_data *clks;
201 int num_clks;
202 u8 max_link_speed;
203 u8 num_lanes;
204
205 int irq;
206 u32 saved_irq_state;
207 raw_spinlock_t irq_lock;
208 struct irq_domain *intx_domain;
209 struct irq_domain *msi_domain;
210 struct irq_domain *msi_bottom_domain;
211 struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
212 struct mutex lock;
213 DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
214
215 const struct mtk_gen3_pcie_pdata *soc;
216};
217
218/* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */
219static const char *const ltssm_str[] = {
220 "detect.quiet", /* 0x00 */
221 "detect.active", /* 0x01 */
222 "polling.active", /* 0x02 */
223 "polling.compliance", /* 0x03 */
224 "polling.configuration", /* 0x04 */
225 "config.linkwidthstart", /* 0x05 */
226 "config.linkwidthaccept", /* 0x06 */
227 "config.lanenumwait", /* 0x07 */
228 "config.lanenumaccept", /* 0x08 */
229 "config.complete", /* 0x09 */
230 "config.idle", /* 0x0A */
231 "recovery.receiverlock", /* 0x0B */
232 "recovery.equalization", /* 0x0C */
233 "recovery.speed", /* 0x0D */
234 "recovery.receiverconfig", /* 0x0E */
235 "recovery.idle", /* 0x0F */
236 "L0", /* 0x10 */
237 "L0s", /* 0x11 */
238 "L1.entry", /* 0x12 */
239 "L1.idle", /* 0x13 */
240 "L2.idle", /* 0x14 */
241 "L2.transmitwake", /* 0x15 */
242 "disable", /* 0x16 */
243 "loopback.entry", /* 0x17 */
244 "loopback.active", /* 0x18 */
245 "loopback.exit", /* 0x19 */
246 "hotreset", /* 0x1A */
247};
248
249/**
250 * mtk_pcie_config_tlp_header() - Configure a configuration TLP header
251 * @bus: PCI bus to query
252 * @devfn: device/function number
253 * @where: offset in config space
254 * @size: data size in TLP header
255 *
256 * Set byte enable field and device information in configuration TLP header.
257 */
258static void mtk_pcie_config_tlp_header(struct pci_bus *bus, unsigned int devfn,
259 int where, int size)
260{
261 struct mtk_gen3_pcie *pcie = bus->sysdata;
262 int bytes;
263 u32 val;
264
265 bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3);
266
267 val = PCIE_CFG_FORCE_BYTE_EN | PCIE_CFG_BYTE_EN(bytes) |
268 PCIE_CFG_HEADER(bus->number, devfn);
269
270 writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG);
271}
272
273static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
274 int where)
275{
276 struct mtk_gen3_pcie *pcie = bus->sysdata;
277
278 return pcie->base + PCIE_CFG_OFFSET_ADDR + where;
279}
280
281static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
282 int where, int size, u32 *val)
283{
284 mtk_pcie_config_tlp_header(bus, devfn, where, size);
285
286 return pci_generic_config_read32(bus, devfn, where, size, val);
287}
288
289static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
290 int where, int size, u32 val)
291{
292 mtk_pcie_config_tlp_header(bus, devfn, where, size);
293
294 if (size <= 2)
295 val <<= (where & 0x3) * 8;
296
297 return pci_generic_config_write32(bus, devfn, where, 4, val);
298}
299
300static struct pci_ops mtk_pcie_ops = {
301 .map_bus = mtk_pcie_map_bus,
302 .read = mtk_pcie_config_read,
303 .write = mtk_pcie_config_write,
304};
305
306static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie,
307 resource_size_t cpu_addr,
308 resource_size_t pci_addr,
309 resource_size_t size,
310 unsigned long type, int *num)
311{
312 resource_size_t remaining = size;
313 resource_size_t table_size;
314 resource_size_t addr_align;
315 const char *range_type;
316 void __iomem *table;
317 u32 val;
318
319 while (remaining && (*num < PCIE_MAX_TRANS_TABLES)) {
320 /* Table size needs to be a power of 2 */
321 table_size = BIT(fls(remaining) - 1);
322
323 if (cpu_addr > 0) {
324 addr_align = BIT(ffs(cpu_addr) - 1);
325 table_size = min(table_size, addr_align);
326 }
327
328 /* Minimum size of translate table is 4KiB */
329 if (table_size < 0x1000) {
330 dev_err(pcie->dev, "illegal table size %#llx\n",
331 (unsigned long long)table_size);
332 return -EINVAL;
333 }
334
335 table = pcie->base + PCIE_TRANS_TABLE_BASE_REG + *num * PCIE_ATR_TLB_SET_OFFSET;
336 writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(table_size) - 1), table);
337 writel_relaxed(upper_32_bits(cpu_addr), table + PCIE_ATR_SRC_ADDR_MSB_OFFSET);
338 writel_relaxed(lower_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET);
339 writel_relaxed(upper_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET);
340
341 if (type == IORESOURCE_IO) {
342 val = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO;
343 range_type = "IO";
344 } else {
345 val = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM;
346 range_type = "MEM";
347 }
348
349 writel_relaxed(val, table + PCIE_ATR_TRSL_PARAM_OFFSET);
350
351 dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n",
352 range_type, *num, (unsigned long long)cpu_addr,
353 (unsigned long long)pci_addr, (unsigned long long)table_size);
354
355 cpu_addr += table_size;
356 pci_addr += table_size;
357 remaining -= table_size;
358 (*num)++;
359 }
360
361 if (remaining)
362 dev_warn(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n",
363 (unsigned long long)cpu_addr, PCIE_MAX_TRANS_TABLES);
364
365 return 0;
366}
367
368static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie)
369{
370 int i;
371 u32 val;
372
373 for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
374 struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
375
376 msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG +
377 i * PCIE_MSI_SET_OFFSET;
378 msi_set->msg_addr = pcie->reg_base + PCIE_MSI_SET_BASE_REG +
379 i * PCIE_MSI_SET_OFFSET;
380
381 /* Configure the MSI capture address */
382 writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base);
383 writel_relaxed(upper_32_bits(msi_set->msg_addr),
384 pcie->base + PCIE_MSI_SET_ADDR_HI_BASE +
385 i * PCIE_MSI_SET_ADDR_HI_OFFSET);
386 }
387
388 val = readl_relaxed(pcie->base + PCIE_MSI_SET_ENABLE_REG);
389 val |= PCIE_MSI_SET_ENABLE;
390 writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG);
391
392 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
393 val |= PCIE_MSI_ENABLE;
394 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
395}
396
397static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
398{
399 struct resource_entry *entry;
400 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
401 unsigned int table_index = 0;
402 int err;
403 u32 val;
404
405 /* Set as RC mode and set controller PCIe Gen speed restriction, if any */
406 val = readl_relaxed(pcie->base + PCIE_SETTING_REG);
407 val |= PCIE_RC_MODE;
408 if (pcie->max_link_speed) {
409 val &= ~PCIE_SETTING_GEN_SUPPORT;
410
411 /* Can enable link speed support only from Gen2 onwards */
412 if (pcie->max_link_speed >= 2)
413 val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT,
414 GENMASK(pcie->max_link_speed - 2, 0));
415 }
416 if (pcie->num_lanes) {
417 val &= ~PCIE_SETTING_LINK_WIDTH;
418
419 /* Zero means one lane, each bit activates x2/x4/x8/x16 */
420 if (pcie->num_lanes > 1)
421 val |= FIELD_PREP(PCIE_SETTING_LINK_WIDTH,
422 GENMASK(fls(pcie->num_lanes >> 2), 0));
423 }
424 writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
425
426 /* Set Link Control 2 (LNKCTL2) speed restriction, if any */
427 if (pcie->max_link_speed) {
428 val = readl_relaxed(pcie->base + PCIE_CONF_LINK2_CTL_STS);
429 val &= ~PCIE_CONF_LINK2_LCR2_LINK_SPEED;
430 val |= FIELD_PREP(PCIE_CONF_LINK2_LCR2_LINK_SPEED, pcie->max_link_speed);
431 writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS);
432 }
433
434 /* Set class code */
435 val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1);
436 val &= ~GENMASK(31, 8);
437 val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI_NORMAL);
438 writel_relaxed(val, pcie->base + PCIE_PCI_IDS_1);
439
440 /* Mask all INTx interrupts */
441 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
442 val &= ~PCIE_INTX_ENABLE;
443 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
444
445 /* Disable DVFSRC voltage request */
446 val = readl_relaxed(pcie->base + PCIE_MISC_CTRL_REG);
447 val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
448 writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG);
449
450 /*
451 * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal
452 * causing occasional PCIe link down. In order to overcome the issue,
453 * PCIE_RSTB signals are not asserted/released at this stage and the
454 * PCIe block is reset using en7523_reset_assert() and
455 * en7581_pci_enable().
456 */
457 if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
458 /* Assert all reset signals */
459 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
460 val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
461 PCIE_PE_RSTB;
462 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
463
464 /*
465 * Described in PCIe CEM specification revision 6.0.
466 *
467 * The deassertion of PERST# should be delayed 100ms (TPVPERL)
468 * for the power and clock to become stable.
469 */
470 msleep(PCIE_T_PVPERL_MS);
471
472 /* De-assert reset signals */
473 val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
474 PCIE_PE_RSTB);
475 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
476 }
477
478 /* Check if the link is up or not */
479 err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
480 !!(val & PCIE_PORT_LINKUP), 20,
481 PCI_PM_D3COLD_WAIT * USEC_PER_MSEC);
482 if (err) {
483 const char *ltssm_state;
484 int ltssm_index;
485
486 val = readl_relaxed(pcie->base + PCIE_LTSSM_STATUS_REG);
487 ltssm_index = PCIE_LTSSM_STATE(val);
488 ltssm_state = ltssm_index >= ARRAY_SIZE(ltssm_str) ?
489 "Unknown state" : ltssm_str[ltssm_index];
490 dev_err(pcie->dev,
491 "PCIe link down, current LTSSM state: %s (%#x)\n",
492 ltssm_state, val);
493 return err;
494 }
495
496 mtk_pcie_enable_msi(pcie);
497
498 /* Set PCIe translation windows */
499 resource_list_for_each_entry(entry, &host->windows) {
500 struct resource *res = entry->res;
501 unsigned long type = resource_type(res);
502 resource_size_t cpu_addr;
503 resource_size_t pci_addr;
504 resource_size_t size;
505
506 if (type == IORESOURCE_IO)
507 cpu_addr = pci_pio_to_address(res->start);
508 else if (type == IORESOURCE_MEM)
509 cpu_addr = res->start;
510 else
511 continue;
512
513 pci_addr = res->start - entry->offset;
514 size = resource_size(res);
515 err = mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size,
516 type, &table_index);
517 if (err)
518 return err;
519 }
520
521 return 0;
522}
523
524static void mtk_pcie_msi_irq_mask(struct irq_data *data)
525{
526 pci_msi_mask_irq(data);
527 irq_chip_mask_parent(data);
528}
529
530static void mtk_pcie_msi_irq_unmask(struct irq_data *data)
531{
532 pci_msi_unmask_irq(data);
533 irq_chip_unmask_parent(data);
534}
535
536static struct irq_chip mtk_msi_irq_chip = {
537 .irq_ack = irq_chip_ack_parent,
538 .irq_mask = mtk_pcie_msi_irq_mask,
539 .irq_unmask = mtk_pcie_msi_irq_unmask,
540 .name = "MSI",
541};
542
543static struct msi_domain_info mtk_msi_domain_info = {
544 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
545 MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX |
546 MSI_FLAG_MULTI_PCI_MSI,
547 .chip = &mtk_msi_irq_chip,
548};
549
550static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
551{
552 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
553 struct mtk_gen3_pcie *pcie = data->domain->host_data;
554 unsigned long hwirq;
555
556 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
557
558 msg->address_hi = upper_32_bits(msi_set->msg_addr);
559 msg->address_lo = lower_32_bits(msi_set->msg_addr);
560 msg->data = hwirq;
561 dev_dbg(pcie->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n",
562 hwirq, msg->address_hi, msg->address_lo, msg->data);
563}
564
565static void mtk_msi_bottom_irq_ack(struct irq_data *data)
566{
567 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
568 unsigned long hwirq;
569
570 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
571
572 writel_relaxed(BIT(hwirq), msi_set->base + PCIE_MSI_SET_STATUS_OFFSET);
573}
574
575static void mtk_msi_bottom_irq_mask(struct irq_data *data)
576{
577 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
578 struct mtk_gen3_pcie *pcie = data->domain->host_data;
579 unsigned long hwirq, flags;
580 u32 val;
581
582 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
583
584 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
585 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
586 val &= ~BIT(hwirq);
587 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
588 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
589}
590
591static void mtk_msi_bottom_irq_unmask(struct irq_data *data)
592{
593 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
594 struct mtk_gen3_pcie *pcie = data->domain->host_data;
595 unsigned long hwirq, flags;
596 u32 val;
597
598 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
599
600 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
601 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
602 val |= BIT(hwirq);
603 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
604 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
605}
606
607static struct irq_chip mtk_msi_bottom_irq_chip = {
608 .irq_ack = mtk_msi_bottom_irq_ack,
609 .irq_mask = mtk_msi_bottom_irq_mask,
610 .irq_unmask = mtk_msi_bottom_irq_unmask,
611 .irq_compose_msi_msg = mtk_compose_msi_msg,
612 .name = "MSI",
613};
614
615static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain,
616 unsigned int virq, unsigned int nr_irqs,
617 void *arg)
618{
619 struct mtk_gen3_pcie *pcie = domain->host_data;
620 struct mtk_msi_set *msi_set;
621 int i, hwirq, set_idx;
622
623 mutex_lock(&pcie->lock);
624
625 hwirq = bitmap_find_free_region(pcie->msi_irq_in_use, PCIE_MSI_IRQS_NUM,
626 order_base_2(nr_irqs));
627
628 mutex_unlock(&pcie->lock);
629
630 if (hwirq < 0)
631 return -ENOSPC;
632
633 set_idx = hwirq / PCIE_MSI_IRQS_PER_SET;
634 msi_set = &pcie->msi_sets[set_idx];
635
636 for (i = 0; i < nr_irqs; i++)
637 irq_domain_set_info(domain, virq + i, hwirq + i,
638 &mtk_msi_bottom_irq_chip, msi_set,
639 handle_edge_irq, NULL, NULL);
640
641 return 0;
642}
643
644static void mtk_msi_bottom_domain_free(struct irq_domain *domain,
645 unsigned int virq, unsigned int nr_irqs)
646{
647 struct mtk_gen3_pcie *pcie = domain->host_data;
648 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
649
650 mutex_lock(&pcie->lock);
651
652 bitmap_release_region(pcie->msi_irq_in_use, data->hwirq,
653 order_base_2(nr_irqs));
654
655 mutex_unlock(&pcie->lock);
656
657 irq_domain_free_irqs_common(domain, virq, nr_irqs);
658}
659
660static const struct irq_domain_ops mtk_msi_bottom_domain_ops = {
661 .alloc = mtk_msi_bottom_domain_alloc,
662 .free = mtk_msi_bottom_domain_free,
663};
664
665static void mtk_intx_mask(struct irq_data *data)
666{
667 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
668 unsigned long flags;
669 u32 val;
670
671 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
672 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
673 val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT);
674 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
675 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
676}
677
678static void mtk_intx_unmask(struct irq_data *data)
679{
680 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
681 unsigned long flags;
682 u32 val;
683
684 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
685 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
686 val |= BIT(data->hwirq + PCIE_INTX_SHIFT);
687 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
688 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
689}
690
691/**
692 * mtk_intx_eoi() - Clear INTx IRQ status at the end of interrupt
693 * @data: pointer to chip specific data
694 *
695 * As an emulated level IRQ, its interrupt status will remain
696 * until the corresponding de-assert message is received; hence that
697 * the status can only be cleared when the interrupt has been serviced.
698 */
699static void mtk_intx_eoi(struct irq_data *data)
700{
701 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
702 unsigned long hwirq;
703
704 hwirq = data->hwirq + PCIE_INTX_SHIFT;
705 writel_relaxed(BIT(hwirq), pcie->base + PCIE_INT_STATUS_REG);
706}
707
708static struct irq_chip mtk_intx_irq_chip = {
709 .irq_mask = mtk_intx_mask,
710 .irq_unmask = mtk_intx_unmask,
711 .irq_eoi = mtk_intx_eoi,
712 .name = "INTx",
713};
714
715static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
716 irq_hw_number_t hwirq)
717{
718 irq_set_chip_data(irq, domain->host_data);
719 irq_set_chip_and_handler_name(irq, &mtk_intx_irq_chip,
720 handle_fasteoi_irq, "INTx");
721 return 0;
722}
723
724static const struct irq_domain_ops intx_domain_ops = {
725 .map = mtk_pcie_intx_map,
726};
727
728static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie)
729{
730 struct device *dev = pcie->dev;
731 struct device_node *intc_node, *node = dev->of_node;
732 int ret;
733
734 raw_spin_lock_init(&pcie->irq_lock);
735
736 /* Setup INTx */
737 intc_node = of_get_child_by_name(node, "interrupt-controller");
738 if (!intc_node) {
739 dev_err(dev, "missing interrupt-controller node\n");
740 return -ENODEV;
741 }
742
743 pcie->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX,
744 &intx_domain_ops, pcie);
745 if (!pcie->intx_domain) {
746 dev_err(dev, "failed to create INTx IRQ domain\n");
747 ret = -ENODEV;
748 goto out_put_node;
749 }
750
751 /* Setup MSI */
752 mutex_init(&pcie->lock);
753
754 pcie->msi_bottom_domain = irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM,
755 &mtk_msi_bottom_domain_ops, pcie);
756 if (!pcie->msi_bottom_domain) {
757 dev_err(dev, "failed to create MSI bottom domain\n");
758 ret = -ENODEV;
759 goto err_msi_bottom_domain;
760 }
761
762 pcie->msi_domain = pci_msi_create_irq_domain(dev->fwnode,
763 &mtk_msi_domain_info,
764 pcie->msi_bottom_domain);
765 if (!pcie->msi_domain) {
766 dev_err(dev, "failed to create MSI domain\n");
767 ret = -ENODEV;
768 goto err_msi_domain;
769 }
770
771 of_node_put(intc_node);
772 return 0;
773
774err_msi_domain:
775 irq_domain_remove(pcie->msi_bottom_domain);
776err_msi_bottom_domain:
777 irq_domain_remove(pcie->intx_domain);
778out_put_node:
779 of_node_put(intc_node);
780 return ret;
781}
782
783static void mtk_pcie_irq_teardown(struct mtk_gen3_pcie *pcie)
784{
785 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
786
787 if (pcie->intx_domain)
788 irq_domain_remove(pcie->intx_domain);
789
790 if (pcie->msi_domain)
791 irq_domain_remove(pcie->msi_domain);
792
793 if (pcie->msi_bottom_domain)
794 irq_domain_remove(pcie->msi_bottom_domain);
795
796 irq_dispose_mapping(pcie->irq);
797}
798
799static void mtk_pcie_msi_handler(struct mtk_gen3_pcie *pcie, int set_idx)
800{
801 struct mtk_msi_set *msi_set = &pcie->msi_sets[set_idx];
802 unsigned long msi_enable, msi_status;
803 irq_hw_number_t bit, hwirq;
804
805 msi_enable = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
806
807 do {
808 msi_status = readl_relaxed(msi_set->base +
809 PCIE_MSI_SET_STATUS_OFFSET);
810 msi_status &= msi_enable;
811 if (!msi_status)
812 break;
813
814 for_each_set_bit(bit, &msi_status, PCIE_MSI_IRQS_PER_SET) {
815 hwirq = bit + set_idx * PCIE_MSI_IRQS_PER_SET;
816 generic_handle_domain_irq(pcie->msi_bottom_domain, hwirq);
817 }
818 } while (true);
819}
820
821static void mtk_pcie_irq_handler(struct irq_desc *desc)
822{
823 struct mtk_gen3_pcie *pcie = irq_desc_get_handler_data(desc);
824 struct irq_chip *irqchip = irq_desc_get_chip(desc);
825 unsigned long status;
826 irq_hw_number_t irq_bit = PCIE_INTX_SHIFT;
827
828 chained_irq_enter(irqchip, desc);
829
830 status = readl_relaxed(pcie->base + PCIE_INT_STATUS_REG);
831 for_each_set_bit_from(irq_bit, &status, PCI_NUM_INTX +
832 PCIE_INTX_SHIFT)
833 generic_handle_domain_irq(pcie->intx_domain,
834 irq_bit - PCIE_INTX_SHIFT);
835
836 irq_bit = PCIE_MSI_SHIFT;
837 for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM +
838 PCIE_MSI_SHIFT) {
839 mtk_pcie_msi_handler(pcie, irq_bit - PCIE_MSI_SHIFT);
840
841 writel_relaxed(BIT(irq_bit), pcie->base + PCIE_INT_STATUS_REG);
842 }
843
844 chained_irq_exit(irqchip, desc);
845}
846
847static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *pcie)
848{
849 struct device *dev = pcie->dev;
850 struct platform_device *pdev = to_platform_device(dev);
851 int err;
852
853 err = mtk_pcie_init_irq_domains(pcie);
854 if (err)
855 return err;
856
857 pcie->irq = platform_get_irq(pdev, 0);
858 if (pcie->irq < 0)
859 return pcie->irq;
860
861 irq_set_chained_handler_and_data(pcie->irq, mtk_pcie_irq_handler, pcie);
862
863 return 0;
864}
865
866static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
867{
868 int i, ret, num_resets = pcie->soc->phy_resets.num_resets;
869 struct device *dev = pcie->dev;
870 struct platform_device *pdev = to_platform_device(dev);
871 struct resource *regs;
872 u32 num_lanes;
873
874 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
875 if (!regs)
876 return -EINVAL;
877 pcie->base = devm_ioremap_resource(dev, regs);
878 if (IS_ERR(pcie->base)) {
879 dev_err(dev, "failed to map register base\n");
880 return PTR_ERR(pcie->base);
881 }
882
883 pcie->reg_base = regs->start;
884
885 for (i = 0; i < num_resets; i++)
886 pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i];
887
888 ret = devm_reset_control_bulk_get_optional_shared(dev, num_resets, pcie->phy_resets);
889 if (ret) {
890 dev_err(dev, "failed to get PHY bulk reset\n");
891 return ret;
892 }
893
894 pcie->mac_reset = devm_reset_control_get_optional_exclusive(dev, "mac");
895 if (IS_ERR(pcie->mac_reset)) {
896 ret = PTR_ERR(pcie->mac_reset);
897 if (ret != -EPROBE_DEFER)
898 dev_err(dev, "failed to get MAC reset\n");
899
900 return ret;
901 }
902
903 pcie->phy = devm_phy_optional_get(dev, "pcie-phy");
904 if (IS_ERR(pcie->phy)) {
905 ret = PTR_ERR(pcie->phy);
906 if (ret != -EPROBE_DEFER)
907 dev_err(dev, "failed to get PHY\n");
908
909 return ret;
910 }
911
912 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks);
913 if (pcie->num_clks < 0) {
914 dev_err(dev, "failed to get clocks\n");
915 return pcie->num_clks;
916 }
917
918 ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes);
919 if (ret == 0) {
920 if (num_lanes == 0 || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2))
921 dev_warn(dev, "invalid num-lanes, using controller defaults\n");
922 else
923 pcie->num_lanes = num_lanes;
924 }
925
926 return 0;
927}
928
929static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
930{
931 struct device *dev = pcie->dev;
932 int err;
933 u32 val;
934
935 /*
936 * Wait for the time needed to complete the bulk assert in
937 * mtk_pcie_setup for EN7581 SoC.
938 */
939 mdelay(PCIE_EN7581_RESET_TIME_MS);
940
941 err = phy_init(pcie->phy);
942 if (err) {
943 dev_err(dev, "failed to initialize PHY\n");
944 return err;
945 }
946
947 err = phy_power_on(pcie->phy);
948 if (err) {
949 dev_err(dev, "failed to power on PHY\n");
950 goto err_phy_on;
951 }
952
953 err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
954 if (err) {
955 dev_err(dev, "failed to deassert PHYs\n");
956 goto err_phy_deassert;
957 }
958
959 /*
960 * Wait for the time needed to complete the bulk de-assert above.
961 * This time is specific for EN7581 SoC.
962 */
963 mdelay(PCIE_EN7581_RESET_TIME_MS);
964
965 pm_runtime_enable(dev);
966 pm_runtime_get_sync(dev);
967
968 err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
969 if (err) {
970 dev_err(dev, "failed to prepare clock\n");
971 goto err_clk_prepare;
972 }
973
974 val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) |
975 FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) |
976 FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) |
977 FIELD_PREP(PCIE_VAL_LN1_UPSTREAM, 0x41);
978 writel_relaxed(val, pcie->base + PCIE_EQ_PRESET_01_REG);
979
980 val = PCIE_K_PHYPARAM_QUERY | PCIE_K_QUERY_TIMEOUT |
981 FIELD_PREP(PCIE_K_PRESET_TO_USE_16G, 0x80) |
982 FIELD_PREP(PCIE_K_PRESET_TO_USE, 0x2) |
983 FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf);
984 writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG);
985
986 err = clk_bulk_enable(pcie->num_clks, pcie->clks);
987 if (err) {
988 dev_err(dev, "failed to prepare clock\n");
989 goto err_clk_enable;
990 }
991
992 return 0;
993
994err_clk_enable:
995 clk_bulk_unprepare(pcie->num_clks, pcie->clks);
996err_clk_prepare:
997 pm_runtime_put_sync(dev);
998 pm_runtime_disable(dev);
999 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
1000err_phy_deassert:
1001 phy_power_off(pcie->phy);
1002err_phy_on:
1003 phy_exit(pcie->phy);
1004
1005 return err;
1006}
1007
1008static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
1009{
1010 struct device *dev = pcie->dev;
1011 int err;
1012
1013 /* PHY power on and enable pipe clock */
1014 err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
1015 if (err) {
1016 dev_err(dev, "failed to deassert PHYs\n");
1017 return err;
1018 }
1019
1020 err = phy_init(pcie->phy);
1021 if (err) {
1022 dev_err(dev, "failed to initialize PHY\n");
1023 goto err_phy_init;
1024 }
1025
1026 err = phy_power_on(pcie->phy);
1027 if (err) {
1028 dev_err(dev, "failed to power on PHY\n");
1029 goto err_phy_on;
1030 }
1031
1032 /* MAC power on and enable transaction layer clocks */
1033 reset_control_deassert(pcie->mac_reset);
1034
1035 pm_runtime_enable(dev);
1036 pm_runtime_get_sync(dev);
1037
1038 err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
1039 if (err) {
1040 dev_err(dev, "failed to enable clocks\n");
1041 goto err_clk_init;
1042 }
1043
1044 return 0;
1045
1046err_clk_init:
1047 pm_runtime_put_sync(dev);
1048 pm_runtime_disable(dev);
1049 reset_control_assert(pcie->mac_reset);
1050 phy_power_off(pcie->phy);
1051err_phy_on:
1052 phy_exit(pcie->phy);
1053err_phy_init:
1054 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
1055
1056 return err;
1057}
1058
1059static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
1060{
1061 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
1062
1063 pm_runtime_put_sync(pcie->dev);
1064 pm_runtime_disable(pcie->dev);
1065 reset_control_assert(pcie->mac_reset);
1066
1067 phy_power_off(pcie->phy);
1068 phy_exit(pcie->phy);
1069 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
1070}
1071
1072static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pcie)
1073{
1074 u32 val;
1075 int ret;
1076
1077 val = readl_relaxed(pcie->base + PCIE_BASE_CFG_REG);
1078 val = FIELD_GET(PCIE_BASE_CFG_SPEED, val);
1079 ret = fls(val);
1080
1081 return ret > 0 ? ret : -EINVAL;
1082}
1083
1084static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
1085{
1086 int err, max_speed;
1087
1088 err = mtk_pcie_parse_port(pcie);
1089 if (err)
1090 return err;
1091
1092 /*
1093 * Deassert the line in order to avoid unbalance in deassert_count
1094 * counter since the bulk is shared.
1095 */
1096 reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
1097 /*
1098 * The controller may have been left out of reset by the bootloader
1099 * so make sure that we get a clean start by asserting resets here.
1100 */
1101 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
1102
1103 reset_control_assert(pcie->mac_reset);
1104 usleep_range(10, 20);
1105
1106 /* Don't touch the hardware registers before power up */
1107 err = pcie->soc->power_up(pcie);
1108 if (err)
1109 return err;
1110
1111 err = of_pci_get_max_link_speed(pcie->dev->of_node);
1112 if (err) {
1113 /* Get the maximum speed supported by the controller */
1114 max_speed = mtk_pcie_get_controller_max_link_speed(pcie);
1115
1116 /* Set max_link_speed only if the controller supports it */
1117 if (max_speed >= 0 && max_speed <= err) {
1118 pcie->max_link_speed = err;
1119 dev_info(pcie->dev,
1120 "maximum controller link speed Gen%d, overriding to Gen%u",
1121 max_speed, pcie->max_link_speed);
1122 }
1123 }
1124
1125 /* Try link up */
1126 err = mtk_pcie_startup_port(pcie);
1127 if (err)
1128 goto err_setup;
1129
1130 err = mtk_pcie_setup_irq(pcie);
1131 if (err)
1132 goto err_setup;
1133
1134 return 0;
1135
1136err_setup:
1137 mtk_pcie_power_down(pcie);
1138
1139 return err;
1140}
1141
1142static int mtk_pcie_probe(struct platform_device *pdev)
1143{
1144 struct device *dev = &pdev->dev;
1145 struct mtk_gen3_pcie *pcie;
1146 struct pci_host_bridge *host;
1147 int err;
1148
1149 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1150 if (!host)
1151 return -ENOMEM;
1152
1153 pcie = pci_host_bridge_priv(host);
1154
1155 pcie->dev = dev;
1156 pcie->soc = device_get_match_data(dev);
1157 platform_set_drvdata(pdev, pcie);
1158
1159 err = mtk_pcie_setup(pcie);
1160 if (err)
1161 return err;
1162
1163 host->ops = &mtk_pcie_ops;
1164 host->sysdata = pcie;
1165
1166 err = pci_host_probe(host);
1167 if (err) {
1168 mtk_pcie_irq_teardown(pcie);
1169 mtk_pcie_power_down(pcie);
1170 return err;
1171 }
1172
1173 return 0;
1174}
1175
1176static void mtk_pcie_remove(struct platform_device *pdev)
1177{
1178 struct mtk_gen3_pcie *pcie = platform_get_drvdata(pdev);
1179 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1180
1181 pci_lock_rescan_remove();
1182 pci_stop_root_bus(host->bus);
1183 pci_remove_root_bus(host->bus);
1184 pci_unlock_rescan_remove();
1185
1186 mtk_pcie_irq_teardown(pcie);
1187 mtk_pcie_power_down(pcie);
1188}
1189
1190static void mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie)
1191{
1192 int i;
1193
1194 raw_spin_lock(&pcie->irq_lock);
1195
1196 pcie->saved_irq_state = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
1197
1198 for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
1199 struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
1200
1201 msi_set->saved_irq_state = readl_relaxed(msi_set->base +
1202 PCIE_MSI_SET_ENABLE_OFFSET);
1203 }
1204
1205 raw_spin_unlock(&pcie->irq_lock);
1206}
1207
1208static void mtk_pcie_irq_restore(struct mtk_gen3_pcie *pcie)
1209{
1210 int i;
1211
1212 raw_spin_lock(&pcie->irq_lock);
1213
1214 writel_relaxed(pcie->saved_irq_state, pcie->base + PCIE_INT_ENABLE_REG);
1215
1216 for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
1217 struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
1218
1219 writel_relaxed(msi_set->saved_irq_state,
1220 msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
1221 }
1222
1223 raw_spin_unlock(&pcie->irq_lock);
1224}
1225
1226static int mtk_pcie_turn_off_link(struct mtk_gen3_pcie *pcie)
1227{
1228 u32 val;
1229
1230 val = readl_relaxed(pcie->base + PCIE_ICMD_PM_REG);
1231 val |= PCIE_TURN_OFF_LINK;
1232 writel_relaxed(val, pcie->base + PCIE_ICMD_PM_REG);
1233
1234 /* Check the link is L2 */
1235 return readl_poll_timeout(pcie->base + PCIE_LTSSM_STATUS_REG, val,
1236 (PCIE_LTSSM_STATE(val) ==
1237 PCIE_LTSSM_STATE_L2_IDLE), 20,
1238 50 * USEC_PER_MSEC);
1239}
1240
1241static int mtk_pcie_suspend_noirq(struct device *dev)
1242{
1243 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
1244 int err;
1245 u32 val;
1246
1247 /* Trigger link to L2 state */
1248 err = mtk_pcie_turn_off_link(pcie);
1249 if (err) {
1250 dev_err(pcie->dev, "cannot enter L2 state\n");
1251 return err;
1252 }
1253
1254 if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
1255 /* Assert the PERST# pin */
1256 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
1257 val |= PCIE_PE_RSTB;
1258 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
1259 }
1260
1261 dev_dbg(pcie->dev, "entered L2 states successfully");
1262
1263 mtk_pcie_irq_save(pcie);
1264 mtk_pcie_power_down(pcie);
1265
1266 return 0;
1267}
1268
1269static int mtk_pcie_resume_noirq(struct device *dev)
1270{
1271 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
1272 int err;
1273
1274 err = pcie->soc->power_up(pcie);
1275 if (err)
1276 return err;
1277
1278 err = mtk_pcie_startup_port(pcie);
1279 if (err) {
1280 mtk_pcie_power_down(pcie);
1281 return err;
1282 }
1283
1284 mtk_pcie_irq_restore(pcie);
1285
1286 return 0;
1287}
1288
1289static const struct dev_pm_ops mtk_pcie_pm_ops = {
1290 NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1291 mtk_pcie_resume_noirq)
1292};
1293
1294static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = {
1295 .power_up = mtk_pcie_power_up,
1296 .phy_resets = {
1297 .id[0] = "phy",
1298 .num_resets = 1,
1299 },
1300};
1301
1302static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = {
1303 .power_up = mtk_pcie_en7581_power_up,
1304 .phy_resets = {
1305 .id[0] = "phy-lane0",
1306 .id[1] = "phy-lane1",
1307 .id[2] = "phy-lane2",
1308 .num_resets = 3,
1309 },
1310 .flags = SKIP_PCIE_RSTB,
1311};
1312
1313static const struct of_device_id mtk_pcie_of_match[] = {
1314 { .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 },
1315 { .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 },
1316 {},
1317};
1318MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
1319
1320static struct platform_driver mtk_pcie_driver = {
1321 .probe = mtk_pcie_probe,
1322 .remove = mtk_pcie_remove,
1323 .driver = {
1324 .name = "mtk-pcie-gen3",
1325 .of_match_table = mtk_pcie_of_match,
1326 .pm = &mtk_pcie_pm_ops,
1327 },
1328};
1329
1330module_platform_driver(mtk_pcie_driver);
1331MODULE_DESCRIPTION("MediaTek Gen3 PCIe host controller driver");
1332MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek PCIe host controller driver.
4 *
5 * Copyright (c) 2020 MediaTek Inc.
6 * Author: Jianjun Wang <jianjun.wang@mediatek.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/iopoll.h>
12#include <linux/irq.h>
13#include <linux/irqchip/chained_irq.h>
14#include <linux/irqdomain.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/msi.h>
18#include <linux/pci.h>
19#include <linux/phy/phy.h>
20#include <linux/platform_device.h>
21#include <linux/pm_domain.h>
22#include <linux/pm_runtime.h>
23#include <linux/reset.h>
24
25#include "../pci.h"
26
27#define PCIE_SETTING_REG 0x80
28#define PCIE_PCI_IDS_1 0x9c
29#define PCI_CLASS(class) (class << 8)
30#define PCIE_RC_MODE BIT(0)
31
32#define PCIE_CFGNUM_REG 0x140
33#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0))
34#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8))
35#define PCIE_CFG_BYTE_EN(bytes) (((bytes) << 16) & GENMASK(19, 16))
36#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
37#define PCIE_CFG_OFFSET_ADDR 0x1000
38#define PCIE_CFG_HEADER(bus, devfn) \
39 (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
40
41#define PCIE_RST_CTRL_REG 0x148
42#define PCIE_MAC_RSTB BIT(0)
43#define PCIE_PHY_RSTB BIT(1)
44#define PCIE_BRG_RSTB BIT(2)
45#define PCIE_PE_RSTB BIT(3)
46
47#define PCIE_LTSSM_STATUS_REG 0x150
48#define PCIE_LTSSM_STATE_MASK GENMASK(28, 24)
49#define PCIE_LTSSM_STATE(val) ((val & PCIE_LTSSM_STATE_MASK) >> 24)
50#define PCIE_LTSSM_STATE_L2_IDLE 0x14
51
52#define PCIE_LINK_STATUS_REG 0x154
53#define PCIE_PORT_LINKUP BIT(8)
54
55#define PCIE_MSI_SET_NUM 8
56#define PCIE_MSI_IRQS_PER_SET 32
57#define PCIE_MSI_IRQS_NUM \
58 (PCIE_MSI_IRQS_PER_SET * PCIE_MSI_SET_NUM)
59
60#define PCIE_INT_ENABLE_REG 0x180
61#define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
62#define PCIE_MSI_SHIFT 8
63#define PCIE_INTX_SHIFT 24
64#define PCIE_INTX_ENABLE \
65 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
66
67#define PCIE_INT_STATUS_REG 0x184
68#define PCIE_MSI_SET_ENABLE_REG 0x190
69#define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
70
71#define PCIE_MSI_SET_BASE_REG 0xc00
72#define PCIE_MSI_SET_OFFSET 0x10
73#define PCIE_MSI_SET_STATUS_OFFSET 0x04
74#define PCIE_MSI_SET_ENABLE_OFFSET 0x08
75
76#define PCIE_MSI_SET_ADDR_HI_BASE 0xc80
77#define PCIE_MSI_SET_ADDR_HI_OFFSET 0x04
78
79#define PCIE_ICMD_PM_REG 0x198
80#define PCIE_TURN_OFF_LINK BIT(4)
81
82#define PCIE_MISC_CTRL_REG 0x348
83#define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1)
84
85#define PCIE_TRANS_TABLE_BASE_REG 0x800
86#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4
87#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8
88#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET 0xc
89#define PCIE_ATR_TRSL_PARAM_OFFSET 0x10
90#define PCIE_ATR_TLB_SET_OFFSET 0x20
91
92#define PCIE_MAX_TRANS_TABLES 8
93#define PCIE_ATR_EN BIT(0)
94#define PCIE_ATR_SIZE(size) \
95 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
96#define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0))
97#define PCIE_ATR_TYPE_MEM PCIE_ATR_ID(0)
98#define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1)
99#define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16))
100#define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0)
101#define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2)
102
103/**
104 * struct mtk_msi_set - MSI information for each set
105 * @base: IO mapped register base
106 * @msg_addr: MSI message address
107 * @saved_irq_state: IRQ enable state saved at suspend time
108 */
109struct mtk_msi_set {
110 void __iomem *base;
111 phys_addr_t msg_addr;
112 u32 saved_irq_state;
113};
114
115/**
116 * struct mtk_gen3_pcie - PCIe port information
117 * @dev: pointer to PCIe device
118 * @base: IO mapped register base
119 * @reg_base: physical register base
120 * @mac_reset: MAC reset control
121 * @phy_reset: PHY reset control
122 * @phy: PHY controller block
123 * @clks: PCIe clocks
124 * @num_clks: PCIe clocks count for this port
125 * @irq: PCIe controller interrupt number
126 * @saved_irq_state: IRQ enable state saved at suspend time
127 * @irq_lock: lock protecting IRQ register access
128 * @intx_domain: legacy INTx IRQ domain
129 * @msi_domain: MSI IRQ domain
130 * @msi_bottom_domain: MSI IRQ bottom domain
131 * @msi_sets: MSI sets information
132 * @lock: lock protecting IRQ bit map
133 * @msi_irq_in_use: bit map for assigned MSI IRQ
134 */
135struct mtk_gen3_pcie {
136 struct device *dev;
137 void __iomem *base;
138 phys_addr_t reg_base;
139 struct reset_control *mac_reset;
140 struct reset_control *phy_reset;
141 struct phy *phy;
142 struct clk_bulk_data *clks;
143 int num_clks;
144
145 int irq;
146 u32 saved_irq_state;
147 raw_spinlock_t irq_lock;
148 struct irq_domain *intx_domain;
149 struct irq_domain *msi_domain;
150 struct irq_domain *msi_bottom_domain;
151 struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
152 struct mutex lock;
153 DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
154};
155
156/* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */
157static const char *const ltssm_str[] = {
158 "detect.quiet", /* 0x00 */
159 "detect.active", /* 0x01 */
160 "polling.active", /* 0x02 */
161 "polling.compliance", /* 0x03 */
162 "polling.configuration", /* 0x04 */
163 "config.linkwidthstart", /* 0x05 */
164 "config.linkwidthaccept", /* 0x06 */
165 "config.lanenumwait", /* 0x07 */
166 "config.lanenumaccept", /* 0x08 */
167 "config.complete", /* 0x09 */
168 "config.idle", /* 0x0A */
169 "recovery.receiverlock", /* 0x0B */
170 "recovery.equalization", /* 0x0C */
171 "recovery.speed", /* 0x0D */
172 "recovery.receiverconfig", /* 0x0E */
173 "recovery.idle", /* 0x0F */
174 "L0", /* 0x10 */
175 "L0s", /* 0x11 */
176 "L1.entry", /* 0x12 */
177 "L1.idle", /* 0x13 */
178 "L2.idle", /* 0x14 */
179 "L2.transmitwake", /* 0x15 */
180 "disable", /* 0x16 */
181 "loopback.entry", /* 0x17 */
182 "loopback.active", /* 0x18 */
183 "loopback.exit", /* 0x19 */
184 "hotreset", /* 0x1A */
185};
186
187/**
188 * mtk_pcie_config_tlp_header() - Configure a configuration TLP header
189 * @bus: PCI bus to query
190 * @devfn: device/function number
191 * @where: offset in config space
192 * @size: data size in TLP header
193 *
194 * Set byte enable field and device information in configuration TLP header.
195 */
196static void mtk_pcie_config_tlp_header(struct pci_bus *bus, unsigned int devfn,
197 int where, int size)
198{
199 struct mtk_gen3_pcie *pcie = bus->sysdata;
200 int bytes;
201 u32 val;
202
203 bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3);
204
205 val = PCIE_CFG_FORCE_BYTE_EN | PCIE_CFG_BYTE_EN(bytes) |
206 PCIE_CFG_HEADER(bus->number, devfn);
207
208 writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG);
209}
210
211static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
212 int where)
213{
214 struct mtk_gen3_pcie *pcie = bus->sysdata;
215
216 return pcie->base + PCIE_CFG_OFFSET_ADDR + where;
217}
218
219static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
220 int where, int size, u32 *val)
221{
222 mtk_pcie_config_tlp_header(bus, devfn, where, size);
223
224 return pci_generic_config_read32(bus, devfn, where, size, val);
225}
226
227static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
228 int where, int size, u32 val)
229{
230 mtk_pcie_config_tlp_header(bus, devfn, where, size);
231
232 if (size <= 2)
233 val <<= (where & 0x3) * 8;
234
235 return pci_generic_config_write32(bus, devfn, where, 4, val);
236}
237
238static struct pci_ops mtk_pcie_ops = {
239 .map_bus = mtk_pcie_map_bus,
240 .read = mtk_pcie_config_read,
241 .write = mtk_pcie_config_write,
242};
243
244static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie,
245 resource_size_t cpu_addr,
246 resource_size_t pci_addr,
247 resource_size_t size,
248 unsigned long type, int num)
249{
250 void __iomem *table;
251 u32 val;
252
253 if (num >= PCIE_MAX_TRANS_TABLES) {
254 dev_err(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n",
255 (unsigned long long)cpu_addr, PCIE_MAX_TRANS_TABLES);
256 return -ENODEV;
257 }
258
259 table = pcie->base + PCIE_TRANS_TABLE_BASE_REG +
260 num * PCIE_ATR_TLB_SET_OFFSET;
261
262 writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(size) - 1),
263 table);
264 writel_relaxed(upper_32_bits(cpu_addr),
265 table + PCIE_ATR_SRC_ADDR_MSB_OFFSET);
266 writel_relaxed(lower_32_bits(pci_addr),
267 table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET);
268 writel_relaxed(upper_32_bits(pci_addr),
269 table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET);
270
271 if (type == IORESOURCE_IO)
272 val = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO;
273 else
274 val = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM;
275
276 writel_relaxed(val, table + PCIE_ATR_TRSL_PARAM_OFFSET);
277
278 return 0;
279}
280
281static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie)
282{
283 int i;
284 u32 val;
285
286 for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
287 struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
288
289 msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG +
290 i * PCIE_MSI_SET_OFFSET;
291 msi_set->msg_addr = pcie->reg_base + PCIE_MSI_SET_BASE_REG +
292 i * PCIE_MSI_SET_OFFSET;
293
294 /* Configure the MSI capture address */
295 writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base);
296 writel_relaxed(upper_32_bits(msi_set->msg_addr),
297 pcie->base + PCIE_MSI_SET_ADDR_HI_BASE +
298 i * PCIE_MSI_SET_ADDR_HI_OFFSET);
299 }
300
301 val = readl_relaxed(pcie->base + PCIE_MSI_SET_ENABLE_REG);
302 val |= PCIE_MSI_SET_ENABLE;
303 writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG);
304
305 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
306 val |= PCIE_MSI_ENABLE;
307 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
308}
309
310static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
311{
312 struct resource_entry *entry;
313 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
314 unsigned int table_index = 0;
315 int err;
316 u32 val;
317
318 /* Set as RC mode */
319 val = readl_relaxed(pcie->base + PCIE_SETTING_REG);
320 val |= PCIE_RC_MODE;
321 writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
322
323 /* Set class code */
324 val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1);
325 val &= ~GENMASK(31, 8);
326 val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI_NORMAL);
327 writel_relaxed(val, pcie->base + PCIE_PCI_IDS_1);
328
329 /* Mask all INTx interrupts */
330 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
331 val &= ~PCIE_INTX_ENABLE;
332 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
333
334 /* Disable DVFSRC voltage request */
335 val = readl_relaxed(pcie->base + PCIE_MISC_CTRL_REG);
336 val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
337 writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG);
338
339 /* Assert all reset signals */
340 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
341 val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
342 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
343
344 /*
345 * Described in PCIe CEM specification sections 2.2 (PERST# Signal)
346 * and 2.2.1 (Initial Power-Up (G3 to S0)).
347 * The deassertion of PERST# should be delayed 100ms (TPVPERL)
348 * for the power and clock to become stable.
349 */
350 msleep(100);
351
352 /* De-assert reset signals */
353 val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
354 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
355
356 /* Check if the link is up or not */
357 err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
358 !!(val & PCIE_PORT_LINKUP), 20,
359 PCI_PM_D3COLD_WAIT * USEC_PER_MSEC);
360 if (err) {
361 const char *ltssm_state;
362 int ltssm_index;
363
364 val = readl_relaxed(pcie->base + PCIE_LTSSM_STATUS_REG);
365 ltssm_index = PCIE_LTSSM_STATE(val);
366 ltssm_state = ltssm_index >= ARRAY_SIZE(ltssm_str) ?
367 "Unknown state" : ltssm_str[ltssm_index];
368 dev_err(pcie->dev,
369 "PCIe link down, current LTSSM state: %s (%#x)\n",
370 ltssm_state, val);
371 return err;
372 }
373
374 mtk_pcie_enable_msi(pcie);
375
376 /* Set PCIe translation windows */
377 resource_list_for_each_entry(entry, &host->windows) {
378 struct resource *res = entry->res;
379 unsigned long type = resource_type(res);
380 resource_size_t cpu_addr;
381 resource_size_t pci_addr;
382 resource_size_t size;
383 const char *range_type;
384
385 if (type == IORESOURCE_IO) {
386 cpu_addr = pci_pio_to_address(res->start);
387 range_type = "IO";
388 } else if (type == IORESOURCE_MEM) {
389 cpu_addr = res->start;
390 range_type = "MEM";
391 } else {
392 continue;
393 }
394
395 pci_addr = res->start - entry->offset;
396 size = resource_size(res);
397 err = mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size,
398 type, table_index);
399 if (err)
400 return err;
401
402 dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n",
403 range_type, table_index, (unsigned long long)cpu_addr,
404 (unsigned long long)pci_addr, (unsigned long long)size);
405
406 table_index++;
407 }
408
409 return 0;
410}
411
412static int mtk_pcie_set_affinity(struct irq_data *data,
413 const struct cpumask *mask, bool force)
414{
415 return -EINVAL;
416}
417
418static void mtk_pcie_msi_irq_mask(struct irq_data *data)
419{
420 pci_msi_mask_irq(data);
421 irq_chip_mask_parent(data);
422}
423
424static void mtk_pcie_msi_irq_unmask(struct irq_data *data)
425{
426 pci_msi_unmask_irq(data);
427 irq_chip_unmask_parent(data);
428}
429
430static struct irq_chip mtk_msi_irq_chip = {
431 .irq_ack = irq_chip_ack_parent,
432 .irq_mask = mtk_pcie_msi_irq_mask,
433 .irq_unmask = mtk_pcie_msi_irq_unmask,
434 .name = "MSI",
435};
436
437static struct msi_domain_info mtk_msi_domain_info = {
438 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
439 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
440 .chip = &mtk_msi_irq_chip,
441};
442
443static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
444{
445 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
446 struct mtk_gen3_pcie *pcie = data->domain->host_data;
447 unsigned long hwirq;
448
449 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
450
451 msg->address_hi = upper_32_bits(msi_set->msg_addr);
452 msg->address_lo = lower_32_bits(msi_set->msg_addr);
453 msg->data = hwirq;
454 dev_dbg(pcie->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n",
455 hwirq, msg->address_hi, msg->address_lo, msg->data);
456}
457
458static void mtk_msi_bottom_irq_ack(struct irq_data *data)
459{
460 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
461 unsigned long hwirq;
462
463 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
464
465 writel_relaxed(BIT(hwirq), msi_set->base + PCIE_MSI_SET_STATUS_OFFSET);
466}
467
468static void mtk_msi_bottom_irq_mask(struct irq_data *data)
469{
470 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
471 struct mtk_gen3_pcie *pcie = data->domain->host_data;
472 unsigned long hwirq, flags;
473 u32 val;
474
475 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
476
477 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
478 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
479 val &= ~BIT(hwirq);
480 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
481 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
482}
483
484static void mtk_msi_bottom_irq_unmask(struct irq_data *data)
485{
486 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
487 struct mtk_gen3_pcie *pcie = data->domain->host_data;
488 unsigned long hwirq, flags;
489 u32 val;
490
491 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
492
493 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
494 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
495 val |= BIT(hwirq);
496 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
497 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
498}
499
500static struct irq_chip mtk_msi_bottom_irq_chip = {
501 .irq_ack = mtk_msi_bottom_irq_ack,
502 .irq_mask = mtk_msi_bottom_irq_mask,
503 .irq_unmask = mtk_msi_bottom_irq_unmask,
504 .irq_compose_msi_msg = mtk_compose_msi_msg,
505 .irq_set_affinity = mtk_pcie_set_affinity,
506 .name = "MSI",
507};
508
509static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain,
510 unsigned int virq, unsigned int nr_irqs,
511 void *arg)
512{
513 struct mtk_gen3_pcie *pcie = domain->host_data;
514 struct mtk_msi_set *msi_set;
515 int i, hwirq, set_idx;
516
517 mutex_lock(&pcie->lock);
518
519 hwirq = bitmap_find_free_region(pcie->msi_irq_in_use, PCIE_MSI_IRQS_NUM,
520 order_base_2(nr_irqs));
521
522 mutex_unlock(&pcie->lock);
523
524 if (hwirq < 0)
525 return -ENOSPC;
526
527 set_idx = hwirq / PCIE_MSI_IRQS_PER_SET;
528 msi_set = &pcie->msi_sets[set_idx];
529
530 for (i = 0; i < nr_irqs; i++)
531 irq_domain_set_info(domain, virq + i, hwirq + i,
532 &mtk_msi_bottom_irq_chip, msi_set,
533 handle_edge_irq, NULL, NULL);
534
535 return 0;
536}
537
538static void mtk_msi_bottom_domain_free(struct irq_domain *domain,
539 unsigned int virq, unsigned int nr_irqs)
540{
541 struct mtk_gen3_pcie *pcie = domain->host_data;
542 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
543
544 mutex_lock(&pcie->lock);
545
546 bitmap_release_region(pcie->msi_irq_in_use, data->hwirq,
547 order_base_2(nr_irqs));
548
549 mutex_unlock(&pcie->lock);
550
551 irq_domain_free_irqs_common(domain, virq, nr_irqs);
552}
553
554static const struct irq_domain_ops mtk_msi_bottom_domain_ops = {
555 .alloc = mtk_msi_bottom_domain_alloc,
556 .free = mtk_msi_bottom_domain_free,
557};
558
559static void mtk_intx_mask(struct irq_data *data)
560{
561 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
562 unsigned long flags;
563 u32 val;
564
565 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
566 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
567 val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT);
568 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
569 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
570}
571
572static void mtk_intx_unmask(struct irq_data *data)
573{
574 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
575 unsigned long flags;
576 u32 val;
577
578 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
579 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
580 val |= BIT(data->hwirq + PCIE_INTX_SHIFT);
581 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
582 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
583}
584
585/**
586 * mtk_intx_eoi() - Clear INTx IRQ status at the end of interrupt
587 * @data: pointer to chip specific data
588 *
589 * As an emulated level IRQ, its interrupt status will remain
590 * until the corresponding de-assert message is received; hence that
591 * the status can only be cleared when the interrupt has been serviced.
592 */
593static void mtk_intx_eoi(struct irq_data *data)
594{
595 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
596 unsigned long hwirq;
597
598 hwirq = data->hwirq + PCIE_INTX_SHIFT;
599 writel_relaxed(BIT(hwirq), pcie->base + PCIE_INT_STATUS_REG);
600}
601
602static struct irq_chip mtk_intx_irq_chip = {
603 .irq_mask = mtk_intx_mask,
604 .irq_unmask = mtk_intx_unmask,
605 .irq_eoi = mtk_intx_eoi,
606 .irq_set_affinity = mtk_pcie_set_affinity,
607 .name = "INTx",
608};
609
610static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
611 irq_hw_number_t hwirq)
612{
613 irq_set_chip_data(irq, domain->host_data);
614 irq_set_chip_and_handler_name(irq, &mtk_intx_irq_chip,
615 handle_fasteoi_irq, "INTx");
616 return 0;
617}
618
619static const struct irq_domain_ops intx_domain_ops = {
620 .map = mtk_pcie_intx_map,
621};
622
623static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie)
624{
625 struct device *dev = pcie->dev;
626 struct device_node *intc_node, *node = dev->of_node;
627 int ret;
628
629 raw_spin_lock_init(&pcie->irq_lock);
630
631 /* Setup INTx */
632 intc_node = of_get_child_by_name(node, "interrupt-controller");
633 if (!intc_node) {
634 dev_err(dev, "missing interrupt-controller node\n");
635 return -ENODEV;
636 }
637
638 pcie->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX,
639 &intx_domain_ops, pcie);
640 if (!pcie->intx_domain) {
641 dev_err(dev, "failed to create INTx IRQ domain\n");
642 ret = -ENODEV;
643 goto out_put_node;
644 }
645
646 /* Setup MSI */
647 mutex_init(&pcie->lock);
648
649 pcie->msi_bottom_domain = irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM,
650 &mtk_msi_bottom_domain_ops, pcie);
651 if (!pcie->msi_bottom_domain) {
652 dev_err(dev, "failed to create MSI bottom domain\n");
653 ret = -ENODEV;
654 goto err_msi_bottom_domain;
655 }
656
657 pcie->msi_domain = pci_msi_create_irq_domain(dev->fwnode,
658 &mtk_msi_domain_info,
659 pcie->msi_bottom_domain);
660 if (!pcie->msi_domain) {
661 dev_err(dev, "failed to create MSI domain\n");
662 ret = -ENODEV;
663 goto err_msi_domain;
664 }
665
666 of_node_put(intc_node);
667 return 0;
668
669err_msi_domain:
670 irq_domain_remove(pcie->msi_bottom_domain);
671err_msi_bottom_domain:
672 irq_domain_remove(pcie->intx_domain);
673out_put_node:
674 of_node_put(intc_node);
675 return ret;
676}
677
678static void mtk_pcie_irq_teardown(struct mtk_gen3_pcie *pcie)
679{
680 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
681
682 if (pcie->intx_domain)
683 irq_domain_remove(pcie->intx_domain);
684
685 if (pcie->msi_domain)
686 irq_domain_remove(pcie->msi_domain);
687
688 if (pcie->msi_bottom_domain)
689 irq_domain_remove(pcie->msi_bottom_domain);
690
691 irq_dispose_mapping(pcie->irq);
692}
693
694static void mtk_pcie_msi_handler(struct mtk_gen3_pcie *pcie, int set_idx)
695{
696 struct mtk_msi_set *msi_set = &pcie->msi_sets[set_idx];
697 unsigned long msi_enable, msi_status;
698 irq_hw_number_t bit, hwirq;
699
700 msi_enable = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
701
702 do {
703 msi_status = readl_relaxed(msi_set->base +
704 PCIE_MSI_SET_STATUS_OFFSET);
705 msi_status &= msi_enable;
706 if (!msi_status)
707 break;
708
709 for_each_set_bit(bit, &msi_status, PCIE_MSI_IRQS_PER_SET) {
710 hwirq = bit + set_idx * PCIE_MSI_IRQS_PER_SET;
711 generic_handle_domain_irq(pcie->msi_bottom_domain, hwirq);
712 }
713 } while (true);
714}
715
716static void mtk_pcie_irq_handler(struct irq_desc *desc)
717{
718 struct mtk_gen3_pcie *pcie = irq_desc_get_handler_data(desc);
719 struct irq_chip *irqchip = irq_desc_get_chip(desc);
720 unsigned long status;
721 irq_hw_number_t irq_bit = PCIE_INTX_SHIFT;
722
723 chained_irq_enter(irqchip, desc);
724
725 status = readl_relaxed(pcie->base + PCIE_INT_STATUS_REG);
726 for_each_set_bit_from(irq_bit, &status, PCI_NUM_INTX +
727 PCIE_INTX_SHIFT)
728 generic_handle_domain_irq(pcie->intx_domain,
729 irq_bit - PCIE_INTX_SHIFT);
730
731 irq_bit = PCIE_MSI_SHIFT;
732 for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM +
733 PCIE_MSI_SHIFT) {
734 mtk_pcie_msi_handler(pcie, irq_bit - PCIE_MSI_SHIFT);
735
736 writel_relaxed(BIT(irq_bit), pcie->base + PCIE_INT_STATUS_REG);
737 }
738
739 chained_irq_exit(irqchip, desc);
740}
741
742static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *pcie)
743{
744 struct device *dev = pcie->dev;
745 struct platform_device *pdev = to_platform_device(dev);
746 int err;
747
748 err = mtk_pcie_init_irq_domains(pcie);
749 if (err)
750 return err;
751
752 pcie->irq = platform_get_irq(pdev, 0);
753 if (pcie->irq < 0)
754 return pcie->irq;
755
756 irq_set_chained_handler_and_data(pcie->irq, mtk_pcie_irq_handler, pcie);
757
758 return 0;
759}
760
761static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
762{
763 struct device *dev = pcie->dev;
764 struct platform_device *pdev = to_platform_device(dev);
765 struct resource *regs;
766 int ret;
767
768 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
769 if (!regs)
770 return -EINVAL;
771 pcie->base = devm_ioremap_resource(dev, regs);
772 if (IS_ERR(pcie->base)) {
773 dev_err(dev, "failed to map register base\n");
774 return PTR_ERR(pcie->base);
775 }
776
777 pcie->reg_base = regs->start;
778
779 pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
780 if (IS_ERR(pcie->phy_reset)) {
781 ret = PTR_ERR(pcie->phy_reset);
782 if (ret != -EPROBE_DEFER)
783 dev_err(dev, "failed to get PHY reset\n");
784
785 return ret;
786 }
787
788 pcie->mac_reset = devm_reset_control_get_optional_exclusive(dev, "mac");
789 if (IS_ERR(pcie->mac_reset)) {
790 ret = PTR_ERR(pcie->mac_reset);
791 if (ret != -EPROBE_DEFER)
792 dev_err(dev, "failed to get MAC reset\n");
793
794 return ret;
795 }
796
797 pcie->phy = devm_phy_optional_get(dev, "pcie-phy");
798 if (IS_ERR(pcie->phy)) {
799 ret = PTR_ERR(pcie->phy);
800 if (ret != -EPROBE_DEFER)
801 dev_err(dev, "failed to get PHY\n");
802
803 return ret;
804 }
805
806 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks);
807 if (pcie->num_clks < 0) {
808 dev_err(dev, "failed to get clocks\n");
809 return pcie->num_clks;
810 }
811
812 return 0;
813}
814
815static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
816{
817 struct device *dev = pcie->dev;
818 int err;
819
820 /* PHY power on and enable pipe clock */
821 reset_control_deassert(pcie->phy_reset);
822
823 err = phy_init(pcie->phy);
824 if (err) {
825 dev_err(dev, "failed to initialize PHY\n");
826 goto err_phy_init;
827 }
828
829 err = phy_power_on(pcie->phy);
830 if (err) {
831 dev_err(dev, "failed to power on PHY\n");
832 goto err_phy_on;
833 }
834
835 /* MAC power on and enable transaction layer clocks */
836 reset_control_deassert(pcie->mac_reset);
837
838 pm_runtime_enable(dev);
839 pm_runtime_get_sync(dev);
840
841 err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
842 if (err) {
843 dev_err(dev, "failed to enable clocks\n");
844 goto err_clk_init;
845 }
846
847 return 0;
848
849err_clk_init:
850 pm_runtime_put_sync(dev);
851 pm_runtime_disable(dev);
852 reset_control_assert(pcie->mac_reset);
853 phy_power_off(pcie->phy);
854err_phy_on:
855 phy_exit(pcie->phy);
856err_phy_init:
857 reset_control_assert(pcie->phy_reset);
858
859 return err;
860}
861
862static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
863{
864 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
865
866 pm_runtime_put_sync(pcie->dev);
867 pm_runtime_disable(pcie->dev);
868 reset_control_assert(pcie->mac_reset);
869
870 phy_power_off(pcie->phy);
871 phy_exit(pcie->phy);
872 reset_control_assert(pcie->phy_reset);
873}
874
875static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
876{
877 int err;
878
879 err = mtk_pcie_parse_port(pcie);
880 if (err)
881 return err;
882
883 /*
884 * The controller may have been left out of reset by the bootloader
885 * so make sure that we get a clean start by asserting resets here.
886 */
887 reset_control_assert(pcie->phy_reset);
888 reset_control_assert(pcie->mac_reset);
889 usleep_range(10, 20);
890
891 /* Don't touch the hardware registers before power up */
892 err = mtk_pcie_power_up(pcie);
893 if (err)
894 return err;
895
896 /* Try link up */
897 err = mtk_pcie_startup_port(pcie);
898 if (err)
899 goto err_setup;
900
901 err = mtk_pcie_setup_irq(pcie);
902 if (err)
903 goto err_setup;
904
905 return 0;
906
907err_setup:
908 mtk_pcie_power_down(pcie);
909
910 return err;
911}
912
913static int mtk_pcie_probe(struct platform_device *pdev)
914{
915 struct device *dev = &pdev->dev;
916 struct mtk_gen3_pcie *pcie;
917 struct pci_host_bridge *host;
918 int err;
919
920 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
921 if (!host)
922 return -ENOMEM;
923
924 pcie = pci_host_bridge_priv(host);
925
926 pcie->dev = dev;
927 platform_set_drvdata(pdev, pcie);
928
929 err = mtk_pcie_setup(pcie);
930 if (err)
931 return err;
932
933 host->ops = &mtk_pcie_ops;
934 host->sysdata = pcie;
935
936 err = pci_host_probe(host);
937 if (err) {
938 mtk_pcie_irq_teardown(pcie);
939 mtk_pcie_power_down(pcie);
940 return err;
941 }
942
943 return 0;
944}
945
946static int mtk_pcie_remove(struct platform_device *pdev)
947{
948 struct mtk_gen3_pcie *pcie = platform_get_drvdata(pdev);
949 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
950
951 pci_lock_rescan_remove();
952 pci_stop_root_bus(host->bus);
953 pci_remove_root_bus(host->bus);
954 pci_unlock_rescan_remove();
955
956 mtk_pcie_irq_teardown(pcie);
957 mtk_pcie_power_down(pcie);
958
959 return 0;
960}
961
962static void mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie)
963{
964 int i;
965
966 raw_spin_lock(&pcie->irq_lock);
967
968 pcie->saved_irq_state = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
969
970 for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
971 struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
972
973 msi_set->saved_irq_state = readl_relaxed(msi_set->base +
974 PCIE_MSI_SET_ENABLE_OFFSET);
975 }
976
977 raw_spin_unlock(&pcie->irq_lock);
978}
979
980static void mtk_pcie_irq_restore(struct mtk_gen3_pcie *pcie)
981{
982 int i;
983
984 raw_spin_lock(&pcie->irq_lock);
985
986 writel_relaxed(pcie->saved_irq_state, pcie->base + PCIE_INT_ENABLE_REG);
987
988 for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
989 struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
990
991 writel_relaxed(msi_set->saved_irq_state,
992 msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
993 }
994
995 raw_spin_unlock(&pcie->irq_lock);
996}
997
998static int mtk_pcie_turn_off_link(struct mtk_gen3_pcie *pcie)
999{
1000 u32 val;
1001
1002 val = readl_relaxed(pcie->base + PCIE_ICMD_PM_REG);
1003 val |= PCIE_TURN_OFF_LINK;
1004 writel_relaxed(val, pcie->base + PCIE_ICMD_PM_REG);
1005
1006 /* Check the link is L2 */
1007 return readl_poll_timeout(pcie->base + PCIE_LTSSM_STATUS_REG, val,
1008 (PCIE_LTSSM_STATE(val) ==
1009 PCIE_LTSSM_STATE_L2_IDLE), 20,
1010 50 * USEC_PER_MSEC);
1011}
1012
1013static int mtk_pcie_suspend_noirq(struct device *dev)
1014{
1015 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
1016 int err;
1017 u32 val;
1018
1019 /* Trigger link to L2 state */
1020 err = mtk_pcie_turn_off_link(pcie);
1021 if (err) {
1022 dev_err(pcie->dev, "cannot enter L2 state\n");
1023 return err;
1024 }
1025
1026 /* Pull down the PERST# pin */
1027 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
1028 val |= PCIE_PE_RSTB;
1029 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
1030
1031 dev_dbg(pcie->dev, "entered L2 states successfully");
1032
1033 mtk_pcie_irq_save(pcie);
1034 mtk_pcie_power_down(pcie);
1035
1036 return 0;
1037}
1038
1039static int mtk_pcie_resume_noirq(struct device *dev)
1040{
1041 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
1042 int err;
1043
1044 err = mtk_pcie_power_up(pcie);
1045 if (err)
1046 return err;
1047
1048 err = mtk_pcie_startup_port(pcie);
1049 if (err) {
1050 mtk_pcie_power_down(pcie);
1051 return err;
1052 }
1053
1054 mtk_pcie_irq_restore(pcie);
1055
1056 return 0;
1057}
1058
1059static const struct dev_pm_ops mtk_pcie_pm_ops = {
1060 NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1061 mtk_pcie_resume_noirq)
1062};
1063
1064static const struct of_device_id mtk_pcie_of_match[] = {
1065 { .compatible = "mediatek,mt8192-pcie" },
1066 {},
1067};
1068MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
1069
1070static struct platform_driver mtk_pcie_driver = {
1071 .probe = mtk_pcie_probe,
1072 .remove = mtk_pcie_remove,
1073 .driver = {
1074 .name = "mtk-pcie-gen3",
1075 .of_match_table = mtk_pcie_of_match,
1076 .pm = &mtk_pcie_pm_ops,
1077 },
1078};
1079
1080module_platform_driver(mtk_pcie_driver);
1081MODULE_LICENSE("GPL v2");