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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Qualcomm PCIe Endpoint controller driver
4 *
5 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org
7 *
8 * Copyright (c) 2021, Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org
10 */
11
12#include <linux/clk.h>
13#include <linux/debugfs.h>
14#include <linux/delay.h>
15#include <linux/gpio/consumer.h>
16#include <linux/interconnect.h>
17#include <linux/mfd/syscon.h>
18#include <linux/phy/pcie.h>
19#include <linux/phy/phy.h>
20#include <linux/platform_device.h>
21#include <linux/pm_domain.h>
22#include <linux/regmap.h>
23#include <linux/reset.h>
24#include <linux/module.h>
25
26#include "../../pci.h"
27#include "pcie-designware.h"
28#include "pcie-qcom-common.h"
29
30/* PARF registers */
31#define PARF_SYS_CTRL 0x00
32#define PARF_DB_CTRL 0x10
33#define PARF_PM_CTRL 0x20
34#define PARF_MHI_CLOCK_RESET_CTRL 0x174
35#define PARF_MHI_BASE_ADDR_LOWER 0x178
36#define PARF_MHI_BASE_ADDR_UPPER 0x17c
37#define PARF_DEBUG_INT_EN 0x190
38#define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4
39#define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8
40#define PARF_Q2A_FLUSH 0x1ac
41#define PARF_LTSSM 0x1b0
42#define PARF_CFG_BITS 0x210
43#define PARF_INT_ALL_STATUS 0x224
44#define PARF_INT_ALL_CLEAR 0x228
45#define PARF_INT_ALL_MASK 0x22c
46#define PARF_SLV_ADDR_MSB_CTRL 0x2c0
47#define PARF_DBI_BASE_ADDR 0x350
48#define PARF_DBI_BASE_ADDR_HI 0x354
49#define PARF_SLV_ADDR_SPACE_SIZE 0x358
50#define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c
51#define PARF_NO_SNOOP_OVERIDE 0x3d4
52#define PARF_ATU_BASE_ADDR 0x634
53#define PARF_ATU_BASE_ADDR_HI 0x638
54#define PARF_SRIS_MODE 0x644
55#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
56#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c
57#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10
58#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84
59#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88
60#define PARF_DEVICE_TYPE 0x1000
61#define PARF_BDF_TO_SID_CFG 0x2c00
62#define PARF_INT_ALL_5_MASK 0x2dcc
63
64/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
65#define PARF_INT_ALL_LINK_DOWN BIT(1)
66#define PARF_INT_ALL_BME BIT(2)
67#define PARF_INT_ALL_PM_TURNOFF BIT(3)
68#define PARF_INT_ALL_DEBUG BIT(4)
69#define PARF_INT_ALL_LTR BIT(5)
70#define PARF_INT_ALL_MHI_Q6 BIT(6)
71#define PARF_INT_ALL_MHI_A7 BIT(7)
72#define PARF_INT_ALL_DSTATE_CHANGE BIT(8)
73#define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9)
74#define PARF_INT_ALL_MMIO_WRITE BIT(10)
75#define PARF_INT_ALL_CFG_WRITE BIT(11)
76#define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12)
77#define PARF_INT_ALL_LINK_UP BIT(13)
78#define PARF_INT_ALL_AER_LEGACY BIT(14)
79#define PARF_INT_ALL_PLS_ERR BIT(15)
80#define PARF_INT_ALL_PME_LEGACY BIT(16)
81#define PARF_INT_ALL_PLS_PME BIT(17)
82#define PARF_INT_ALL_EDMA BIT(22)
83
84/* PARF_BDF_TO_SID_CFG register fields */
85#define PARF_BDF_TO_SID_BYPASS BIT(0)
86
87/* PARF_DEBUG_INT_EN register fields */
88#define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1)
89#define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2)
90#define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3)
91
92/* PARF_NO_SNOOP_OVERIDE register fields */
93#define WR_NO_SNOOP_OVERIDE_EN BIT(1)
94#define RD_NO_SNOOP_OVERIDE_EN BIT(3)
95
96/* PARF_DEVICE_TYPE register fields */
97#define PARF_DEVICE_TYPE_EP 0x0
98
99/* PARF_PM_CTRL register fields */
100#define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1)
101#define PARF_PM_CTRL_READY_ENTR_L23 BIT(2)
102#define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5)
103
104/* PARF_MHI_CLOCK_RESET_CTRL fields */
105#define PARF_MSTR_AXI_CLK_EN BIT(1)
106
107/* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */
108#define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0)
109
110/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
111#define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31)
112
113/* PARF_Q2A_FLUSH register fields */
114#define PARF_Q2A_FLUSH_EN BIT(16)
115
116/* PARF_SYS_CTRL register fields */
117#define PARF_SYS_CTRL_AUX_PWR_DET BIT(4)
118#define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6)
119#define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10)
120#define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11)
121
122/* PARF_DB_CTRL register fields */
123#define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0)
124#define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1)
125#define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4)
126#define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5)
127#define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6)
128
129/* PARF_CFG_BITS register fields */
130#define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1)
131
132/* PARF_INT_ALL_5_MASK fields */
133#define PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR BIT(0)
134
135/* ELBI registers */
136#define ELBI_SYS_STTS 0x08
137#define ELBI_CS2_ENABLE 0xa4
138
139/* DBI registers */
140#define DBI_CON_STATUS 0x44
141
142/* DBI register fields */
143#define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0)
144
145#define XMLH_LINK_UP 0x400
146#define CORE_RESET_TIME_US_MIN 1000
147#define CORE_RESET_TIME_US_MAX 1005
148#define WAKE_DELAY_US 2000 /* 2 ms */
149
150#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \
151 Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]))
152
153#define to_pcie_ep(x) dev_get_drvdata((x)->dev)
154
155enum qcom_pcie_ep_link_status {
156 QCOM_PCIE_EP_LINK_DISABLED,
157 QCOM_PCIE_EP_LINK_ENABLED,
158 QCOM_PCIE_EP_LINK_UP,
159 QCOM_PCIE_EP_LINK_DOWN,
160};
161
162/**
163 * struct qcom_pcie_ep_cfg - Per SoC config struct
164 * @hdma_support: HDMA support on this SoC
165 * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping
166 * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check
167 */
168struct qcom_pcie_ep_cfg {
169 bool hdma_support;
170 bool override_no_snoop;
171 bool disable_mhi_ram_parity_check;
172};
173
174/**
175 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
176 * @pci: Designware PCIe controller struct
177 * @parf: Qualcomm PCIe specific PARF register base
178 * @elbi: Designware PCIe specific ELBI register base
179 * @mmio: MMIO register base
180 * @perst_map: PERST regmap
181 * @mmio_res: MMIO region resource
182 * @core_reset: PCIe Endpoint core reset
183 * @reset: PERST# GPIO
184 * @wake: WAKE# GPIO
185 * @phy: PHY controller block
186 * @debugfs: PCIe Endpoint Debugfs directory
187 * @icc_mem: Handle to an interconnect path between PCIe and MEM
188 * @clks: PCIe clocks
189 * @num_clks: PCIe clocks count
190 * @perst_en: Flag for PERST enable
191 * @perst_sep_en: Flag for PERST separation enable
192 * @cfg: PCIe EP config struct
193 * @link_status: PCIe Link status
194 * @global_irq: Qualcomm PCIe specific Global IRQ
195 * @perst_irq: PERST# IRQ
196 */
197struct qcom_pcie_ep {
198 struct dw_pcie pci;
199
200 void __iomem *parf;
201 void __iomem *elbi;
202 void __iomem *mmio;
203 struct regmap *perst_map;
204 struct resource *mmio_res;
205
206 struct reset_control *core_reset;
207 struct gpio_desc *reset;
208 struct gpio_desc *wake;
209 struct phy *phy;
210 struct dentry *debugfs;
211
212 struct icc_path *icc_mem;
213
214 struct clk_bulk_data *clks;
215 int num_clks;
216
217 u32 perst_en;
218 u32 perst_sep_en;
219
220 const struct qcom_pcie_ep_cfg *cfg;
221 enum qcom_pcie_ep_link_status link_status;
222 int global_irq;
223 int perst_irq;
224};
225
226static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep)
227{
228 struct dw_pcie *pci = &pcie_ep->pci;
229 struct device *dev = pci->dev;
230 int ret;
231
232 ret = reset_control_assert(pcie_ep->core_reset);
233 if (ret) {
234 dev_err(dev, "Cannot assert core reset\n");
235 return ret;
236 }
237
238 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
239
240 ret = reset_control_deassert(pcie_ep->core_reset);
241 if (ret) {
242 dev_err(dev, "Cannot de-assert core reset\n");
243 return ret;
244 }
245
246 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
247
248 return 0;
249}
250
251/*
252 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid
253 * device reset during host reboot and hibernation. The driver is
254 * expected to handle this situation.
255 */
256static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep)
257{
258 if (pcie_ep->perst_map) {
259 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0);
260 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0);
261 }
262}
263
264static int qcom_pcie_dw_link_up(struct dw_pcie *pci)
265{
266 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
267 u32 reg;
268
269 reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS);
270
271 return reg & XMLH_LINK_UP;
272}
273
274static int qcom_pcie_dw_start_link(struct dw_pcie *pci)
275{
276 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
277
278 enable_irq(pcie_ep->perst_irq);
279
280 return 0;
281}
282
283static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)
284{
285 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
286
287 disable_irq(pcie_ep->perst_irq);
288}
289
290static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base,
291 u32 reg, size_t size, u32 val)
292{
293 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
294 int ret;
295
296 writel(1, pcie_ep->elbi + ELBI_CS2_ENABLE);
297
298 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
299 if (ret)
300 dev_err(pci->dev, "Failed to write DBI2 register (0x%x): %d\n", reg, ret);
301
302 writel(0, pcie_ep->elbi + ELBI_CS2_ENABLE);
303}
304
305static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)
306{
307 struct dw_pcie *pci = &pcie_ep->pci;
308 u32 offset, status;
309 int speed, width;
310 int ret;
311
312 if (!pcie_ep->icc_mem)
313 return;
314
315 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
316 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
317
318 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
319 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
320
321 ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
322 if (ret)
323 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
324 ret);
325}
326
327static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
328{
329 struct dw_pcie *pci = &pcie_ep->pci;
330 int ret;
331
332 ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks);
333 if (ret)
334 return ret;
335
336 ret = qcom_pcie_ep_core_reset(pcie_ep);
337 if (ret)
338 goto err_disable_clk;
339
340 ret = phy_init(pcie_ep->phy);
341 if (ret)
342 goto err_disable_clk;
343
344 ret = phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP);
345 if (ret)
346 goto err_phy_exit;
347
348 ret = phy_power_on(pcie_ep->phy);
349 if (ret)
350 goto err_phy_exit;
351
352 /*
353 * Some Qualcomm platforms require interconnect bandwidth constraints
354 * to be set before enabling interconnect clocks.
355 *
356 * Set an initial peak bandwidth corresponding to single-lane Gen 1
357 * for the pcie-mem path.
358 */
359 ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
360 if (ret) {
361 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
362 ret);
363 goto err_phy_off;
364 }
365
366 return 0;
367
368err_phy_off:
369 phy_power_off(pcie_ep->phy);
370err_phy_exit:
371 phy_exit(pcie_ep->phy);
372err_disable_clk:
373 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
374
375 return ret;
376}
377
378static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep)
379{
380 icc_set_bw(pcie_ep->icc_mem, 0, 0);
381 phy_power_off(pcie_ep->phy);
382 phy_exit(pcie_ep->phy);
383 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
384}
385
386static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
387{
388 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
389 struct device *dev = pci->dev;
390 u32 val, offset;
391 int ret;
392
393 ret = qcom_pcie_enable_resources(pcie_ep);
394 if (ret) {
395 dev_err(dev, "Failed to enable resources: %d\n", ret);
396 return ret;
397 }
398
399 /* Perform cleanup that requires refclk */
400 pci_epc_deinit_notify(pci->ep.epc);
401 dw_pcie_ep_cleanup(&pci->ep);
402
403 /* Assert WAKE# to RC to indicate device is ready */
404 gpiod_set_value_cansleep(pcie_ep->wake, 1);
405 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500);
406 gpiod_set_value_cansleep(pcie_ep->wake, 0);
407
408 qcom_pcie_ep_configure_tcsr(pcie_ep);
409
410 /* Disable BDF to SID mapping */
411 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG);
412 val |= PARF_BDF_TO_SID_BYPASS;
413 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG);
414
415 /* Enable debug IRQ */
416 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN);
417 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF |
418 PARF_DEBUG_INT_CFG_BUS_MASTER_EN |
419 PARF_DEBUG_INT_PM_DSTATE_CHANGE;
420 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN);
421
422 /* Configure PCIe to endpoint mode */
423 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE);
424
425 /* Allow entering L1 state */
426 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
427 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1;
428 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
429
430 /* Read halts write */
431 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
432 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN;
433 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
434
435 /* Write after write halt */
436 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
437 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN;
438 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
439
440 /* Q2A flush disable */
441 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH);
442 val &= ~PARF_Q2A_FLUSH_EN;
443 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH);
444
445 /*
446 * Disable Master AXI clock during idle. Do not allow DBI access
447 * to take the core out of L1. Disable core clock gating that
448 * gates PIPE clock from propagating to core clock. Report to the
449 * host that Vaux is present.
450 */
451 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL);
452 val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS;
453 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE |
454 PARF_SYS_CTRL_CORE_CLK_CGC_DIS |
455 PARF_SYS_CTRL_AUX_PWR_DET;
456 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL);
457
458 /* Disable the debouncers */
459 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL);
460 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK |
461 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK |
462 PARF_DB_CTRL_MST_WKP_BLOCK;
463 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL);
464
465 /* Request to exit from L1SS for MSI and LTR MSG */
466 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS);
467 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN;
468 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS);
469
470 dw_pcie_dbi_ro_wr_en(pci);
471
472 /* Set the L0s Exit Latency to 2us-4us = 0x6 */
473 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
474 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
475 val &= ~PCI_EXP_LNKCAP_L0SEL;
476 val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6);
477 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
478
479 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */
480 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
481 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
482 val &= ~PCI_EXP_LNKCAP_L1EL;
483 val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6);
484 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
485
486 dw_pcie_dbi_ro_wr_dis(pci);
487
488 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK);
489 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME |
490 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE |
491 PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA;
492 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
493
494 if (pcie_ep->cfg && pcie_ep->cfg->disable_mhi_ram_parity_check) {
495 val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_5_MASK);
496 val &= ~PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR;
497 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_5_MASK);
498 }
499
500 ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep);
501 if (ret) {
502 dev_err(dev, "Failed to complete initialization: %d\n", ret);
503 goto err_disable_resources;
504 }
505
506 if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) {
507 qcom_pcie_common_set_16gt_equalization(pci);
508 qcom_pcie_common_set_16gt_lane_margining(pci);
509 }
510
511 /*
512 * The physical address of the MMIO region which is exposed as the BAR
513 * should be written to MHI BASE registers.
514 */
515 writel_relaxed(pcie_ep->mmio_res->start,
516 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
517 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
518
519 /* Gate Master AXI clock to MHI bus during L1SS */
520 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
521 val &= ~PARF_MSTR_AXI_CLK_EN;
522 writel_relaxed(val, pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
523
524 pci_epc_init_notify(pcie_ep->pci.ep.epc);
525
526 /* Enable LTSSM */
527 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM);
528 val |= BIT(8);
529 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
530
531 if (pcie_ep->cfg && pcie_ep->cfg->override_no_snoop)
532 writel_relaxed(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,
533 pcie_ep->parf + PARF_NO_SNOOP_OVERIDE);
534
535 return 0;
536
537err_disable_resources:
538 qcom_pcie_disable_resources(pcie_ep);
539
540 return ret;
541}
542
543static void qcom_pcie_perst_assert(struct dw_pcie *pci)
544{
545 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
546
547 qcom_pcie_disable_resources(pcie_ep);
548 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;
549}
550
551/* Common DWC controller ops */
552static const struct dw_pcie_ops pci_ops = {
553 .link_up = qcom_pcie_dw_link_up,
554 .start_link = qcom_pcie_dw_start_link,
555 .stop_link = qcom_pcie_dw_stop_link,
556 .write_dbi2 = qcom_pcie_dw_write_dbi2,
557};
558
559static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev,
560 struct qcom_pcie_ep *pcie_ep)
561{
562 struct device *dev = &pdev->dev;
563 struct dw_pcie *pci = &pcie_ep->pci;
564 struct device_node *syscon;
565 struct resource *res;
566 int ret;
567
568 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
569 if (IS_ERR(pcie_ep->parf))
570 return PTR_ERR(pcie_ep->parf);
571
572 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
573 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
574 if (IS_ERR(pci->dbi_base))
575 return PTR_ERR(pci->dbi_base);
576 pci->dbi_base2 = pci->dbi_base;
577
578 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
579 pcie_ep->elbi = devm_pci_remap_cfg_resource(dev, res);
580 if (IS_ERR(pcie_ep->elbi))
581 return PTR_ERR(pcie_ep->elbi);
582
583 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
584 "mmio");
585 if (!pcie_ep->mmio_res) {
586 dev_err(dev, "Failed to get mmio resource\n");
587 return -EINVAL;
588 }
589
590 pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res);
591 if (IS_ERR(pcie_ep->mmio))
592 return PTR_ERR(pcie_ep->mmio);
593
594 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0);
595 if (!syscon) {
596 dev_dbg(dev, "PERST separation not available\n");
597 return 0;
598 }
599
600 pcie_ep->perst_map = syscon_node_to_regmap(syscon);
601 of_node_put(syscon);
602 if (IS_ERR(pcie_ep->perst_map))
603 return PTR_ERR(pcie_ep->perst_map);
604
605 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
606 1, &pcie_ep->perst_en);
607 if (ret < 0) {
608 dev_err(dev, "No Perst Enable offset in syscon\n");
609 return ret;
610 }
611
612 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
613 2, &pcie_ep->perst_sep_en);
614 if (ret < 0) {
615 dev_err(dev, "No Perst Separation Enable offset in syscon\n");
616 return ret;
617 }
618
619 return 0;
620}
621
622static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
623 struct qcom_pcie_ep *pcie_ep)
624{
625 struct device *dev = &pdev->dev;
626 int ret;
627
628 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep);
629 if (ret) {
630 dev_err(dev, "Failed to get io resources %d\n", ret);
631 return ret;
632 }
633
634 pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks);
635 if (pcie_ep->num_clks < 0) {
636 dev_err(dev, "Failed to get clocks\n");
637 return pcie_ep->num_clks;
638 }
639
640 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core");
641 if (IS_ERR(pcie_ep->core_reset))
642 return PTR_ERR(pcie_ep->core_reset);
643
644 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN);
645 if (IS_ERR(pcie_ep->reset))
646 return PTR_ERR(pcie_ep->reset);
647
648 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW);
649 if (IS_ERR(pcie_ep->wake))
650 return PTR_ERR(pcie_ep->wake);
651
652 pcie_ep->phy = devm_phy_optional_get(dev, "pciephy");
653 if (IS_ERR(pcie_ep->phy))
654 ret = PTR_ERR(pcie_ep->phy);
655
656 pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem");
657 if (IS_ERR(pcie_ep->icc_mem))
658 ret = PTR_ERR(pcie_ep->icc_mem);
659
660 return ret;
661}
662
663/* TODO: Notify clients about PCIe state change */
664static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data)
665{
666 struct qcom_pcie_ep *pcie_ep = data;
667 struct dw_pcie *pci = &pcie_ep->pci;
668 struct device *dev = pci->dev;
669 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS);
670 u32 dstate, val;
671
672 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR);
673
674 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) {
675 dev_dbg(dev, "Received Linkdown event\n");
676 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN;
677 dw_pcie_ep_linkdown(&pci->ep);
678 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) {
679 dev_dbg(dev, "Received Bus Master Enable event\n");
680 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED;
681 qcom_pcie_ep_icc_update(pcie_ep);
682 pci_epc_bus_master_enable_notify(pci->ep.epc);
683 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) {
684 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n");
685 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
686 val |= PARF_PM_CTRL_READY_ENTR_L23;
687 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
688 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) {
689 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) &
690 DBI_CON_STATUS_POWER_STATE_MASK;
691 dev_dbg(dev, "Received D%d state event\n", dstate);
692 if (dstate == 3) {
693 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
694 val |= PARF_PM_CTRL_REQ_EXIT_L1;
695 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
696 }
697 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {
698 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n");
699 dw_pcie_ep_linkup(&pci->ep);
700 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP;
701 } else {
702 dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n",
703 status);
704 }
705
706 return IRQ_HANDLED;
707}
708
709static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data)
710{
711 struct qcom_pcie_ep *pcie_ep = data;
712 struct dw_pcie *pci = &pcie_ep->pci;
713 struct device *dev = pci->dev;
714 u32 perst;
715
716 perst = gpiod_get_value(pcie_ep->reset);
717 if (perst) {
718 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n");
719 qcom_pcie_perst_assert(pci);
720 } else {
721 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n");
722 qcom_pcie_perst_deassert(pci);
723 }
724
725 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset),
726 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW));
727
728 return IRQ_HANDLED;
729}
730
731static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
732 struct qcom_pcie_ep *pcie_ep)
733{
734 struct device *dev = pcie_ep->pci.dev;
735 char *name;
736 int ret;
737
738 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_global_irq%d",
739 pcie_ep->pci.ep.epc->domain_nr);
740 if (!name)
741 return -ENOMEM;
742
743 pcie_ep->global_irq = platform_get_irq_byname(pdev, "global");
744 if (pcie_ep->global_irq < 0)
745 return pcie_ep->global_irq;
746
747 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL,
748 qcom_pcie_ep_global_irq_thread,
749 IRQF_ONESHOT,
750 name, pcie_ep);
751 if (ret) {
752 dev_err(&pdev->dev, "Failed to request Global IRQ\n");
753 return ret;
754 }
755
756 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_perst_irq%d",
757 pcie_ep->pci.ep.epc->domain_nr);
758 if (!name)
759 return -ENOMEM;
760
761 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset);
762 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN);
763 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL,
764 qcom_pcie_ep_perst_irq_thread,
765 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
766 name, pcie_ep);
767 if (ret) {
768 dev_err(&pdev->dev, "Failed to request PERST IRQ\n");
769 disable_irq(pcie_ep->global_irq);
770 return ret;
771 }
772
773 return 0;
774}
775
776static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
777 unsigned int type, u16 interrupt_num)
778{
779 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
780
781 switch (type) {
782 case PCI_IRQ_INTX:
783 return dw_pcie_ep_raise_intx_irq(ep, func_no);
784 case PCI_IRQ_MSI:
785 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
786 default:
787 dev_err(pci->dev, "Unknown IRQ type\n");
788 return -EINVAL;
789 }
790}
791
792static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data)
793{
794 struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *)
795 dev_get_drvdata(s->private);
796
797 seq_printf(s, "L0s transition count: %u\n",
798 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
799
800 seq_printf(s, "L1 transition count: %u\n",
801 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
802
803 seq_printf(s, "L1.1 transition count: %u\n",
804 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
805
806 seq_printf(s, "L1.2 transition count: %u\n",
807 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
808
809 seq_printf(s, "L2 transition count: %u\n",
810 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
811
812 return 0;
813}
814
815static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep)
816{
817 struct dw_pcie *pci = &pcie_ep->pci;
818
819 debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs,
820 qcom_pcie_ep_link_transition_count);
821}
822
823static const struct pci_epc_features qcom_pcie_epc_features = {
824 .linkup_notifier = true,
825 .msi_capable = true,
826 .msix_capable = false,
827 .align = SZ_4K,
828};
829
830static const struct pci_epc_features *
831qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep)
832{
833 return &qcom_pcie_epc_features;
834}
835
836static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
837{
838 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
839 enum pci_barno bar;
840
841 for (bar = BAR_0; bar <= BAR_5; bar++)
842 dw_pcie_ep_reset_bar(pci, bar);
843}
844
845static const struct dw_pcie_ep_ops pci_ep_ops = {
846 .init = qcom_pcie_ep_init,
847 .raise_irq = qcom_pcie_ep_raise_irq,
848 .get_features = qcom_pcie_epc_get_features,
849};
850
851static int qcom_pcie_ep_probe(struct platform_device *pdev)
852{
853 struct device *dev = &pdev->dev;
854 struct qcom_pcie_ep *pcie_ep;
855 char *name;
856 int ret;
857
858 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
859 if (!pcie_ep)
860 return -ENOMEM;
861
862 pcie_ep->pci.dev = dev;
863 pcie_ep->pci.ops = &pci_ops;
864 pcie_ep->pci.ep.ops = &pci_ep_ops;
865 pcie_ep->pci.edma.nr_irqs = 1;
866
867 pcie_ep->cfg = of_device_get_match_data(dev);
868 if (pcie_ep->cfg && pcie_ep->cfg->hdma_support) {
869 pcie_ep->pci.edma.ll_wr_cnt = 8;
870 pcie_ep->pci.edma.ll_rd_cnt = 8;
871 pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE;
872 }
873
874 platform_set_drvdata(pdev, pcie_ep);
875
876 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep);
877 if (ret)
878 return ret;
879
880 ret = dw_pcie_ep_init(&pcie_ep->pci.ep);
881 if (ret) {
882 dev_err(dev, "Failed to initialize endpoint: %d\n", ret);
883 return ret;
884 }
885
886 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep);
887 if (ret)
888 goto err_ep_deinit;
889
890 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
891 if (!name) {
892 ret = -ENOMEM;
893 goto err_disable_irqs;
894 }
895
896 pcie_ep->debugfs = debugfs_create_dir(name, NULL);
897 qcom_pcie_ep_init_debugfs(pcie_ep);
898
899 return 0;
900
901err_disable_irqs:
902 disable_irq(pcie_ep->global_irq);
903 disable_irq(pcie_ep->perst_irq);
904
905err_ep_deinit:
906 dw_pcie_ep_deinit(&pcie_ep->pci.ep);
907
908 return ret;
909}
910
911static void qcom_pcie_ep_remove(struct platform_device *pdev)
912{
913 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev);
914
915 disable_irq(pcie_ep->global_irq);
916 disable_irq(pcie_ep->perst_irq);
917
918 debugfs_remove_recursive(pcie_ep->debugfs);
919
920 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED)
921 return;
922
923 qcom_pcie_disable_resources(pcie_ep);
924}
925
926static const struct qcom_pcie_ep_cfg cfg_1_34_0 = {
927 .hdma_support = true,
928 .override_no_snoop = true,
929 .disable_mhi_ram_parity_check = true,
930};
931
932static const struct of_device_id qcom_pcie_ep_match[] = {
933 { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0},
934 { .compatible = "qcom,sdx55-pcie-ep", },
935 { .compatible = "qcom,sm8450-pcie-ep", },
936 { }
937};
938MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match);
939
940static struct platform_driver qcom_pcie_ep_driver = {
941 .probe = qcom_pcie_ep_probe,
942 .remove = qcom_pcie_ep_remove,
943 .driver = {
944 .name = "qcom-pcie-ep",
945 .of_match_table = qcom_pcie_ep_match,
946 },
947};
948builtin_platform_driver(qcom_pcie_ep_driver);
949
950MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>");
951MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
952MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver");
953MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Qualcomm PCIe Endpoint controller driver
4 *
5 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org
7 *
8 * Copyright (c) 2021, Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org
10 */
11
12#include <linux/clk.h>
13#include <linux/debugfs.h>
14#include <linux/delay.h>
15#include <linux/gpio/consumer.h>
16#include <linux/mfd/syscon.h>
17#include <linux/phy/pcie.h>
18#include <linux/phy/phy.h>
19#include <linux/platform_device.h>
20#include <linux/pm_domain.h>
21#include <linux/regmap.h>
22#include <linux/reset.h>
23#include <linux/module.h>
24
25#include "pcie-designware.h"
26
27/* PARF registers */
28#define PARF_SYS_CTRL 0x00
29#define PARF_DB_CTRL 0x10
30#define PARF_PM_CTRL 0x20
31#define PARF_MHI_CLOCK_RESET_CTRL 0x174
32#define PARF_MHI_BASE_ADDR_LOWER 0x178
33#define PARF_MHI_BASE_ADDR_UPPER 0x17c
34#define PARF_DEBUG_INT_EN 0x190
35#define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4
36#define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8
37#define PARF_Q2A_FLUSH 0x1ac
38#define PARF_LTSSM 0x1b0
39#define PARF_CFG_BITS 0x210
40#define PARF_INT_ALL_STATUS 0x224
41#define PARF_INT_ALL_CLEAR 0x228
42#define PARF_INT_ALL_MASK 0x22c
43#define PARF_SLV_ADDR_MSB_CTRL 0x2c0
44#define PARF_DBI_BASE_ADDR 0x350
45#define PARF_DBI_BASE_ADDR_HI 0x354
46#define PARF_SLV_ADDR_SPACE_SIZE 0x358
47#define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c
48#define PARF_ATU_BASE_ADDR 0x634
49#define PARF_ATU_BASE_ADDR_HI 0x638
50#define PARF_SRIS_MODE 0x644
51#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
52#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c
53#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10
54#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84
55#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88
56#define PARF_DEVICE_TYPE 0x1000
57#define PARF_BDF_TO_SID_CFG 0x2c00
58
59/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
60#define PARF_INT_ALL_LINK_DOWN BIT(1)
61#define PARF_INT_ALL_BME BIT(2)
62#define PARF_INT_ALL_PM_TURNOFF BIT(3)
63#define PARF_INT_ALL_DEBUG BIT(4)
64#define PARF_INT_ALL_LTR BIT(5)
65#define PARF_INT_ALL_MHI_Q6 BIT(6)
66#define PARF_INT_ALL_MHI_A7 BIT(7)
67#define PARF_INT_ALL_DSTATE_CHANGE BIT(8)
68#define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9)
69#define PARF_INT_ALL_MMIO_WRITE BIT(10)
70#define PARF_INT_ALL_CFG_WRITE BIT(11)
71#define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12)
72#define PARF_INT_ALL_LINK_UP BIT(13)
73#define PARF_INT_ALL_AER_LEGACY BIT(14)
74#define PARF_INT_ALL_PLS_ERR BIT(15)
75#define PARF_INT_ALL_PME_LEGACY BIT(16)
76#define PARF_INT_ALL_PLS_PME BIT(17)
77
78/* PARF_BDF_TO_SID_CFG register fields */
79#define PARF_BDF_TO_SID_BYPASS BIT(0)
80
81/* PARF_DEBUG_INT_EN register fields */
82#define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1)
83#define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2)
84#define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3)
85
86/* PARF_DEVICE_TYPE register fields */
87#define PARF_DEVICE_TYPE_EP 0x0
88
89/* PARF_PM_CTRL register fields */
90#define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1)
91#define PARF_PM_CTRL_READY_ENTR_L23 BIT(2)
92#define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5)
93
94/* PARF_MHI_CLOCK_RESET_CTRL fields */
95#define PARF_MSTR_AXI_CLK_EN BIT(1)
96
97/* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */
98#define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0)
99
100/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
101#define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31)
102
103/* PARF_Q2A_FLUSH register fields */
104#define PARF_Q2A_FLUSH_EN BIT(16)
105
106/* PARF_SYS_CTRL register fields */
107#define PARF_SYS_CTRL_AUX_PWR_DET BIT(4)
108#define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6)
109#define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10)
110#define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11)
111
112/* PARF_DB_CTRL register fields */
113#define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0)
114#define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1)
115#define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4)
116#define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5)
117#define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6)
118
119/* PARF_CFG_BITS register fields */
120#define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1)
121
122/* ELBI registers */
123#define ELBI_SYS_STTS 0x08
124
125/* DBI registers */
126#define DBI_CON_STATUS 0x44
127
128/* DBI register fields */
129#define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0)
130
131#define XMLH_LINK_UP 0x400
132#define CORE_RESET_TIME_US_MIN 1000
133#define CORE_RESET_TIME_US_MAX 1005
134#define WAKE_DELAY_US 2000 /* 2 ms */
135
136#define to_pcie_ep(x) dev_get_drvdata((x)->dev)
137
138enum qcom_pcie_ep_link_status {
139 QCOM_PCIE_EP_LINK_DISABLED,
140 QCOM_PCIE_EP_LINK_ENABLED,
141 QCOM_PCIE_EP_LINK_UP,
142 QCOM_PCIE_EP_LINK_DOWN,
143};
144
145/**
146 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
147 * @pci: Designware PCIe controller struct
148 * @parf: Qualcomm PCIe specific PARF register base
149 * @elbi: Designware PCIe specific ELBI register base
150 * @mmio: MMIO register base
151 * @perst_map: PERST regmap
152 * @mmio_res: MMIO region resource
153 * @core_reset: PCIe Endpoint core reset
154 * @reset: PERST# GPIO
155 * @wake: WAKE# GPIO
156 * @phy: PHY controller block
157 * @debugfs: PCIe Endpoint Debugfs directory
158 * @clks: PCIe clocks
159 * @num_clks: PCIe clocks count
160 * @perst_en: Flag for PERST enable
161 * @perst_sep_en: Flag for PERST separation enable
162 * @link_status: PCIe Link status
163 * @global_irq: Qualcomm PCIe specific Global IRQ
164 * @perst_irq: PERST# IRQ
165 */
166struct qcom_pcie_ep {
167 struct dw_pcie pci;
168
169 void __iomem *parf;
170 void __iomem *elbi;
171 void __iomem *mmio;
172 struct regmap *perst_map;
173 struct resource *mmio_res;
174
175 struct reset_control *core_reset;
176 struct gpio_desc *reset;
177 struct gpio_desc *wake;
178 struct phy *phy;
179 struct dentry *debugfs;
180
181 struct clk_bulk_data *clks;
182 int num_clks;
183
184 u32 perst_en;
185 u32 perst_sep_en;
186
187 enum qcom_pcie_ep_link_status link_status;
188 int global_irq;
189 int perst_irq;
190};
191
192static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep)
193{
194 struct dw_pcie *pci = &pcie_ep->pci;
195 struct device *dev = pci->dev;
196 int ret;
197
198 ret = reset_control_assert(pcie_ep->core_reset);
199 if (ret) {
200 dev_err(dev, "Cannot assert core reset\n");
201 return ret;
202 }
203
204 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
205
206 ret = reset_control_deassert(pcie_ep->core_reset);
207 if (ret) {
208 dev_err(dev, "Cannot de-assert core reset\n");
209 return ret;
210 }
211
212 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
213
214 return 0;
215}
216
217/*
218 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid
219 * device reset during host reboot and hibernation. The driver is
220 * expected to handle this situation.
221 */
222static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep)
223{
224 if (pcie_ep->perst_map) {
225 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0);
226 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0);
227 }
228}
229
230static int qcom_pcie_dw_link_up(struct dw_pcie *pci)
231{
232 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
233 u32 reg;
234
235 reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS);
236
237 return reg & XMLH_LINK_UP;
238}
239
240static int qcom_pcie_dw_start_link(struct dw_pcie *pci)
241{
242 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
243
244 enable_irq(pcie_ep->perst_irq);
245
246 return 0;
247}
248
249static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)
250{
251 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
252
253 disable_irq(pcie_ep->perst_irq);
254}
255
256static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
257{
258 int ret;
259
260 ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks);
261 if (ret)
262 return ret;
263
264 ret = qcom_pcie_ep_core_reset(pcie_ep);
265 if (ret)
266 goto err_disable_clk;
267
268 ret = phy_init(pcie_ep->phy);
269 if (ret)
270 goto err_disable_clk;
271
272 ret = phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP);
273 if (ret)
274 goto err_phy_exit;
275
276 ret = phy_power_on(pcie_ep->phy);
277 if (ret)
278 goto err_phy_exit;
279
280 return 0;
281
282err_phy_exit:
283 phy_exit(pcie_ep->phy);
284err_disable_clk:
285 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
286
287 return ret;
288}
289
290static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep)
291{
292 phy_power_off(pcie_ep->phy);
293 phy_exit(pcie_ep->phy);
294 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
295}
296
297static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
298{
299 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
300 struct device *dev = pci->dev;
301 u32 val, offset;
302 int ret;
303
304 ret = qcom_pcie_enable_resources(pcie_ep);
305 if (ret) {
306 dev_err(dev, "Failed to enable resources: %d\n", ret);
307 return ret;
308 }
309
310 /* Assert WAKE# to RC to indicate device is ready */
311 gpiod_set_value_cansleep(pcie_ep->wake, 1);
312 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500);
313 gpiod_set_value_cansleep(pcie_ep->wake, 0);
314
315 qcom_pcie_ep_configure_tcsr(pcie_ep);
316
317 /* Disable BDF to SID mapping */
318 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG);
319 val |= PARF_BDF_TO_SID_BYPASS;
320 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG);
321
322 /* Enable debug IRQ */
323 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN);
324 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF |
325 PARF_DEBUG_INT_CFG_BUS_MASTER_EN |
326 PARF_DEBUG_INT_PM_DSTATE_CHANGE;
327 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN);
328
329 /* Configure PCIe to endpoint mode */
330 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE);
331
332 /* Allow entering L1 state */
333 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
334 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1;
335 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
336
337 /* Read halts write */
338 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
339 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN;
340 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
341
342 /* Write after write halt */
343 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
344 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN;
345 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
346
347 /* Q2A flush disable */
348 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH);
349 val &= ~PARF_Q2A_FLUSH_EN;
350 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH);
351
352 /*
353 * Disable Master AXI clock during idle. Do not allow DBI access
354 * to take the core out of L1. Disable core clock gating that
355 * gates PIPE clock from propagating to core clock. Report to the
356 * host that Vaux is present.
357 */
358 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL);
359 val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS;
360 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE |
361 PARF_SYS_CTRL_CORE_CLK_CGC_DIS |
362 PARF_SYS_CTRL_AUX_PWR_DET;
363 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL);
364
365 /* Disable the debouncers */
366 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL);
367 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK |
368 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK |
369 PARF_DB_CTRL_MST_WKP_BLOCK;
370 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL);
371
372 /* Request to exit from L1SS for MSI and LTR MSG */
373 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS);
374 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN;
375 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS);
376
377 dw_pcie_dbi_ro_wr_en(pci);
378
379 /* Set the L0s Exit Latency to 2us-4us = 0x6 */
380 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
381 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
382 val &= ~PCI_EXP_LNKCAP_L0SEL;
383 val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6);
384 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
385
386 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */
387 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
388 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
389 val &= ~PCI_EXP_LNKCAP_L1EL;
390 val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6);
391 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
392
393 dw_pcie_dbi_ro_wr_dis(pci);
394
395 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK);
396 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME |
397 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE |
398 PARF_INT_ALL_LINK_UP;
399 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
400
401 ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep);
402 if (ret) {
403 dev_err(dev, "Failed to complete initialization: %d\n", ret);
404 goto err_disable_resources;
405 }
406
407 /*
408 * The physical address of the MMIO region which is exposed as the BAR
409 * should be written to MHI BASE registers.
410 */
411 writel_relaxed(pcie_ep->mmio_res->start,
412 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
413 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
414
415 /* Gate Master AXI clock to MHI bus during L1SS */
416 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
417 val &= ~PARF_MSTR_AXI_CLK_EN;
418 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
419
420 dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
421
422 /* Enable LTSSM */
423 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM);
424 val |= BIT(8);
425 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
426
427 return 0;
428
429err_disable_resources:
430 qcom_pcie_disable_resources(pcie_ep);
431
432 return ret;
433}
434
435static void qcom_pcie_perst_assert(struct dw_pcie *pci)
436{
437 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
438 struct device *dev = pci->dev;
439
440 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) {
441 dev_dbg(dev, "Link is already disabled\n");
442 return;
443 }
444
445 qcom_pcie_disable_resources(pcie_ep);
446 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;
447}
448
449/* Common DWC controller ops */
450static const struct dw_pcie_ops pci_ops = {
451 .link_up = qcom_pcie_dw_link_up,
452 .start_link = qcom_pcie_dw_start_link,
453 .stop_link = qcom_pcie_dw_stop_link,
454};
455
456static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev,
457 struct qcom_pcie_ep *pcie_ep)
458{
459 struct device *dev = &pdev->dev;
460 struct dw_pcie *pci = &pcie_ep->pci;
461 struct device_node *syscon;
462 struct resource *res;
463 int ret;
464
465 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
466 if (IS_ERR(pcie_ep->parf))
467 return PTR_ERR(pcie_ep->parf);
468
469 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
470 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
471 if (IS_ERR(pci->dbi_base))
472 return PTR_ERR(pci->dbi_base);
473 pci->dbi_base2 = pci->dbi_base;
474
475 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
476 pcie_ep->elbi = devm_pci_remap_cfg_resource(dev, res);
477 if (IS_ERR(pcie_ep->elbi))
478 return PTR_ERR(pcie_ep->elbi);
479
480 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
481 "mmio");
482 if (!pcie_ep->mmio_res) {
483 dev_err(dev, "Failed to get mmio resource\n");
484 return -EINVAL;
485 }
486
487 pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res);
488 if (IS_ERR(pcie_ep->mmio))
489 return PTR_ERR(pcie_ep->mmio);
490
491 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0);
492 if (!syscon) {
493 dev_dbg(dev, "PERST separation not available\n");
494 return 0;
495 }
496
497 pcie_ep->perst_map = syscon_node_to_regmap(syscon);
498 of_node_put(syscon);
499 if (IS_ERR(pcie_ep->perst_map))
500 return PTR_ERR(pcie_ep->perst_map);
501
502 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
503 1, &pcie_ep->perst_en);
504 if (ret < 0) {
505 dev_err(dev, "No Perst Enable offset in syscon\n");
506 return ret;
507 }
508
509 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
510 2, &pcie_ep->perst_sep_en);
511 if (ret < 0) {
512 dev_err(dev, "No Perst Separation Enable offset in syscon\n");
513 return ret;
514 }
515
516 return 0;
517}
518
519static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
520 struct qcom_pcie_ep *pcie_ep)
521{
522 struct device *dev = &pdev->dev;
523 int ret;
524
525 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep);
526 if (ret) {
527 dev_err(dev, "Failed to get io resources %d\n", ret);
528 return ret;
529 }
530
531 pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks);
532 if (pcie_ep->num_clks < 0) {
533 dev_err(dev, "Failed to get clocks\n");
534 return pcie_ep->num_clks;
535 }
536
537 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core");
538 if (IS_ERR(pcie_ep->core_reset))
539 return PTR_ERR(pcie_ep->core_reset);
540
541 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN);
542 if (IS_ERR(pcie_ep->reset))
543 return PTR_ERR(pcie_ep->reset);
544
545 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW);
546 if (IS_ERR(pcie_ep->wake))
547 return PTR_ERR(pcie_ep->wake);
548
549 pcie_ep->phy = devm_phy_optional_get(dev, "pciephy");
550 if (IS_ERR(pcie_ep->phy))
551 ret = PTR_ERR(pcie_ep->phy);
552
553 return ret;
554}
555
556/* TODO: Notify clients about PCIe state change */
557static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data)
558{
559 struct qcom_pcie_ep *pcie_ep = data;
560 struct dw_pcie *pci = &pcie_ep->pci;
561 struct device *dev = pci->dev;
562 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS);
563 u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK);
564 u32 dstate, val;
565
566 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR);
567 status &= mask;
568
569 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) {
570 dev_dbg(dev, "Received Linkdown event\n");
571 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN;
572 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) {
573 dev_dbg(dev, "Received BME event. Link is enabled!\n");
574 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED;
575 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) {
576 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n");
577 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
578 val |= PARF_PM_CTRL_READY_ENTR_L23;
579 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
580 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) {
581 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) &
582 DBI_CON_STATUS_POWER_STATE_MASK;
583 dev_dbg(dev, "Received D%d state event\n", dstate);
584 if (dstate == 3) {
585 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
586 val |= PARF_PM_CTRL_REQ_EXIT_L1;
587 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
588 }
589 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {
590 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n");
591 dw_pcie_ep_linkup(&pci->ep);
592 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP;
593 } else {
594 dev_dbg(dev, "Received unknown event: %d\n", status);
595 }
596
597 return IRQ_HANDLED;
598}
599
600static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data)
601{
602 struct qcom_pcie_ep *pcie_ep = data;
603 struct dw_pcie *pci = &pcie_ep->pci;
604 struct device *dev = pci->dev;
605 u32 perst;
606
607 perst = gpiod_get_value(pcie_ep->reset);
608 if (perst) {
609 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n");
610 qcom_pcie_perst_assert(pci);
611 } else {
612 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n");
613 qcom_pcie_perst_deassert(pci);
614 }
615
616 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset),
617 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW));
618
619 return IRQ_HANDLED;
620}
621
622static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
623 struct qcom_pcie_ep *pcie_ep)
624{
625 int ret;
626
627 pcie_ep->global_irq = platform_get_irq_byname(pdev, "global");
628 if (pcie_ep->global_irq < 0)
629 return pcie_ep->global_irq;
630
631 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL,
632 qcom_pcie_ep_global_irq_thread,
633 IRQF_ONESHOT,
634 "global_irq", pcie_ep);
635 if (ret) {
636 dev_err(&pdev->dev, "Failed to request Global IRQ\n");
637 return ret;
638 }
639
640 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset);
641 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN);
642 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL,
643 qcom_pcie_ep_perst_irq_thread,
644 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
645 "perst_irq", pcie_ep);
646 if (ret) {
647 dev_err(&pdev->dev, "Failed to request PERST IRQ\n");
648 disable_irq(pcie_ep->global_irq);
649 return ret;
650 }
651
652 return 0;
653}
654
655static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
656 enum pci_epc_irq_type type, u16 interrupt_num)
657{
658 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
659
660 switch (type) {
661 case PCI_EPC_IRQ_LEGACY:
662 return dw_pcie_ep_raise_legacy_irq(ep, func_no);
663 case PCI_EPC_IRQ_MSI:
664 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
665 default:
666 dev_err(pci->dev, "Unknown IRQ type\n");
667 return -EINVAL;
668 }
669}
670
671static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data)
672{
673 struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *)
674 dev_get_drvdata(s->private);
675
676 seq_printf(s, "L0s transition count: %u\n",
677 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
678
679 seq_printf(s, "L1 transition count: %u\n",
680 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
681
682 seq_printf(s, "L1.1 transition count: %u\n",
683 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
684
685 seq_printf(s, "L1.2 transition count: %u\n",
686 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
687
688 seq_printf(s, "L2 transition count: %u\n",
689 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
690
691 return 0;
692}
693
694static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep)
695{
696 struct dw_pcie *pci = &pcie_ep->pci;
697
698 debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs,
699 qcom_pcie_ep_link_transition_count);
700}
701
702static const struct pci_epc_features qcom_pcie_epc_features = {
703 .linkup_notifier = true,
704 .core_init_notifier = true,
705 .msi_capable = true,
706 .msix_capable = false,
707};
708
709static const struct pci_epc_features *
710qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep)
711{
712 return &qcom_pcie_epc_features;
713}
714
715static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
716{
717 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
718 enum pci_barno bar;
719
720 for (bar = BAR_0; bar <= BAR_5; bar++)
721 dw_pcie_ep_reset_bar(pci, bar);
722}
723
724static const struct dw_pcie_ep_ops pci_ep_ops = {
725 .ep_init = qcom_pcie_ep_init,
726 .raise_irq = qcom_pcie_ep_raise_irq,
727 .get_features = qcom_pcie_epc_get_features,
728};
729
730static int qcom_pcie_ep_probe(struct platform_device *pdev)
731{
732 struct device *dev = &pdev->dev;
733 struct qcom_pcie_ep *pcie_ep;
734 char *name;
735 int ret;
736
737 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
738 if (!pcie_ep)
739 return -ENOMEM;
740
741 pcie_ep->pci.dev = dev;
742 pcie_ep->pci.ops = &pci_ops;
743 pcie_ep->pci.ep.ops = &pci_ep_ops;
744 platform_set_drvdata(pdev, pcie_ep);
745
746 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep);
747 if (ret)
748 return ret;
749
750 ret = qcom_pcie_enable_resources(pcie_ep);
751 if (ret) {
752 dev_err(dev, "Failed to enable resources: %d\n", ret);
753 return ret;
754 }
755
756 ret = dw_pcie_ep_init(&pcie_ep->pci.ep);
757 if (ret) {
758 dev_err(dev, "Failed to initialize endpoint: %d\n", ret);
759 goto err_disable_resources;
760 }
761
762 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep);
763 if (ret)
764 goto err_disable_resources;
765
766 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
767 if (!name) {
768 ret = -ENOMEM;
769 goto err_disable_irqs;
770 }
771
772 pcie_ep->debugfs = debugfs_create_dir(name, NULL);
773 qcom_pcie_ep_init_debugfs(pcie_ep);
774
775 return 0;
776
777err_disable_irqs:
778 disable_irq(pcie_ep->global_irq);
779 disable_irq(pcie_ep->perst_irq);
780
781err_disable_resources:
782 qcom_pcie_disable_resources(pcie_ep);
783
784 return ret;
785}
786
787static int qcom_pcie_ep_remove(struct platform_device *pdev)
788{
789 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev);
790
791 disable_irq(pcie_ep->global_irq);
792 disable_irq(pcie_ep->perst_irq);
793
794 debugfs_remove_recursive(pcie_ep->debugfs);
795
796 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED)
797 return 0;
798
799 qcom_pcie_disable_resources(pcie_ep);
800
801 return 0;
802}
803
804static const struct of_device_id qcom_pcie_ep_match[] = {
805 { .compatible = "qcom,sdx55-pcie-ep", },
806 { .compatible = "qcom,sm8450-pcie-ep", },
807 { }
808};
809MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match);
810
811static struct platform_driver qcom_pcie_ep_driver = {
812 .probe = qcom_pcie_ep_probe,
813 .remove = qcom_pcie_ep_remove,
814 .driver = {
815 .name = "qcom-pcie-ep",
816 .of_match_table = qcom_pcie_ep_match,
817 },
818};
819builtin_platform_driver(qcom_pcie_ep_driver);
820
821MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>");
822MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
823MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver");
824MODULE_LICENSE("GPL v2");