1// SPDX-License-Identifier: GPL-2.0
 2/*
 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 4 */
 5
 6#include <linux/pci.h>
 7
 8#include "pcie-designware.h"
 9#include "pcie-qcom-common.h"
10
11void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci)
12{
13	u32 reg;
14
15	/*
16	 * GEN3_RELATED_OFF register is repurposed to apply equalization
17	 * settings at various data transmission rates through registers namely
18	 * GEN3_EQ_*. The RATE_SHADOW_SEL bit field of GEN3_RELATED_OFF
19	 * determines the data rate for which these equalization settings are
20	 * applied.
21	 */
22	reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
23	reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
24	reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
25	reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK,
26			  GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT);
27	dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg);
28
29	reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF);
30	reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 |
31		GEN3_EQ_FMDC_N_EVALS |
32		GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA |
33		GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA);
34	reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) |
35		FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) |
36		FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) |
37		FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5);
38	dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg);
39
40	reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
41	reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE |
42		GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE |
43		GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL |
44		GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC);
45	dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg);
46}
47EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_equalization);
48
49void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci)
50{
51	u32 reg;
52
53	reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF);
54	reg &= ~(MARGINING_MAX_VOLTAGE_OFFSET |
55		MARGINING_NUM_VOLTAGE_STEPS |
56		MARGINING_MAX_TIMING_OFFSET |
57		MARGINING_NUM_TIMING_STEPS);
58	reg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) |
59		FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) |
60		FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) |
61		FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10);
62	dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg);
63
64	reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF);
65	reg |= MARGINING_IND_ERROR_SAMPLER |
66		MARGINING_SAMPLE_REPORTING_METHOD |
67		MARGINING_IND_LEFT_RIGHT_TIMING |
68		MARGINING_VOLTAGE_SUPPORTED;
69	reg &= ~(MARGINING_IND_UP_DOWN_VOLTAGE |
70		MARGINING_MAXLANES |
71		MARGINING_SAMPLE_RATE_TIMING |
72		MARGINING_SAMPLE_RATE_VOLTAGE);
73	reg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) |
74		FIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) |
75		FIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f);
76	dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg);
77}
78EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_lane_margining);