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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
4 *
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/clk-provider.h>
11#include <linux/container_of.h>
12#include <linux/delay.h>
13#include <linux/gpio/consumer.h>
14#include <linux/io.h>
15#include <linux/irqchip/chained_irq.h>
16#include <linux/irqdomain.h>
17#include <linux/mfd/syscon.h>
18#include <linux/of.h>
19#include <linux/pci.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/regmap.h>
23
24#include "../../pci.h"
25#include "pcie-cadence.h"
26
27#define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
28
29#define ENABLE_REG_SYS_2 0x108
30#define STATUS_REG_SYS_2 0x508
31#define STATUS_CLR_REG_SYS_2 0x708
32#define LINK_DOWN BIT(1)
33#define J7200_LINK_DOWN BIT(10)
34
35#define J721E_PCIE_USER_CMD_STATUS 0x4
36#define LINK_TRAINING_ENABLE BIT(0)
37
38#define J721E_PCIE_USER_LINKSTATUS 0x14
39#define LINK_STATUS GENMASK(1, 0)
40
41enum link_status {
42 NO_RECEIVERS_DETECTED,
43 LINK_TRAINING_IN_PROGRESS,
44 LINK_UP_DL_IN_PROGRESS,
45 LINK_UP_DL_COMPLETED,
46};
47
48#define J721E_MODE_RC BIT(7)
49#define LANE_COUNT(n) ((n) << 8)
50
51#define ACSPCIE_PAD_DISABLE_MASK GENMASK(1, 0)
52#define GENERATION_SEL_MASK GENMASK(1, 0)
53
54struct j721e_pcie {
55 struct cdns_pcie *cdns_pcie;
56 struct clk *refclk;
57 u32 mode;
58 u32 num_lanes;
59 u32 max_lanes;
60 struct gpio_desc *reset_gpio;
61 void __iomem *user_cfg_base;
62 void __iomem *intd_cfg_base;
63 u32 linkdown_irq_regfield;
64};
65
66enum j721e_pcie_mode {
67 PCI_MODE_RC,
68 PCI_MODE_EP,
69};
70
71struct j721e_pcie_data {
72 enum j721e_pcie_mode mode;
73 unsigned int quirk_retrain_flag:1;
74 unsigned int quirk_detect_quiet_flag:1;
75 unsigned int quirk_disable_flr:1;
76 u32 linkdown_irq_regfield;
77 unsigned int byte_access_allowed:1;
78 unsigned int max_lanes;
79};
80
81static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
82{
83 return readl(pcie->user_cfg_base + offset);
84}
85
86static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset,
87 u32 value)
88{
89 writel(value, pcie->user_cfg_base + offset);
90}
91
92static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset)
93{
94 return readl(pcie->intd_cfg_base + offset);
95}
96
97static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset,
98 u32 value)
99{
100 writel(value, pcie->intd_cfg_base + offset);
101}
102
103static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
104{
105 struct j721e_pcie *pcie = priv;
106 struct device *dev = pcie->cdns_pcie->dev;
107 u32 reg;
108
109 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2);
110 if (!(reg & pcie->linkdown_irq_regfield))
111 return IRQ_NONE;
112
113 dev_err(dev, "LINK DOWN!\n");
114
115 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield);
116 return IRQ_HANDLED;
117}
118
119static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
120{
121 u32 reg;
122
123 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2);
124 reg |= pcie->linkdown_irq_regfield;
125 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg);
126}
127
128static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie)
129{
130 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
131 u32 reg;
132
133 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
134 reg |= LINK_TRAINING_ENABLE;
135 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
136
137 return 0;
138}
139
140static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie)
141{
142 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
143 u32 reg;
144
145 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
146 reg &= ~LINK_TRAINING_ENABLE;
147 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
148}
149
150static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie)
151{
152 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
153 u32 reg;
154
155 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);
156 reg &= LINK_STATUS;
157 if (reg == LINK_UP_DL_COMPLETED)
158 return true;
159
160 return false;
161}
162
163static const struct cdns_pcie_ops j721e_pcie_ops = {
164 .start_link = j721e_pcie_start_link,
165 .stop_link = j721e_pcie_stop_link,
166 .link_up = j721e_pcie_link_up,
167};
168
169static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon,
170 unsigned int offset)
171{
172 struct device *dev = pcie->cdns_pcie->dev;
173 u32 mask = J721E_MODE_RC;
174 u32 mode = pcie->mode;
175 u32 val = 0;
176 int ret = 0;
177
178 if (mode == PCI_MODE_RC)
179 val = J721E_MODE_RC;
180
181 ret = regmap_update_bits(syscon, offset, mask, val);
182 if (ret)
183 dev_err(dev, "failed to set pcie mode\n");
184
185 return ret;
186}
187
188static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
189 struct regmap *syscon, unsigned int offset)
190{
191 struct device *dev = pcie->cdns_pcie->dev;
192 struct device_node *np = dev->of_node;
193 int link_speed;
194 u32 val = 0;
195 int ret;
196
197 link_speed = of_pci_get_max_link_speed(np);
198 if (link_speed < 2)
199 link_speed = 2;
200
201 val = link_speed - 1;
202 ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val);
203 if (ret)
204 dev_err(dev, "failed to set link speed\n");
205
206 return ret;
207}
208
209static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
210 struct regmap *syscon, unsigned int offset)
211{
212 struct device *dev = pcie->cdns_pcie->dev;
213 u32 lanes = pcie->num_lanes;
214 u32 mask = BIT(8);
215 u32 val = 0;
216 int ret;
217
218 if (pcie->max_lanes == 4)
219 mask = GENMASK(9, 8);
220
221 val = LANE_COUNT(lanes - 1);
222 ret = regmap_update_bits(syscon, offset, mask, val);
223 if (ret)
224 dev_err(dev, "failed to set link count\n");
225
226 return ret;
227}
228
229static int j721e_enable_acspcie_refclk(struct j721e_pcie *pcie,
230 struct regmap *syscon)
231{
232 struct device *dev = pcie->cdns_pcie->dev;
233 struct device_node *node = dev->of_node;
234 u32 mask = ACSPCIE_PAD_DISABLE_MASK;
235 struct of_phandle_args args;
236 u32 val;
237 int ret;
238
239 ret = of_parse_phandle_with_fixed_args(node,
240 "ti,syscon-acspcie-proxy-ctrl",
241 1, 0, &args);
242 if (ret) {
243 dev_err(dev,
244 "ti,syscon-acspcie-proxy-ctrl has invalid arguments\n");
245 return ret;
246 }
247
248 /* Clear PAD IO disable bits to enable refclk output */
249 val = ~(args.args[0]);
250 ret = regmap_update_bits(syscon, 0, mask, val);
251 if (ret) {
252 dev_err(dev, "failed to enable ACSPCIE refclk: %d\n", ret);
253 return ret;
254 }
255
256 return 0;
257}
258
259static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
260{
261 struct device *dev = pcie->cdns_pcie->dev;
262 struct device_node *node = dev->of_node;
263 struct of_phandle_args args;
264 unsigned int offset = 0;
265 struct regmap *syscon;
266 int ret;
267
268 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl");
269 if (IS_ERR(syscon)) {
270 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n");
271 return PTR_ERR(syscon);
272 }
273
274 /* Do not error out to maintain old DT compatibility */
275 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1,
276 0, &args);
277 if (!ret)
278 offset = args.args[0];
279
280 ret = j721e_pcie_set_mode(pcie, syscon, offset);
281 if (ret < 0) {
282 dev_err(dev, "Failed to set pci mode\n");
283 return ret;
284 }
285
286 ret = j721e_pcie_set_link_speed(pcie, syscon, offset);
287 if (ret < 0) {
288 dev_err(dev, "Failed to set link speed\n");
289 return ret;
290 }
291
292 ret = j721e_pcie_set_lane_count(pcie, syscon, offset);
293 if (ret < 0) {
294 dev_err(dev, "Failed to set num-lanes\n");
295 return ret;
296 }
297
298 /* Enable ACSPCIE refclk output if the optional property exists */
299 syscon = syscon_regmap_lookup_by_phandle_optional(node,
300 "ti,syscon-acspcie-proxy-ctrl");
301 if (!syscon)
302 return 0;
303
304 return j721e_enable_acspcie_refclk(pcie, syscon);
305}
306
307static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
308 int where, int size, u32 *value)
309{
310 if (pci_is_root_bus(bus))
311 return pci_generic_config_read32(bus, devfn, where, size,
312 value);
313
314 return pci_generic_config_read(bus, devfn, where, size, value);
315}
316
317static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
318 int where, int size, u32 value)
319{
320 if (pci_is_root_bus(bus))
321 return pci_generic_config_write32(bus, devfn, where, size,
322 value);
323
324 return pci_generic_config_write(bus, devfn, where, size, value);
325}
326
327static struct pci_ops cdns_ti_pcie_host_ops = {
328 .map_bus = cdns_pci_map_bus,
329 .read = cdns_ti_pcie_config_read,
330 .write = cdns_ti_pcie_config_write,
331};
332
333static const struct j721e_pcie_data j721e_pcie_rc_data = {
334 .mode = PCI_MODE_RC,
335 .quirk_retrain_flag = true,
336 .byte_access_allowed = false,
337 .linkdown_irq_regfield = LINK_DOWN,
338 .max_lanes = 2,
339};
340
341static const struct j721e_pcie_data j721e_pcie_ep_data = {
342 .mode = PCI_MODE_EP,
343 .linkdown_irq_regfield = LINK_DOWN,
344 .max_lanes = 2,
345};
346
347static const struct j721e_pcie_data j7200_pcie_rc_data = {
348 .mode = PCI_MODE_RC,
349 .quirk_detect_quiet_flag = true,
350 .linkdown_irq_regfield = J7200_LINK_DOWN,
351 .byte_access_allowed = true,
352 .max_lanes = 2,
353};
354
355static const struct j721e_pcie_data j7200_pcie_ep_data = {
356 .mode = PCI_MODE_EP,
357 .quirk_detect_quiet_flag = true,
358 .quirk_disable_flr = true,
359 .max_lanes = 2,
360};
361
362static const struct j721e_pcie_data am64_pcie_rc_data = {
363 .mode = PCI_MODE_RC,
364 .linkdown_irq_regfield = J7200_LINK_DOWN,
365 .byte_access_allowed = true,
366 .max_lanes = 1,
367};
368
369static const struct j721e_pcie_data am64_pcie_ep_data = {
370 .mode = PCI_MODE_EP,
371 .linkdown_irq_regfield = J7200_LINK_DOWN,
372 .max_lanes = 1,
373};
374
375static const struct j721e_pcie_data j784s4_pcie_rc_data = {
376 .mode = PCI_MODE_RC,
377 .quirk_retrain_flag = true,
378 .byte_access_allowed = false,
379 .linkdown_irq_regfield = LINK_DOWN,
380 .max_lanes = 4,
381};
382
383static const struct j721e_pcie_data j784s4_pcie_ep_data = {
384 .mode = PCI_MODE_EP,
385 .linkdown_irq_regfield = LINK_DOWN,
386 .max_lanes = 4,
387};
388
389static const struct j721e_pcie_data j722s_pcie_rc_data = {
390 .mode = PCI_MODE_RC,
391 .linkdown_irq_regfield = J7200_LINK_DOWN,
392 .byte_access_allowed = true,
393 .max_lanes = 1,
394};
395
396static const struct of_device_id of_j721e_pcie_match[] = {
397 {
398 .compatible = "ti,j721e-pcie-host",
399 .data = &j721e_pcie_rc_data,
400 },
401 {
402 .compatible = "ti,j721e-pcie-ep",
403 .data = &j721e_pcie_ep_data,
404 },
405 {
406 .compatible = "ti,j7200-pcie-host",
407 .data = &j7200_pcie_rc_data,
408 },
409 {
410 .compatible = "ti,j7200-pcie-ep",
411 .data = &j7200_pcie_ep_data,
412 },
413 {
414 .compatible = "ti,am64-pcie-host",
415 .data = &am64_pcie_rc_data,
416 },
417 {
418 .compatible = "ti,am64-pcie-ep",
419 .data = &am64_pcie_ep_data,
420 },
421 {
422 .compatible = "ti,j784s4-pcie-host",
423 .data = &j784s4_pcie_rc_data,
424 },
425 {
426 .compatible = "ti,j784s4-pcie-ep",
427 .data = &j784s4_pcie_ep_data,
428 },
429 {
430 .compatible = "ti,j722s-pcie-host",
431 .data = &j722s_pcie_rc_data,
432 },
433 {},
434};
435
436static int j721e_pcie_probe(struct platform_device *pdev)
437{
438 struct device *dev = &pdev->dev;
439 struct device_node *node = dev->of_node;
440 struct pci_host_bridge *bridge;
441 const struct j721e_pcie_data *data;
442 struct cdns_pcie *cdns_pcie;
443 struct j721e_pcie *pcie;
444 struct cdns_pcie_rc *rc = NULL;
445 struct cdns_pcie_ep *ep = NULL;
446 struct gpio_desc *gpiod;
447 void __iomem *base;
448 struct clk *clk;
449 u32 num_lanes;
450 u32 mode;
451 int ret;
452 int irq;
453
454 data = of_device_get_match_data(dev);
455 if (!data)
456 return -EINVAL;
457
458 mode = (u32)data->mode;
459
460 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
461 if (!pcie)
462 return -ENOMEM;
463
464 switch (mode) {
465 case PCI_MODE_RC:
466 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST))
467 return -ENODEV;
468
469 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
470 if (!bridge)
471 return -ENOMEM;
472
473 if (!data->byte_access_allowed)
474 bridge->ops = &cdns_ti_pcie_host_ops;
475 rc = pci_host_bridge_priv(bridge);
476 rc->quirk_retrain_flag = data->quirk_retrain_flag;
477 rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
478
479 cdns_pcie = &rc->pcie;
480 cdns_pcie->dev = dev;
481 cdns_pcie->ops = &j721e_pcie_ops;
482 pcie->cdns_pcie = cdns_pcie;
483 break;
484 case PCI_MODE_EP:
485 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP))
486 return -ENODEV;
487
488 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
489 if (!ep)
490 return -ENOMEM;
491
492 ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
493 ep->quirk_disable_flr = data->quirk_disable_flr;
494
495 cdns_pcie = &ep->pcie;
496 cdns_pcie->dev = dev;
497 cdns_pcie->ops = &j721e_pcie_ops;
498 pcie->cdns_pcie = cdns_pcie;
499 break;
500 default:
501 dev_err(dev, "INVALID device type %d\n", mode);
502 return 0;
503 }
504
505 pcie->mode = mode;
506 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield;
507
508 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg");
509 if (IS_ERR(base))
510 return PTR_ERR(base);
511 pcie->intd_cfg_base = base;
512
513 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg");
514 if (IS_ERR(base))
515 return PTR_ERR(base);
516 pcie->user_cfg_base = base;
517
518 ret = of_property_read_u32(node, "num-lanes", &num_lanes);
519 if (ret || num_lanes > data->max_lanes) {
520 dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");
521 num_lanes = 1;
522 }
523
524 pcie->num_lanes = num_lanes;
525 pcie->max_lanes = data->max_lanes;
526
527 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
528 return -EINVAL;
529
530 irq = platform_get_irq_byname(pdev, "link_state");
531 if (irq < 0)
532 return irq;
533
534 dev_set_drvdata(dev, pcie);
535 pm_runtime_enable(dev);
536 ret = pm_runtime_get_sync(dev);
537 if (ret < 0) {
538 dev_err_probe(dev, ret, "pm_runtime_get_sync failed\n");
539 goto err_get_sync;
540 }
541
542 ret = j721e_pcie_ctrl_init(pcie);
543 if (ret < 0) {
544 dev_err_probe(dev, ret, "pm_runtime_get_sync failed\n");
545 goto err_get_sync;
546 }
547
548 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0,
549 "j721e-pcie-link-down-irq", pcie);
550 if (ret < 0) {
551 dev_err_probe(dev, ret, "failed to request link state IRQ %d\n", irq);
552 goto err_get_sync;
553 }
554
555 j721e_pcie_config_link_irq(pcie);
556
557 switch (mode) {
558 case PCI_MODE_RC:
559 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
560 if (IS_ERR(gpiod)) {
561 ret = dev_err_probe(dev, PTR_ERR(gpiod), "Failed to get reset GPIO\n");
562 goto err_get_sync;
563 }
564 pcie->reset_gpio = gpiod;
565
566 ret = cdns_pcie_init_phy(dev, cdns_pcie);
567 if (ret) {
568 dev_err_probe(dev, ret, "Failed to init phy\n");
569 goto err_get_sync;
570 }
571
572 clk = devm_clk_get_optional(dev, "pcie_refclk");
573 if (IS_ERR(clk)) {
574 ret = dev_err_probe(dev, PTR_ERR(clk), "failed to get pcie_refclk\n");
575 goto err_pcie_setup;
576 }
577
578 ret = clk_prepare_enable(clk);
579 if (ret) {
580 dev_err_probe(dev, ret, "failed to enable pcie_refclk\n");
581 goto err_pcie_setup;
582 }
583 pcie->refclk = clk;
584
585 /*
586 * Section 2.2 of the PCI Express Card Electromechanical
587 * Specification (Revision 5.1) mandates that the deassertion
588 * of the PERST# signal should be delayed by 100 ms (TPVPERL).
589 * This shall ensure that the power and the reference clock
590 * are stable.
591 */
592 if (gpiod) {
593 msleep(PCIE_T_PVPERL_MS);
594 gpiod_set_value_cansleep(gpiod, 1);
595 }
596
597 ret = cdns_pcie_host_setup(rc);
598 if (ret < 0) {
599 clk_disable_unprepare(pcie->refclk);
600 goto err_pcie_setup;
601 }
602
603 break;
604 case PCI_MODE_EP:
605 ret = cdns_pcie_init_phy(dev, cdns_pcie);
606 if (ret) {
607 dev_err_probe(dev, ret, "Failed to init phy\n");
608 goto err_get_sync;
609 }
610
611 ret = cdns_pcie_ep_setup(ep);
612 if (ret < 0)
613 goto err_pcie_setup;
614
615 break;
616 }
617
618 return 0;
619
620err_pcie_setup:
621 cdns_pcie_disable_phy(cdns_pcie);
622
623err_get_sync:
624 pm_runtime_put(dev);
625 pm_runtime_disable(dev);
626
627 return ret;
628}
629
630static void j721e_pcie_remove(struct platform_device *pdev)
631{
632 struct j721e_pcie *pcie = platform_get_drvdata(pdev);
633 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
634 struct device *dev = &pdev->dev;
635
636 clk_disable_unprepare(pcie->refclk);
637 cdns_pcie_disable_phy(cdns_pcie);
638 pm_runtime_put(dev);
639 pm_runtime_disable(dev);
640}
641
642static int j721e_pcie_suspend_noirq(struct device *dev)
643{
644 struct j721e_pcie *pcie = dev_get_drvdata(dev);
645
646 if (pcie->mode == PCI_MODE_RC) {
647 gpiod_set_value_cansleep(pcie->reset_gpio, 0);
648 clk_disable_unprepare(pcie->refclk);
649 }
650
651 cdns_pcie_disable_phy(pcie->cdns_pcie);
652
653 return 0;
654}
655
656static int j721e_pcie_resume_noirq(struct device *dev)
657{
658 struct j721e_pcie *pcie = dev_get_drvdata(dev);
659 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
660 int ret;
661
662 ret = j721e_pcie_ctrl_init(pcie);
663 if (ret < 0)
664 return ret;
665
666 j721e_pcie_config_link_irq(pcie);
667
668 /*
669 * This is not called explicitly in the probe, it is called by
670 * cdns_pcie_init_phy().
671 */
672 ret = cdns_pcie_enable_phy(pcie->cdns_pcie);
673 if (ret < 0)
674 return ret;
675
676 if (pcie->mode == PCI_MODE_RC) {
677 struct cdns_pcie_rc *rc = cdns_pcie_to_rc(cdns_pcie);
678
679 ret = clk_prepare_enable(pcie->refclk);
680 if (ret < 0)
681 return ret;
682
683 /*
684 * Section 2.2 of the PCI Express Card Electromechanical
685 * Specification (Revision 5.1) mandates that the deassertion
686 * of the PERST# signal should be delayed by 100 ms (TPVPERL).
687 * This shall ensure that the power and the reference clock
688 * are stable.
689 */
690 if (pcie->reset_gpio) {
691 msleep(PCIE_T_PVPERL_MS);
692 gpiod_set_value_cansleep(pcie->reset_gpio, 1);
693 }
694
695 ret = cdns_pcie_host_link_setup(rc);
696 if (ret < 0) {
697 clk_disable_unprepare(pcie->refclk);
698 return ret;
699 }
700
701 /*
702 * Reset internal status of BARs to force reinitialization in
703 * cdns_pcie_host_init().
704 */
705 for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++)
706 rc->avail_ib_bar[bar] = true;
707
708 ret = cdns_pcie_host_init(rc);
709 if (ret) {
710 clk_disable_unprepare(pcie->refclk);
711 return ret;
712 }
713 }
714
715 return 0;
716}
717
718static DEFINE_NOIRQ_DEV_PM_OPS(j721e_pcie_pm_ops,
719 j721e_pcie_suspend_noirq,
720 j721e_pcie_resume_noirq);
721
722static struct platform_driver j721e_pcie_driver = {
723 .probe = j721e_pcie_probe,
724 .remove = j721e_pcie_remove,
725 .driver = {
726 .name = "j721e-pcie",
727 .of_match_table = of_j721e_pcie_match,
728 .suppress_bind_attrs = true,
729 .pm = pm_sleep_ptr(&j721e_pcie_pm_ops),
730 },
731};
732builtin_platform_driver(j721e_pcie_driver);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
4 *
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio/consumer.h>
12#include <linux/io.h>
13#include <linux/irqchip/chained_irq.h>
14#include <linux/irqdomain.h>
15#include <linux/mfd/syscon.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/pci.h>
19#include <linux/pm_runtime.h>
20#include <linux/regmap.h>
21
22#include "../../pci.h"
23#include "pcie-cadence.h"
24
25#define ENABLE_REG_SYS_2 0x108
26#define STATUS_REG_SYS_2 0x508
27#define STATUS_CLR_REG_SYS_2 0x708
28#define LINK_DOWN BIT(1)
29#define J7200_LINK_DOWN BIT(10)
30
31#define J721E_PCIE_USER_CMD_STATUS 0x4
32#define LINK_TRAINING_ENABLE BIT(0)
33
34#define J721E_PCIE_USER_LINKSTATUS 0x14
35#define LINK_STATUS GENMASK(1, 0)
36
37enum link_status {
38 NO_RECEIVERS_DETECTED,
39 LINK_TRAINING_IN_PROGRESS,
40 LINK_UP_DL_IN_PROGRESS,
41 LINK_UP_DL_COMPLETED,
42};
43
44#define J721E_MODE_RC BIT(7)
45#define LANE_COUNT_MASK BIT(8)
46#define LANE_COUNT(n) ((n) << 8)
47
48#define GENERATION_SEL_MASK GENMASK(1, 0)
49
50#define MAX_LANES 2
51
52struct j721e_pcie {
53 struct cdns_pcie *cdns_pcie;
54 struct clk *refclk;
55 u32 mode;
56 u32 num_lanes;
57 void __iomem *user_cfg_base;
58 void __iomem *intd_cfg_base;
59 u32 linkdown_irq_regfield;
60};
61
62enum j721e_pcie_mode {
63 PCI_MODE_RC,
64 PCI_MODE_EP,
65};
66
67struct j721e_pcie_data {
68 enum j721e_pcie_mode mode;
69 unsigned int quirk_retrain_flag:1;
70 unsigned int quirk_detect_quiet_flag:1;
71 unsigned int quirk_disable_flr:1;
72 u32 linkdown_irq_regfield;
73 unsigned int byte_access_allowed:1;
74};
75
76static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
77{
78 return readl(pcie->user_cfg_base + offset);
79}
80
81static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset,
82 u32 value)
83{
84 writel(value, pcie->user_cfg_base + offset);
85}
86
87static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset)
88{
89 return readl(pcie->intd_cfg_base + offset);
90}
91
92static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset,
93 u32 value)
94{
95 writel(value, pcie->intd_cfg_base + offset);
96}
97
98static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
99{
100 struct j721e_pcie *pcie = priv;
101 struct device *dev = pcie->cdns_pcie->dev;
102 u32 reg;
103
104 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2);
105 if (!(reg & pcie->linkdown_irq_regfield))
106 return IRQ_NONE;
107
108 dev_err(dev, "LINK DOWN!\n");
109
110 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield);
111 return IRQ_HANDLED;
112}
113
114static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
115{
116 u32 reg;
117
118 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2);
119 reg |= pcie->linkdown_irq_regfield;
120 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg);
121}
122
123static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie)
124{
125 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
126 u32 reg;
127
128 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
129 reg |= LINK_TRAINING_ENABLE;
130 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
131
132 return 0;
133}
134
135static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie)
136{
137 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
138 u32 reg;
139
140 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
141 reg &= ~LINK_TRAINING_ENABLE;
142 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
143}
144
145static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie)
146{
147 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
148 u32 reg;
149
150 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);
151 reg &= LINK_STATUS;
152 if (reg == LINK_UP_DL_COMPLETED)
153 return true;
154
155 return false;
156}
157
158static const struct cdns_pcie_ops j721e_pcie_ops = {
159 .start_link = j721e_pcie_start_link,
160 .stop_link = j721e_pcie_stop_link,
161 .link_up = j721e_pcie_link_up,
162};
163
164static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon,
165 unsigned int offset)
166{
167 struct device *dev = pcie->cdns_pcie->dev;
168 u32 mask = J721E_MODE_RC;
169 u32 mode = pcie->mode;
170 u32 val = 0;
171 int ret = 0;
172
173 if (mode == PCI_MODE_RC)
174 val = J721E_MODE_RC;
175
176 ret = regmap_update_bits(syscon, offset, mask, val);
177 if (ret)
178 dev_err(dev, "failed to set pcie mode\n");
179
180 return ret;
181}
182
183static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
184 struct regmap *syscon, unsigned int offset)
185{
186 struct device *dev = pcie->cdns_pcie->dev;
187 struct device_node *np = dev->of_node;
188 int link_speed;
189 u32 val = 0;
190 int ret;
191
192 link_speed = of_pci_get_max_link_speed(np);
193 if (link_speed < 2)
194 link_speed = 2;
195
196 val = link_speed - 1;
197 ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val);
198 if (ret)
199 dev_err(dev, "failed to set link speed\n");
200
201 return ret;
202}
203
204static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
205 struct regmap *syscon, unsigned int offset)
206{
207 struct device *dev = pcie->cdns_pcie->dev;
208 u32 lanes = pcie->num_lanes;
209 u32 val = 0;
210 int ret;
211
212 val = LANE_COUNT(lanes - 1);
213 ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
214 if (ret)
215 dev_err(dev, "failed to set link count\n");
216
217 return ret;
218}
219
220static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
221{
222 struct device *dev = pcie->cdns_pcie->dev;
223 struct device_node *node = dev->of_node;
224 struct of_phandle_args args;
225 unsigned int offset = 0;
226 struct regmap *syscon;
227 int ret;
228
229 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl");
230 if (IS_ERR(syscon)) {
231 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n");
232 return PTR_ERR(syscon);
233 }
234
235 /* Do not error out to maintain old DT compatibility */
236 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1,
237 0, &args);
238 if (!ret)
239 offset = args.args[0];
240
241 ret = j721e_pcie_set_mode(pcie, syscon, offset);
242 if (ret < 0) {
243 dev_err(dev, "Failed to set pci mode\n");
244 return ret;
245 }
246
247 ret = j721e_pcie_set_link_speed(pcie, syscon, offset);
248 if (ret < 0) {
249 dev_err(dev, "Failed to set link speed\n");
250 return ret;
251 }
252
253 ret = j721e_pcie_set_lane_count(pcie, syscon, offset);
254 if (ret < 0) {
255 dev_err(dev, "Failed to set num-lanes\n");
256 return ret;
257 }
258
259 return 0;
260}
261
262static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
263 int where, int size, u32 *value)
264{
265 if (pci_is_root_bus(bus))
266 return pci_generic_config_read32(bus, devfn, where, size,
267 value);
268
269 return pci_generic_config_read(bus, devfn, where, size, value);
270}
271
272static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
273 int where, int size, u32 value)
274{
275 if (pci_is_root_bus(bus))
276 return pci_generic_config_write32(bus, devfn, where, size,
277 value);
278
279 return pci_generic_config_write(bus, devfn, where, size, value);
280}
281
282static struct pci_ops cdns_ti_pcie_host_ops = {
283 .map_bus = cdns_pci_map_bus,
284 .read = cdns_ti_pcie_config_read,
285 .write = cdns_ti_pcie_config_write,
286};
287
288static const struct j721e_pcie_data j721e_pcie_rc_data = {
289 .mode = PCI_MODE_RC,
290 .quirk_retrain_flag = true,
291 .byte_access_allowed = false,
292 .linkdown_irq_regfield = LINK_DOWN,
293};
294
295static const struct j721e_pcie_data j721e_pcie_ep_data = {
296 .mode = PCI_MODE_EP,
297 .linkdown_irq_regfield = LINK_DOWN,
298};
299
300static const struct j721e_pcie_data j7200_pcie_rc_data = {
301 .mode = PCI_MODE_RC,
302 .quirk_detect_quiet_flag = true,
303 .linkdown_irq_regfield = J7200_LINK_DOWN,
304 .byte_access_allowed = true,
305};
306
307static const struct j721e_pcie_data j7200_pcie_ep_data = {
308 .mode = PCI_MODE_EP,
309 .quirk_detect_quiet_flag = true,
310 .quirk_disable_flr = true,
311};
312
313static const struct j721e_pcie_data am64_pcie_rc_data = {
314 .mode = PCI_MODE_RC,
315 .linkdown_irq_regfield = J7200_LINK_DOWN,
316 .byte_access_allowed = true,
317};
318
319static const struct j721e_pcie_data am64_pcie_ep_data = {
320 .mode = PCI_MODE_EP,
321 .linkdown_irq_regfield = J7200_LINK_DOWN,
322};
323
324static const struct of_device_id of_j721e_pcie_match[] = {
325 {
326 .compatible = "ti,j721e-pcie-host",
327 .data = &j721e_pcie_rc_data,
328 },
329 {
330 .compatible = "ti,j721e-pcie-ep",
331 .data = &j721e_pcie_ep_data,
332 },
333 {
334 .compatible = "ti,j7200-pcie-host",
335 .data = &j7200_pcie_rc_data,
336 },
337 {
338 .compatible = "ti,j7200-pcie-ep",
339 .data = &j7200_pcie_ep_data,
340 },
341 {
342 .compatible = "ti,am64-pcie-host",
343 .data = &am64_pcie_rc_data,
344 },
345 {
346 .compatible = "ti,am64-pcie-ep",
347 .data = &am64_pcie_ep_data,
348 },
349 {},
350};
351
352static int j721e_pcie_probe(struct platform_device *pdev)
353{
354 struct device *dev = &pdev->dev;
355 struct device_node *node = dev->of_node;
356 struct pci_host_bridge *bridge;
357 const struct j721e_pcie_data *data;
358 struct cdns_pcie *cdns_pcie;
359 struct j721e_pcie *pcie;
360 struct cdns_pcie_rc *rc = NULL;
361 struct cdns_pcie_ep *ep = NULL;
362 struct gpio_desc *gpiod;
363 void __iomem *base;
364 struct clk *clk;
365 u32 num_lanes;
366 u32 mode;
367 int ret;
368 int irq;
369
370 data = of_device_get_match_data(dev);
371 if (!data)
372 return -EINVAL;
373
374 mode = (u32)data->mode;
375
376 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
377 if (!pcie)
378 return -ENOMEM;
379
380 switch (mode) {
381 case PCI_MODE_RC:
382 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST))
383 return -ENODEV;
384
385 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
386 if (!bridge)
387 return -ENOMEM;
388
389 if (!data->byte_access_allowed)
390 bridge->ops = &cdns_ti_pcie_host_ops;
391 rc = pci_host_bridge_priv(bridge);
392 rc->quirk_retrain_flag = data->quirk_retrain_flag;
393 rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
394
395 cdns_pcie = &rc->pcie;
396 cdns_pcie->dev = dev;
397 cdns_pcie->ops = &j721e_pcie_ops;
398 pcie->cdns_pcie = cdns_pcie;
399 break;
400 case PCI_MODE_EP:
401 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP))
402 return -ENODEV;
403
404 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
405 if (!ep)
406 return -ENOMEM;
407
408 ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
409 ep->quirk_disable_flr = data->quirk_disable_flr;
410
411 cdns_pcie = &ep->pcie;
412 cdns_pcie->dev = dev;
413 cdns_pcie->ops = &j721e_pcie_ops;
414 pcie->cdns_pcie = cdns_pcie;
415 break;
416 default:
417 dev_err(dev, "INVALID device type %d\n", mode);
418 return 0;
419 }
420
421 pcie->mode = mode;
422 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield;
423
424 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg");
425 if (IS_ERR(base))
426 return PTR_ERR(base);
427 pcie->intd_cfg_base = base;
428
429 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg");
430 if (IS_ERR(base))
431 return PTR_ERR(base);
432 pcie->user_cfg_base = base;
433
434 ret = of_property_read_u32(node, "num-lanes", &num_lanes);
435 if (ret || num_lanes > MAX_LANES)
436 num_lanes = 1;
437 pcie->num_lanes = num_lanes;
438
439 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
440 return -EINVAL;
441
442 irq = platform_get_irq_byname(pdev, "link_state");
443 if (irq < 0)
444 return irq;
445
446 dev_set_drvdata(dev, pcie);
447 pm_runtime_enable(dev);
448 ret = pm_runtime_get_sync(dev);
449 if (ret < 0) {
450 dev_err(dev, "pm_runtime_get_sync failed\n");
451 goto err_get_sync;
452 }
453
454 ret = j721e_pcie_ctrl_init(pcie);
455 if (ret < 0) {
456 dev_err(dev, "pm_runtime_get_sync failed\n");
457 goto err_get_sync;
458 }
459
460 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0,
461 "j721e-pcie-link-down-irq", pcie);
462 if (ret < 0) {
463 dev_err(dev, "failed to request link state IRQ %d\n", irq);
464 goto err_get_sync;
465 }
466
467 j721e_pcie_config_link_irq(pcie);
468
469 switch (mode) {
470 case PCI_MODE_RC:
471 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
472 if (IS_ERR(gpiod)) {
473 ret = PTR_ERR(gpiod);
474 if (ret != -EPROBE_DEFER)
475 dev_err(dev, "Failed to get reset GPIO\n");
476 goto err_get_sync;
477 }
478
479 ret = cdns_pcie_init_phy(dev, cdns_pcie);
480 if (ret) {
481 dev_err(dev, "Failed to init phy\n");
482 goto err_get_sync;
483 }
484
485 clk = devm_clk_get_optional(dev, "pcie_refclk");
486 if (IS_ERR(clk)) {
487 ret = PTR_ERR(clk);
488 dev_err(dev, "failed to get pcie_refclk\n");
489 goto err_pcie_setup;
490 }
491
492 ret = clk_prepare_enable(clk);
493 if (ret) {
494 dev_err(dev, "failed to enable pcie_refclk\n");
495 goto err_pcie_setup;
496 }
497 pcie->refclk = clk;
498
499 /*
500 * "Power Sequencing and Reset Signal Timings" table in
501 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
502 * indicates PERST# should be deasserted after minimum of 100us
503 * once REFCLK is stable. The REFCLK to the connector in RC
504 * mode is selected while enabling the PHY. So deassert PERST#
505 * after 100 us.
506 */
507 if (gpiod) {
508 usleep_range(100, 200);
509 gpiod_set_value_cansleep(gpiod, 1);
510 }
511
512 ret = cdns_pcie_host_setup(rc);
513 if (ret < 0) {
514 clk_disable_unprepare(pcie->refclk);
515 goto err_pcie_setup;
516 }
517
518 break;
519 case PCI_MODE_EP:
520 ret = cdns_pcie_init_phy(dev, cdns_pcie);
521 if (ret) {
522 dev_err(dev, "Failed to init phy\n");
523 goto err_get_sync;
524 }
525
526 ret = cdns_pcie_ep_setup(ep);
527 if (ret < 0)
528 goto err_pcie_setup;
529
530 break;
531 }
532
533 return 0;
534
535err_pcie_setup:
536 cdns_pcie_disable_phy(cdns_pcie);
537
538err_get_sync:
539 pm_runtime_put(dev);
540 pm_runtime_disable(dev);
541
542 return ret;
543}
544
545static int j721e_pcie_remove(struct platform_device *pdev)
546{
547 struct j721e_pcie *pcie = platform_get_drvdata(pdev);
548 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
549 struct device *dev = &pdev->dev;
550
551 clk_disable_unprepare(pcie->refclk);
552 cdns_pcie_disable_phy(cdns_pcie);
553 pm_runtime_put(dev);
554 pm_runtime_disable(dev);
555
556 return 0;
557}
558
559static struct platform_driver j721e_pcie_driver = {
560 .probe = j721e_pcie_probe,
561 .remove = j721e_pcie_remove,
562 .driver = {
563 .name = "j721e-pcie",
564 .of_match_table = of_j721e_pcie_match,
565 .suppress_bind_attrs = true,
566 },
567};
568builtin_platform_driver(j721e_pcie_driver);