1/* SPDX-License-Identifier: GPL-2.0-only
 2 *
 3 * Copyright (C) 2020-21 Intel Corporation
 4 */
 5
 6#ifndef IOSM_IPC_CHNL_CFG_H
 7#define IOSM_IPC_CHNL_CFG_H
 8
 9#include "iosm_ipc_mux.h"
10
11/* Number of TDs on the trace channel */
12#define IPC_MEM_TDS_TRC 32
13
14/* Trace channel TD buffer size. */
15#define IPC_MEM_MAX_DL_TRC_BUF_SIZE 8192
16
17/* Channel ID */
18enum ipc_channel_id {
19	IPC_MEM_IP_CHL_ID_0 = 0,
20	IPC_MEM_CTRL_CHL_ID_1,
21	IPC_MEM_CTRL_CHL_ID_2,
22	IPC_MEM_CTRL_CHL_ID_3,
23	IPC_MEM_CTRL_CHL_ID_4,
24	IPC_MEM_CTRL_CHL_ID_5,
25	IPC_MEM_CTRL_CHL_ID_6,
26	IPC_MEM_CTRL_CHL_ID_7,
27};
28
29/**
30 * struct ipc_chnl_cfg - IPC channel configuration structure
31 * @id:				Interface ID
32 * @ul_pipe:			Uplink datastream
33 * @dl_pipe:			Downlink datastream
34 * @ul_nr_of_entries:		Number of Transfer descriptor uplink pipe
35 * @dl_nr_of_entries:		Number of Transfer descriptor downlink pipe
36 * @dl_buf_size:		Downlink buffer size
37 * @wwan_port_type:		Wwan subsystem port type
38 * @accumulation_backoff:	Time in usec for data accumalation
39 */
40struct ipc_chnl_cfg {
41	u32 id;
42	u32 ul_pipe;
43	u32 dl_pipe;
44	u32 ul_nr_of_entries;
45	u32 dl_nr_of_entries;
46	u32 dl_buf_size;
47	u32 wwan_port_type;
48	u32 accumulation_backoff;
49};
50
51/**
52 * ipc_chnl_cfg_get - Get pipe configuration.
53 * @chnl_cfg:		Array of ipc_chnl_cfg struct
54 * @index:		Channel index (up to MAX_CHANNELS)
55 *
56 * Return: 0 on success and failure value on error
57 */
58int ipc_chnl_cfg_get(struct ipc_chnl_cfg *chnl_cfg, int index);
59
60#endif

 1/* SPDX-License-Identifier: GPL-2.0-only
 2 *
 3 * Copyright (C) 2020-21 Intel Corporation
 4 */
 5
 6#ifndef IOSM_IPC_CHNL_CFG_H
 7#define IOSM_IPC_CHNL_CFG_H
 8
 9#include "iosm_ipc_mux.h"
10
11/* Number of TDs on the trace channel */
12#define IPC_MEM_TDS_TRC 32
13
14/* Trace channel TD buffer size. */
15#define IPC_MEM_MAX_DL_TRC_BUF_SIZE 8192
16
17/* Channel ID */
18enum ipc_channel_id {
19	IPC_MEM_IP_CHL_ID_0 = 0,
20	IPC_MEM_CTRL_CHL_ID_1,
21	IPC_MEM_CTRL_CHL_ID_2,
22	IPC_MEM_CTRL_CHL_ID_3,
23	IPC_MEM_CTRL_CHL_ID_4,
24	IPC_MEM_CTRL_CHL_ID_5,
25	IPC_MEM_CTRL_CHL_ID_6,
26	IPC_MEM_CTRL_CHL_ID_7,
27};
28
29/**
30 * struct ipc_chnl_cfg - IPC channel configuration structure
31 * @id:				Interface ID
32 * @ul_pipe:			Uplink datastream
33 * @dl_pipe:			Downlink datastream
34 * @ul_nr_of_entries:		Number of Transfer descriptor uplink pipe
35 * @dl_nr_of_entries:		Number of Transfer descriptor downlink pipe
36 * @dl_buf_size:		Downlink buffer size
37 * @wwan_port_type:		Wwan subsystem port type
38 * @accumulation_backoff:	Time in usec for data accumalation
39 */
40struct ipc_chnl_cfg {
41	u32 id;
42	u32 ul_pipe;
43	u32 dl_pipe;
44	u32 ul_nr_of_entries;
45	u32 dl_nr_of_entries;
46	u32 dl_buf_size;
47	u32 wwan_port_type;
48	u32 accumulation_backoff;
49};
50
51/**
52 * ipc_chnl_cfg_get - Get pipe configuration.
53 * @chnl_cfg:		Array of ipc_chnl_cfg struct
54 * @index:		Channel index (upto MAX_CHANNELS)
55 *
56 * Return: 0 on success and failure value on error
57 */
58int ipc_chnl_cfg_get(struct ipc_chnl_cfg *chnl_cfg, int index);
59
60#endif