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1// SPDX-License-Identifier: GPL-2.0
2/* Microchip LAN937X switch driver main logic
3 * Copyright (C) 2019-2024 Microchip Technology Inc.
4 */
5#include <linux/kernel.h>
6#include <linux/module.h>
7#include <linux/iopoll.h>
8#include <linux/phy.h>
9#include <linux/of_net.h>
10#include <linux/if_bridge.h>
11#include <linux/if_vlan.h>
12#include <linux/math.h>
13#include <net/dsa.h>
14#include <net/switchdev.h>
15
16#include "lan937x_reg.h"
17#include "ksz_common.h"
18#include "ksz9477.h"
19#include "lan937x.h"
20
21/* marker for ports without built-in PHY */
22#define LAN937X_NO_PHY U8_MAX
23
24/*
25 * lan9370_phy_addr - Mapping of LAN9370 switch ports to PHY addresses.
26 *
27 * Each entry corresponds to a specific port on the LAN9370 switch,
28 * where ports 1-4 are connected to integrated 100BASE-T1 PHYs, and
29 * Port 5 is connected to an RGMII interface without a PHY. The values
30 * are based on the documentation (DS00003108E, section 3.3).
31 */
32static const u8 lan9370_phy_addr[] = {
33 [0] = 2, /* Port 1, T1 AFE0 */
34 [1] = 3, /* Port 2, T1 AFE1 */
35 [2] = 5, /* Port 3, T1 AFE3 */
36 [3] = 6, /* Port 4, T1 AFE4 */
37 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */
38};
39
40/*
41 * lan9371_phy_addr - Mapping of LAN9371 switch ports to PHY addresses.
42 *
43 * The values are based on the documentation (DS00003109E, section 3.3).
44 */
45static const u8 lan9371_phy_addr[] = {
46 [0] = 2, /* Port 1, T1 AFE0 */
47 [1] = 3, /* Port 2, T1 AFE1 */
48 [2] = 5, /* Port 3, T1 AFE3 */
49 [3] = 8, /* Port 4, TX PHY */
50 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */
51 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */
52};
53
54/*
55 * lan9372_phy_addr - Mapping of LAN9372 switch ports to PHY addresses.
56 *
57 * The values are based on the documentation (DS00003110F, section 3.3).
58 */
59static const u8 lan9372_phy_addr[] = {
60 [0] = 2, /* Port 1, T1 AFE0 */
61 [1] = 3, /* Port 2, T1 AFE1 */
62 [2] = 5, /* Port 3, T1 AFE3 */
63 [3] = 8, /* Port 4, TX PHY */
64 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */
65 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */
66 [6] = 6, /* Port 7, T1 AFE4 */
67 [7] = 4, /* Port 8, T1 AFE2 */
68};
69
70/*
71 * lan9373_phy_addr - Mapping of LAN9373 switch ports to PHY addresses.
72 *
73 * The values are based on the documentation (DS00003110F, section 3.3).
74 */
75static const u8 lan9373_phy_addr[] = {
76 [0] = 2, /* Port 1, T1 AFE0 */
77 [1] = 3, /* Port 2, T1 AFE1 */
78 [2] = 5, /* Port 3, T1 AFE3 */
79 [3] = LAN937X_NO_PHY, /* Port 4, SGMII */
80 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */
81 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */
82 [6] = 6, /* Port 7, T1 AFE4 */
83 [7] = 4, /* Port 8, T1 AFE2 */
84};
85
86/*
87 * lan9374_phy_addr - Mapping of LAN9374 switch ports to PHY addresses.
88 *
89 * The values are based on the documentation (DS00003110F, section 3.3).
90 */
91static const u8 lan9374_phy_addr[] = {
92 [0] = 2, /* Port 1, T1 AFE0 */
93 [1] = 3, /* Port 2, T1 AFE1 */
94 [2] = 5, /* Port 3, T1 AFE3 */
95 [3] = 7, /* Port 4, T1 AFE5 */
96 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */
97 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */
98 [6] = 6, /* Port 7, T1 AFE4 */
99 [7] = 4, /* Port 8, T1 AFE2 */
100};
101
102static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
103{
104 return regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0);
105}
106
107static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset,
108 u8 bits, bool set)
109{
110 return regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset),
111 bits, set ? bits : 0);
112}
113
114/**
115 * lan937x_create_phy_addr_map - Create port-to-PHY address map for MDIO bus.
116 * @dev: Pointer to device structure.
117 * @side_mdio: Boolean indicating if the PHYs are accessed over a side MDIO bus.
118 *
119 * This function sets up the PHY address mapping for the LAN937x switches,
120 * which support two access modes for internal PHYs:
121 * 1. **SPI Access**: A straightforward one-to-one port-to-PHY address
122 * mapping is applied.
123 * 2. **MDIO Access**: The PHY address mapping varies based on chip variant
124 * and strap configuration. An offset is calculated based on strap settings
125 * to ensure correct PHY addresses are assigned. The offset calculation logic
126 * is based on Microchip's Article Number 000015828, available at:
127 * https://microchip.my.site.com/s/article/LAN9374-Virtual-PHY-PHY-Address-Mapping
128 *
129 * The function first checks if side MDIO access is disabled, in which case a
130 * simple direct mapping (port number = PHY address) is applied. If side MDIO
131 * access is enabled, it reads the strap configuration to determine the correct
132 * offset for PHY addresses.
133 *
134 * The appropriate mapping table is selected based on the chip ID, and the
135 * `phy_addr_map` is populated with the correct addresses for each port. Any
136 * port with no PHY is assigned a `LAN937X_NO_PHY` marker.
137 *
138 * Return: 0 on success, error code on failure.
139 */
140int lan937x_create_phy_addr_map(struct ksz_device *dev, bool side_mdio)
141{
142 static const u8 *phy_addr_map;
143 u32 strap_val;
144 u8 offset = 0;
145 size_t size;
146 int ret, i;
147
148 if (!side_mdio) {
149 /* simple direct mapping */
150 for (i = 0; i < dev->info->port_cnt; i++)
151 dev->phy_addr_map[i] = i;
152
153 return 0;
154 }
155
156 ret = ksz_read32(dev, REG_SW_CFG_STRAP_VAL, &strap_val);
157 if (ret < 0)
158 return ret;
159
160 if (!(strap_val & SW_CASCADE_ID_CFG) && !(strap_val & SW_VPHY_ADD_CFG))
161 offset = 0;
162 else if (!(strap_val & SW_CASCADE_ID_CFG) && (strap_val & SW_VPHY_ADD_CFG))
163 offset = 7;
164 else if ((strap_val & SW_CASCADE_ID_CFG) && !(strap_val & SW_VPHY_ADD_CFG))
165 offset = 15;
166 else
167 offset = 22;
168
169 switch (dev->info->chip_id) {
170 case LAN9370_CHIP_ID:
171 phy_addr_map = lan9370_phy_addr;
172 size = ARRAY_SIZE(lan9370_phy_addr);
173 break;
174 case LAN9371_CHIP_ID:
175 phy_addr_map = lan9371_phy_addr;
176 size = ARRAY_SIZE(lan9371_phy_addr);
177 break;
178 case LAN9372_CHIP_ID:
179 phy_addr_map = lan9372_phy_addr;
180 size = ARRAY_SIZE(lan9372_phy_addr);
181 break;
182 case LAN9373_CHIP_ID:
183 phy_addr_map = lan9373_phy_addr;
184 size = ARRAY_SIZE(lan9373_phy_addr);
185 break;
186 case LAN9374_CHIP_ID:
187 phy_addr_map = lan9374_phy_addr;
188 size = ARRAY_SIZE(lan9374_phy_addr);
189 break;
190 default:
191 return -EINVAL;
192 }
193
194 if (size < dev->info->port_cnt)
195 return -EINVAL;
196
197 for (i = 0; i < dev->info->port_cnt; i++) {
198 if (phy_addr_map[i] == LAN937X_NO_PHY)
199 dev->phy_addr_map[i] = phy_addr_map[i];
200 else
201 dev->phy_addr_map[i] = phy_addr_map[i] + offset;
202 }
203
204 return 0;
205}
206
207/**
208 * lan937x_mdio_bus_preinit - Pre-initialize MDIO bus for accessing PHYs.
209 * @dev: Pointer to device structure.
210 * @side_mdio: Boolean indicating if the PHYs are accessed over a side MDIO bus.
211 *
212 * This function configures the LAN937x switch for PHY access either through
213 * SPI or the side MDIO bus, unlocking the necessary registers for each access
214 * mode.
215 *
216 * Operation Modes:
217 * 1. **SPI Access**: Enables SPI indirect access to address clock domain
218 * crossing issues when SPI is used for PHY access.
219 * 2. **MDIO Access**: Grants access to internal PHYs over the side MDIO bus,
220 * required when using the MDIO bus for PHY management.
221 *
222 * Return: 0 on success, error code on failure.
223 */
224int lan937x_mdio_bus_preinit(struct ksz_device *dev, bool side_mdio)
225{
226 u16 data16;
227 int ret;
228
229 /* Unlock access to the PHYs, needed for SPI and side MDIO access */
230 ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false);
231 if (ret < 0)
232 goto print_error;
233
234 if (side_mdio)
235 /* Allow access to internal PHYs over MDIO bus */
236 data16 = VPHY_MDIO_INTERNAL_ENABLE;
237 else
238 /* Enable SPI indirect access to address clock domain crossing
239 * issue
240 */
241 data16 = VPHY_SPI_INDIRECT_ENABLE;
242
243 ret = ksz_rmw16(dev, REG_VPHY_SPECIAL_CTRL__2,
244 VPHY_SPI_INDIRECT_ENABLE | VPHY_MDIO_INTERNAL_ENABLE,
245 data16);
246
247print_error:
248 if (ret < 0)
249 dev_err(dev->dev, "failed to preinit the MDIO bus\n");
250
251 return ret;
252}
253
254static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg)
255{
256 u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE;
257 u16 temp;
258
259 if (is_lan937x_tx_phy(dev, addr))
260 addr_base = REG_PORT_TX_PHY_CTRL_BASE;
261
262 /* get register address based on the logical port */
263 temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2)));
264
265 return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp);
266}
267
268static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, int reg,
269 u16 val)
270{
271 unsigned int value;
272 int ret;
273
274 /* Check for internal phy port */
275 if (!dev->info->internal_phy[addr])
276 return -EOPNOTSUPP;
277
278 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
279 if (ret < 0)
280 return ret;
281
282 /* Write the data to be written to the VPHY reg */
283 ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val);
284 if (ret < 0)
285 return ret;
286
287 /* Write the Write En and Busy bit */
288 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2,
289 (VPHY_IND_WRITE | VPHY_IND_BUSY));
290 if (ret < 0)
291 return ret;
292
293 ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2,
294 value, !(value & VPHY_IND_BUSY), 10,
295 1000);
296 if (ret < 0) {
297 dev_err(dev->dev, "Failed to write phy register\n");
298 return ret;
299 }
300
301 return 0;
302}
303
304static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int reg,
305 u16 *val)
306{
307 unsigned int value;
308 int ret;
309
310 /* Check for internal phy port, return 0xffff for non-existent phy */
311 if (!dev->info->internal_phy[addr])
312 return 0xffff;
313
314 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
315 if (ret < 0)
316 return ret;
317
318 /* Write Read and Busy bit to start the transaction */
319 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY);
320 if (ret < 0)
321 return ret;
322
323 ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2,
324 value, !(value & VPHY_IND_BUSY), 10,
325 1000);
326 if (ret < 0) {
327 dev_err(dev->dev, "Failed to read phy register\n");
328 return ret;
329 }
330
331 /* Read the VPHY register which has the PHY data */
332 return ksz_read16(dev, REG_VPHY_IND_DATA__2, val);
333}
334
335int lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data)
336{
337 return lan937x_internal_phy_read(dev, addr, reg, data);
338}
339
340int lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val)
341{
342 return lan937x_internal_phy_write(dev, addr, reg, val);
343}
344
345int lan937x_reset_switch(struct ksz_device *dev)
346{
347 u32 data32;
348 int ret;
349
350 /* reset switch */
351 ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
352 if (ret < 0)
353 return ret;
354
355 /* Enable Auto Aging */
356 ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true);
357 if (ret < 0)
358 return ret;
359
360 /* disable interrupts */
361 ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
362 if (ret < 0)
363 return ret;
364
365 ret = ksz_write32(dev, REG_SW_INT_STATUS__4, POR_READY_INT);
366 if (ret < 0)
367 return ret;
368
369 ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF);
370 if (ret < 0)
371 return ret;
372
373 return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
374}
375
376void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port)
377{
378 const u32 *masks = dev->info->masks;
379 const u16 *regs = dev->info->regs;
380 struct dsa_switch *ds = dev->ds;
381 u8 member;
382
383 /* enable tag tail for host port */
384 if (cpu_port)
385 lan937x_port_cfg(dev, port, REG_PORT_CTRL_0,
386 PORT_TAIL_TAG_ENABLE, true);
387
388 /* Enable the Port Queue split */
389 ksz9477_port_queue_split(dev, port);
390
391 /* set back pressure for half duplex */
392 lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE,
393 true);
394
395 /* enable 802.1p priority */
396 lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
397
398 if (!dev->info->internal_phy[port])
399 lan937x_port_cfg(dev, port, regs[P_XMII_CTRL_0],
400 masks[P_MII_TX_FLOW_CTRL] |
401 masks[P_MII_RX_FLOW_CTRL],
402 true);
403
404 if (cpu_port)
405 member = dsa_user_ports(ds);
406 else
407 member = BIT(dsa_upstream_port(ds, port));
408
409 dev->dev_ops->cfg_port_member(dev, port, member);
410}
411
412void lan937x_config_cpu_port(struct dsa_switch *ds)
413{
414 struct ksz_device *dev = ds->priv;
415 struct dsa_port *dp;
416
417 dsa_switch_for_each_cpu_port(dp, ds) {
418 if (dev->info->cpu_ports & (1 << dp->index)) {
419 dev->cpu_port = dp->index;
420
421 /* enable cpu port */
422 lan937x_port_setup(dev, dp->index, true);
423 }
424 }
425
426 dsa_switch_for_each_user_port(dp, ds) {
427 ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED);
428 }
429}
430
431int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu)
432{
433 struct dsa_switch *ds = dev->ds;
434 int ret;
435
436 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
437
438 if (dsa_is_cpu_port(ds, port))
439 new_mtu += LAN937X_TAG_LEN;
440
441 if (new_mtu >= FR_MIN_SIZE)
442 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0,
443 PORT_JUMBO_PACKET, true);
444 else
445 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0,
446 PORT_JUMBO_PACKET, false);
447 if (ret < 0) {
448 dev_err(ds->dev, "failed to enable jumbo\n");
449 return ret;
450 }
451
452 /* Write the frame size in PORT_MAX_FR_SIZE register */
453 ret = ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu);
454 if (ret) {
455 dev_err(ds->dev, "failed to update mtu for port %d\n", port);
456 return ret;
457 }
458
459 return 0;
460}
461
462int lan937x_set_ageing_time(struct ksz_device *dev, unsigned int msecs)
463{
464 u8 data, mult, value8;
465 bool in_msec = false;
466 u32 max_val, value;
467 u32 secs = msecs;
468 int ret;
469
470#define MAX_TIMER_VAL ((1 << 20) - 1)
471
472 /* The aging timer comprises a 3-bit multiplier and a 20-bit second
473 * value. Either of them cannot be zero. The maximum timer is then
474 * 7 * 1048575 = 7340025 seconds. As this value is too large for
475 * practical use it can be interpreted as microseconds, making the
476 * maximum timer 7340 seconds with finer control. This allows for
477 * maximum 122 minutes compared to 29 minutes in KSZ9477 switch.
478 */
479 if (msecs % 1000)
480 in_msec = true;
481 else
482 secs /= 1000;
483 if (!secs)
484 secs = 1;
485
486 /* Return error if too large. */
487 else if (secs > 7 * MAX_TIMER_VAL)
488 return -EINVAL;
489
490 /* Configure how to interpret the number value. */
491 ret = ksz_rmw8(dev, REG_SW_LUE_CTRL_2, SW_AGE_CNT_IN_MICROSEC,
492 in_msec ? SW_AGE_CNT_IN_MICROSEC : 0);
493 if (ret < 0)
494 return ret;
495
496 ret = ksz_read8(dev, REG_SW_LUE_CTRL_0, &value8);
497 if (ret < 0)
498 return ret;
499
500 /* Check whether there is need to update the multiplier. */
501 mult = FIELD_GET(SW_AGE_CNT_M, value8);
502 max_val = MAX_TIMER_VAL;
503 if (mult > 0) {
504 /* Try to use the same multiplier already in the register as
505 * the hardware default uses multiplier 4 and 75 seconds for
506 * 300 seconds.
507 */
508 max_val = DIV_ROUND_UP(secs, mult);
509 if (max_val > MAX_TIMER_VAL || max_val * mult != secs)
510 max_val = MAX_TIMER_VAL;
511 }
512
513 data = DIV_ROUND_UP(secs, max_val);
514 if (mult != data) {
515 value8 &= ~SW_AGE_CNT_M;
516 value8 |= FIELD_PREP(SW_AGE_CNT_M, data);
517 ret = ksz_write8(dev, REG_SW_LUE_CTRL_0, value8);
518 if (ret < 0)
519 return ret;
520 }
521
522 secs = DIV_ROUND_UP(secs, data);
523
524 value = FIELD_GET(SW_AGE_PERIOD_7_0_M, secs);
525
526 ret = ksz_write8(dev, REG_SW_AGE_PERIOD__1, value);
527 if (ret < 0)
528 return ret;
529
530 value = FIELD_GET(SW_AGE_PERIOD_19_8_M, secs);
531
532 return ksz_write16(dev, REG_SW_AGE_PERIOD__2, value);
533}
534
535static void lan937x_set_tune_adj(struct ksz_device *dev, int port,
536 u16 reg, u8 val)
537{
538 u16 data16;
539
540 ksz_pread16(dev, port, reg, &data16);
541
542 /* Update tune Adjust */
543 data16 |= FIELD_PREP(PORT_TUNE_ADJ, val);
544 ksz_pwrite16(dev, port, reg, data16);
545
546 /* write DLL reset to take effect */
547 data16 |= PORT_DLL_RESET;
548 ksz_pwrite16(dev, port, reg, data16);
549}
550
551static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int port)
552{
553 u8 val;
554
555 /* Apply different codes based on the ports as per characterization
556 * results
557 */
558 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_TX_DELAY_2NS :
559 RGMII_2_TX_DELAY_2NS;
560
561 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val);
562}
563
564static void lan937x_set_rgmii_rx_delay(struct ksz_device *dev, int port)
565{
566 u8 val;
567
568 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_RX_DELAY_2NS :
569 RGMII_2_RX_DELAY_2NS;
570
571 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_4, val);
572}
573
574void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
575 struct phylink_config *config)
576{
577 config->mac_capabilities = MAC_100FD;
578
579 if (dev->info->supports_rgmii[port]) {
580 /* MII/RMII/RGMII ports */
581 config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
582 MAC_100HD | MAC_10 | MAC_1000FD;
583 } else if (is_lan937x_tx_phy(dev, port)) {
584 config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
585 MAC_100HD | MAC_10;
586 }
587}
588
589void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port)
590{
591 struct ksz_port *p = &dev->ports[port];
592
593 if (p->rgmii_tx_val) {
594 lan937x_set_rgmii_tx_delay(dev, port);
595 dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n",
596 port);
597 }
598
599 if (p->rgmii_rx_val) {
600 lan937x_set_rgmii_rx_delay(dev, port);
601 dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n",
602 port);
603 }
604}
605
606int lan937x_tc_cbs_set_cinc(struct ksz_device *dev, int port, u32 val)
607{
608 return ksz_pwrite32(dev, port, REG_PORT_MTI_CREDIT_INCREMENT, val);
609}
610
611int lan937x_switch_init(struct ksz_device *dev)
612{
613 dev->port_mask = (1 << dev->info->port_cnt) - 1;
614
615 return 0;
616}
617
618int lan937x_setup(struct dsa_switch *ds)
619{
620 struct ksz_device *dev = ds->priv;
621 int ret;
622
623 /* The VLAN aware is a global setting. Mixed vlan
624 * filterings are not supported.
625 */
626 ds->vlan_filtering_is_global = true;
627
628 /* Enable aggressive back off for half duplex & UNH mode */
629 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_0, (SW_PAUSE_UNH_MODE |
630 SW_NEW_BACKOFF |
631 SW_AGGR_BACKOFF), true);
632 if (ret < 0)
633 return ret;
634
635 /* If NO_EXC_COLLISION_DROP bit is set, the switch will not drop
636 * packets when 16 or more collisions occur
637 */
638 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true);
639 if (ret < 0)
640 return ret;
641
642 /* enable global MIB counter freeze function */
643 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
644 if (ret < 0)
645 return ret;
646
647 /* disable CLK125 & CLK25, 1: disable, 0: enable */
648 ret = lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
649 (SW_CLK125_ENB | SW_CLK25_ENB), true);
650 if (ret < 0)
651 return ret;
652
653 /* Disable global VPHY support. Related to CPU interface only? */
654 return ksz_rmw32(dev, REG_SW_CFG_STRAP_OVR, SW_VPHY_DISABLE,
655 SW_VPHY_DISABLE);
656}
657
658void lan937x_teardown(struct dsa_switch *ds)
659{
660
661}
662
663void lan937x_switch_exit(struct ksz_device *dev)
664{
665 lan937x_reset_switch(dev);
666}
667
668MODULE_AUTHOR("Arun Ramadoss <arun.ramadoss@microchip.com>");
669MODULE_DESCRIPTION("Microchip LAN937x Series Switch DSA Driver");
670MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/* Microchip LAN937X switch driver main logic
3 * Copyright (C) 2019-2022 Microchip Technology Inc.
4 */
5#include <linux/kernel.h>
6#include <linux/module.h>
7#include <linux/iopoll.h>
8#include <linux/phy.h>
9#include <linux/of_net.h>
10#include <linux/if_bridge.h>
11#include <linux/if_vlan.h>
12#include <linux/math.h>
13#include <net/dsa.h>
14#include <net/switchdev.h>
15
16#include "lan937x_reg.h"
17#include "ksz_common.h"
18#include "lan937x.h"
19
20static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
21{
22 return regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
23}
24
25static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset,
26 u8 bits, bool set)
27{
28 return regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
29 bits, set ? bits : 0);
30}
31
32static int lan937x_enable_spi_indirect_access(struct ksz_device *dev)
33{
34 u16 data16;
35 int ret;
36
37 /* Enable Phy access through SPI */
38 ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false);
39 if (ret < 0)
40 return ret;
41
42 ret = ksz_read16(dev, REG_VPHY_SPECIAL_CTRL__2, &data16);
43 if (ret < 0)
44 return ret;
45
46 /* Allow SPI access */
47 data16 |= VPHY_SPI_INDIRECT_ENABLE;
48
49 return ksz_write16(dev, REG_VPHY_SPECIAL_CTRL__2, data16);
50}
51
52static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg)
53{
54 u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE;
55 u16 temp;
56
57 /* get register address based on the logical port */
58 temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2)));
59
60 return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp);
61}
62
63static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, int reg,
64 u16 val)
65{
66 unsigned int value;
67 int ret;
68
69 /* Check for internal phy port */
70 if (!dev->info->internal_phy[addr])
71 return -EOPNOTSUPP;
72
73 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
74 if (ret < 0)
75 return ret;
76
77 /* Write the data to be written to the VPHY reg */
78 ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val);
79 if (ret < 0)
80 return ret;
81
82 /* Write the Write En and Busy bit */
83 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2,
84 (VPHY_IND_WRITE | VPHY_IND_BUSY));
85 if (ret < 0)
86 return ret;
87
88 ret = regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2,
89 value, !(value & VPHY_IND_BUSY), 10,
90 1000);
91 if (ret < 0) {
92 dev_err(dev->dev, "Failed to write phy register\n");
93 return ret;
94 }
95
96 return 0;
97}
98
99static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int reg,
100 u16 *val)
101{
102 unsigned int value;
103 int ret;
104
105 /* Check for internal phy port, return 0xffff for non-existent phy */
106 if (!dev->info->internal_phy[addr])
107 return 0xffff;
108
109 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
110 if (ret < 0)
111 return ret;
112
113 /* Write Read and Busy bit to start the transaction */
114 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY);
115 if (ret < 0)
116 return ret;
117
118 ret = regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2,
119 value, !(value & VPHY_IND_BUSY), 10,
120 1000);
121 if (ret < 0) {
122 dev_err(dev->dev, "Failed to read phy register\n");
123 return ret;
124 }
125
126 /* Read the VPHY register which has the PHY data */
127 return ksz_read16(dev, REG_VPHY_IND_DATA__2, val);
128}
129
130int lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data)
131{
132 return lan937x_internal_phy_read(dev, addr, reg, data);
133}
134
135int lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val)
136{
137 return lan937x_internal_phy_write(dev, addr, reg, val);
138}
139
140int lan937x_reset_switch(struct ksz_device *dev)
141{
142 u32 data32;
143 int ret;
144
145 /* reset switch */
146 ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
147 if (ret < 0)
148 return ret;
149
150 /* Enable Auto Aging */
151 ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true);
152 if (ret < 0)
153 return ret;
154
155 /* disable interrupts */
156 ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
157 if (ret < 0)
158 return ret;
159
160 ret = ksz_write32(dev, REG_SW_INT_STATUS__4, POR_READY_INT);
161 if (ret < 0)
162 return ret;
163
164 ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF);
165 if (ret < 0)
166 return ret;
167
168 return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
169}
170
171void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port)
172{
173 const u32 *masks = dev->info->masks;
174 const u16 *regs = dev->info->regs;
175 struct dsa_switch *ds = dev->ds;
176 u8 member;
177
178 /* enable tag tail for host port */
179 if (cpu_port)
180 lan937x_port_cfg(dev, port, REG_PORT_CTRL_0,
181 PORT_TAIL_TAG_ENABLE, true);
182
183 /* set back pressure for half duplex */
184 lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE,
185 true);
186
187 /* enable 802.1p priority */
188 lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
189
190 if (!dev->info->internal_phy[port])
191 lan937x_port_cfg(dev, port, regs[P_XMII_CTRL_0],
192 masks[P_MII_TX_FLOW_CTRL] |
193 masks[P_MII_RX_FLOW_CTRL],
194 true);
195
196 if (cpu_port)
197 member = dsa_user_ports(ds);
198 else
199 member = BIT(dsa_upstream_port(ds, port));
200
201 dev->dev_ops->cfg_port_member(dev, port, member);
202}
203
204void lan937x_config_cpu_port(struct dsa_switch *ds)
205{
206 struct ksz_device *dev = ds->priv;
207 struct dsa_port *dp;
208
209 dsa_switch_for_each_cpu_port(dp, ds) {
210 if (dev->info->cpu_ports & (1 << dp->index)) {
211 dev->cpu_port = dp->index;
212
213 /* enable cpu port */
214 lan937x_port_setup(dev, dp->index, true);
215 }
216 }
217
218 dsa_switch_for_each_user_port(dp, ds) {
219 ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED);
220 }
221}
222
223int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu)
224{
225 struct dsa_switch *ds = dev->ds;
226 int ret;
227
228 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
229
230 if (dsa_is_cpu_port(ds, port))
231 new_mtu += LAN937X_TAG_LEN;
232
233 if (new_mtu >= FR_MIN_SIZE)
234 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0,
235 PORT_JUMBO_PACKET, true);
236 else
237 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0,
238 PORT_JUMBO_PACKET, false);
239 if (ret < 0) {
240 dev_err(ds->dev, "failed to enable jumbo\n");
241 return ret;
242 }
243
244 /* Write the frame size in PORT_MAX_FR_SIZE register */
245 ret = ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu);
246 if (ret) {
247 dev_err(ds->dev, "failed to update mtu for port %d\n", port);
248 return ret;
249 }
250
251 return 0;
252}
253
254int lan937x_set_ageing_time(struct ksz_device *dev, unsigned int msecs)
255{
256 u32 secs = msecs / 1000;
257 u32 value;
258 int ret;
259
260 value = FIELD_GET(SW_AGE_PERIOD_7_0_M, secs);
261
262 ret = ksz_write8(dev, REG_SW_AGE_PERIOD__1, value);
263 if (ret < 0)
264 return ret;
265
266 value = FIELD_GET(SW_AGE_PERIOD_19_8_M, secs);
267
268 return ksz_write16(dev, REG_SW_AGE_PERIOD__2, value);
269}
270
271static void lan937x_set_tune_adj(struct ksz_device *dev, int port,
272 u16 reg, u8 val)
273{
274 u16 data16;
275
276 ksz_pread16(dev, port, reg, &data16);
277
278 /* Update tune Adjust */
279 data16 |= FIELD_PREP(PORT_TUNE_ADJ, val);
280 ksz_pwrite16(dev, port, reg, data16);
281
282 /* write DLL reset to take effect */
283 data16 |= PORT_DLL_RESET;
284 ksz_pwrite16(dev, port, reg, data16);
285}
286
287static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int port)
288{
289 u8 val;
290
291 /* Apply different codes based on the ports as per characterization
292 * results
293 */
294 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_TX_DELAY_2NS :
295 RGMII_2_TX_DELAY_2NS;
296
297 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val);
298}
299
300static void lan937x_set_rgmii_rx_delay(struct ksz_device *dev, int port)
301{
302 u8 val;
303
304 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_RX_DELAY_2NS :
305 RGMII_2_RX_DELAY_2NS;
306
307 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_4, val);
308}
309
310void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
311 struct phylink_config *config)
312{
313 config->mac_capabilities = MAC_100FD;
314
315 if (dev->info->supports_rgmii[port]) {
316 /* MII/RMII/RGMII ports */
317 config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
318 MAC_100HD | MAC_10 | MAC_1000FD;
319 }
320}
321
322void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port)
323{
324 struct ksz_port *p = &dev->ports[port];
325
326 if (p->rgmii_tx_val) {
327 lan937x_set_rgmii_tx_delay(dev, port);
328 dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n",
329 port);
330 }
331
332 if (p->rgmii_rx_val) {
333 lan937x_set_rgmii_rx_delay(dev, port);
334 dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n",
335 port);
336 }
337}
338
339int lan937x_switch_init(struct ksz_device *dev)
340{
341 dev->port_mask = (1 << dev->info->port_cnt) - 1;
342
343 return 0;
344}
345
346int lan937x_setup(struct dsa_switch *ds)
347{
348 struct ksz_device *dev = ds->priv;
349 int ret;
350
351 /* enable Indirect Access from SPI to the VPHY registers */
352 ret = lan937x_enable_spi_indirect_access(dev);
353 if (ret < 0) {
354 dev_err(dev->dev, "failed to enable spi indirect access");
355 return ret;
356 }
357
358 /* The VLAN aware is a global setting. Mixed vlan
359 * filterings are not supported.
360 */
361 ds->vlan_filtering_is_global = true;
362
363 /* Enable aggressive back off for half duplex & UNH mode */
364 lan937x_cfg(dev, REG_SW_MAC_CTRL_0,
365 (SW_PAUSE_UNH_MODE | SW_NEW_BACKOFF | SW_AGGR_BACKOFF),
366 true);
367
368 /* If NO_EXC_COLLISION_DROP bit is set, the switch will not drop
369 * packets when 16 or more collisions occur
370 */
371 lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true);
372
373 /* enable global MIB counter freeze function */
374 lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
375
376 /* disable CLK125 & CLK25, 1: disable, 0: enable */
377 lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
378 (SW_CLK125_ENB | SW_CLK25_ENB), true);
379
380 return 0;
381}
382
383void lan937x_teardown(struct dsa_switch *ds)
384{
385
386}
387
388void lan937x_switch_exit(struct ksz_device *dev)
389{
390 lan937x_reset_switch(dev);
391}
392
393MODULE_AUTHOR("Arun Ramadoss <arun.ramadoss@microchip.com>");
394MODULE_DESCRIPTION("Microchip LAN937x Series Switch DSA Driver");
395MODULE_LICENSE("GPL");