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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Microchip switch driver common header
3 *
4 * Copyright (C) 2017-2024 Microchip Technology Inc.
5 */
6
7#ifndef __KSZ_COMMON_H
8#define __KSZ_COMMON_H
9
10#include <linux/etherdevice.h>
11#include <linux/kernel.h>
12#include <linux/mutex.h>
13#include <linux/phy.h>
14#include <linux/regmap.h>
15#include <net/dsa.h>
16#include <linux/irq.h>
17#include <linux/platform_data/microchip-ksz.h>
18
19#include "ksz_ptp.h"
20
21#define KSZ_MAX_NUM_PORTS 8
22/* all KSZ switches count ports from 1 */
23#define KSZ_PORT_1 0
24#define KSZ_PORT_2 1
25#define KSZ_PORT_4 3
26
27struct ksz_device;
28struct ksz_port;
29struct phylink_mac_ops;
30
31enum ksz_regmap_width {
32 KSZ_REGMAP_8,
33 KSZ_REGMAP_16,
34 KSZ_REGMAP_32,
35 __KSZ_NUM_REGMAPS,
36};
37
38struct vlan_table {
39 u32 table[3];
40};
41
42struct ksz_port_mib {
43 struct mutex cnt_mutex; /* structure access */
44 u8 cnt_ptr;
45 u64 *counters;
46 struct rtnl_link_stats64 stats64;
47 struct ethtool_pause_stats pause_stats;
48 struct spinlock stats64_lock;
49};
50
51struct ksz_mib_names {
52 int index;
53 char string[ETH_GSTRING_LEN];
54};
55
56struct ksz_chip_data {
57 u32 chip_id;
58 const char *dev_name;
59 int num_vlans;
60 int num_alus;
61 int num_statics;
62 int cpu_ports;
63 int port_cnt;
64 u8 port_nirqs;
65 u8 num_tx_queues;
66 u8 num_ipms; /* number of Internal Priority Maps */
67 bool tc_cbs_supported;
68
69 /**
70 * @phy_side_mdio_supported: Indicates if the chip supports an additional
71 * side MDIO channel for accessing integrated PHYs.
72 */
73 bool phy_side_mdio_supported;
74 const struct ksz_dev_ops *ops;
75 const struct phylink_mac_ops *phylink_mac_ops;
76 bool phy_errata_9477;
77 bool ksz87xx_eee_link_erratum;
78 const struct ksz_mib_names *mib_names;
79 int mib_cnt;
80 u8 reg_mib_cnt;
81 const u16 *regs;
82 const u32 *masks;
83 const u8 *shifts;
84 const u8 *xmii_ctrl0;
85 const u8 *xmii_ctrl1;
86 int stp_ctrl_reg;
87 int broadcast_ctrl_reg;
88 int multicast_ctrl_reg;
89 int start_ctrl_reg;
90 bool supports_mii[KSZ_MAX_NUM_PORTS];
91 bool supports_rmii[KSZ_MAX_NUM_PORTS];
92 bool supports_rgmii[KSZ_MAX_NUM_PORTS];
93 bool internal_phy[KSZ_MAX_NUM_PORTS];
94 bool gbit_capable[KSZ_MAX_NUM_PORTS];
95 const struct regmap_access_table *wr_table;
96 const struct regmap_access_table *rd_table;
97};
98
99struct ksz_irq {
100 u16 masked;
101 u16 reg_mask;
102 u16 reg_status;
103 struct irq_domain *domain;
104 int nirqs;
105 int irq_num;
106 char name[16];
107 struct ksz_device *dev;
108};
109
110struct ksz_ptp_irq {
111 struct ksz_port *port;
112 u16 ts_reg;
113 bool ts_en;
114 char name[16];
115 int num;
116};
117
118struct ksz_switch_macaddr {
119 unsigned char addr[ETH_ALEN];
120 refcount_t refcount;
121};
122
123struct ksz_port {
124 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */
125 bool learning;
126 bool isolated;
127 int stp_state;
128 struct phy_device phydev;
129
130 u32 fiber:1; /* port is fiber */
131 u32 force:1;
132 u32 read:1; /* read MIB counters in background */
133 u32 freeze:1; /* MIB counter freeze is enabled */
134
135 struct ksz_port_mib mib;
136 phy_interface_t interface;
137 u32 rgmii_tx_val;
138 u32 rgmii_rx_val;
139 struct ksz_device *ksz_dev;
140 void *acl_priv;
141 struct ksz_irq pirq;
142 u8 num;
143#if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP)
144 struct hwtstamp_config tstamp_config;
145 bool hwts_tx_en;
146 bool hwts_rx_en;
147 struct ksz_irq ptpirq;
148 struct ksz_ptp_irq ptpmsg_irq[3];
149 ktime_t tstamp_msg;
150 struct completion tstamp_msg_comp;
151#endif
152 bool manual_flow;
153};
154
155struct ksz_device {
156 struct dsa_switch *ds;
157 struct ksz_platform_data *pdata;
158 const struct ksz_chip_data *info;
159
160 struct mutex dev_mutex; /* device access */
161 struct mutex regmap_mutex; /* regmap access */
162 struct mutex alu_mutex; /* ALU access */
163 struct mutex vlan_mutex; /* vlan access */
164 const struct ksz_dev_ops *dev_ops;
165
166 struct device *dev;
167 struct regmap *regmap[__KSZ_NUM_REGMAPS];
168
169 void *priv;
170 int irq;
171
172 struct gpio_desc *reset_gpio; /* Optional reset GPIO */
173
174 /* chip specific data */
175 u32 chip_id;
176 u8 chip_rev;
177 int cpu_port; /* port connected to CPU */
178 int phy_port_cnt;
179 phy_interface_t compat_interface;
180 bool synclko_125;
181 bool synclko_disable;
182 bool wakeup_source;
183 bool pme_active_high;
184
185 struct vlan_table *vlan_cache;
186
187 struct ksz_port *ports;
188 struct delayed_work mib_read;
189 unsigned long mib_read_interval;
190 u16 mirror_rx;
191 u16 mirror_tx;
192 u16 port_mask;
193 struct mutex lock_irq; /* IRQ Access */
194 struct ksz_irq girq;
195 struct ksz_ptp_data ptp_data;
196
197 struct ksz_switch_macaddr *switch_macaddr;
198 struct net_device *hsr_dev; /* HSR */
199 u8 hsr_ports;
200
201 /**
202 * @phy_addr_map: Array mapping switch ports to their corresponding PHY
203 * addresses.
204 */
205 u8 phy_addr_map[KSZ_MAX_NUM_PORTS];
206
207 /**
208 * @parent_mdio_bus: Pointer to the external MDIO bus controller.
209 *
210 * This points to an external MDIO bus controller that is used to access
211 * the PHYs integrated within the switch. Unlike an integrated MDIO
212 * bus, this external controller provides a direct path for managing
213 * the switch’s internal PHYs, bypassing the main SPI interface.
214 */
215 struct mii_bus *parent_mdio_bus;
216};
217
218/* List of supported models */
219enum ksz_model {
220 KSZ8563,
221 KSZ8567,
222 KSZ8795,
223 KSZ8794,
224 KSZ8765,
225 KSZ88X3,
226 KSZ8864,
227 KSZ8895,
228 KSZ9477,
229 KSZ9896,
230 KSZ9897,
231 KSZ9893,
232 KSZ9563,
233 KSZ9567,
234 LAN9370,
235 LAN9371,
236 LAN9372,
237 LAN9373,
238 LAN9374,
239 LAN9646,
240};
241
242enum ksz_regs {
243 REG_SW_MAC_ADDR,
244 REG_IND_CTRL_0,
245 REG_IND_DATA_8,
246 REG_IND_DATA_CHECK,
247 REG_IND_DATA_HI,
248 REG_IND_DATA_LO,
249 REG_IND_MIB_CHECK,
250 REG_IND_BYTE,
251 P_FORCE_CTRL,
252 P_LINK_STATUS,
253 P_LOCAL_CTRL,
254 P_NEG_RESTART_CTRL,
255 P_REMOTE_STATUS,
256 P_SPEED_STATUS,
257 S_TAIL_TAG_CTRL,
258 P_STP_CTRL,
259 S_START_CTRL,
260 S_BROADCAST_CTRL,
261 S_MULTICAST_CTRL,
262 P_XMII_CTRL_0,
263 P_XMII_CTRL_1,
264 REG_SW_PME_CTRL,
265 REG_PORT_PME_STATUS,
266 REG_PORT_PME_CTRL,
267};
268
269enum ksz_masks {
270 PORT_802_1P_REMAPPING,
271 SW_TAIL_TAG_ENABLE,
272 MIB_COUNTER_OVERFLOW,
273 MIB_COUNTER_VALID,
274 VLAN_TABLE_FID,
275 VLAN_TABLE_MEMBERSHIP,
276 VLAN_TABLE_VALID,
277 STATIC_MAC_TABLE_VALID,
278 STATIC_MAC_TABLE_USE_FID,
279 STATIC_MAC_TABLE_FID,
280 STATIC_MAC_TABLE_OVERRIDE,
281 STATIC_MAC_TABLE_FWD_PORTS,
282 DYNAMIC_MAC_TABLE_ENTRIES_H,
283 DYNAMIC_MAC_TABLE_MAC_EMPTY,
284 DYNAMIC_MAC_TABLE_NOT_READY,
285 DYNAMIC_MAC_TABLE_ENTRIES,
286 DYNAMIC_MAC_TABLE_FID,
287 DYNAMIC_MAC_TABLE_SRC_PORT,
288 DYNAMIC_MAC_TABLE_TIMESTAMP,
289 ALU_STAT_WRITE,
290 ALU_STAT_READ,
291 P_MII_TX_FLOW_CTRL,
292 P_MII_RX_FLOW_CTRL,
293};
294
295enum ksz_shifts {
296 VLAN_TABLE_MEMBERSHIP_S,
297 VLAN_TABLE,
298 STATIC_MAC_FWD_PORTS,
299 STATIC_MAC_FID,
300 DYNAMIC_MAC_ENTRIES_H,
301 DYNAMIC_MAC_ENTRIES,
302 DYNAMIC_MAC_FID,
303 DYNAMIC_MAC_TIMESTAMP,
304 DYNAMIC_MAC_SRC_PORT,
305 ALU_STAT_INDEX,
306};
307
308enum ksz_xmii_ctrl0 {
309 P_MII_100MBIT,
310 P_MII_10MBIT,
311 P_MII_FULL_DUPLEX,
312 P_MII_HALF_DUPLEX,
313};
314
315enum ksz_xmii_ctrl1 {
316 P_RGMII_SEL,
317 P_RMII_SEL,
318 P_GMII_SEL,
319 P_MII_SEL,
320 P_GMII_1GBIT,
321 P_GMII_NOT_1GBIT,
322};
323
324struct alu_struct {
325 /* entry 1 */
326 u8 is_static:1;
327 u8 is_src_filter:1;
328 u8 is_dst_filter:1;
329 u8 prio_age:3;
330 u32 _reserv_0_1:23;
331 u8 mstp:3;
332 /* entry 2 */
333 u8 is_override:1;
334 u8 is_use_fid:1;
335 u32 _reserv_1_1:23;
336 u8 port_forward:7;
337 /* entry 3 & 4*/
338 u32 _reserv_2_1:9;
339 u8 fid:7;
340 u8 mac[ETH_ALEN];
341};
342
343struct ksz_dev_ops {
344 int (*setup)(struct dsa_switch *ds);
345 void (*teardown)(struct dsa_switch *ds);
346 u32 (*get_port_addr)(int port, int offset);
347 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member);
348 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port);
349 void (*port_cleanup)(struct ksz_device *dev, int port);
350 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port);
351 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs);
352
353 /**
354 * @mdio_bus_preinit: Function pointer to pre-initialize the MDIO bus
355 * for accessing PHYs.
356 * @dev: Pointer to device structure.
357 * @side_mdio: Boolean indicating if the PHYs are accessed over a side
358 * MDIO bus.
359 *
360 * This function pointer is used to configure the MDIO bus for PHY
361 * access before initiating regular PHY operations. It enables either
362 * SPI/I2C or side MDIO access modes by unlocking necessary registers
363 * and setting up access permissions for the selected mode.
364 *
365 * Return:
366 * - 0 on success.
367 * - Negative error code on failure.
368 */
369 int (*mdio_bus_preinit)(struct ksz_device *dev, bool side_mdio);
370
371 /**
372 * @create_phy_addr_map: Function pointer to create a port-to-PHY
373 * address map.
374 * @dev: Pointer to device structure.
375 * @side_mdio: Boolean indicating if the PHYs are accessed over a side
376 * MDIO bus.
377 *
378 * This function pointer is responsible for mapping switch ports to PHY
379 * addresses according to the configured access mode (SPI or side MDIO)
380 * and the device’s strap configuration. The mapping setup may vary
381 * depending on the chip variant and configuration. Ensures the correct
382 * address mapping for PHY communication.
383 *
384 * Return:
385 * - 0 on success.
386 * - Negative error code on failure (e.g., invalid configuration).
387 */
388 int (*create_phy_addr_map)(struct ksz_device *dev, bool side_mdio);
389 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val);
390 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val);
391 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr,
392 u64 *cnt);
393 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr,
394 u64 *dropped, u64 *cnt);
395 void (*r_mib_stat64)(struct ksz_device *dev, int port);
396 int (*vlan_filtering)(struct ksz_device *dev, int port,
397 bool flag, struct netlink_ext_ack *extack);
398 int (*vlan_add)(struct ksz_device *dev, int port,
399 const struct switchdev_obj_port_vlan *vlan,
400 struct netlink_ext_ack *extack);
401 int (*vlan_del)(struct ksz_device *dev, int port,
402 const struct switchdev_obj_port_vlan *vlan);
403 int (*mirror_add)(struct ksz_device *dev, int port,
404 struct dsa_mall_mirror_tc_entry *mirror,
405 bool ingress, struct netlink_ext_ack *extack);
406 void (*mirror_del)(struct ksz_device *dev, int port,
407 struct dsa_mall_mirror_tc_entry *mirror);
408 int (*fdb_add)(struct ksz_device *dev, int port,
409 const unsigned char *addr, u16 vid, struct dsa_db db);
410 int (*fdb_del)(struct ksz_device *dev, int port,
411 const unsigned char *addr, u16 vid, struct dsa_db db);
412 int (*fdb_dump)(struct ksz_device *dev, int port,
413 dsa_fdb_dump_cb_t *cb, void *data);
414 int (*mdb_add)(struct ksz_device *dev, int port,
415 const struct switchdev_obj_port_mdb *mdb,
416 struct dsa_db db);
417 int (*mdb_del)(struct ksz_device *dev, int port,
418 const struct switchdev_obj_port_mdb *mdb,
419 struct dsa_db db);
420 void (*get_caps)(struct ksz_device *dev, int port,
421 struct phylink_config *config);
422 int (*change_mtu)(struct ksz_device *dev, int port, int mtu);
423 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value);
424 int (*pme_pread8)(struct ksz_device *dev, int port, int offset,
425 u8 *data);
426 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset,
427 u8 data);
428 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
429 void (*port_init_cnt)(struct ksz_device *dev, int port);
430 void (*phylink_mac_link_up)(struct ksz_device *dev, int port,
431 unsigned int mode,
432 phy_interface_t interface,
433 struct phy_device *phydev, int speed,
434 int duplex, bool tx_pause, bool rx_pause);
435 void (*setup_rgmii_delay)(struct ksz_device *dev, int port);
436 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val);
437 void (*config_cpu_port)(struct dsa_switch *ds);
438 int (*enable_stp_addr)(struct ksz_device *dev);
439 int (*reset)(struct ksz_device *dev);
440 int (*init)(struct ksz_device *dev);
441 void (*exit)(struct ksz_device *dev);
442};
443
444struct ksz_device *ksz_switch_alloc(struct device *base, void *priv);
445int ksz_switch_register(struct ksz_device *dev);
446void ksz_switch_remove(struct ksz_device *dev);
447
448void ksz_init_mib_timer(struct ksz_device *dev);
449bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port);
450void ksz_r_mib_stats64(struct ksz_device *dev, int port);
451void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port);
452void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
453bool ksz_get_gbit(struct ksz_device *dev, int port);
454phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
455extern const struct ksz_chip_data ksz_switch_chips[];
456int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
457 struct netlink_ext_ack *extack);
458void ksz_switch_macaddr_put(struct dsa_switch *ds);
459void ksz_switch_shutdown(struct ksz_device *dev);
460int ksz_handle_wake_reason(struct ksz_device *dev, int port);
461
462/* Common register access functions */
463static inline struct regmap *ksz_regmap_8(struct ksz_device *dev)
464{
465 return dev->regmap[KSZ_REGMAP_8];
466}
467
468static inline struct regmap *ksz_regmap_16(struct ksz_device *dev)
469{
470 return dev->regmap[KSZ_REGMAP_16];
471}
472
473static inline struct regmap *ksz_regmap_32(struct ksz_device *dev)
474{
475 return dev->regmap[KSZ_REGMAP_32];
476}
477
478static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val)
479{
480 unsigned int value;
481 int ret = regmap_read(ksz_regmap_8(dev), reg, &value);
482
483 if (ret)
484 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg,
485 ERR_PTR(ret));
486
487 *val = value;
488 return ret;
489}
490
491static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val)
492{
493 unsigned int value;
494 int ret = regmap_read(ksz_regmap_16(dev), reg, &value);
495
496 if (ret)
497 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg,
498 ERR_PTR(ret));
499
500 *val = value;
501 return ret;
502}
503
504static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val)
505{
506 unsigned int value;
507 int ret = regmap_read(ksz_regmap_32(dev), reg, &value);
508
509 if (ret)
510 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg,
511 ERR_PTR(ret));
512
513 *val = value;
514 return ret;
515}
516
517static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val)
518{
519 u32 value[2];
520 int ret;
521
522 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2);
523 if (ret)
524 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg,
525 ERR_PTR(ret));
526 else
527 *val = (u64)value[0] << 32 | value[1];
528
529 return ret;
530}
531
532static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value)
533{
534 int ret;
535
536 ret = regmap_write(ksz_regmap_8(dev), reg, value);
537 if (ret)
538 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg,
539 ERR_PTR(ret));
540
541 return ret;
542}
543
544static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value)
545{
546 int ret;
547
548 ret = regmap_write(ksz_regmap_16(dev), reg, value);
549 if (ret)
550 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg,
551 ERR_PTR(ret));
552
553 return ret;
554}
555
556static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value)
557{
558 int ret;
559
560 ret = regmap_write(ksz_regmap_32(dev), reg, value);
561 if (ret)
562 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg,
563 ERR_PTR(ret));
564
565 return ret;
566}
567
568static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask,
569 u16 value)
570{
571 int ret;
572
573 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value);
574 if (ret)
575 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg,
576 ERR_PTR(ret));
577
578 return ret;
579}
580
581static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask,
582 u32 value)
583{
584 int ret;
585
586 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value);
587 if (ret)
588 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg,
589 ERR_PTR(ret));
590
591 return ret;
592}
593
594static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
595{
596 u32 val[2];
597
598 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
599 value = swab64(value);
600 val[0] = swab32(value & 0xffffffffULL);
601 val[1] = swab32(value >> 32ULL);
602
603 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2);
604}
605
606static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val)
607{
608 int ret;
609
610 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val);
611 if (ret)
612 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset,
613 ERR_PTR(ret));
614
615 return ret;
616}
617
618static inline int ksz_pread8(struct ksz_device *dev, int port, int offset,
619 u8 *data)
620{
621 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data);
622}
623
624static inline int ksz_pread16(struct ksz_device *dev, int port, int offset,
625 u16 *data)
626{
627 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data);
628}
629
630static inline int ksz_pread32(struct ksz_device *dev, int port, int offset,
631 u32 *data)
632{
633 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data);
634}
635
636static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset,
637 u8 data)
638{
639 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data);
640}
641
642static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset,
643 u16 data)
644{
645 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset),
646 data);
647}
648
649static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset,
650 u32 data)
651{
652 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset),
653 data);
654}
655
656static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset,
657 u8 mask, u8 val)
658{
659 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset),
660 mask, val);
661}
662
663static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset,
664 u32 mask, u32 val)
665{
666 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset),
667 mask, val);
668}
669
670static inline void ksz_regmap_lock(void *__mtx)
671{
672 struct mutex *mtx = __mtx;
673 mutex_lock(mtx);
674}
675
676static inline void ksz_regmap_unlock(void *__mtx)
677{
678 struct mutex *mtx = __mtx;
679 mutex_unlock(mtx);
680}
681
682static inline bool ksz_is_ksz87xx(struct ksz_device *dev)
683{
684 return dev->chip_id == KSZ8795_CHIP_ID ||
685 dev->chip_id == KSZ8794_CHIP_ID ||
686 dev->chip_id == KSZ8765_CHIP_ID;
687}
688
689static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
690{
691 return dev->chip_id == KSZ88X3_CHIP_ID;
692}
693
694static inline bool ksz_is_8895_family(struct ksz_device *dev)
695{
696 return dev->chip_id == KSZ8895_CHIP_ID ||
697 dev->chip_id == KSZ8864_CHIP_ID;
698}
699
700static inline bool is_ksz8(struct ksz_device *dev)
701{
702 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) ||
703 ksz_is_8895_family(dev);
704}
705
706static inline bool is_ksz88xx(struct ksz_device *dev)
707{
708 return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev);
709}
710
711static inline bool is_ksz9477(struct ksz_device *dev)
712{
713 return dev->chip_id == KSZ9477_CHIP_ID;
714}
715
716static inline int is_lan937x(struct ksz_device *dev)
717{
718 return dev->chip_id == LAN9370_CHIP_ID ||
719 dev->chip_id == LAN9371_CHIP_ID ||
720 dev->chip_id == LAN9372_CHIP_ID ||
721 dev->chip_id == LAN9373_CHIP_ID ||
722 dev->chip_id == LAN9374_CHIP_ID;
723}
724
725static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port)
726{
727 return (dev->chip_id == LAN9371_CHIP_ID ||
728 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4;
729}
730
731/* STP State Defines */
732#define PORT_TX_ENABLE BIT(2)
733#define PORT_RX_ENABLE BIT(1)
734#define PORT_LEARN_DISABLE BIT(0)
735
736/* Switch ID Defines */
737#define REG_CHIP_ID0 0x00
738
739#define SW_FAMILY_ID_M GENMASK(15, 8)
740#define KSZ87_FAMILY_ID 0x87
741#define KSZ88_FAMILY_ID 0x88
742#define KSZ8895_FAMILY_ID 0x95
743
744#define KSZ8_PORT_STATUS_0 0x08
745#define KSZ8_PORT_FIBER_MODE BIT(7)
746
747#define SW_CHIP_ID_M GENMASK(7, 4)
748#define KSZ87_CHIP_ID_94 0x6
749#define KSZ87_CHIP_ID_95 0x9
750#define KSZ88_CHIP_ID_63 0x3
751#define KSZ8895_CHIP_ID_95 0x4
752#define KSZ8895_CHIP_ID_95R 0x6
753
754/* KSZ8895 specific register */
755#define REG_KSZ8864_CHIP_ID 0xFE
756#define SW_KSZ8864 BIT(7)
757
758#define SW_REV_ID_M GENMASK(7, 4)
759
760/* KSZ9893, KSZ9563, KSZ8563 specific register */
761#define REG_CHIP_ID4 0x0f
762#define SKU_ID_KSZ8563 0x3c
763#define SKU_ID_KSZ9563 0x1c
764
765/* Driver set switch broadcast storm protection at 10% rate. */
766#define BROADCAST_STORM_PROT_RATE 10
767
768/* 148,800 frames * 67 ms / 100 */
769#define BROADCAST_STORM_VALUE 9969
770
771#define BROADCAST_STORM_RATE_HI 0x07
772#define BROADCAST_STORM_RATE_LO 0xFF
773#define BROADCAST_STORM_RATE 0x07FF
774
775#define MULTICAST_STORM_DISABLE BIT(6)
776
777#define SW_START 0x01
778
779/* xMII configuration */
780#define P_MII_DUPLEX_M BIT(6)
781#define P_MII_100MBIT_M BIT(4)
782
783#define P_GMII_1GBIT_M BIT(6)
784#define P_RGMII_ID_IG_ENABLE BIT(4)
785#define P_RGMII_ID_EG_ENABLE BIT(3)
786#define P_MII_MAC_MODE BIT(2)
787#define P_MII_SEL_M 0x3
788
789/* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */
790#define PME_WOL_MAGICPKT BIT(2)
791#define PME_WOL_LINKUP BIT(1)
792#define PME_WOL_ENERGY BIT(0)
793
794#define PME_ENABLE BIT(1)
795#define PME_POLARITY BIT(0)
796
797#define KSZ87XX_REG_INT_EN 0x7D
798#define KSZ87XX_INT_PME_MASK BIT(4)
799
800/* Interrupt */
801#define REG_SW_PORT_INT_STATUS__1 0x001B
802#define REG_SW_PORT_INT_MASK__1 0x001F
803
804#define REG_PORT_INT_STATUS 0x001B
805#define REG_PORT_INT_MASK 0x001F
806
807#define PORT_SRC_PHY_INT 1
808#define PORT_SRC_PTP_INT 2
809
810#define KSZ8795_HUGE_PACKET_SIZE 2000
811#define KSZ8863_HUGE_PACKET_SIZE 1916
812#define KSZ8863_NORMAL_PACKET_SIZE 1536
813#define KSZ8_LEGAL_PACKET_SIZE 1518
814#define KSZ9477_MAX_FRAME_SIZE 9000
815
816#define KSZ8873_REG_GLOBAL_CTRL_12 0x0e
817/* Drive Strength of I/O Pad
818 * 0: 8mA, 1: 16mA
819 */
820#define KSZ8873_DRIVE_STRENGTH_16MA BIT(6)
821
822#define KSZ8795_REG_SW_CTRL_20 0xa3
823#define KSZ9477_REG_SW_IO_STRENGTH 0x010d
824#define SW_DRIVE_STRENGTH_M 0x7
825#define SW_DRIVE_STRENGTH_2MA 0
826#define SW_DRIVE_STRENGTH_4MA 1
827#define SW_DRIVE_STRENGTH_8MA 2
828#define SW_DRIVE_STRENGTH_12MA 3
829#define SW_DRIVE_STRENGTH_16MA 4
830#define SW_DRIVE_STRENGTH_20MA 5
831#define SW_DRIVE_STRENGTH_24MA 6
832#define SW_DRIVE_STRENGTH_28MA 7
833#define SW_HI_SPEED_DRIVE_STRENGTH_S 4
834#define SW_LO_SPEED_DRIVE_STRENGTH_S 0
835
836#define KSZ9477_REG_PORT_OUT_RATE_0 0x0420
837#define KSZ9477_OUT_RATE_NO_LIMIT 0
838
839#define KSZ9477_PORT_MRI_TC_MAP__4 0x0808
840
841#define KSZ9477_PORT_TC_MAP_S 4
842
843/* CBS related registers */
844#define REG_PORT_MTI_QUEUE_INDEX__4 0x0900
845
846#define REG_PORT_MTI_QUEUE_CTRL_0 0x0914
847
848#define MTI_SCHEDULE_MODE_M GENMASK(7, 6)
849#define MTI_SCHEDULE_STRICT_PRIO 0
850#define MTI_SCHEDULE_WRR 2
851#define MTI_SHAPING_M GENMASK(5, 4)
852#define MTI_SHAPING_OFF 0
853#define MTI_SHAPING_SRP 1
854#define MTI_SHAPING_TIME_AWARE 2
855
856#define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915
857#define KSZ9477_DEFAULT_WRR_WEIGHT 1
858
859#define REG_PORT_MTI_HI_WATER_MARK 0x0916
860#define REG_PORT_MTI_LO_WATER_MARK 0x0918
861
862/* Regmap tables generation */
863#define KSZ_SPI_OP_RD 3
864#define KSZ_SPI_OP_WR 2
865
866#define swabnot_used(x) 0
867
868#define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \
869 swab##swp((opcode) << ((regbits) + (regpad)))
870
871#define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \
872 { \
873 .name = #width, \
874 .val_bits = (width), \
875 .reg_stride = 1, \
876 .reg_bits = (regbits) + (regalign), \
877 .pad_bits = (regpad), \
878 .max_register = BIT(regbits) - 1, \
879 .cache_type = REGCACHE_NONE, \
880 .read_flag_mask = \
881 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \
882 regbits, regpad), \
883 .write_flag_mask = \
884 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \
885 regbits, regpad), \
886 .lock = ksz_regmap_lock, \
887 .unlock = ksz_regmap_unlock, \
888 .reg_format_endian = REGMAP_ENDIAN_BIG, \
889 .val_format_endian = REGMAP_ENDIAN_BIG \
890 }
891
892#define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \
893 static const struct regmap_config ksz##_regmap_config[] = { \
894 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \
895 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \
896 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \
897 }
898
899#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Microchip switch driver common header
3 *
4 * Copyright (C) 2017-2019 Microchip Technology Inc.
5 */
6
7#ifndef __KSZ_COMMON_H
8#define __KSZ_COMMON_H
9
10#include <linux/etherdevice.h>
11#include <linux/kernel.h>
12#include <linux/mutex.h>
13#include <linux/phy.h>
14#include <linux/regmap.h>
15#include <net/dsa.h>
16#include <linux/irq.h>
17
18#define KSZ_MAX_NUM_PORTS 8
19
20struct ksz_device;
21
22struct vlan_table {
23 u32 table[3];
24};
25
26struct ksz_port_mib {
27 struct mutex cnt_mutex; /* structure access */
28 u8 cnt_ptr;
29 u64 *counters;
30 struct rtnl_link_stats64 stats64;
31 struct ethtool_pause_stats pause_stats;
32 struct spinlock stats64_lock;
33};
34
35struct ksz_mib_names {
36 int index;
37 char string[ETH_GSTRING_LEN];
38};
39
40struct ksz_chip_data {
41 u32 chip_id;
42 const char *dev_name;
43 int num_vlans;
44 int num_alus;
45 int num_statics;
46 int cpu_ports;
47 int port_cnt;
48 u8 port_nirqs;
49 const struct ksz_dev_ops *ops;
50 bool phy_errata_9477;
51 bool ksz87xx_eee_link_erratum;
52 const struct ksz_mib_names *mib_names;
53 int mib_cnt;
54 u8 reg_mib_cnt;
55 const u16 *regs;
56 const u32 *masks;
57 const u8 *shifts;
58 const u8 *xmii_ctrl0;
59 const u8 *xmii_ctrl1;
60 int stp_ctrl_reg;
61 int broadcast_ctrl_reg;
62 int multicast_ctrl_reg;
63 int start_ctrl_reg;
64 bool supports_mii[KSZ_MAX_NUM_PORTS];
65 bool supports_rmii[KSZ_MAX_NUM_PORTS];
66 bool supports_rgmii[KSZ_MAX_NUM_PORTS];
67 bool internal_phy[KSZ_MAX_NUM_PORTS];
68 bool gbit_capable[KSZ_MAX_NUM_PORTS];
69 const struct regmap_access_table *wr_table;
70 const struct regmap_access_table *rd_table;
71};
72
73struct ksz_irq {
74 u16 masked;
75 u16 reg_mask;
76 u16 reg_status;
77 struct irq_domain *domain;
78 int nirqs;
79 int irq_num;
80 char name[16];
81 struct ksz_device *dev;
82};
83
84struct ksz_port {
85 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */
86 bool learning;
87 int stp_state;
88 struct phy_device phydev;
89
90 u32 on:1; /* port is not disabled by hardware */
91 u32 fiber:1; /* port is fiber */
92 u32 force:1;
93 u32 read:1; /* read MIB counters in background */
94 u32 freeze:1; /* MIB counter freeze is enabled */
95
96 struct ksz_port_mib mib;
97 phy_interface_t interface;
98 u32 rgmii_tx_val;
99 u32 rgmii_rx_val;
100 struct ksz_device *ksz_dev;
101 struct ksz_irq pirq;
102 u8 num;
103};
104
105struct ksz_device {
106 struct dsa_switch *ds;
107 struct ksz_platform_data *pdata;
108 const struct ksz_chip_data *info;
109
110 struct mutex dev_mutex; /* device access */
111 struct mutex regmap_mutex; /* regmap access */
112 struct mutex alu_mutex; /* ALU access */
113 struct mutex vlan_mutex; /* vlan access */
114 const struct ksz_dev_ops *dev_ops;
115
116 struct device *dev;
117 struct regmap *regmap[3];
118
119 void *priv;
120 int irq;
121
122 struct gpio_desc *reset_gpio; /* Optional reset GPIO */
123
124 /* chip specific data */
125 u32 chip_id;
126 u8 chip_rev;
127 int cpu_port; /* port connected to CPU */
128 int phy_port_cnt;
129 phy_interface_t compat_interface;
130 bool synclko_125;
131 bool synclko_disable;
132
133 struct vlan_table *vlan_cache;
134
135 struct ksz_port *ports;
136 struct delayed_work mib_read;
137 unsigned long mib_read_interval;
138 u16 mirror_rx;
139 u16 mirror_tx;
140 u16 port_mask;
141 struct mutex lock_irq; /* IRQ Access */
142 struct ksz_irq girq;
143};
144
145/* List of supported models */
146enum ksz_model {
147 KSZ8563,
148 KSZ8795,
149 KSZ8794,
150 KSZ8765,
151 KSZ8830,
152 KSZ9477,
153 KSZ9896,
154 KSZ9897,
155 KSZ9893,
156 KSZ9563,
157 KSZ9567,
158 LAN9370,
159 LAN9371,
160 LAN9372,
161 LAN9373,
162 LAN9374,
163};
164
165enum ksz_chip_id {
166 KSZ8563_CHIP_ID = 0x8563,
167 KSZ8795_CHIP_ID = 0x8795,
168 KSZ8794_CHIP_ID = 0x8794,
169 KSZ8765_CHIP_ID = 0x8765,
170 KSZ8830_CHIP_ID = 0x8830,
171 KSZ9477_CHIP_ID = 0x00947700,
172 KSZ9896_CHIP_ID = 0x00989600,
173 KSZ9897_CHIP_ID = 0x00989700,
174 KSZ9893_CHIP_ID = 0x00989300,
175 KSZ9563_CHIP_ID = 0x00956300,
176 KSZ9567_CHIP_ID = 0x00956700,
177 LAN9370_CHIP_ID = 0x00937000,
178 LAN9371_CHIP_ID = 0x00937100,
179 LAN9372_CHIP_ID = 0x00937200,
180 LAN9373_CHIP_ID = 0x00937300,
181 LAN9374_CHIP_ID = 0x00937400,
182};
183
184enum ksz_regs {
185 REG_IND_CTRL_0,
186 REG_IND_DATA_8,
187 REG_IND_DATA_CHECK,
188 REG_IND_DATA_HI,
189 REG_IND_DATA_LO,
190 REG_IND_MIB_CHECK,
191 REG_IND_BYTE,
192 P_FORCE_CTRL,
193 P_LINK_STATUS,
194 P_LOCAL_CTRL,
195 P_NEG_RESTART_CTRL,
196 P_REMOTE_STATUS,
197 P_SPEED_STATUS,
198 S_TAIL_TAG_CTRL,
199 P_STP_CTRL,
200 S_START_CTRL,
201 S_BROADCAST_CTRL,
202 S_MULTICAST_CTRL,
203 P_XMII_CTRL_0,
204 P_XMII_CTRL_1,
205};
206
207enum ksz_masks {
208 PORT_802_1P_REMAPPING,
209 SW_TAIL_TAG_ENABLE,
210 MIB_COUNTER_OVERFLOW,
211 MIB_COUNTER_VALID,
212 VLAN_TABLE_FID,
213 VLAN_TABLE_MEMBERSHIP,
214 VLAN_TABLE_VALID,
215 STATIC_MAC_TABLE_VALID,
216 STATIC_MAC_TABLE_USE_FID,
217 STATIC_MAC_TABLE_FID,
218 STATIC_MAC_TABLE_OVERRIDE,
219 STATIC_MAC_TABLE_FWD_PORTS,
220 DYNAMIC_MAC_TABLE_ENTRIES_H,
221 DYNAMIC_MAC_TABLE_MAC_EMPTY,
222 DYNAMIC_MAC_TABLE_NOT_READY,
223 DYNAMIC_MAC_TABLE_ENTRIES,
224 DYNAMIC_MAC_TABLE_FID,
225 DYNAMIC_MAC_TABLE_SRC_PORT,
226 DYNAMIC_MAC_TABLE_TIMESTAMP,
227 ALU_STAT_WRITE,
228 ALU_STAT_READ,
229 P_MII_TX_FLOW_CTRL,
230 P_MII_RX_FLOW_CTRL,
231};
232
233enum ksz_shifts {
234 VLAN_TABLE_MEMBERSHIP_S,
235 VLAN_TABLE,
236 STATIC_MAC_FWD_PORTS,
237 STATIC_MAC_FID,
238 DYNAMIC_MAC_ENTRIES_H,
239 DYNAMIC_MAC_ENTRIES,
240 DYNAMIC_MAC_FID,
241 DYNAMIC_MAC_TIMESTAMP,
242 DYNAMIC_MAC_SRC_PORT,
243 ALU_STAT_INDEX,
244};
245
246enum ksz_xmii_ctrl0 {
247 P_MII_100MBIT,
248 P_MII_10MBIT,
249 P_MII_FULL_DUPLEX,
250 P_MII_HALF_DUPLEX,
251};
252
253enum ksz_xmii_ctrl1 {
254 P_RGMII_SEL,
255 P_RMII_SEL,
256 P_GMII_SEL,
257 P_MII_SEL,
258 P_GMII_1GBIT,
259 P_GMII_NOT_1GBIT,
260};
261
262struct alu_struct {
263 /* entry 1 */
264 u8 is_static:1;
265 u8 is_src_filter:1;
266 u8 is_dst_filter:1;
267 u8 prio_age:3;
268 u32 _reserv_0_1:23;
269 u8 mstp:3;
270 /* entry 2 */
271 u8 is_override:1;
272 u8 is_use_fid:1;
273 u32 _reserv_1_1:23;
274 u8 port_forward:7;
275 /* entry 3 & 4*/
276 u32 _reserv_2_1:9;
277 u8 fid:7;
278 u8 mac[ETH_ALEN];
279};
280
281struct ksz_dev_ops {
282 int (*setup)(struct dsa_switch *ds);
283 void (*teardown)(struct dsa_switch *ds);
284 u32 (*get_port_addr)(int port, int offset);
285 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member);
286 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port);
287 void (*port_cleanup)(struct ksz_device *dev, int port);
288 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port);
289 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs);
290 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val);
291 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val);
292 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr,
293 u64 *cnt);
294 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr,
295 u64 *dropped, u64 *cnt);
296 void (*r_mib_stat64)(struct ksz_device *dev, int port);
297 int (*vlan_filtering)(struct ksz_device *dev, int port,
298 bool flag, struct netlink_ext_ack *extack);
299 int (*vlan_add)(struct ksz_device *dev, int port,
300 const struct switchdev_obj_port_vlan *vlan,
301 struct netlink_ext_ack *extack);
302 int (*vlan_del)(struct ksz_device *dev, int port,
303 const struct switchdev_obj_port_vlan *vlan);
304 int (*mirror_add)(struct ksz_device *dev, int port,
305 struct dsa_mall_mirror_tc_entry *mirror,
306 bool ingress, struct netlink_ext_ack *extack);
307 void (*mirror_del)(struct ksz_device *dev, int port,
308 struct dsa_mall_mirror_tc_entry *mirror);
309 int (*fdb_add)(struct ksz_device *dev, int port,
310 const unsigned char *addr, u16 vid, struct dsa_db db);
311 int (*fdb_del)(struct ksz_device *dev, int port,
312 const unsigned char *addr, u16 vid, struct dsa_db db);
313 int (*fdb_dump)(struct ksz_device *dev, int port,
314 dsa_fdb_dump_cb_t *cb, void *data);
315 int (*mdb_add)(struct ksz_device *dev, int port,
316 const struct switchdev_obj_port_mdb *mdb,
317 struct dsa_db db);
318 int (*mdb_del)(struct ksz_device *dev, int port,
319 const struct switchdev_obj_port_mdb *mdb,
320 struct dsa_db db);
321 void (*get_caps)(struct ksz_device *dev, int port,
322 struct phylink_config *config);
323 int (*change_mtu)(struct ksz_device *dev, int port, int mtu);
324 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
325 void (*port_init_cnt)(struct ksz_device *dev, int port);
326 void (*phylink_mac_config)(struct ksz_device *dev, int port,
327 unsigned int mode,
328 const struct phylink_link_state *state);
329 void (*phylink_mac_link_up)(struct ksz_device *dev, int port,
330 unsigned int mode,
331 phy_interface_t interface,
332 struct phy_device *phydev, int speed,
333 int duplex, bool tx_pause, bool rx_pause);
334 void (*setup_rgmii_delay)(struct ksz_device *dev, int port);
335 void (*config_cpu_port)(struct dsa_switch *ds);
336 int (*enable_stp_addr)(struct ksz_device *dev);
337 int (*reset)(struct ksz_device *dev);
338 int (*init)(struct ksz_device *dev);
339 void (*exit)(struct ksz_device *dev);
340};
341
342struct ksz_device *ksz_switch_alloc(struct device *base, void *priv);
343int ksz_switch_register(struct ksz_device *dev);
344void ksz_switch_remove(struct ksz_device *dev);
345
346void ksz_init_mib_timer(struct ksz_device *dev);
347void ksz_r_mib_stats64(struct ksz_device *dev, int port);
348void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port);
349void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
350bool ksz_get_gbit(struct ksz_device *dev, int port);
351phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
352extern const struct ksz_chip_data ksz_switch_chips[];
353
354/* Common register access functions */
355
356static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val)
357{
358 unsigned int value;
359 int ret = regmap_read(dev->regmap[0], reg, &value);
360
361 if (ret)
362 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg,
363 ERR_PTR(ret));
364
365 *val = value;
366 return ret;
367}
368
369static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val)
370{
371 unsigned int value;
372 int ret = regmap_read(dev->regmap[1], reg, &value);
373
374 if (ret)
375 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg,
376 ERR_PTR(ret));
377
378 *val = value;
379 return ret;
380}
381
382static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val)
383{
384 unsigned int value;
385 int ret = regmap_read(dev->regmap[2], reg, &value);
386
387 if (ret)
388 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg,
389 ERR_PTR(ret));
390
391 *val = value;
392 return ret;
393}
394
395static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val)
396{
397 u32 value[2];
398 int ret;
399
400 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2);
401 if (ret)
402 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg,
403 ERR_PTR(ret));
404 else
405 *val = (u64)value[0] << 32 | value[1];
406
407 return ret;
408}
409
410static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value)
411{
412 int ret;
413
414 ret = regmap_write(dev->regmap[0], reg, value);
415 if (ret)
416 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg,
417 ERR_PTR(ret));
418
419 return ret;
420}
421
422static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value)
423{
424 int ret;
425
426 ret = regmap_write(dev->regmap[1], reg, value);
427 if (ret)
428 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg,
429 ERR_PTR(ret));
430
431 return ret;
432}
433
434static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value)
435{
436 int ret;
437
438 ret = regmap_write(dev->regmap[2], reg, value);
439 if (ret)
440 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg,
441 ERR_PTR(ret));
442
443 return ret;
444}
445
446static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
447{
448 u32 val[2];
449
450 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
451 value = swab64(value);
452 val[0] = swab32(value & 0xffffffffULL);
453 val[1] = swab32(value >> 32ULL);
454
455 return regmap_bulk_write(dev->regmap[2], reg, val, 2);
456}
457
458static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val)
459{
460 return regmap_update_bits(dev->regmap[0], offset, mask, val);
461}
462
463static inline int ksz_pread8(struct ksz_device *dev, int port, int offset,
464 u8 *data)
465{
466 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data);
467}
468
469static inline int ksz_pread16(struct ksz_device *dev, int port, int offset,
470 u16 *data)
471{
472 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data);
473}
474
475static inline int ksz_pread32(struct ksz_device *dev, int port, int offset,
476 u32 *data)
477{
478 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data);
479}
480
481static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset,
482 u8 data)
483{
484 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data);
485}
486
487static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset,
488 u16 data)
489{
490 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset),
491 data);
492}
493
494static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset,
495 u32 data)
496{
497 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset),
498 data);
499}
500
501static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset,
502 u8 mask, u8 val)
503{
504 regmap_update_bits(dev->regmap[0],
505 dev->dev_ops->get_port_addr(port, offset),
506 mask, val);
507}
508
509static inline void ksz_regmap_lock(void *__mtx)
510{
511 struct mutex *mtx = __mtx;
512 mutex_lock(mtx);
513}
514
515static inline void ksz_regmap_unlock(void *__mtx)
516{
517 struct mutex *mtx = __mtx;
518 mutex_unlock(mtx);
519}
520
521static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
522{
523 return dev->chip_id == KSZ8830_CHIP_ID;
524}
525
526static inline int is_lan937x(struct ksz_device *dev)
527{
528 return dev->chip_id == LAN9370_CHIP_ID ||
529 dev->chip_id == LAN9371_CHIP_ID ||
530 dev->chip_id == LAN9372_CHIP_ID ||
531 dev->chip_id == LAN9373_CHIP_ID ||
532 dev->chip_id == LAN9374_CHIP_ID;
533}
534
535/* STP State Defines */
536#define PORT_TX_ENABLE BIT(2)
537#define PORT_RX_ENABLE BIT(1)
538#define PORT_LEARN_DISABLE BIT(0)
539
540/* Switch ID Defines */
541#define REG_CHIP_ID0 0x00
542
543#define SW_FAMILY_ID_M GENMASK(15, 8)
544#define KSZ87_FAMILY_ID 0x87
545#define KSZ88_FAMILY_ID 0x88
546
547#define KSZ8_PORT_STATUS_0 0x08
548#define KSZ8_PORT_FIBER_MODE BIT(7)
549
550#define SW_CHIP_ID_M GENMASK(7, 4)
551#define KSZ87_CHIP_ID_94 0x6
552#define KSZ87_CHIP_ID_95 0x9
553#define KSZ88_CHIP_ID_63 0x3
554
555#define SW_REV_ID_M GENMASK(7, 4)
556
557/* KSZ9893, KSZ9563, KSZ8563 specific register */
558#define REG_CHIP_ID4 0x0f
559#define SKU_ID_KSZ8563 0x3c
560#define SKU_ID_KSZ9563 0x1c
561
562/* Driver set switch broadcast storm protection at 10% rate. */
563#define BROADCAST_STORM_PROT_RATE 10
564
565/* 148,800 frames * 67 ms / 100 */
566#define BROADCAST_STORM_VALUE 9969
567
568#define BROADCAST_STORM_RATE_HI 0x07
569#define BROADCAST_STORM_RATE_LO 0xFF
570#define BROADCAST_STORM_RATE 0x07FF
571
572#define MULTICAST_STORM_DISABLE BIT(6)
573
574#define SW_START 0x01
575
576/* xMII configuration */
577#define P_MII_DUPLEX_M BIT(6)
578#define P_MII_100MBIT_M BIT(4)
579
580#define P_GMII_1GBIT_M BIT(6)
581#define P_RGMII_ID_IG_ENABLE BIT(4)
582#define P_RGMII_ID_EG_ENABLE BIT(3)
583#define P_MII_MAC_MODE BIT(2)
584#define P_MII_SEL_M 0x3
585
586/* Interrupt */
587#define REG_SW_PORT_INT_STATUS__1 0x001B
588#define REG_SW_PORT_INT_MASK__1 0x001F
589
590#define REG_PORT_INT_STATUS 0x001B
591#define REG_PORT_INT_MASK 0x001F
592
593#define PORT_SRC_PHY_INT 1
594
595#define KSZ8795_HUGE_PACKET_SIZE 2000
596#define KSZ8863_HUGE_PACKET_SIZE 1916
597#define KSZ8863_NORMAL_PACKET_SIZE 1536
598#define KSZ8_LEGAL_PACKET_SIZE 1518
599#define KSZ9477_MAX_FRAME_SIZE 9000
600
601/* Regmap tables generation */
602#define KSZ_SPI_OP_RD 3
603#define KSZ_SPI_OP_WR 2
604
605#define swabnot_used(x) 0
606
607#define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \
608 swab##swp((opcode) << ((regbits) + (regpad)))
609
610#define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \
611 { \
612 .name = #width, \
613 .val_bits = (width), \
614 .reg_stride = 1, \
615 .reg_bits = (regbits) + (regalign), \
616 .pad_bits = (regpad), \
617 .max_register = BIT(regbits) - 1, \
618 .cache_type = REGCACHE_NONE, \
619 .read_flag_mask = \
620 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \
621 regbits, regpad), \
622 .write_flag_mask = \
623 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \
624 regbits, regpad), \
625 .lock = ksz_regmap_lock, \
626 .unlock = ksz_regmap_unlock, \
627 .reg_format_endian = REGMAP_ENDIAN_BIG, \
628 .val_format_endian = REGMAP_ENDIAN_BIG \
629 }
630
631#define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \
632 static const struct regmap_config ksz##_regmap_config[] = { \
633 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \
634 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \
635 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \
636 }
637
638#endif