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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Avionic Design GmbH
4 * Copyright (C) 2013 NVIDIA Corporation
5 */
6
7#include <linux/clk.h>
8#include <linux/delay.h>
9#include <linux/host1x.h>
10#include <linux/iommu.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/platform_device.h>
14#include <linux/pm_domain.h>
15#include <linux/pm_opp.h>
16#include <linux/pm_runtime.h>
17#include <linux/reset.h>
18
19#include <soc/tegra/common.h>
20#include <soc/tegra/pmc.h>
21
22#include "drm.h"
23#include "gem.h"
24#include "gr3d.h"
25
26enum {
27 RST_MC,
28 RST_GR3D,
29 RST_MC2,
30 RST_GR3D2,
31 RST_GR3D_MAX,
32};
33
34struct gr3d_soc {
35 unsigned int version;
36 unsigned int num_clocks;
37 unsigned int num_resets;
38};
39
40struct gr3d {
41 struct tegra_drm_client client;
42 struct host1x_channel *channel;
43
44 const struct gr3d_soc *soc;
45 struct clk_bulk_data *clocks;
46 unsigned int nclocks;
47 struct reset_control_bulk_data resets[RST_GR3D_MAX];
48 unsigned int nresets;
49 struct dev_pm_domain_list *pd_list;
50
51 DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
52};
53
54static inline struct gr3d *to_gr3d(struct tegra_drm_client *client)
55{
56 return container_of(client, struct gr3d, client);
57}
58
59static int gr3d_init(struct host1x_client *client)
60{
61 struct tegra_drm_client *drm = host1x_to_drm_client(client);
62 struct drm_device *dev = dev_get_drvdata(client->host);
63 unsigned long flags = HOST1X_SYNCPT_HAS_BASE;
64 struct gr3d *gr3d = to_gr3d(drm);
65 int err;
66
67 gr3d->channel = host1x_channel_request(client);
68 if (!gr3d->channel)
69 return -ENOMEM;
70
71 client->syncpts[0] = host1x_syncpt_request(client, flags);
72 if (!client->syncpts[0]) {
73 err = -ENOMEM;
74 dev_err(client->dev, "failed to request syncpoint: %d\n", err);
75 goto put;
76 }
77
78 err = host1x_client_iommu_attach(client);
79 if (err < 0) {
80 dev_err(client->dev, "failed to attach to domain: %d\n", err);
81 goto free;
82 }
83
84 err = tegra_drm_register_client(dev->dev_private, drm);
85 if (err < 0) {
86 dev_err(client->dev, "failed to register client: %d\n", err);
87 goto detach_iommu;
88 }
89
90 return 0;
91
92detach_iommu:
93 host1x_client_iommu_detach(client);
94free:
95 host1x_syncpt_put(client->syncpts[0]);
96put:
97 host1x_channel_put(gr3d->channel);
98 return err;
99}
100
101static int gr3d_exit(struct host1x_client *client)
102{
103 struct tegra_drm_client *drm = host1x_to_drm_client(client);
104 struct drm_device *dev = dev_get_drvdata(client->host);
105 struct gr3d *gr3d = to_gr3d(drm);
106 int err;
107
108 err = tegra_drm_unregister_client(dev->dev_private, drm);
109 if (err < 0)
110 return err;
111
112 pm_runtime_dont_use_autosuspend(client->dev);
113 pm_runtime_force_suspend(client->dev);
114
115 host1x_client_iommu_detach(client);
116 host1x_syncpt_put(client->syncpts[0]);
117 host1x_channel_put(gr3d->channel);
118
119 gr3d->channel = NULL;
120
121 return 0;
122}
123
124static const struct host1x_client_ops gr3d_client_ops = {
125 .init = gr3d_init,
126 .exit = gr3d_exit,
127};
128
129static int gr3d_open_channel(struct tegra_drm_client *client,
130 struct tegra_drm_context *context)
131{
132 struct gr3d *gr3d = to_gr3d(client);
133
134 context->channel = host1x_channel_get(gr3d->channel);
135 if (!context->channel)
136 return -ENOMEM;
137
138 return 0;
139}
140
141static void gr3d_close_channel(struct tegra_drm_context *context)
142{
143 host1x_channel_put(context->channel);
144}
145
146static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset)
147{
148 struct gr3d *gr3d = dev_get_drvdata(dev);
149
150 switch (class) {
151 case HOST1X_CLASS_HOST1X:
152 if (offset == 0x2b)
153 return 1;
154
155 break;
156
157 case HOST1X_CLASS_GR3D:
158 if (offset >= GR3D_NUM_REGS)
159 break;
160
161 if (test_bit(offset, gr3d->addr_regs))
162 return 1;
163
164 break;
165 }
166
167 return 0;
168}
169
170static const struct tegra_drm_client_ops gr3d_ops = {
171 .open_channel = gr3d_open_channel,
172 .close_channel = gr3d_close_channel,
173 .is_addr_reg = gr3d_is_addr_reg,
174 .submit = tegra_drm_submit,
175};
176
177static const struct gr3d_soc tegra20_gr3d_soc = {
178 .version = 0x20,
179 .num_clocks = 1,
180 .num_resets = 2,
181};
182
183static const struct gr3d_soc tegra30_gr3d_soc = {
184 .version = 0x30,
185 .num_clocks = 2,
186 .num_resets = 4,
187};
188
189static const struct gr3d_soc tegra114_gr3d_soc = {
190 .version = 0x35,
191 .num_clocks = 1,
192 .num_resets = 2,
193};
194
195static const struct of_device_id tegra_gr3d_match[] = {
196 { .compatible = "nvidia,tegra114-gr3d", .data = &tegra114_gr3d_soc },
197 { .compatible = "nvidia,tegra30-gr3d", .data = &tegra30_gr3d_soc },
198 { .compatible = "nvidia,tegra20-gr3d", .data = &tegra20_gr3d_soc },
199 { }
200};
201MODULE_DEVICE_TABLE(of, tegra_gr3d_match);
202
203static const u32 gr3d_addr_regs[] = {
204 GR3D_IDX_ATTRIBUTE( 0),
205 GR3D_IDX_ATTRIBUTE( 1),
206 GR3D_IDX_ATTRIBUTE( 2),
207 GR3D_IDX_ATTRIBUTE( 3),
208 GR3D_IDX_ATTRIBUTE( 4),
209 GR3D_IDX_ATTRIBUTE( 5),
210 GR3D_IDX_ATTRIBUTE( 6),
211 GR3D_IDX_ATTRIBUTE( 7),
212 GR3D_IDX_ATTRIBUTE( 8),
213 GR3D_IDX_ATTRIBUTE( 9),
214 GR3D_IDX_ATTRIBUTE(10),
215 GR3D_IDX_ATTRIBUTE(11),
216 GR3D_IDX_ATTRIBUTE(12),
217 GR3D_IDX_ATTRIBUTE(13),
218 GR3D_IDX_ATTRIBUTE(14),
219 GR3D_IDX_ATTRIBUTE(15),
220 GR3D_IDX_INDEX_BASE,
221 GR3D_QR_ZTAG_ADDR,
222 GR3D_QR_CTAG_ADDR,
223 GR3D_QR_CZ_ADDR,
224 GR3D_TEX_TEX_ADDR( 0),
225 GR3D_TEX_TEX_ADDR( 1),
226 GR3D_TEX_TEX_ADDR( 2),
227 GR3D_TEX_TEX_ADDR( 3),
228 GR3D_TEX_TEX_ADDR( 4),
229 GR3D_TEX_TEX_ADDR( 5),
230 GR3D_TEX_TEX_ADDR( 6),
231 GR3D_TEX_TEX_ADDR( 7),
232 GR3D_TEX_TEX_ADDR( 8),
233 GR3D_TEX_TEX_ADDR( 9),
234 GR3D_TEX_TEX_ADDR(10),
235 GR3D_TEX_TEX_ADDR(11),
236 GR3D_TEX_TEX_ADDR(12),
237 GR3D_TEX_TEX_ADDR(13),
238 GR3D_TEX_TEX_ADDR(14),
239 GR3D_TEX_TEX_ADDR(15),
240 GR3D_DW_MEMORY_OUTPUT_ADDRESS,
241 GR3D_GLOBAL_SURFADDR( 0),
242 GR3D_GLOBAL_SURFADDR( 1),
243 GR3D_GLOBAL_SURFADDR( 2),
244 GR3D_GLOBAL_SURFADDR( 3),
245 GR3D_GLOBAL_SURFADDR( 4),
246 GR3D_GLOBAL_SURFADDR( 5),
247 GR3D_GLOBAL_SURFADDR( 6),
248 GR3D_GLOBAL_SURFADDR( 7),
249 GR3D_GLOBAL_SURFADDR( 8),
250 GR3D_GLOBAL_SURFADDR( 9),
251 GR3D_GLOBAL_SURFADDR(10),
252 GR3D_GLOBAL_SURFADDR(11),
253 GR3D_GLOBAL_SURFADDR(12),
254 GR3D_GLOBAL_SURFADDR(13),
255 GR3D_GLOBAL_SURFADDR(14),
256 GR3D_GLOBAL_SURFADDR(15),
257 GR3D_GLOBAL_SPILLSURFADDR,
258 GR3D_GLOBAL_SURFOVERADDR( 0),
259 GR3D_GLOBAL_SURFOVERADDR( 1),
260 GR3D_GLOBAL_SURFOVERADDR( 2),
261 GR3D_GLOBAL_SURFOVERADDR( 3),
262 GR3D_GLOBAL_SURFOVERADDR( 4),
263 GR3D_GLOBAL_SURFOVERADDR( 5),
264 GR3D_GLOBAL_SURFOVERADDR( 6),
265 GR3D_GLOBAL_SURFOVERADDR( 7),
266 GR3D_GLOBAL_SURFOVERADDR( 8),
267 GR3D_GLOBAL_SURFOVERADDR( 9),
268 GR3D_GLOBAL_SURFOVERADDR(10),
269 GR3D_GLOBAL_SURFOVERADDR(11),
270 GR3D_GLOBAL_SURFOVERADDR(12),
271 GR3D_GLOBAL_SURFOVERADDR(13),
272 GR3D_GLOBAL_SURFOVERADDR(14),
273 GR3D_GLOBAL_SURFOVERADDR(15),
274 GR3D_GLOBAL_SAMP01SURFADDR( 0),
275 GR3D_GLOBAL_SAMP01SURFADDR( 1),
276 GR3D_GLOBAL_SAMP01SURFADDR( 2),
277 GR3D_GLOBAL_SAMP01SURFADDR( 3),
278 GR3D_GLOBAL_SAMP01SURFADDR( 4),
279 GR3D_GLOBAL_SAMP01SURFADDR( 5),
280 GR3D_GLOBAL_SAMP01SURFADDR( 6),
281 GR3D_GLOBAL_SAMP01SURFADDR( 7),
282 GR3D_GLOBAL_SAMP01SURFADDR( 8),
283 GR3D_GLOBAL_SAMP01SURFADDR( 9),
284 GR3D_GLOBAL_SAMP01SURFADDR(10),
285 GR3D_GLOBAL_SAMP01SURFADDR(11),
286 GR3D_GLOBAL_SAMP01SURFADDR(12),
287 GR3D_GLOBAL_SAMP01SURFADDR(13),
288 GR3D_GLOBAL_SAMP01SURFADDR(14),
289 GR3D_GLOBAL_SAMP01SURFADDR(15),
290 GR3D_GLOBAL_SAMP23SURFADDR( 0),
291 GR3D_GLOBAL_SAMP23SURFADDR( 1),
292 GR3D_GLOBAL_SAMP23SURFADDR( 2),
293 GR3D_GLOBAL_SAMP23SURFADDR( 3),
294 GR3D_GLOBAL_SAMP23SURFADDR( 4),
295 GR3D_GLOBAL_SAMP23SURFADDR( 5),
296 GR3D_GLOBAL_SAMP23SURFADDR( 6),
297 GR3D_GLOBAL_SAMP23SURFADDR( 7),
298 GR3D_GLOBAL_SAMP23SURFADDR( 8),
299 GR3D_GLOBAL_SAMP23SURFADDR( 9),
300 GR3D_GLOBAL_SAMP23SURFADDR(10),
301 GR3D_GLOBAL_SAMP23SURFADDR(11),
302 GR3D_GLOBAL_SAMP23SURFADDR(12),
303 GR3D_GLOBAL_SAMP23SURFADDR(13),
304 GR3D_GLOBAL_SAMP23SURFADDR(14),
305 GR3D_GLOBAL_SAMP23SURFADDR(15),
306};
307
308static int gr3d_power_up_legacy_domain(struct device *dev, const char *name,
309 unsigned int id)
310{
311 struct gr3d *gr3d = dev_get_drvdata(dev);
312 struct reset_control *reset;
313 struct clk *clk;
314 unsigned int i;
315 int err;
316
317 /*
318 * Tegra20 device-tree doesn't specify 3d clock name and there is only
319 * one clock for Tegra20. Tegra30+ device-trees always specified names
320 * for the clocks.
321 */
322 if (gr3d->nclocks == 1) {
323 if (id == TEGRA_POWERGATE_3D1)
324 return 0;
325
326 clk = gr3d->clocks[0].clk;
327 } else {
328 for (i = 0; i < gr3d->nclocks; i++) {
329 if (WARN_ON(!gr3d->clocks[i].id))
330 continue;
331
332 if (!strcmp(gr3d->clocks[i].id, name)) {
333 clk = gr3d->clocks[i].clk;
334 break;
335 }
336 }
337
338 if (WARN_ON(i == gr3d->nclocks))
339 return -EINVAL;
340 }
341
342 /*
343 * We use array of resets, which includes MC resets, and MC
344 * reset shouldn't be asserted while hardware is gated because
345 * MC flushing will fail for gated hardware. Hence for legacy
346 * PD we request the individual reset separately.
347 */
348 reset = reset_control_get_exclusive_released(dev, name);
349 if (IS_ERR(reset))
350 return PTR_ERR(reset);
351
352 err = reset_control_acquire(reset);
353 if (err) {
354 dev_err(dev, "failed to acquire %s reset: %d\n", name, err);
355 } else {
356 err = tegra_powergate_sequence_power_up(id, clk, reset);
357 reset_control_release(reset);
358 }
359
360 reset_control_put(reset);
361 if (err)
362 return err;
363
364 /*
365 * tegra_powergate_sequence_power_up() leaves clocks enabled,
366 * while GENPD not. Hence keep clock-enable balanced.
367 */
368 clk_disable_unprepare(clk);
369
370 return 0;
371}
372
373static int gr3d_init_power(struct device *dev, struct gr3d *gr3d)
374{
375 struct dev_pm_domain_attach_data pd_data = {
376 .pd_names = (const char *[]) { "3d0", "3d1" },
377 .num_pd_names = 2,
378 .pd_flags = PD_FLAG_REQUIRED_OPP,
379 };
380 int err;
381
382 err = of_count_phandle_with_args(dev->of_node, "power-domains",
383 "#power-domain-cells");
384 if (err < 0) {
385 if (err != -ENOENT)
386 return err;
387
388 /*
389 * Older device-trees don't use GENPD. In this case we should
390 * toggle power domain manually.
391 */
392 err = gr3d_power_up_legacy_domain(dev, "3d",
393 TEGRA_POWERGATE_3D);
394 if (err)
395 return err;
396
397 err = gr3d_power_up_legacy_domain(dev, "3d2",
398 TEGRA_POWERGATE_3D1);
399 if (err)
400 return err;
401
402 return 0;
403 }
404
405 /*
406 * The PM domain core automatically attaches a single power domain,
407 * otherwise it skips attaching completely. We have a single domain
408 * on Tegra20 and two domains on Tegra30+.
409 */
410 if (dev->pm_domain)
411 return 0;
412
413 err = devm_pm_domain_attach_list(dev, &pd_data, &gr3d->pd_list);
414 if (err < 0)
415 return err;
416
417 return 0;
418}
419
420static int gr3d_get_clocks(struct device *dev, struct gr3d *gr3d)
421{
422 int err;
423
424 err = devm_clk_bulk_get_all(dev, &gr3d->clocks);
425 if (err < 0) {
426 dev_err(dev, "failed to get clock: %d\n", err);
427 return err;
428 }
429 gr3d->nclocks = err;
430
431 if (gr3d->nclocks != gr3d->soc->num_clocks) {
432 dev_err(dev, "invalid number of clocks: %u\n", gr3d->nclocks);
433 return -ENOENT;
434 }
435
436 return 0;
437}
438
439static int gr3d_get_resets(struct device *dev, struct gr3d *gr3d)
440{
441 int err;
442
443 gr3d->resets[RST_MC].id = "mc";
444 gr3d->resets[RST_MC2].id = "mc2";
445 gr3d->resets[RST_GR3D].id = "3d";
446 gr3d->resets[RST_GR3D2].id = "3d2";
447 gr3d->nresets = gr3d->soc->num_resets;
448
449 err = devm_reset_control_bulk_get_optional_exclusive_released(
450 dev, gr3d->nresets, gr3d->resets);
451 if (err) {
452 dev_err(dev, "failed to get reset: %d\n", err);
453 return err;
454 }
455
456 if (WARN_ON(!gr3d->resets[RST_GR3D].rstc) ||
457 WARN_ON(!gr3d->resets[RST_GR3D2].rstc && gr3d->nresets == 4))
458 return -ENOENT;
459
460 return 0;
461}
462
463static int gr3d_probe(struct platform_device *pdev)
464{
465 struct host1x_syncpt **syncpts;
466 struct gr3d *gr3d;
467 unsigned int i;
468 int err;
469
470 gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL);
471 if (!gr3d)
472 return -ENOMEM;
473
474 platform_set_drvdata(pdev, gr3d);
475
476 gr3d->soc = of_device_get_match_data(&pdev->dev);
477
478 syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL);
479 if (!syncpts)
480 return -ENOMEM;
481
482 err = gr3d_get_clocks(&pdev->dev, gr3d);
483 if (err)
484 return err;
485
486 err = gr3d_get_resets(&pdev->dev, gr3d);
487 if (err)
488 return err;
489
490 err = gr3d_init_power(&pdev->dev, gr3d);
491 if (err)
492 return err;
493
494 INIT_LIST_HEAD(&gr3d->client.base.list);
495 gr3d->client.base.ops = &gr3d_client_ops;
496 gr3d->client.base.dev = &pdev->dev;
497 gr3d->client.base.class = HOST1X_CLASS_GR3D;
498 gr3d->client.base.syncpts = syncpts;
499 gr3d->client.base.num_syncpts = 1;
500
501 INIT_LIST_HEAD(&gr3d->client.list);
502 gr3d->client.version = gr3d->soc->version;
503 gr3d->client.ops = &gr3d_ops;
504
505 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
506 if (err)
507 return err;
508
509 err = host1x_client_register(&gr3d->client.base);
510 if (err < 0) {
511 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
512 err);
513 return err;
514 }
515
516 /* initialize address register map */
517 for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++)
518 set_bit(gr3d_addr_regs[i], gr3d->addr_regs);
519
520 return 0;
521}
522
523static void gr3d_remove(struct platform_device *pdev)
524{
525 struct gr3d *gr3d = platform_get_drvdata(pdev);
526
527 pm_runtime_disable(&pdev->dev);
528 host1x_client_unregister(&gr3d->client.base);
529}
530
531static int __maybe_unused gr3d_runtime_suspend(struct device *dev)
532{
533 struct gr3d *gr3d = dev_get_drvdata(dev);
534 int err;
535
536 host1x_channel_stop(gr3d->channel);
537
538 err = reset_control_bulk_assert(gr3d->nresets, gr3d->resets);
539 if (err) {
540 dev_err(dev, "failed to assert reset: %d\n", err);
541 return err;
542 }
543
544 usleep_range(10, 20);
545
546 /*
547 * Older device-trees don't specify MC resets and power-gating can't
548 * be done safely in that case. Hence we will keep the power ungated
549 * for older DTBs. For newer DTBs, GENPD will perform the power-gating.
550 */
551
552 clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks);
553 reset_control_bulk_release(gr3d->nresets, gr3d->resets);
554
555 return 0;
556}
557
558static int __maybe_unused gr3d_runtime_resume(struct device *dev)
559{
560 struct gr3d *gr3d = dev_get_drvdata(dev);
561 int err;
562
563 err = reset_control_bulk_acquire(gr3d->nresets, gr3d->resets);
564 if (err) {
565 dev_err(dev, "failed to acquire reset: %d\n", err);
566 return err;
567 }
568
569 err = clk_bulk_prepare_enable(gr3d->nclocks, gr3d->clocks);
570 if (err) {
571 dev_err(dev, "failed to enable clock: %d\n", err);
572 goto release_reset;
573 }
574
575 err = reset_control_bulk_deassert(gr3d->nresets, gr3d->resets);
576 if (err) {
577 dev_err(dev, "failed to deassert reset: %d\n", err);
578 goto disable_clk;
579 }
580
581 pm_runtime_enable(dev);
582 pm_runtime_use_autosuspend(dev);
583 pm_runtime_set_autosuspend_delay(dev, 500);
584
585 return 0;
586
587disable_clk:
588 clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks);
589release_reset:
590 reset_control_bulk_release(gr3d->nresets, gr3d->resets);
591
592 return err;
593}
594
595static const struct dev_pm_ops tegra_gr3d_pm = {
596 SET_RUNTIME_PM_OPS(gr3d_runtime_suspend, gr3d_runtime_resume, NULL)
597 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
598 pm_runtime_force_resume)
599};
600
601struct platform_driver tegra_gr3d_driver = {
602 .driver = {
603 .name = "tegra-gr3d",
604 .of_match_table = tegra_gr3d_match,
605 .pm = &tegra_gr3d_pm,
606 },
607 .probe = gr3d_probe,
608 .remove = gr3d_remove,
609};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Avionic Design GmbH
4 * Copyright (C) 2013 NVIDIA Corporation
5 */
6
7#include <linux/clk.h>
8#include <linux/delay.h>
9#include <linux/host1x.h>
10#include <linux/iommu.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14#include <linux/pm_domain.h>
15#include <linux/pm_opp.h>
16#include <linux/pm_runtime.h>
17#include <linux/reset.h>
18
19#include <soc/tegra/common.h>
20#include <soc/tegra/pmc.h>
21
22#include "drm.h"
23#include "gem.h"
24#include "gr3d.h"
25
26enum {
27 RST_MC,
28 RST_GR3D,
29 RST_MC2,
30 RST_GR3D2,
31 RST_GR3D_MAX,
32};
33
34struct gr3d_soc {
35 unsigned int version;
36 unsigned int num_clocks;
37 unsigned int num_resets;
38};
39
40struct gr3d {
41 struct tegra_drm_client client;
42 struct host1x_channel *channel;
43
44 const struct gr3d_soc *soc;
45 struct clk_bulk_data *clocks;
46 unsigned int nclocks;
47 struct reset_control_bulk_data resets[RST_GR3D_MAX];
48 unsigned int nresets;
49
50 DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
51};
52
53static inline struct gr3d *to_gr3d(struct tegra_drm_client *client)
54{
55 return container_of(client, struct gr3d, client);
56}
57
58static int gr3d_init(struct host1x_client *client)
59{
60 struct tegra_drm_client *drm = host1x_to_drm_client(client);
61 struct drm_device *dev = dev_get_drvdata(client->host);
62 unsigned long flags = HOST1X_SYNCPT_HAS_BASE;
63 struct gr3d *gr3d = to_gr3d(drm);
64 int err;
65
66 gr3d->channel = host1x_channel_request(client);
67 if (!gr3d->channel)
68 return -ENOMEM;
69
70 client->syncpts[0] = host1x_syncpt_request(client, flags);
71 if (!client->syncpts[0]) {
72 err = -ENOMEM;
73 dev_err(client->dev, "failed to request syncpoint: %d\n", err);
74 goto put;
75 }
76
77 err = host1x_client_iommu_attach(client);
78 if (err < 0) {
79 dev_err(client->dev, "failed to attach to domain: %d\n", err);
80 goto free;
81 }
82
83 pm_runtime_enable(client->dev);
84 pm_runtime_use_autosuspend(client->dev);
85 pm_runtime_set_autosuspend_delay(client->dev, 200);
86
87 err = tegra_drm_register_client(dev->dev_private, drm);
88 if (err < 0) {
89 dev_err(client->dev, "failed to register client: %d\n", err);
90 goto disable_rpm;
91 }
92
93 return 0;
94
95disable_rpm:
96 pm_runtime_dont_use_autosuspend(client->dev);
97 pm_runtime_force_suspend(client->dev);
98
99 host1x_client_iommu_detach(client);
100free:
101 host1x_syncpt_put(client->syncpts[0]);
102put:
103 host1x_channel_put(gr3d->channel);
104 return err;
105}
106
107static int gr3d_exit(struct host1x_client *client)
108{
109 struct tegra_drm_client *drm = host1x_to_drm_client(client);
110 struct drm_device *dev = dev_get_drvdata(client->host);
111 struct gr3d *gr3d = to_gr3d(drm);
112 int err;
113
114 err = tegra_drm_unregister_client(dev->dev_private, drm);
115 if (err < 0)
116 return err;
117
118 pm_runtime_dont_use_autosuspend(client->dev);
119 pm_runtime_force_suspend(client->dev);
120
121 host1x_client_iommu_detach(client);
122 host1x_syncpt_put(client->syncpts[0]);
123 host1x_channel_put(gr3d->channel);
124
125 gr3d->channel = NULL;
126
127 return 0;
128}
129
130static const struct host1x_client_ops gr3d_client_ops = {
131 .init = gr3d_init,
132 .exit = gr3d_exit,
133};
134
135static int gr3d_open_channel(struct tegra_drm_client *client,
136 struct tegra_drm_context *context)
137{
138 struct gr3d *gr3d = to_gr3d(client);
139
140 context->channel = host1x_channel_get(gr3d->channel);
141 if (!context->channel)
142 return -ENOMEM;
143
144 return 0;
145}
146
147static void gr3d_close_channel(struct tegra_drm_context *context)
148{
149 host1x_channel_put(context->channel);
150}
151
152static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset)
153{
154 struct gr3d *gr3d = dev_get_drvdata(dev);
155
156 switch (class) {
157 case HOST1X_CLASS_HOST1X:
158 if (offset == 0x2b)
159 return 1;
160
161 break;
162
163 case HOST1X_CLASS_GR3D:
164 if (offset >= GR3D_NUM_REGS)
165 break;
166
167 if (test_bit(offset, gr3d->addr_regs))
168 return 1;
169
170 break;
171 }
172
173 return 0;
174}
175
176static const struct tegra_drm_client_ops gr3d_ops = {
177 .open_channel = gr3d_open_channel,
178 .close_channel = gr3d_close_channel,
179 .is_addr_reg = gr3d_is_addr_reg,
180 .submit = tegra_drm_submit,
181};
182
183static const struct gr3d_soc tegra20_gr3d_soc = {
184 .version = 0x20,
185 .num_clocks = 1,
186 .num_resets = 2,
187};
188
189static const struct gr3d_soc tegra30_gr3d_soc = {
190 .version = 0x30,
191 .num_clocks = 2,
192 .num_resets = 4,
193};
194
195static const struct gr3d_soc tegra114_gr3d_soc = {
196 .version = 0x35,
197 .num_clocks = 1,
198 .num_resets = 2,
199};
200
201static const struct of_device_id tegra_gr3d_match[] = {
202 { .compatible = "nvidia,tegra114-gr3d", .data = &tegra114_gr3d_soc },
203 { .compatible = "nvidia,tegra30-gr3d", .data = &tegra30_gr3d_soc },
204 { .compatible = "nvidia,tegra20-gr3d", .data = &tegra20_gr3d_soc },
205 { }
206};
207MODULE_DEVICE_TABLE(of, tegra_gr3d_match);
208
209static const u32 gr3d_addr_regs[] = {
210 GR3D_IDX_ATTRIBUTE( 0),
211 GR3D_IDX_ATTRIBUTE( 1),
212 GR3D_IDX_ATTRIBUTE( 2),
213 GR3D_IDX_ATTRIBUTE( 3),
214 GR3D_IDX_ATTRIBUTE( 4),
215 GR3D_IDX_ATTRIBUTE( 5),
216 GR3D_IDX_ATTRIBUTE( 6),
217 GR3D_IDX_ATTRIBUTE( 7),
218 GR3D_IDX_ATTRIBUTE( 8),
219 GR3D_IDX_ATTRIBUTE( 9),
220 GR3D_IDX_ATTRIBUTE(10),
221 GR3D_IDX_ATTRIBUTE(11),
222 GR3D_IDX_ATTRIBUTE(12),
223 GR3D_IDX_ATTRIBUTE(13),
224 GR3D_IDX_ATTRIBUTE(14),
225 GR3D_IDX_ATTRIBUTE(15),
226 GR3D_IDX_INDEX_BASE,
227 GR3D_QR_ZTAG_ADDR,
228 GR3D_QR_CTAG_ADDR,
229 GR3D_QR_CZ_ADDR,
230 GR3D_TEX_TEX_ADDR( 0),
231 GR3D_TEX_TEX_ADDR( 1),
232 GR3D_TEX_TEX_ADDR( 2),
233 GR3D_TEX_TEX_ADDR( 3),
234 GR3D_TEX_TEX_ADDR( 4),
235 GR3D_TEX_TEX_ADDR( 5),
236 GR3D_TEX_TEX_ADDR( 6),
237 GR3D_TEX_TEX_ADDR( 7),
238 GR3D_TEX_TEX_ADDR( 8),
239 GR3D_TEX_TEX_ADDR( 9),
240 GR3D_TEX_TEX_ADDR(10),
241 GR3D_TEX_TEX_ADDR(11),
242 GR3D_TEX_TEX_ADDR(12),
243 GR3D_TEX_TEX_ADDR(13),
244 GR3D_TEX_TEX_ADDR(14),
245 GR3D_TEX_TEX_ADDR(15),
246 GR3D_DW_MEMORY_OUTPUT_ADDRESS,
247 GR3D_GLOBAL_SURFADDR( 0),
248 GR3D_GLOBAL_SURFADDR( 1),
249 GR3D_GLOBAL_SURFADDR( 2),
250 GR3D_GLOBAL_SURFADDR( 3),
251 GR3D_GLOBAL_SURFADDR( 4),
252 GR3D_GLOBAL_SURFADDR( 5),
253 GR3D_GLOBAL_SURFADDR( 6),
254 GR3D_GLOBAL_SURFADDR( 7),
255 GR3D_GLOBAL_SURFADDR( 8),
256 GR3D_GLOBAL_SURFADDR( 9),
257 GR3D_GLOBAL_SURFADDR(10),
258 GR3D_GLOBAL_SURFADDR(11),
259 GR3D_GLOBAL_SURFADDR(12),
260 GR3D_GLOBAL_SURFADDR(13),
261 GR3D_GLOBAL_SURFADDR(14),
262 GR3D_GLOBAL_SURFADDR(15),
263 GR3D_GLOBAL_SPILLSURFADDR,
264 GR3D_GLOBAL_SURFOVERADDR( 0),
265 GR3D_GLOBAL_SURFOVERADDR( 1),
266 GR3D_GLOBAL_SURFOVERADDR( 2),
267 GR3D_GLOBAL_SURFOVERADDR( 3),
268 GR3D_GLOBAL_SURFOVERADDR( 4),
269 GR3D_GLOBAL_SURFOVERADDR( 5),
270 GR3D_GLOBAL_SURFOVERADDR( 6),
271 GR3D_GLOBAL_SURFOVERADDR( 7),
272 GR3D_GLOBAL_SURFOVERADDR( 8),
273 GR3D_GLOBAL_SURFOVERADDR( 9),
274 GR3D_GLOBAL_SURFOVERADDR(10),
275 GR3D_GLOBAL_SURFOVERADDR(11),
276 GR3D_GLOBAL_SURFOVERADDR(12),
277 GR3D_GLOBAL_SURFOVERADDR(13),
278 GR3D_GLOBAL_SURFOVERADDR(14),
279 GR3D_GLOBAL_SURFOVERADDR(15),
280 GR3D_GLOBAL_SAMP01SURFADDR( 0),
281 GR3D_GLOBAL_SAMP01SURFADDR( 1),
282 GR3D_GLOBAL_SAMP01SURFADDR( 2),
283 GR3D_GLOBAL_SAMP01SURFADDR( 3),
284 GR3D_GLOBAL_SAMP01SURFADDR( 4),
285 GR3D_GLOBAL_SAMP01SURFADDR( 5),
286 GR3D_GLOBAL_SAMP01SURFADDR( 6),
287 GR3D_GLOBAL_SAMP01SURFADDR( 7),
288 GR3D_GLOBAL_SAMP01SURFADDR( 8),
289 GR3D_GLOBAL_SAMP01SURFADDR( 9),
290 GR3D_GLOBAL_SAMP01SURFADDR(10),
291 GR3D_GLOBAL_SAMP01SURFADDR(11),
292 GR3D_GLOBAL_SAMP01SURFADDR(12),
293 GR3D_GLOBAL_SAMP01SURFADDR(13),
294 GR3D_GLOBAL_SAMP01SURFADDR(14),
295 GR3D_GLOBAL_SAMP01SURFADDR(15),
296 GR3D_GLOBAL_SAMP23SURFADDR( 0),
297 GR3D_GLOBAL_SAMP23SURFADDR( 1),
298 GR3D_GLOBAL_SAMP23SURFADDR( 2),
299 GR3D_GLOBAL_SAMP23SURFADDR( 3),
300 GR3D_GLOBAL_SAMP23SURFADDR( 4),
301 GR3D_GLOBAL_SAMP23SURFADDR( 5),
302 GR3D_GLOBAL_SAMP23SURFADDR( 6),
303 GR3D_GLOBAL_SAMP23SURFADDR( 7),
304 GR3D_GLOBAL_SAMP23SURFADDR( 8),
305 GR3D_GLOBAL_SAMP23SURFADDR( 9),
306 GR3D_GLOBAL_SAMP23SURFADDR(10),
307 GR3D_GLOBAL_SAMP23SURFADDR(11),
308 GR3D_GLOBAL_SAMP23SURFADDR(12),
309 GR3D_GLOBAL_SAMP23SURFADDR(13),
310 GR3D_GLOBAL_SAMP23SURFADDR(14),
311 GR3D_GLOBAL_SAMP23SURFADDR(15),
312};
313
314static int gr3d_power_up_legacy_domain(struct device *dev, const char *name,
315 unsigned int id)
316{
317 struct gr3d *gr3d = dev_get_drvdata(dev);
318 struct reset_control *reset;
319 struct clk *clk;
320 unsigned int i;
321 int err;
322
323 /*
324 * Tegra20 device-tree doesn't specify 3d clock name and there is only
325 * one clock for Tegra20. Tegra30+ device-trees always specified names
326 * for the clocks.
327 */
328 if (gr3d->nclocks == 1) {
329 if (id == TEGRA_POWERGATE_3D1)
330 return 0;
331
332 clk = gr3d->clocks[0].clk;
333 } else {
334 for (i = 0; i < gr3d->nclocks; i++) {
335 if (WARN_ON(!gr3d->clocks[i].id))
336 continue;
337
338 if (!strcmp(gr3d->clocks[i].id, name)) {
339 clk = gr3d->clocks[i].clk;
340 break;
341 }
342 }
343
344 if (WARN_ON(i == gr3d->nclocks))
345 return -EINVAL;
346 }
347
348 /*
349 * We use array of resets, which includes MC resets, and MC
350 * reset shouldn't be asserted while hardware is gated because
351 * MC flushing will fail for gated hardware. Hence for legacy
352 * PD we request the individual reset separately.
353 */
354 reset = reset_control_get_exclusive_released(dev, name);
355 if (IS_ERR(reset))
356 return PTR_ERR(reset);
357
358 err = reset_control_acquire(reset);
359 if (err) {
360 dev_err(dev, "failed to acquire %s reset: %d\n", name, err);
361 } else {
362 err = tegra_powergate_sequence_power_up(id, clk, reset);
363 reset_control_release(reset);
364 }
365
366 reset_control_put(reset);
367 if (err)
368 return err;
369
370 /*
371 * tegra_powergate_sequence_power_up() leaves clocks enabled,
372 * while GENPD not. Hence keep clock-enable balanced.
373 */
374 clk_disable_unprepare(clk);
375
376 return 0;
377}
378
379static void gr3d_del_link(void *link)
380{
381 device_link_del(link);
382}
383
384static int gr3d_init_power(struct device *dev, struct gr3d *gr3d)
385{
386 static const char * const opp_genpd_names[] = { "3d0", "3d1", NULL };
387 const u32 link_flags = DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME;
388 struct device **opp_virt_devs, *pd_dev;
389 struct device_link *link;
390 unsigned int i;
391 int err;
392
393 err = of_count_phandle_with_args(dev->of_node, "power-domains",
394 "#power-domain-cells");
395 if (err < 0) {
396 if (err != -ENOENT)
397 return err;
398
399 /*
400 * Older device-trees don't use GENPD. In this case we should
401 * toggle power domain manually.
402 */
403 err = gr3d_power_up_legacy_domain(dev, "3d",
404 TEGRA_POWERGATE_3D);
405 if (err)
406 return err;
407
408 err = gr3d_power_up_legacy_domain(dev, "3d2",
409 TEGRA_POWERGATE_3D1);
410 if (err)
411 return err;
412
413 return 0;
414 }
415
416 /*
417 * The PM domain core automatically attaches a single power domain,
418 * otherwise it skips attaching completely. We have a single domain
419 * on Tegra20 and two domains on Tegra30+.
420 */
421 if (dev->pm_domain)
422 return 0;
423
424 err = devm_pm_opp_attach_genpd(dev, opp_genpd_names, &opp_virt_devs);
425 if (err)
426 return err;
427
428 for (i = 0; opp_genpd_names[i]; i++) {
429 pd_dev = opp_virt_devs[i];
430 if (!pd_dev) {
431 dev_err(dev, "failed to get %s power domain\n",
432 opp_genpd_names[i]);
433 return -EINVAL;
434 }
435
436 link = device_link_add(dev, pd_dev, link_flags);
437 if (!link) {
438 dev_err(dev, "failed to link to %s\n", dev_name(pd_dev));
439 return -EINVAL;
440 }
441
442 err = devm_add_action_or_reset(dev, gr3d_del_link, link);
443 if (err)
444 return err;
445 }
446
447 return 0;
448}
449
450static int gr3d_get_clocks(struct device *dev, struct gr3d *gr3d)
451{
452 int err;
453
454 err = devm_clk_bulk_get_all(dev, &gr3d->clocks);
455 if (err < 0) {
456 dev_err(dev, "failed to get clock: %d\n", err);
457 return err;
458 }
459 gr3d->nclocks = err;
460
461 if (gr3d->nclocks != gr3d->soc->num_clocks) {
462 dev_err(dev, "invalid number of clocks: %u\n", gr3d->nclocks);
463 return -ENOENT;
464 }
465
466 return 0;
467}
468
469static int gr3d_get_resets(struct device *dev, struct gr3d *gr3d)
470{
471 int err;
472
473 gr3d->resets[RST_MC].id = "mc";
474 gr3d->resets[RST_MC2].id = "mc2";
475 gr3d->resets[RST_GR3D].id = "3d";
476 gr3d->resets[RST_GR3D2].id = "3d2";
477 gr3d->nresets = gr3d->soc->num_resets;
478
479 err = devm_reset_control_bulk_get_optional_exclusive_released(
480 dev, gr3d->nresets, gr3d->resets);
481 if (err) {
482 dev_err(dev, "failed to get reset: %d\n", err);
483 return err;
484 }
485
486 if (WARN_ON(!gr3d->resets[RST_GR3D].rstc) ||
487 WARN_ON(!gr3d->resets[RST_GR3D2].rstc && gr3d->nresets == 4))
488 return -ENOENT;
489
490 return 0;
491}
492
493static int gr3d_probe(struct platform_device *pdev)
494{
495 struct host1x_syncpt **syncpts;
496 struct gr3d *gr3d;
497 unsigned int i;
498 int err;
499
500 gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL);
501 if (!gr3d)
502 return -ENOMEM;
503
504 platform_set_drvdata(pdev, gr3d);
505
506 gr3d->soc = of_device_get_match_data(&pdev->dev);
507
508 syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL);
509 if (!syncpts)
510 return -ENOMEM;
511
512 err = gr3d_get_clocks(&pdev->dev, gr3d);
513 if (err)
514 return err;
515
516 err = gr3d_get_resets(&pdev->dev, gr3d);
517 if (err)
518 return err;
519
520 err = gr3d_init_power(&pdev->dev, gr3d);
521 if (err)
522 return err;
523
524 INIT_LIST_HEAD(&gr3d->client.base.list);
525 gr3d->client.base.ops = &gr3d_client_ops;
526 gr3d->client.base.dev = &pdev->dev;
527 gr3d->client.base.class = HOST1X_CLASS_GR3D;
528 gr3d->client.base.syncpts = syncpts;
529 gr3d->client.base.num_syncpts = 1;
530
531 INIT_LIST_HEAD(&gr3d->client.list);
532 gr3d->client.version = gr3d->soc->version;
533 gr3d->client.ops = &gr3d_ops;
534
535 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
536 if (err)
537 return err;
538
539 err = host1x_client_register(&gr3d->client.base);
540 if (err < 0) {
541 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
542 err);
543 return err;
544 }
545
546 /* initialize address register map */
547 for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++)
548 set_bit(gr3d_addr_regs[i], gr3d->addr_regs);
549
550 return 0;
551}
552
553static int gr3d_remove(struct platform_device *pdev)
554{
555 struct gr3d *gr3d = platform_get_drvdata(pdev);
556 int err;
557
558 err = host1x_client_unregister(&gr3d->client.base);
559 if (err < 0) {
560 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
561 err);
562 return err;
563 }
564
565 return 0;
566}
567
568static int __maybe_unused gr3d_runtime_suspend(struct device *dev)
569{
570 struct gr3d *gr3d = dev_get_drvdata(dev);
571 int err;
572
573 host1x_channel_stop(gr3d->channel);
574
575 err = reset_control_bulk_assert(gr3d->nresets, gr3d->resets);
576 if (err) {
577 dev_err(dev, "failed to assert reset: %d\n", err);
578 return err;
579 }
580
581 usleep_range(10, 20);
582
583 /*
584 * Older device-trees don't specify MC resets and power-gating can't
585 * be done safely in that case. Hence we will keep the power ungated
586 * for older DTBs. For newer DTBs, GENPD will perform the power-gating.
587 */
588
589 clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks);
590 reset_control_bulk_release(gr3d->nresets, gr3d->resets);
591
592 return 0;
593}
594
595static int __maybe_unused gr3d_runtime_resume(struct device *dev)
596{
597 struct gr3d *gr3d = dev_get_drvdata(dev);
598 int err;
599
600 err = reset_control_bulk_acquire(gr3d->nresets, gr3d->resets);
601 if (err) {
602 dev_err(dev, "failed to acquire reset: %d\n", err);
603 return err;
604 }
605
606 err = clk_bulk_prepare_enable(gr3d->nclocks, gr3d->clocks);
607 if (err) {
608 dev_err(dev, "failed to enable clock: %d\n", err);
609 goto release_reset;
610 }
611
612 err = reset_control_bulk_deassert(gr3d->nresets, gr3d->resets);
613 if (err) {
614 dev_err(dev, "failed to deassert reset: %d\n", err);
615 goto disable_clk;
616 }
617
618 return 0;
619
620disable_clk:
621 clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks);
622release_reset:
623 reset_control_bulk_release(gr3d->nresets, gr3d->resets);
624
625 return err;
626}
627
628static const struct dev_pm_ops tegra_gr3d_pm = {
629 SET_RUNTIME_PM_OPS(gr3d_runtime_suspend, gr3d_runtime_resume, NULL)
630 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
631 pm_runtime_force_resume)
632};
633
634struct platform_driver tegra_gr3d_driver = {
635 .driver = {
636 .name = "tegra-gr3d",
637 .of_match_table = tegra_gr3d_match,
638 .pm = &tegra_gr3d_pm,
639 },
640 .probe = gr3d_probe,
641 .remove = gr3d_remove,
642};