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1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "sienna_cichlid.h"
25#include "amdgpu_reset.h"
26#include "amdgpu_amdkfd.h"
27#include "amdgpu_dpm.h"
28#include "amdgpu_job.h"
29#include "amdgpu_ring.h"
30#include "amdgpu_ras.h"
31#include "amdgpu_psp.h"
32#include "amdgpu_xgmi.h"
33
34static bool sienna_cichlid_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
35{
36#if 0
37 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
38
39 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7) &&
40 adev->pm.fw_version >= 0x3a5500 && !amdgpu_sriov_vf(adev))
41 return true;
42#endif
43 return amdgpu_reset_method == AMD_RESET_METHOD_MODE2;
44}
45
46static struct amdgpu_reset_handler *
47sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
48 struct amdgpu_reset_context *reset_context)
49{
50 struct amdgpu_reset_handler *handler;
51 int i;
52
53 if (reset_context->method != AMD_RESET_METHOD_NONE) {
54 for_each_handler(i, handler, reset_ctl) {
55 if (handler->reset_method == reset_context->method)
56 return handler;
57 }
58 }
59
60 if (sienna_cichlid_is_mode2_default(reset_ctl)) {
61 for_each_handler(i, handler, reset_ctl) {
62 if (handler->reset_method == AMD_RESET_METHOD_MODE2)
63 return handler;
64 }
65 }
66
67 return NULL;
68}
69
70static int sienna_cichlid_mode2_suspend_ip(struct amdgpu_device *adev)
71{
72 int r, i;
73
74 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
75 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
76
77 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
78 if (!(adev->ip_blocks[i].version->type ==
79 AMD_IP_BLOCK_TYPE_GFX ||
80 adev->ip_blocks[i].version->type ==
81 AMD_IP_BLOCK_TYPE_SDMA))
82 continue;
83
84 r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]);
85 if (r)
86 return r;
87 }
88
89 return 0;
90}
91
92static int
93sienna_cichlid_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
94 struct amdgpu_reset_context *reset_context)
95{
96 int r = 0;
97 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
98
99 if (!amdgpu_sriov_vf(adev)) {
100 if (adev->gfxhub.funcs->mode2_save_regs)
101 adev->gfxhub.funcs->mode2_save_regs(adev);
102 if (adev->gfxhub.funcs->halt)
103 adev->gfxhub.funcs->halt(adev);
104 r = sienna_cichlid_mode2_suspend_ip(adev);
105 }
106
107 return r;
108}
109
110static void sienna_cichlid_async_reset(struct work_struct *work)
111{
112 struct amdgpu_reset_handler *handler;
113 struct amdgpu_reset_control *reset_ctl =
114 container_of(work, struct amdgpu_reset_control, reset_work);
115 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
116 int i;
117
118 for_each_handler(i, handler, reset_ctl) {
119 if (handler->reset_method == reset_ctl->active_reset) {
120 dev_dbg(adev->dev, "Resetting device\n");
121 handler->do_reset(adev);
122 break;
123 }
124 }
125}
126
127static int sienna_cichlid_mode2_reset(struct amdgpu_device *adev)
128{
129 /* disable BM */
130 pci_clear_master(adev->pdev);
131 return amdgpu_dpm_mode2_reset(adev);
132}
133
134static int
135sienna_cichlid_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
136 struct amdgpu_reset_context *reset_context)
137{
138 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
139 int r;
140
141 r = sienna_cichlid_mode2_reset(adev);
142 if (r) {
143 dev_err(adev->dev,
144 "ASIC reset failed with error, %d ", r);
145 }
146 return r;
147}
148
149static int sienna_cichlid_mode2_restore_ip(struct amdgpu_device *adev)
150{
151 int i, r;
152 struct psp_context *psp = &adev->psp;
153
154 r = psp_rlc_autoload_start(psp);
155 if (r) {
156 dev_err(adev->dev, "Failed to start rlc autoload\n");
157 return r;
158 }
159
160 /* Reinit GFXHUB */
161 if (adev->gfxhub.funcs->mode2_restore_regs)
162 adev->gfxhub.funcs->mode2_restore_regs(adev);
163 adev->gfxhub.funcs->init(adev);
164 r = adev->gfxhub.funcs->gart_enable(adev);
165 if (r) {
166 dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n");
167 return r;
168 }
169
170 for (i = 0; i < adev->num_ip_blocks; i++) {
171 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
172 r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
173 if (r)
174 return r;
175 }
176 }
177
178 for (i = 0; i < adev->num_ip_blocks; i++) {
179 if (!(adev->ip_blocks[i].version->type ==
180 AMD_IP_BLOCK_TYPE_GFX ||
181 adev->ip_blocks[i].version->type ==
182 AMD_IP_BLOCK_TYPE_SDMA))
183 continue;
184 r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
185 if (r)
186 return r;
187 }
188
189 for (i = 0; i < adev->num_ip_blocks; i++) {
190 if (!(adev->ip_blocks[i].version->type ==
191 AMD_IP_BLOCK_TYPE_GFX ||
192 adev->ip_blocks[i].version->type ==
193 AMD_IP_BLOCK_TYPE_SDMA))
194 continue;
195
196 if (adev->ip_blocks[i].version->funcs->late_init) {
197 r = adev->ip_blocks[i].version->funcs->late_init(
198 &adev->ip_blocks[i]);
199 if (r) {
200 dev_err(adev->dev,
201 "late_init of IP block <%s> failed %d after reset\n",
202 adev->ip_blocks[i].version->funcs->name,
203 r);
204 return r;
205 }
206 }
207 adev->ip_blocks[i].status.late_initialized = true;
208 }
209
210 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
211 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
212
213 return r;
214}
215
216static int
217sienna_cichlid_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
218 struct amdgpu_reset_context *reset_context)
219{
220 int r;
221 struct amdgpu_device *tmp_adev = (struct amdgpu_device *)reset_ctl->handle;
222
223 amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_RESET_RECOVERY);
224 dev_info(tmp_adev->dev,
225 "GPU reset succeeded, trying to resume\n");
226 r = sienna_cichlid_mode2_restore_ip(tmp_adev);
227 if (r)
228 goto end;
229
230 /*
231 * Add this ASIC as tracked as reset was already
232 * complete successfully.
233 */
234 amdgpu_register_gpu_instance(tmp_adev);
235
236 /* Resume RAS */
237 amdgpu_ras_resume(tmp_adev);
238
239 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
240
241 amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_DEFAULT);
242 r = amdgpu_ib_ring_tests(tmp_adev);
243 if (r) {
244 dev_err(tmp_adev->dev,
245 "ib ring test failed (%d).\n", r);
246 r = -EAGAIN;
247 goto end;
248 }
249
250end:
251 if (r)
252 return -EAGAIN;
253 else
254 return r;
255}
256
257static struct amdgpu_reset_handler sienna_cichlid_mode2_handler = {
258 .reset_method = AMD_RESET_METHOD_MODE2,
259 .prepare_env = NULL,
260 .prepare_hwcontext = sienna_cichlid_mode2_prepare_hwcontext,
261 .perform_reset = sienna_cichlid_mode2_perform_reset,
262 .restore_hwcontext = sienna_cichlid_mode2_restore_hwcontext,
263 .restore_env = NULL,
264 .do_reset = sienna_cichlid_mode2_reset,
265};
266
267static struct amdgpu_reset_handler
268 *sienna_cichlid_rst_handlers[AMDGPU_RESET_MAX_HANDLERS] = {
269 &sienna_cichlid_mode2_handler,
270 };
271
272int sienna_cichlid_reset_init(struct amdgpu_device *adev)
273{
274 struct amdgpu_reset_control *reset_ctl;
275
276 reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);
277 if (!reset_ctl)
278 return -ENOMEM;
279
280 reset_ctl->handle = adev;
281 reset_ctl->async_reset = sienna_cichlid_async_reset;
282 reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
283 reset_ctl->get_reset_handler = sienna_cichlid_get_reset_handler;
284
285 INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
286 /* Only mode2 is handled through reset control now */
287 reset_ctl->reset_handlers = &sienna_cichlid_rst_handlers;
288 adev->reset_cntl = reset_ctl;
289
290 return 0;
291}
292
293int sienna_cichlid_reset_fini(struct amdgpu_device *adev)
294{
295 kfree(adev->reset_cntl);
296 adev->reset_cntl = NULL;
297 return 0;
298}
1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "sienna_cichlid.h"
25#include "amdgpu_reset.h"
26#include "amdgpu_amdkfd.h"
27#include "amdgpu_dpm.h"
28#include "amdgpu_job.h"
29#include "amdgpu_ring.h"
30#include "amdgpu_ras.h"
31#include "amdgpu_psp.h"
32#include "amdgpu_xgmi.h"
33
34static bool sienna_cichlid_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
35{
36#if 0
37 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
38
39 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7) &&
40 adev->pm.fw_version >= 0x3a5500 && !amdgpu_sriov_vf(adev))
41 return true;
42#endif
43 return false;
44}
45
46static struct amdgpu_reset_handler *
47sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
48 struct amdgpu_reset_context *reset_context)
49{
50 struct amdgpu_reset_handler *handler;
51
52 if (reset_context->method != AMD_RESET_METHOD_NONE) {
53 list_for_each_entry(handler, &reset_ctl->reset_handlers,
54 handler_list) {
55 if (handler->reset_method == reset_context->method)
56 return handler;
57 }
58 }
59
60 if (sienna_cichlid_is_mode2_default(reset_ctl)) {
61 list_for_each_entry (handler, &reset_ctl->reset_handlers,
62 handler_list) {
63 if (handler->reset_method == AMD_RESET_METHOD_MODE2)
64 return handler;
65 }
66 }
67
68 return NULL;
69}
70
71static int sienna_cichlid_mode2_suspend_ip(struct amdgpu_device *adev)
72{
73 int r, i;
74
75 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
76 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
77
78 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
79 if (!(adev->ip_blocks[i].version->type ==
80 AMD_IP_BLOCK_TYPE_GFX ||
81 adev->ip_blocks[i].version->type ==
82 AMD_IP_BLOCK_TYPE_SDMA))
83 continue;
84
85 r = adev->ip_blocks[i].version->funcs->suspend(adev);
86
87 if (r) {
88 dev_err(adev->dev,
89 "suspend of IP block <%s> failed %d\n",
90 adev->ip_blocks[i].version->funcs->name, r);
91 return r;
92 }
93 adev->ip_blocks[i].status.hw = false;
94 }
95
96 return r;
97}
98
99static int
100sienna_cichlid_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
101 struct amdgpu_reset_context *reset_context)
102{
103 int r = 0;
104 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
105
106 if (!amdgpu_sriov_vf(adev)) {
107 if (adev->gfxhub.funcs->mode2_save_regs)
108 adev->gfxhub.funcs->mode2_save_regs(adev);
109 if (adev->gfxhub.funcs->halt)
110 adev->gfxhub.funcs->halt(adev);
111 r = sienna_cichlid_mode2_suspend_ip(adev);
112 }
113
114 return r;
115}
116
117static void sienna_cichlid_async_reset(struct work_struct *work)
118{
119 struct amdgpu_reset_handler *handler;
120 struct amdgpu_reset_control *reset_ctl =
121 container_of(work, struct amdgpu_reset_control, reset_work);
122 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
123
124 list_for_each_entry(handler, &reset_ctl->reset_handlers,
125 handler_list) {
126 if (handler->reset_method == reset_ctl->active_reset) {
127 dev_dbg(adev->dev, "Resetting device\n");
128 handler->do_reset(adev);
129 break;
130 }
131 }
132}
133
134static int sienna_cichlid_mode2_reset(struct amdgpu_device *adev)
135{
136 /* disable BM */
137 pci_clear_master(adev->pdev);
138 return amdgpu_dpm_mode2_reset(adev);
139}
140
141static int
142sienna_cichlid_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
143 struct amdgpu_reset_context *reset_context)
144{
145 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
146 int r;
147
148 r = sienna_cichlid_mode2_reset(adev);
149 if (r) {
150 dev_err(adev->dev,
151 "ASIC reset failed with error, %d ", r);
152 }
153 return r;
154}
155
156static int sienna_cichlid_mode2_restore_ip(struct amdgpu_device *adev)
157{
158 int i, r;
159 struct psp_context *psp = &adev->psp;
160
161 r = psp_rlc_autoload_start(psp);
162 if (r) {
163 dev_err(adev->dev, "Failed to start rlc autoload\n");
164 return r;
165 }
166
167 /* Reinit GFXHUB */
168 if (adev->gfxhub.funcs->mode2_restore_regs)
169 adev->gfxhub.funcs->mode2_restore_regs(adev);
170 adev->gfxhub.funcs->init(adev);
171 r = adev->gfxhub.funcs->gart_enable(adev);
172 if (r) {
173 dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n");
174 return r;
175 }
176
177 for (i = 0; i < adev->num_ip_blocks; i++) {
178 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
179 r = adev->ip_blocks[i].version->funcs->resume(adev);
180 if (r) {
181 dev_err(adev->dev,
182 "resume of IP block <%s> failed %d\n",
183 adev->ip_blocks[i].version->funcs->name, r);
184 return r;
185 }
186
187 adev->ip_blocks[i].status.hw = true;
188 }
189 }
190
191 for (i = 0; i < adev->num_ip_blocks; i++) {
192 if (!(adev->ip_blocks[i].version->type ==
193 AMD_IP_BLOCK_TYPE_GFX ||
194 adev->ip_blocks[i].version->type ==
195 AMD_IP_BLOCK_TYPE_SDMA))
196 continue;
197 r = adev->ip_blocks[i].version->funcs->resume(adev);
198 if (r) {
199 dev_err(adev->dev,
200 "resume of IP block <%s> failed %d\n",
201 adev->ip_blocks[i].version->funcs->name, r);
202 return r;
203 }
204
205 adev->ip_blocks[i].status.hw = true;
206 }
207
208 for (i = 0; i < adev->num_ip_blocks; i++) {
209 if (!(adev->ip_blocks[i].version->type ==
210 AMD_IP_BLOCK_TYPE_GFX ||
211 adev->ip_blocks[i].version->type ==
212 AMD_IP_BLOCK_TYPE_SDMA))
213 continue;
214
215 if (adev->ip_blocks[i].version->funcs->late_init) {
216 r = adev->ip_blocks[i].version->funcs->late_init(
217 (void *)adev);
218 if (r) {
219 dev_err(adev->dev,
220 "late_init of IP block <%s> failed %d after reset\n",
221 adev->ip_blocks[i].version->funcs->name,
222 r);
223 return r;
224 }
225 }
226 adev->ip_blocks[i].status.late_initialized = true;
227 }
228
229 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
230 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
231
232 return r;
233}
234
235static int
236sienna_cichlid_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
237 struct amdgpu_reset_context *reset_context)
238{
239 int r;
240 struct amdgpu_device *tmp_adev = (struct amdgpu_device *)reset_ctl->handle;
241
242 dev_info(tmp_adev->dev,
243 "GPU reset succeeded, trying to resume\n");
244 r = sienna_cichlid_mode2_restore_ip(tmp_adev);
245 if (r)
246 goto end;
247
248 /*
249 * Add this ASIC as tracked as reset was already
250 * complete successfully.
251 */
252 amdgpu_register_gpu_instance(tmp_adev);
253
254 /* Resume RAS */
255 amdgpu_ras_resume(tmp_adev);
256
257 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
258
259 r = amdgpu_ib_ring_tests(tmp_adev);
260 if (r) {
261 dev_err(tmp_adev->dev,
262 "ib ring test failed (%d).\n", r);
263 r = -EAGAIN;
264 goto end;
265 }
266
267end:
268 if (r)
269 return -EAGAIN;
270 else
271 return r;
272}
273
274static struct amdgpu_reset_handler sienna_cichlid_mode2_handler = {
275 .reset_method = AMD_RESET_METHOD_MODE2,
276 .prepare_env = NULL,
277 .prepare_hwcontext = sienna_cichlid_mode2_prepare_hwcontext,
278 .perform_reset = sienna_cichlid_mode2_perform_reset,
279 .restore_hwcontext = sienna_cichlid_mode2_restore_hwcontext,
280 .restore_env = NULL,
281 .do_reset = sienna_cichlid_mode2_reset,
282};
283
284int sienna_cichlid_reset_init(struct amdgpu_device *adev)
285{
286 struct amdgpu_reset_control *reset_ctl;
287
288 reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);
289 if (!reset_ctl)
290 return -ENOMEM;
291
292 reset_ctl->handle = adev;
293 reset_ctl->async_reset = sienna_cichlid_async_reset;
294 reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
295 reset_ctl->get_reset_handler = sienna_cichlid_get_reset_handler;
296
297 INIT_LIST_HEAD(&reset_ctl->reset_handlers);
298 INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
299 /* Only mode2 is handled through reset control now */
300 amdgpu_reset_add_handler(reset_ctl, &sienna_cichlid_mode2_handler);
301
302 adev->reset_cntl = reset_ctl;
303
304 return 0;
305}
306
307int sienna_cichlid_reset_fini(struct amdgpu_device *adev)
308{
309 kfree(adev->reset_cntl);
310 adev->reset_cntl = NULL;
311 return 0;
312}