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1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include <linux/firmware.h>
26#include <linux/module.h>
27
28#include "amdgpu.h"
29#include "amdgpu_ucode.h"
30#include "amdgpu_trace.h"
31#include "cikd.h"
32#include "cik.h"
33
34#include "bif/bif_4_1_d.h"
35#include "bif/bif_4_1_sh_mask.h"
36
37#include "gca/gfx_7_2_d.h"
38#include "gca/gfx_7_2_enum.h"
39#include "gca/gfx_7_2_sh_mask.h"
40
41#include "gmc/gmc_7_1_d.h"
42#include "gmc/gmc_7_1_sh_mask.h"
43
44#include "oss/oss_2_0_d.h"
45#include "oss/oss_2_0_sh_mask.h"
46
47static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
48{
49 SDMA0_REGISTER_OFFSET,
50 SDMA1_REGISTER_OFFSET
51};
52
53static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
54static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
55static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
56static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
57static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block);
58
59MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin");
60MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin");
61MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin");
62MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin");
63MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin");
64MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin");
65MODULE_FIRMWARE("amdgpu/kabini_sdma.bin");
66MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin");
67MODULE_FIRMWARE("amdgpu/mullins_sdma.bin");
68MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin");
69
70u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
71
72
73static void cik_sdma_free_microcode(struct amdgpu_device *adev)
74{
75 int i;
76
77 for (i = 0; i < adev->sdma.num_instances; i++)
78 amdgpu_ucode_release(&adev->sdma.instance[i].fw);
79}
80
81/*
82 * sDMA - System DMA
83 * Starting with CIK, the GPU has new asynchronous
84 * DMA engines. These engines are used for compute
85 * and gfx. There are two DMA engines (SDMA0, SDMA1)
86 * and each one supports 1 ring buffer used for gfx
87 * and 2 queues used for compute.
88 *
89 * The programming model is very similar to the CP
90 * (ring buffer, IBs, etc.), but sDMA has it's own
91 * packet format that is different from the PM4 format
92 * used by the CP. sDMA supports copying data, writing
93 * embedded data, solid fills, and a number of other
94 * things. It also has support for tiling/detiling of
95 * buffers.
96 */
97
98/**
99 * cik_sdma_init_microcode - load ucode images from disk
100 *
101 * @adev: amdgpu_device pointer
102 *
103 * Use the firmware interface to load the ucode images into
104 * the driver (not loaded into hw).
105 * Returns 0 on success, error on failure.
106 */
107static int cik_sdma_init_microcode(struct amdgpu_device *adev)
108{
109 const char *chip_name;
110 int err = 0, i;
111
112 DRM_DEBUG("\n");
113
114 switch (adev->asic_type) {
115 case CHIP_BONAIRE:
116 chip_name = "bonaire";
117 break;
118 case CHIP_HAWAII:
119 chip_name = "hawaii";
120 break;
121 case CHIP_KAVERI:
122 chip_name = "kaveri";
123 break;
124 case CHIP_KABINI:
125 chip_name = "kabini";
126 break;
127 case CHIP_MULLINS:
128 chip_name = "mullins";
129 break;
130 default: BUG();
131 }
132
133 for (i = 0; i < adev->sdma.num_instances; i++) {
134 if (i == 0)
135 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
136 "amdgpu/%s_sdma.bin", chip_name);
137 else
138 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
139 "amdgpu/%s_sdma1.bin", chip_name);
140 if (err)
141 goto out;
142 }
143out:
144 if (err) {
145 pr_err("cik_sdma: Failed to load firmware \"%s_sdma%s.bin\"\n",
146 chip_name, i == 0 ? "" : "1");
147 for (i = 0; i < adev->sdma.num_instances; i++)
148 amdgpu_ucode_release(&adev->sdma.instance[i].fw);
149 }
150 return err;
151}
152
153/**
154 * cik_sdma_ring_get_rptr - get the current read pointer
155 *
156 * @ring: amdgpu ring pointer
157 *
158 * Get the current rptr from the hardware (CIK+).
159 */
160static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
161{
162 u32 rptr;
163
164 rptr = *ring->rptr_cpu_addr;
165
166 return (rptr & 0x3fffc) >> 2;
167}
168
169/**
170 * cik_sdma_ring_get_wptr - get the current write pointer
171 *
172 * @ring: amdgpu ring pointer
173 *
174 * Get the current wptr from the hardware (CIK+).
175 */
176static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
177{
178 struct amdgpu_device *adev = ring->adev;
179
180 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
181}
182
183/**
184 * cik_sdma_ring_set_wptr - commit the write pointer
185 *
186 * @ring: amdgpu ring pointer
187 *
188 * Write the wptr back to the hardware (CIK+).
189 */
190static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
191{
192 struct amdgpu_device *adev = ring->adev;
193
194 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
195 (ring->wptr << 2) & 0x3fffc);
196}
197
198static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
199{
200 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
201 int i;
202
203 for (i = 0; i < count; i++)
204 if (sdma && sdma->burst_nop && (i == 0))
205 amdgpu_ring_write(ring, ring->funcs->nop |
206 SDMA_NOP_COUNT(count - 1));
207 else
208 amdgpu_ring_write(ring, ring->funcs->nop);
209}
210
211/**
212 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
213 *
214 * @ring: amdgpu ring pointer
215 * @job: job to retrive vmid from
216 * @ib: IB object to schedule
217 * @flags: unused
218 *
219 * Schedule an IB in the DMA ring (CIK).
220 */
221static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
222 struct amdgpu_job *job,
223 struct amdgpu_ib *ib,
224 uint32_t flags)
225{
226 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
227 u32 extra_bits = vmid & 0xf;
228
229 /* IB packet must end on a 8 DW boundary */
230 cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7);
231
232 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
233 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
234 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
235 amdgpu_ring_write(ring, ib->length_dw);
236
237}
238
239/**
240 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
241 *
242 * @ring: amdgpu ring pointer
243 *
244 * Emit an hdp flush packet on the requested DMA ring.
245 */
246static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
247{
248 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
249 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
250 u32 ref_and_mask;
251
252 if (ring->me == 0)
253 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
254 else
255 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
256
257 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
258 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
259 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
260 amdgpu_ring_write(ring, ref_and_mask); /* reference */
261 amdgpu_ring_write(ring, ref_and_mask); /* mask */
262 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
263}
264
265/**
266 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
267 *
268 * @ring: amdgpu ring pointer
269 * @addr: address
270 * @seq: sequence number
271 * @flags: fence related flags
272 *
273 * Add a DMA fence packet to the ring to write
274 * the fence seq number and DMA trap packet to generate
275 * an interrupt if needed (CIK).
276 */
277static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
278 unsigned flags)
279{
280 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
281 /* write the fence */
282 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
283 amdgpu_ring_write(ring, lower_32_bits(addr));
284 amdgpu_ring_write(ring, upper_32_bits(addr));
285 amdgpu_ring_write(ring, lower_32_bits(seq));
286
287 /* optionally write high bits as well */
288 if (write64bit) {
289 addr += 4;
290 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
291 amdgpu_ring_write(ring, lower_32_bits(addr));
292 amdgpu_ring_write(ring, upper_32_bits(addr));
293 amdgpu_ring_write(ring, upper_32_bits(seq));
294 }
295
296 /* generate an interrupt */
297 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
298}
299
300/**
301 * cik_sdma_gfx_stop - stop the gfx async dma engines
302 *
303 * @adev: amdgpu_device pointer
304 *
305 * Stop the gfx async dma ring buffers (CIK).
306 */
307static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
308{
309 u32 rb_cntl;
310 int i;
311
312 for (i = 0; i < adev->sdma.num_instances; i++) {
313 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
314 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
315 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
316 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
317 }
318}
319
320/**
321 * cik_sdma_rlc_stop - stop the compute async dma engines
322 *
323 * @adev: amdgpu_device pointer
324 *
325 * Stop the compute async dma queues (CIK).
326 */
327static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
328{
329 /* XXX todo */
330}
331
332/**
333 * cik_ctx_switch_enable - stop the async dma engines context switch
334 *
335 * @adev: amdgpu_device pointer
336 * @enable: enable/disable the DMA MEs context switch.
337 *
338 * Halt or unhalt the async dma engines context switch (VI).
339 */
340static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
341{
342 u32 f32_cntl, phase_quantum = 0;
343 int i;
344
345 if (amdgpu_sdma_phase_quantum) {
346 unsigned value = amdgpu_sdma_phase_quantum;
347 unsigned unit = 0;
348
349 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
350 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
351 value = (value + 1) >> 1;
352 unit++;
353 }
354 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
355 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
356 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
357 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
358 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
359 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
360 WARN_ONCE(1,
361 "clamping sdma_phase_quantum to %uK clock cycles\n",
362 value << unit);
363 }
364 phase_quantum =
365 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
366 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
367 }
368
369 for (i = 0; i < adev->sdma.num_instances; i++) {
370 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
371 if (enable) {
372 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
373 AUTO_CTXSW_ENABLE, 1);
374 if (amdgpu_sdma_phase_quantum) {
375 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
376 phase_quantum);
377 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
378 phase_quantum);
379 }
380 } else {
381 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
382 AUTO_CTXSW_ENABLE, 0);
383 }
384
385 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
386 }
387}
388
389/**
390 * cik_sdma_enable - stop the async dma engines
391 *
392 * @adev: amdgpu_device pointer
393 * @enable: enable/disable the DMA MEs.
394 *
395 * Halt or unhalt the async dma engines (CIK).
396 */
397static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
398{
399 u32 me_cntl;
400 int i;
401
402 if (!enable) {
403 cik_sdma_gfx_stop(adev);
404 cik_sdma_rlc_stop(adev);
405 }
406
407 for (i = 0; i < adev->sdma.num_instances; i++) {
408 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
409 if (enable)
410 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
411 else
412 me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
413 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
414 }
415}
416
417/**
418 * cik_sdma_gfx_resume - setup and start the async dma engines
419 *
420 * @adev: amdgpu_device pointer
421 *
422 * Set up the gfx DMA ring buffers and enable them (CIK).
423 * Returns 0 for success, error for failure.
424 */
425static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
426{
427 struct amdgpu_ring *ring;
428 u32 rb_cntl, ib_cntl;
429 u32 rb_bufsz;
430 int i, j, r;
431
432 for (i = 0; i < adev->sdma.num_instances; i++) {
433 ring = &adev->sdma.instance[i].ring;
434
435 mutex_lock(&adev->srbm_mutex);
436 for (j = 0; j < 16; j++) {
437 cik_srbm_select(adev, 0, 0, 0, j);
438 /* SDMA GFX */
439 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
440 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
441 /* XXX SDMA RLC - todo */
442 }
443 cik_srbm_select(adev, 0, 0, 0, 0);
444 mutex_unlock(&adev->srbm_mutex);
445
446 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
447 adev->gfx.config.gb_addr_config & 0x70);
448
449 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
450 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
451
452 /* Set ring buffer size in dwords */
453 rb_bufsz = order_base_2(ring->ring_size / 4);
454 rb_cntl = rb_bufsz << 1;
455#ifdef __BIG_ENDIAN
456 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
457 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
458#endif
459 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
460
461 /* Initialize the ring buffer's read and write pointers */
462 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
463 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
464 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
465 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
466
467 /* set the wb address whether it's enabled or not */
468 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
469 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
470 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
471 ((ring->rptr_gpu_addr) & 0xFFFFFFFC));
472
473 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
474
475 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
476 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
477
478 ring->wptr = 0;
479 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
480
481 /* enable DMA RB */
482 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
483 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
484
485 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
486#ifdef __BIG_ENDIAN
487 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
488#endif
489 /* enable DMA IBs */
490 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
491 }
492
493 cik_sdma_enable(adev, true);
494
495 for (i = 0; i < adev->sdma.num_instances; i++) {
496 ring = &adev->sdma.instance[i].ring;
497 r = amdgpu_ring_test_helper(ring);
498 if (r)
499 return r;
500 }
501
502 return 0;
503}
504
505/**
506 * cik_sdma_rlc_resume - setup and start the async dma engines
507 *
508 * @adev: amdgpu_device pointer
509 *
510 * Set up the compute DMA queues and enable them (CIK).
511 * Returns 0 for success, error for failure.
512 */
513static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
514{
515 /* XXX todo */
516 return 0;
517}
518
519/**
520 * cik_sdma_load_microcode - load the sDMA ME ucode
521 *
522 * @adev: amdgpu_device pointer
523 *
524 * Loads the sDMA0/1 ucode.
525 * Returns 0 for success, -EINVAL if the ucode is not available.
526 */
527static int cik_sdma_load_microcode(struct amdgpu_device *adev)
528{
529 const struct sdma_firmware_header_v1_0 *hdr;
530 const __le32 *fw_data;
531 u32 fw_size;
532 int i, j;
533
534 /* halt the MEs */
535 cik_sdma_enable(adev, false);
536
537 for (i = 0; i < adev->sdma.num_instances; i++) {
538 if (!adev->sdma.instance[i].fw)
539 return -EINVAL;
540 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
541 amdgpu_ucode_print_sdma_hdr(&hdr->header);
542 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
543 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
544 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
545 if (adev->sdma.instance[i].feature_version >= 20)
546 adev->sdma.instance[i].burst_nop = true;
547 fw_data = (const __le32 *)
548 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
549 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
550 for (j = 0; j < fw_size; j++)
551 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
552 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
553 }
554
555 return 0;
556}
557
558/**
559 * cik_sdma_start - setup and start the async dma engines
560 *
561 * @adev: amdgpu_device pointer
562 *
563 * Set up the DMA engines and enable them (CIK).
564 * Returns 0 for success, error for failure.
565 */
566static int cik_sdma_start(struct amdgpu_device *adev)
567{
568 int r;
569
570 r = cik_sdma_load_microcode(adev);
571 if (r)
572 return r;
573
574 /* halt the engine before programing */
575 cik_sdma_enable(adev, false);
576 /* enable sdma ring preemption */
577 cik_ctx_switch_enable(adev, true);
578
579 /* start the gfx rings and rlc compute queues */
580 r = cik_sdma_gfx_resume(adev);
581 if (r)
582 return r;
583 r = cik_sdma_rlc_resume(adev);
584 if (r)
585 return r;
586
587 return 0;
588}
589
590/**
591 * cik_sdma_ring_test_ring - simple async dma engine test
592 *
593 * @ring: amdgpu_ring structure holding ring information
594 *
595 * Test the DMA engine by writing using it to write an
596 * value to memory. (CIK).
597 * Returns 0 for success, error for failure.
598 */
599static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
600{
601 struct amdgpu_device *adev = ring->adev;
602 unsigned i;
603 unsigned index;
604 int r;
605 u32 tmp;
606 u64 gpu_addr;
607
608 r = amdgpu_device_wb_get(adev, &index);
609 if (r)
610 return r;
611
612 gpu_addr = adev->wb.gpu_addr + (index * 4);
613 tmp = 0xCAFEDEAD;
614 adev->wb.wb[index] = cpu_to_le32(tmp);
615
616 r = amdgpu_ring_alloc(ring, 5);
617 if (r)
618 goto error_free_wb;
619
620 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
621 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
622 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
623 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
624 amdgpu_ring_write(ring, 0xDEADBEEF);
625 amdgpu_ring_commit(ring);
626
627 for (i = 0; i < adev->usec_timeout; i++) {
628 tmp = le32_to_cpu(adev->wb.wb[index]);
629 if (tmp == 0xDEADBEEF)
630 break;
631 udelay(1);
632 }
633
634 if (i >= adev->usec_timeout)
635 r = -ETIMEDOUT;
636
637error_free_wb:
638 amdgpu_device_wb_free(adev, index);
639 return r;
640}
641
642/**
643 * cik_sdma_ring_test_ib - test an IB on the DMA engine
644 *
645 * @ring: amdgpu_ring structure holding ring information
646 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
647 *
648 * Test a simple IB in the DMA ring (CIK).
649 * Returns 0 on success, error on failure.
650 */
651static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
652{
653 struct amdgpu_device *adev = ring->adev;
654 struct amdgpu_ib ib;
655 struct dma_fence *f = NULL;
656 unsigned index;
657 u32 tmp = 0;
658 u64 gpu_addr;
659 long r;
660
661 r = amdgpu_device_wb_get(adev, &index);
662 if (r)
663 return r;
664
665 gpu_addr = adev->wb.gpu_addr + (index * 4);
666 tmp = 0xCAFEDEAD;
667 adev->wb.wb[index] = cpu_to_le32(tmp);
668 memset(&ib, 0, sizeof(ib));
669 r = amdgpu_ib_get(adev, NULL, 256,
670 AMDGPU_IB_POOL_DIRECT, &ib);
671 if (r)
672 goto err0;
673
674 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
675 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
676 ib.ptr[1] = lower_32_bits(gpu_addr);
677 ib.ptr[2] = upper_32_bits(gpu_addr);
678 ib.ptr[3] = 1;
679 ib.ptr[4] = 0xDEADBEEF;
680 ib.length_dw = 5;
681 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
682 if (r)
683 goto err1;
684
685 r = dma_fence_wait_timeout(f, false, timeout);
686 if (r == 0) {
687 r = -ETIMEDOUT;
688 goto err1;
689 } else if (r < 0) {
690 goto err1;
691 }
692 tmp = le32_to_cpu(adev->wb.wb[index]);
693 if (tmp == 0xDEADBEEF)
694 r = 0;
695 else
696 r = -EINVAL;
697
698err1:
699 amdgpu_ib_free(adev, &ib, NULL);
700 dma_fence_put(f);
701err0:
702 amdgpu_device_wb_free(adev, index);
703 return r;
704}
705
706/**
707 * cik_sdma_vm_copy_pte - update PTEs by copying them from the GART
708 *
709 * @ib: indirect buffer to fill with commands
710 * @pe: addr of the page entry
711 * @src: src addr to copy from
712 * @count: number of page entries to update
713 *
714 * Update PTEs by copying them from the GART using sDMA (CIK).
715 */
716static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
717 uint64_t pe, uint64_t src,
718 unsigned count)
719{
720 unsigned bytes = count * 8;
721
722 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
723 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
724 ib->ptr[ib->length_dw++] = bytes;
725 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
726 ib->ptr[ib->length_dw++] = lower_32_bits(src);
727 ib->ptr[ib->length_dw++] = upper_32_bits(src);
728 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
729 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
730}
731
732/**
733 * cik_sdma_vm_write_pte - update PTEs by writing them manually
734 *
735 * @ib: indirect buffer to fill with commands
736 * @pe: addr of the page entry
737 * @value: dst addr to write into pe
738 * @count: number of page entries to update
739 * @incr: increase next addr by incr bytes
740 *
741 * Update PTEs by writing them manually using sDMA (CIK).
742 */
743static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
744 uint64_t value, unsigned count,
745 uint32_t incr)
746{
747 unsigned ndw = count * 2;
748
749 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
750 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
751 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
752 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
753 ib->ptr[ib->length_dw++] = ndw;
754 for (; ndw > 0; ndw -= 2) {
755 ib->ptr[ib->length_dw++] = lower_32_bits(value);
756 ib->ptr[ib->length_dw++] = upper_32_bits(value);
757 value += incr;
758 }
759}
760
761/**
762 * cik_sdma_vm_set_pte_pde - update the page tables using sDMA
763 *
764 * @ib: indirect buffer to fill with commands
765 * @pe: addr of the page entry
766 * @addr: dst addr to write into pe
767 * @count: number of page entries to update
768 * @incr: increase next addr by incr bytes
769 * @flags: access flags
770 *
771 * Update the page tables using sDMA (CIK).
772 */
773static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
774 uint64_t addr, unsigned count,
775 uint32_t incr, uint64_t flags)
776{
777 /* for physically contiguous pages (vram) */
778 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
779 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
780 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
781 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
782 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
783 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
784 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
785 ib->ptr[ib->length_dw++] = incr; /* increment size */
786 ib->ptr[ib->length_dw++] = 0;
787 ib->ptr[ib->length_dw++] = count; /* number of entries */
788}
789
790/**
791 * cik_sdma_ring_pad_ib - pad the IB to the required number of dw
792 *
793 * @ring: amdgpu_ring structure holding ring information
794 * @ib: indirect buffer to fill with padding
795 *
796 */
797static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
798{
799 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
800 u32 pad_count;
801 int i;
802
803 pad_count = (-ib->length_dw) & 7;
804 for (i = 0; i < pad_count; i++)
805 if (sdma && sdma->burst_nop && (i == 0))
806 ib->ptr[ib->length_dw++] =
807 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
808 SDMA_NOP_COUNT(pad_count - 1);
809 else
810 ib->ptr[ib->length_dw++] =
811 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
812}
813
814/**
815 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
816 *
817 * @ring: amdgpu_ring pointer
818 *
819 * Make sure all previous operations are completed (CIK).
820 */
821static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
822{
823 uint32_t seq = ring->fence_drv.sync_seq;
824 uint64_t addr = ring->fence_drv.gpu_addr;
825
826 /* wait for idle */
827 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
828 SDMA_POLL_REG_MEM_EXTRA_OP(0) |
829 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
830 SDMA_POLL_REG_MEM_EXTRA_M));
831 amdgpu_ring_write(ring, addr & 0xfffffffc);
832 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
833 amdgpu_ring_write(ring, seq); /* reference */
834 amdgpu_ring_write(ring, 0xffffffff); /* mask */
835 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
836}
837
838/**
839 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
840 *
841 * @ring: amdgpu_ring pointer
842 * @vmid: vmid number to use
843 * @pd_addr: address
844 *
845 * Update the page table base and flush the VM TLB
846 * using sDMA (CIK).
847 */
848static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
849 unsigned vmid, uint64_t pd_addr)
850{
851 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
852 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
853
854 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
855
856 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
857 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
858 amdgpu_ring_write(ring, 0);
859 amdgpu_ring_write(ring, 0); /* reference */
860 amdgpu_ring_write(ring, 0); /* mask */
861 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
862}
863
864static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
865 uint32_t reg, uint32_t val)
866{
867 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
868 amdgpu_ring_write(ring, reg);
869 amdgpu_ring_write(ring, val);
870}
871
872static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
873 bool enable)
874{
875 u32 orig, data;
876
877 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
878 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
879 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
880 } else {
881 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
882 data |= 0xff000000;
883 if (data != orig)
884 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
885
886 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
887 data |= 0xff000000;
888 if (data != orig)
889 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
890 }
891}
892
893static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
894 bool enable)
895{
896 u32 orig, data;
897
898 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
899 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
900 data |= 0x100;
901 if (orig != data)
902 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
903
904 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
905 data |= 0x100;
906 if (orig != data)
907 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
908 } else {
909 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
910 data &= ~0x100;
911 if (orig != data)
912 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
913
914 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
915 data &= ~0x100;
916 if (orig != data)
917 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
918 }
919}
920
921static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block)
922{
923 struct amdgpu_device *adev = ip_block->adev;
924 int r;
925
926 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
927
928 r = cik_sdma_init_microcode(adev);
929 if (r)
930 return r;
931
932 cik_sdma_set_ring_funcs(adev);
933 cik_sdma_set_irq_funcs(adev);
934 cik_sdma_set_buffer_funcs(adev);
935 cik_sdma_set_vm_pte_funcs(adev);
936
937 return 0;
938}
939
940static int cik_sdma_sw_init(struct amdgpu_ip_block *ip_block)
941{
942 struct amdgpu_ring *ring;
943 struct amdgpu_device *adev = ip_block->adev;
944 int r, i;
945
946 /* SDMA trap event */
947 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224,
948 &adev->sdma.trap_irq);
949 if (r)
950 return r;
951
952 /* SDMA Privileged inst */
953 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
954 &adev->sdma.illegal_inst_irq);
955 if (r)
956 return r;
957
958 /* SDMA Privileged inst */
959 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247,
960 &adev->sdma.illegal_inst_irq);
961 if (r)
962 return r;
963
964 for (i = 0; i < adev->sdma.num_instances; i++) {
965 ring = &adev->sdma.instance[i].ring;
966 ring->ring_obj = NULL;
967 sprintf(ring->name, "sdma%d", i);
968 r = amdgpu_ring_init(adev, ring, 1024,
969 &adev->sdma.trap_irq,
970 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
971 AMDGPU_SDMA_IRQ_INSTANCE1,
972 AMDGPU_RING_PRIO_DEFAULT, NULL);
973 if (r)
974 return r;
975 }
976
977 return r;
978}
979
980static int cik_sdma_sw_fini(struct amdgpu_ip_block *ip_block)
981{
982 struct amdgpu_device *adev = ip_block->adev;
983 int i;
984
985 for (i = 0; i < adev->sdma.num_instances; i++)
986 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
987
988 cik_sdma_free_microcode(adev);
989 return 0;
990}
991
992static int cik_sdma_hw_init(struct amdgpu_ip_block *ip_block)
993{
994 int r;
995 struct amdgpu_device *adev = ip_block->adev;
996
997 r = cik_sdma_start(adev);
998 if (r)
999 return r;
1000
1001 return r;
1002}
1003
1004static int cik_sdma_hw_fini(struct amdgpu_ip_block *ip_block)
1005{
1006 struct amdgpu_device *adev = ip_block->adev;
1007
1008 cik_ctx_switch_enable(adev, false);
1009 cik_sdma_enable(adev, false);
1010
1011 return 0;
1012}
1013
1014static int cik_sdma_suspend(struct amdgpu_ip_block *ip_block)
1015{
1016 return cik_sdma_hw_fini(ip_block);
1017}
1018
1019static int cik_sdma_resume(struct amdgpu_ip_block *ip_block)
1020{
1021 cik_sdma_soft_reset(ip_block);
1022
1023 return cik_sdma_hw_init(ip_block);
1024}
1025
1026static bool cik_sdma_is_idle(void *handle)
1027{
1028 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1029 u32 tmp = RREG32(mmSRBM_STATUS2);
1030
1031 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1032 SRBM_STATUS2__SDMA1_BUSY_MASK))
1033 return false;
1034
1035 return true;
1036}
1037
1038static int cik_sdma_wait_for_idle(struct amdgpu_ip_block *ip_block)
1039{
1040 unsigned i;
1041 u32 tmp;
1042 struct amdgpu_device *adev = ip_block->adev;
1043
1044 for (i = 0; i < adev->usec_timeout; i++) {
1045 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1046 SRBM_STATUS2__SDMA1_BUSY_MASK);
1047
1048 if (!tmp)
1049 return 0;
1050 udelay(1);
1051 }
1052 return -ETIMEDOUT;
1053}
1054
1055static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block)
1056{
1057 u32 srbm_soft_reset = 0;
1058 struct amdgpu_device *adev = ip_block->adev;
1059 u32 tmp;
1060
1061 /* sdma0 */
1062 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1063 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1064 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1065 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1066
1067 /* sdma1 */
1068 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1069 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1070 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1071 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1072
1073 if (srbm_soft_reset) {
1074 tmp = RREG32(mmSRBM_SOFT_RESET);
1075 tmp |= srbm_soft_reset;
1076 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1077 WREG32(mmSRBM_SOFT_RESET, tmp);
1078 tmp = RREG32(mmSRBM_SOFT_RESET);
1079
1080 udelay(50);
1081
1082 tmp &= ~srbm_soft_reset;
1083 WREG32(mmSRBM_SOFT_RESET, tmp);
1084 tmp = RREG32(mmSRBM_SOFT_RESET);
1085
1086 /* Wait a little for things to settle down */
1087 udelay(50);
1088 }
1089
1090 return 0;
1091}
1092
1093static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1094 struct amdgpu_irq_src *src,
1095 unsigned type,
1096 enum amdgpu_interrupt_state state)
1097{
1098 u32 sdma_cntl;
1099
1100 switch (type) {
1101 case AMDGPU_SDMA_IRQ_INSTANCE0:
1102 switch (state) {
1103 case AMDGPU_IRQ_STATE_DISABLE:
1104 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1105 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1106 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1107 break;
1108 case AMDGPU_IRQ_STATE_ENABLE:
1109 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1110 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1111 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1112 break;
1113 default:
1114 break;
1115 }
1116 break;
1117 case AMDGPU_SDMA_IRQ_INSTANCE1:
1118 switch (state) {
1119 case AMDGPU_IRQ_STATE_DISABLE:
1120 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1121 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1122 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1123 break;
1124 case AMDGPU_IRQ_STATE_ENABLE:
1125 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1126 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1127 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1128 break;
1129 default:
1130 break;
1131 }
1132 break;
1133 default:
1134 break;
1135 }
1136 return 0;
1137}
1138
1139static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1140 struct amdgpu_irq_src *source,
1141 struct amdgpu_iv_entry *entry)
1142{
1143 u8 instance_id, queue_id;
1144
1145 instance_id = (entry->ring_id & 0x3) >> 0;
1146 queue_id = (entry->ring_id & 0xc) >> 2;
1147 DRM_DEBUG("IH: SDMA trap\n");
1148 switch (instance_id) {
1149 case 0:
1150 switch (queue_id) {
1151 case 0:
1152 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1153 break;
1154 case 1:
1155 /* XXX compute */
1156 break;
1157 case 2:
1158 /* XXX compute */
1159 break;
1160 }
1161 break;
1162 case 1:
1163 switch (queue_id) {
1164 case 0:
1165 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1166 break;
1167 case 1:
1168 /* XXX compute */
1169 break;
1170 case 2:
1171 /* XXX compute */
1172 break;
1173 }
1174 break;
1175 }
1176
1177 return 0;
1178}
1179
1180static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1181 struct amdgpu_irq_src *source,
1182 struct amdgpu_iv_entry *entry)
1183{
1184 u8 instance_id;
1185
1186 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1187 instance_id = (entry->ring_id & 0x3) >> 0;
1188 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1189 return 0;
1190}
1191
1192static int cik_sdma_set_clockgating_state(void *handle,
1193 enum amd_clockgating_state state)
1194{
1195 bool gate = false;
1196 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1197
1198 if (state == AMD_CG_STATE_GATE)
1199 gate = true;
1200
1201 cik_enable_sdma_mgcg(adev, gate);
1202 cik_enable_sdma_mgls(adev, gate);
1203
1204 return 0;
1205}
1206
1207static int cik_sdma_set_powergating_state(void *handle,
1208 enum amd_powergating_state state)
1209{
1210 return 0;
1211}
1212
1213static const struct amd_ip_funcs cik_sdma_ip_funcs = {
1214 .name = "cik_sdma",
1215 .early_init = cik_sdma_early_init,
1216 .sw_init = cik_sdma_sw_init,
1217 .sw_fini = cik_sdma_sw_fini,
1218 .hw_init = cik_sdma_hw_init,
1219 .hw_fini = cik_sdma_hw_fini,
1220 .suspend = cik_sdma_suspend,
1221 .resume = cik_sdma_resume,
1222 .is_idle = cik_sdma_is_idle,
1223 .wait_for_idle = cik_sdma_wait_for_idle,
1224 .soft_reset = cik_sdma_soft_reset,
1225 .set_clockgating_state = cik_sdma_set_clockgating_state,
1226 .set_powergating_state = cik_sdma_set_powergating_state,
1227};
1228
1229static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1230 .type = AMDGPU_RING_TYPE_SDMA,
1231 .align_mask = 0xf,
1232 .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),
1233 .support_64bit_ptrs = false,
1234 .get_rptr = cik_sdma_ring_get_rptr,
1235 .get_wptr = cik_sdma_ring_get_wptr,
1236 .set_wptr = cik_sdma_ring_set_wptr,
1237 .emit_frame_size =
1238 6 + /* cik_sdma_ring_emit_hdp_flush */
1239 3 + /* hdp invalidate */
1240 6 + /* cik_sdma_ring_emit_pipeline_sync */
1241 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
1242 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
1243 .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
1244 .emit_ib = cik_sdma_ring_emit_ib,
1245 .emit_fence = cik_sdma_ring_emit_fence,
1246 .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1247 .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1248 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1249 .test_ring = cik_sdma_ring_test_ring,
1250 .test_ib = cik_sdma_ring_test_ib,
1251 .insert_nop = cik_sdma_ring_insert_nop,
1252 .pad_ib = cik_sdma_ring_pad_ib,
1253 .emit_wreg = cik_sdma_ring_emit_wreg,
1254};
1255
1256static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1257{
1258 int i;
1259
1260 for (i = 0; i < adev->sdma.num_instances; i++) {
1261 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1262 adev->sdma.instance[i].ring.me = i;
1263 }
1264}
1265
1266static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1267 .set = cik_sdma_set_trap_irq_state,
1268 .process = cik_sdma_process_trap_irq,
1269};
1270
1271static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1272 .process = cik_sdma_process_illegal_inst_irq,
1273};
1274
1275static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1276{
1277 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1278 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1279 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1280}
1281
1282/**
1283 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1284 *
1285 * @ib: indirect buffer to copy to
1286 * @src_offset: src GPU address
1287 * @dst_offset: dst GPU address
1288 * @byte_count: number of bytes to xfer
1289 * @copy_flags: unused
1290 *
1291 * Copy GPU buffers using the DMA engine (CIK).
1292 * Used by the amdgpu ttm implementation to move pages if
1293 * registered as the asic copy callback.
1294 */
1295static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1296 uint64_t src_offset,
1297 uint64_t dst_offset,
1298 uint32_t byte_count,
1299 uint32_t copy_flags)
1300{
1301 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1302 ib->ptr[ib->length_dw++] = byte_count;
1303 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1304 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1305 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1306 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1307 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1308}
1309
1310/**
1311 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1312 *
1313 * @ib: indirect buffer to fill
1314 * @src_data: value to write to buffer
1315 * @dst_offset: dst GPU address
1316 * @byte_count: number of bytes to xfer
1317 *
1318 * Fill GPU buffers using the DMA engine (CIK).
1319 */
1320static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1321 uint32_t src_data,
1322 uint64_t dst_offset,
1323 uint32_t byte_count)
1324{
1325 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1326 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1327 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1328 ib->ptr[ib->length_dw++] = src_data;
1329 ib->ptr[ib->length_dw++] = byte_count;
1330}
1331
1332static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1333 .copy_max_bytes = 0x1fffff,
1334 .copy_num_dw = 7,
1335 .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1336
1337 .fill_max_bytes = 0x1fffff,
1338 .fill_num_dw = 5,
1339 .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1340};
1341
1342static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1343{
1344 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1345 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1346}
1347
1348static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1349 .copy_pte_num_dw = 7,
1350 .copy_pte = cik_sdma_vm_copy_pte,
1351
1352 .write_pte = cik_sdma_vm_write_pte,
1353 .set_pte_pde = cik_sdma_vm_set_pte_pde,
1354};
1355
1356static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1357{
1358 unsigned i;
1359
1360 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1361 for (i = 0; i < adev->sdma.num_instances; i++) {
1362 adev->vm_manager.vm_pte_scheds[i] =
1363 &adev->sdma.instance[i].ring.sched;
1364 }
1365 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1366}
1367
1368const struct amdgpu_ip_block_version cik_sdma_ip_block =
1369{
1370 .type = AMD_IP_BLOCK_TYPE_SDMA,
1371 .major = 2,
1372 .minor = 0,
1373 .rev = 0,
1374 .funcs = &cik_sdma_ip_funcs,
1375};
1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include <linux/firmware.h>
26#include <linux/module.h>
27
28#include "amdgpu.h"
29#include "amdgpu_ucode.h"
30#include "amdgpu_trace.h"
31#include "cikd.h"
32#include "cik.h"
33
34#include "bif/bif_4_1_d.h"
35#include "bif/bif_4_1_sh_mask.h"
36
37#include "gca/gfx_7_2_d.h"
38#include "gca/gfx_7_2_enum.h"
39#include "gca/gfx_7_2_sh_mask.h"
40
41#include "gmc/gmc_7_1_d.h"
42#include "gmc/gmc_7_1_sh_mask.h"
43
44#include "oss/oss_2_0_d.h"
45#include "oss/oss_2_0_sh_mask.h"
46
47static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
48{
49 SDMA0_REGISTER_OFFSET,
50 SDMA1_REGISTER_OFFSET
51};
52
53static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
54static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
55static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
56static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
57static int cik_sdma_soft_reset(void *handle);
58
59MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin");
60MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin");
61MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin");
62MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin");
63MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin");
64MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin");
65MODULE_FIRMWARE("amdgpu/kabini_sdma.bin");
66MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin");
67MODULE_FIRMWARE("amdgpu/mullins_sdma.bin");
68MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin");
69
70u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
71
72
73static void cik_sdma_free_microcode(struct amdgpu_device *adev)
74{
75 int i;
76 for (i = 0; i < adev->sdma.num_instances; i++) {
77 release_firmware(adev->sdma.instance[i].fw);
78 adev->sdma.instance[i].fw = NULL;
79 }
80}
81
82/*
83 * sDMA - System DMA
84 * Starting with CIK, the GPU has new asynchronous
85 * DMA engines. These engines are used for compute
86 * and gfx. There are two DMA engines (SDMA0, SDMA1)
87 * and each one supports 1 ring buffer used for gfx
88 * and 2 queues used for compute.
89 *
90 * The programming model is very similar to the CP
91 * (ring buffer, IBs, etc.), but sDMA has it's own
92 * packet format that is different from the PM4 format
93 * used by the CP. sDMA supports copying data, writing
94 * embedded data, solid fills, and a number of other
95 * things. It also has support for tiling/detiling of
96 * buffers.
97 */
98
99/**
100 * cik_sdma_init_microcode - load ucode images from disk
101 *
102 * @adev: amdgpu_device pointer
103 *
104 * Use the firmware interface to load the ucode images into
105 * the driver (not loaded into hw).
106 * Returns 0 on success, error on failure.
107 */
108static int cik_sdma_init_microcode(struct amdgpu_device *adev)
109{
110 const char *chip_name;
111 char fw_name[30];
112 int err = 0, i;
113
114 DRM_DEBUG("\n");
115
116 switch (adev->asic_type) {
117 case CHIP_BONAIRE:
118 chip_name = "bonaire";
119 break;
120 case CHIP_HAWAII:
121 chip_name = "hawaii";
122 break;
123 case CHIP_KAVERI:
124 chip_name = "kaveri";
125 break;
126 case CHIP_KABINI:
127 chip_name = "kabini";
128 break;
129 case CHIP_MULLINS:
130 chip_name = "mullins";
131 break;
132 default: BUG();
133 }
134
135 for (i = 0; i < adev->sdma.num_instances; i++) {
136 if (i == 0)
137 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
138 else
139 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
140 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
141 if (err)
142 goto out;
143 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
144 }
145out:
146 if (err) {
147 pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name);
148 for (i = 0; i < adev->sdma.num_instances; i++) {
149 release_firmware(adev->sdma.instance[i].fw);
150 adev->sdma.instance[i].fw = NULL;
151 }
152 }
153 return err;
154}
155
156/**
157 * cik_sdma_ring_get_rptr - get the current read pointer
158 *
159 * @ring: amdgpu ring pointer
160 *
161 * Get the current rptr from the hardware (CIK+).
162 */
163static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
164{
165 u32 rptr;
166
167 rptr = *ring->rptr_cpu_addr;
168
169 return (rptr & 0x3fffc) >> 2;
170}
171
172/**
173 * cik_sdma_ring_get_wptr - get the current write pointer
174 *
175 * @ring: amdgpu ring pointer
176 *
177 * Get the current wptr from the hardware (CIK+).
178 */
179static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
180{
181 struct amdgpu_device *adev = ring->adev;
182
183 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
184}
185
186/**
187 * cik_sdma_ring_set_wptr - commit the write pointer
188 *
189 * @ring: amdgpu ring pointer
190 *
191 * Write the wptr back to the hardware (CIK+).
192 */
193static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
194{
195 struct amdgpu_device *adev = ring->adev;
196
197 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
198 (ring->wptr << 2) & 0x3fffc);
199}
200
201static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
202{
203 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
204 int i;
205
206 for (i = 0; i < count; i++)
207 if (sdma && sdma->burst_nop && (i == 0))
208 amdgpu_ring_write(ring, ring->funcs->nop |
209 SDMA_NOP_COUNT(count - 1));
210 else
211 amdgpu_ring_write(ring, ring->funcs->nop);
212}
213
214/**
215 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
216 *
217 * @ring: amdgpu ring pointer
218 * @job: job to retrive vmid from
219 * @ib: IB object to schedule
220 * @flags: unused
221 *
222 * Schedule an IB in the DMA ring (CIK).
223 */
224static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
225 struct amdgpu_job *job,
226 struct amdgpu_ib *ib,
227 uint32_t flags)
228{
229 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
230 u32 extra_bits = vmid & 0xf;
231
232 /* IB packet must end on a 8 DW boundary */
233 cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7);
234
235 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
236 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
237 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
238 amdgpu_ring_write(ring, ib->length_dw);
239
240}
241
242/**
243 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
244 *
245 * @ring: amdgpu ring pointer
246 *
247 * Emit an hdp flush packet on the requested DMA ring.
248 */
249static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
250{
251 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
252 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
253 u32 ref_and_mask;
254
255 if (ring->me == 0)
256 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
257 else
258 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
259
260 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
261 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
262 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
263 amdgpu_ring_write(ring, ref_and_mask); /* reference */
264 amdgpu_ring_write(ring, ref_and_mask); /* mask */
265 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
266}
267
268/**
269 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
270 *
271 * @ring: amdgpu ring pointer
272 * @addr: address
273 * @seq: sequence number
274 * @flags: fence related flags
275 *
276 * Add a DMA fence packet to the ring to write
277 * the fence seq number and DMA trap packet to generate
278 * an interrupt if needed (CIK).
279 */
280static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
281 unsigned flags)
282{
283 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
284 /* write the fence */
285 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
286 amdgpu_ring_write(ring, lower_32_bits(addr));
287 amdgpu_ring_write(ring, upper_32_bits(addr));
288 amdgpu_ring_write(ring, lower_32_bits(seq));
289
290 /* optionally write high bits as well */
291 if (write64bit) {
292 addr += 4;
293 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
294 amdgpu_ring_write(ring, lower_32_bits(addr));
295 amdgpu_ring_write(ring, upper_32_bits(addr));
296 amdgpu_ring_write(ring, upper_32_bits(seq));
297 }
298
299 /* generate an interrupt */
300 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
301}
302
303/**
304 * cik_sdma_gfx_stop - stop the gfx async dma engines
305 *
306 * @adev: amdgpu_device pointer
307 *
308 * Stop the gfx async dma ring buffers (CIK).
309 */
310static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
311{
312 u32 rb_cntl;
313 int i;
314
315 amdgpu_sdma_unset_buffer_funcs_helper(adev);
316
317 for (i = 0; i < adev->sdma.num_instances; i++) {
318 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
319 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
320 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
321 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
322 }
323}
324
325/**
326 * cik_sdma_rlc_stop - stop the compute async dma engines
327 *
328 * @adev: amdgpu_device pointer
329 *
330 * Stop the compute async dma queues (CIK).
331 */
332static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
333{
334 /* XXX todo */
335}
336
337/**
338 * cik_ctx_switch_enable - stop the async dma engines context switch
339 *
340 * @adev: amdgpu_device pointer
341 * @enable: enable/disable the DMA MEs context switch.
342 *
343 * Halt or unhalt the async dma engines context switch (VI).
344 */
345static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
346{
347 u32 f32_cntl, phase_quantum = 0;
348 int i;
349
350 if (amdgpu_sdma_phase_quantum) {
351 unsigned value = amdgpu_sdma_phase_quantum;
352 unsigned unit = 0;
353
354 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
355 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
356 value = (value + 1) >> 1;
357 unit++;
358 }
359 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
360 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
361 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
362 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
363 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
364 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
365 WARN_ONCE(1,
366 "clamping sdma_phase_quantum to %uK clock cycles\n",
367 value << unit);
368 }
369 phase_quantum =
370 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
371 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
372 }
373
374 for (i = 0; i < adev->sdma.num_instances; i++) {
375 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
376 if (enable) {
377 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
378 AUTO_CTXSW_ENABLE, 1);
379 if (amdgpu_sdma_phase_quantum) {
380 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
381 phase_quantum);
382 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
383 phase_quantum);
384 }
385 } else {
386 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
387 AUTO_CTXSW_ENABLE, 0);
388 }
389
390 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
391 }
392}
393
394/**
395 * cik_sdma_enable - stop the async dma engines
396 *
397 * @adev: amdgpu_device pointer
398 * @enable: enable/disable the DMA MEs.
399 *
400 * Halt or unhalt the async dma engines (CIK).
401 */
402static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
403{
404 u32 me_cntl;
405 int i;
406
407 if (!enable) {
408 cik_sdma_gfx_stop(adev);
409 cik_sdma_rlc_stop(adev);
410 }
411
412 for (i = 0; i < adev->sdma.num_instances; i++) {
413 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
414 if (enable)
415 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
416 else
417 me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
418 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
419 }
420}
421
422/**
423 * cik_sdma_gfx_resume - setup and start the async dma engines
424 *
425 * @adev: amdgpu_device pointer
426 *
427 * Set up the gfx DMA ring buffers and enable them (CIK).
428 * Returns 0 for success, error for failure.
429 */
430static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
431{
432 struct amdgpu_ring *ring;
433 u32 rb_cntl, ib_cntl;
434 u32 rb_bufsz;
435 int i, j, r;
436
437 for (i = 0; i < adev->sdma.num_instances; i++) {
438 ring = &adev->sdma.instance[i].ring;
439
440 mutex_lock(&adev->srbm_mutex);
441 for (j = 0; j < 16; j++) {
442 cik_srbm_select(adev, 0, 0, 0, j);
443 /* SDMA GFX */
444 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
445 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
446 /* XXX SDMA RLC - todo */
447 }
448 cik_srbm_select(adev, 0, 0, 0, 0);
449 mutex_unlock(&adev->srbm_mutex);
450
451 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
452 adev->gfx.config.gb_addr_config & 0x70);
453
454 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
455 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
456
457 /* Set ring buffer size in dwords */
458 rb_bufsz = order_base_2(ring->ring_size / 4);
459 rb_cntl = rb_bufsz << 1;
460#ifdef __BIG_ENDIAN
461 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
462 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
463#endif
464 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
465
466 /* Initialize the ring buffer's read and write pointers */
467 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
468 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
469 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
470 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
471
472 /* set the wb address whether it's enabled or not */
473 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
474 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
475 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
476 ((ring->rptr_gpu_addr) & 0xFFFFFFFC));
477
478 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
479
480 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
481 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
482
483 ring->wptr = 0;
484 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
485
486 /* enable DMA RB */
487 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
488 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
489
490 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
491#ifdef __BIG_ENDIAN
492 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
493#endif
494 /* enable DMA IBs */
495 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
496
497 ring->sched.ready = true;
498 }
499
500 cik_sdma_enable(adev, true);
501
502 for (i = 0; i < adev->sdma.num_instances; i++) {
503 ring = &adev->sdma.instance[i].ring;
504 r = amdgpu_ring_test_helper(ring);
505 if (r)
506 return r;
507
508 if (adev->mman.buffer_funcs_ring == ring)
509 amdgpu_ttm_set_buffer_funcs_status(adev, true);
510 }
511
512 return 0;
513}
514
515/**
516 * cik_sdma_rlc_resume - setup and start the async dma engines
517 *
518 * @adev: amdgpu_device pointer
519 *
520 * Set up the compute DMA queues and enable them (CIK).
521 * Returns 0 for success, error for failure.
522 */
523static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
524{
525 /* XXX todo */
526 return 0;
527}
528
529/**
530 * cik_sdma_load_microcode - load the sDMA ME ucode
531 *
532 * @adev: amdgpu_device pointer
533 *
534 * Loads the sDMA0/1 ucode.
535 * Returns 0 for success, -EINVAL if the ucode is not available.
536 */
537static int cik_sdma_load_microcode(struct amdgpu_device *adev)
538{
539 const struct sdma_firmware_header_v1_0 *hdr;
540 const __le32 *fw_data;
541 u32 fw_size;
542 int i, j;
543
544 /* halt the MEs */
545 cik_sdma_enable(adev, false);
546
547 for (i = 0; i < adev->sdma.num_instances; i++) {
548 if (!adev->sdma.instance[i].fw)
549 return -EINVAL;
550 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
551 amdgpu_ucode_print_sdma_hdr(&hdr->header);
552 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
553 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
554 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
555 if (adev->sdma.instance[i].feature_version >= 20)
556 adev->sdma.instance[i].burst_nop = true;
557 fw_data = (const __le32 *)
558 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
559 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
560 for (j = 0; j < fw_size; j++)
561 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
562 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
563 }
564
565 return 0;
566}
567
568/**
569 * cik_sdma_start - setup and start the async dma engines
570 *
571 * @adev: amdgpu_device pointer
572 *
573 * Set up the DMA engines and enable them (CIK).
574 * Returns 0 for success, error for failure.
575 */
576static int cik_sdma_start(struct amdgpu_device *adev)
577{
578 int r;
579
580 r = cik_sdma_load_microcode(adev);
581 if (r)
582 return r;
583
584 /* halt the engine before programing */
585 cik_sdma_enable(adev, false);
586 /* enable sdma ring preemption */
587 cik_ctx_switch_enable(adev, true);
588
589 /* start the gfx rings and rlc compute queues */
590 r = cik_sdma_gfx_resume(adev);
591 if (r)
592 return r;
593 r = cik_sdma_rlc_resume(adev);
594 if (r)
595 return r;
596
597 return 0;
598}
599
600/**
601 * cik_sdma_ring_test_ring - simple async dma engine test
602 *
603 * @ring: amdgpu_ring structure holding ring information
604 *
605 * Test the DMA engine by writing using it to write an
606 * value to memory. (CIK).
607 * Returns 0 for success, error for failure.
608 */
609static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
610{
611 struct amdgpu_device *adev = ring->adev;
612 unsigned i;
613 unsigned index;
614 int r;
615 u32 tmp;
616 u64 gpu_addr;
617
618 r = amdgpu_device_wb_get(adev, &index);
619 if (r)
620 return r;
621
622 gpu_addr = adev->wb.gpu_addr + (index * 4);
623 tmp = 0xCAFEDEAD;
624 adev->wb.wb[index] = cpu_to_le32(tmp);
625
626 r = amdgpu_ring_alloc(ring, 5);
627 if (r)
628 goto error_free_wb;
629
630 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
631 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
632 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
633 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
634 amdgpu_ring_write(ring, 0xDEADBEEF);
635 amdgpu_ring_commit(ring);
636
637 for (i = 0; i < adev->usec_timeout; i++) {
638 tmp = le32_to_cpu(adev->wb.wb[index]);
639 if (tmp == 0xDEADBEEF)
640 break;
641 udelay(1);
642 }
643
644 if (i >= adev->usec_timeout)
645 r = -ETIMEDOUT;
646
647error_free_wb:
648 amdgpu_device_wb_free(adev, index);
649 return r;
650}
651
652/**
653 * cik_sdma_ring_test_ib - test an IB on the DMA engine
654 *
655 * @ring: amdgpu_ring structure holding ring information
656 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
657 *
658 * Test a simple IB in the DMA ring (CIK).
659 * Returns 0 on success, error on failure.
660 */
661static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
662{
663 struct amdgpu_device *adev = ring->adev;
664 struct amdgpu_ib ib;
665 struct dma_fence *f = NULL;
666 unsigned index;
667 u32 tmp = 0;
668 u64 gpu_addr;
669 long r;
670
671 r = amdgpu_device_wb_get(adev, &index);
672 if (r)
673 return r;
674
675 gpu_addr = adev->wb.gpu_addr + (index * 4);
676 tmp = 0xCAFEDEAD;
677 adev->wb.wb[index] = cpu_to_le32(tmp);
678 memset(&ib, 0, sizeof(ib));
679 r = amdgpu_ib_get(adev, NULL, 256,
680 AMDGPU_IB_POOL_DIRECT, &ib);
681 if (r)
682 goto err0;
683
684 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
685 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
686 ib.ptr[1] = lower_32_bits(gpu_addr);
687 ib.ptr[2] = upper_32_bits(gpu_addr);
688 ib.ptr[3] = 1;
689 ib.ptr[4] = 0xDEADBEEF;
690 ib.length_dw = 5;
691 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
692 if (r)
693 goto err1;
694
695 r = dma_fence_wait_timeout(f, false, timeout);
696 if (r == 0) {
697 r = -ETIMEDOUT;
698 goto err1;
699 } else if (r < 0) {
700 goto err1;
701 }
702 tmp = le32_to_cpu(adev->wb.wb[index]);
703 if (tmp == 0xDEADBEEF)
704 r = 0;
705 else
706 r = -EINVAL;
707
708err1:
709 amdgpu_ib_free(adev, &ib, NULL);
710 dma_fence_put(f);
711err0:
712 amdgpu_device_wb_free(adev, index);
713 return r;
714}
715
716/**
717 * cik_sdma_vm_copy_pte - update PTEs by copying them from the GART
718 *
719 * @ib: indirect buffer to fill with commands
720 * @pe: addr of the page entry
721 * @src: src addr to copy from
722 * @count: number of page entries to update
723 *
724 * Update PTEs by copying them from the GART using sDMA (CIK).
725 */
726static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
727 uint64_t pe, uint64_t src,
728 unsigned count)
729{
730 unsigned bytes = count * 8;
731
732 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
733 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
734 ib->ptr[ib->length_dw++] = bytes;
735 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
736 ib->ptr[ib->length_dw++] = lower_32_bits(src);
737 ib->ptr[ib->length_dw++] = upper_32_bits(src);
738 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
739 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
740}
741
742/**
743 * cik_sdma_vm_write_pte - update PTEs by writing them manually
744 *
745 * @ib: indirect buffer to fill with commands
746 * @pe: addr of the page entry
747 * @value: dst addr to write into pe
748 * @count: number of page entries to update
749 * @incr: increase next addr by incr bytes
750 *
751 * Update PTEs by writing them manually using sDMA (CIK).
752 */
753static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
754 uint64_t value, unsigned count,
755 uint32_t incr)
756{
757 unsigned ndw = count * 2;
758
759 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
760 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
761 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
762 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
763 ib->ptr[ib->length_dw++] = ndw;
764 for (; ndw > 0; ndw -= 2) {
765 ib->ptr[ib->length_dw++] = lower_32_bits(value);
766 ib->ptr[ib->length_dw++] = upper_32_bits(value);
767 value += incr;
768 }
769}
770
771/**
772 * cik_sdma_vm_set_pte_pde - update the page tables using sDMA
773 *
774 * @ib: indirect buffer to fill with commands
775 * @pe: addr of the page entry
776 * @addr: dst addr to write into pe
777 * @count: number of page entries to update
778 * @incr: increase next addr by incr bytes
779 * @flags: access flags
780 *
781 * Update the page tables using sDMA (CIK).
782 */
783static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
784 uint64_t addr, unsigned count,
785 uint32_t incr, uint64_t flags)
786{
787 /* for physically contiguous pages (vram) */
788 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
789 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
790 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
791 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
792 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
793 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
794 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
795 ib->ptr[ib->length_dw++] = incr; /* increment size */
796 ib->ptr[ib->length_dw++] = 0;
797 ib->ptr[ib->length_dw++] = count; /* number of entries */
798}
799
800/**
801 * cik_sdma_ring_pad_ib - pad the IB to the required number of dw
802 *
803 * @ring: amdgpu_ring structure holding ring information
804 * @ib: indirect buffer to fill with padding
805 *
806 */
807static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
808{
809 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
810 u32 pad_count;
811 int i;
812
813 pad_count = (-ib->length_dw) & 7;
814 for (i = 0; i < pad_count; i++)
815 if (sdma && sdma->burst_nop && (i == 0))
816 ib->ptr[ib->length_dw++] =
817 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
818 SDMA_NOP_COUNT(pad_count - 1);
819 else
820 ib->ptr[ib->length_dw++] =
821 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
822}
823
824/**
825 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
826 *
827 * @ring: amdgpu_ring pointer
828 *
829 * Make sure all previous operations are completed (CIK).
830 */
831static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
832{
833 uint32_t seq = ring->fence_drv.sync_seq;
834 uint64_t addr = ring->fence_drv.gpu_addr;
835
836 /* wait for idle */
837 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
838 SDMA_POLL_REG_MEM_EXTRA_OP(0) |
839 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
840 SDMA_POLL_REG_MEM_EXTRA_M));
841 amdgpu_ring_write(ring, addr & 0xfffffffc);
842 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
843 amdgpu_ring_write(ring, seq); /* reference */
844 amdgpu_ring_write(ring, 0xffffffff); /* mask */
845 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
846}
847
848/**
849 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
850 *
851 * @ring: amdgpu_ring pointer
852 * @vmid: vmid number to use
853 * @pd_addr: address
854 *
855 * Update the page table base and flush the VM TLB
856 * using sDMA (CIK).
857 */
858static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
859 unsigned vmid, uint64_t pd_addr)
860{
861 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
862 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
863
864 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
865
866 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
867 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
868 amdgpu_ring_write(ring, 0);
869 amdgpu_ring_write(ring, 0); /* reference */
870 amdgpu_ring_write(ring, 0); /* mask */
871 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
872}
873
874static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
875 uint32_t reg, uint32_t val)
876{
877 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
878 amdgpu_ring_write(ring, reg);
879 amdgpu_ring_write(ring, val);
880}
881
882static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
883 bool enable)
884{
885 u32 orig, data;
886
887 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
888 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
889 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
890 } else {
891 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
892 data |= 0xff000000;
893 if (data != orig)
894 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
895
896 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
897 data |= 0xff000000;
898 if (data != orig)
899 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
900 }
901}
902
903static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
904 bool enable)
905{
906 u32 orig, data;
907
908 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
909 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
910 data |= 0x100;
911 if (orig != data)
912 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
913
914 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
915 data |= 0x100;
916 if (orig != data)
917 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
918 } else {
919 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
920 data &= ~0x100;
921 if (orig != data)
922 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
923
924 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
925 data &= ~0x100;
926 if (orig != data)
927 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
928 }
929}
930
931static int cik_sdma_early_init(void *handle)
932{
933 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
934
935 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
936
937 cik_sdma_set_ring_funcs(adev);
938 cik_sdma_set_irq_funcs(adev);
939 cik_sdma_set_buffer_funcs(adev);
940 cik_sdma_set_vm_pte_funcs(adev);
941
942 return 0;
943}
944
945static int cik_sdma_sw_init(void *handle)
946{
947 struct amdgpu_ring *ring;
948 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
949 int r, i;
950
951 r = cik_sdma_init_microcode(adev);
952 if (r) {
953 DRM_ERROR("Failed to load sdma firmware!\n");
954 return r;
955 }
956
957 /* SDMA trap event */
958 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224,
959 &adev->sdma.trap_irq);
960 if (r)
961 return r;
962
963 /* SDMA Privileged inst */
964 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
965 &adev->sdma.illegal_inst_irq);
966 if (r)
967 return r;
968
969 /* SDMA Privileged inst */
970 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247,
971 &adev->sdma.illegal_inst_irq);
972 if (r)
973 return r;
974
975 for (i = 0; i < adev->sdma.num_instances; i++) {
976 ring = &adev->sdma.instance[i].ring;
977 ring->ring_obj = NULL;
978 sprintf(ring->name, "sdma%d", i);
979 r = amdgpu_ring_init(adev, ring, 1024,
980 &adev->sdma.trap_irq,
981 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
982 AMDGPU_SDMA_IRQ_INSTANCE1,
983 AMDGPU_RING_PRIO_DEFAULT, NULL);
984 if (r)
985 return r;
986 }
987
988 return r;
989}
990
991static int cik_sdma_sw_fini(void *handle)
992{
993 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
994 int i;
995
996 for (i = 0; i < adev->sdma.num_instances; i++)
997 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
998
999 cik_sdma_free_microcode(adev);
1000 return 0;
1001}
1002
1003static int cik_sdma_hw_init(void *handle)
1004{
1005 int r;
1006 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1007
1008 r = cik_sdma_start(adev);
1009 if (r)
1010 return r;
1011
1012 return r;
1013}
1014
1015static int cik_sdma_hw_fini(void *handle)
1016{
1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1018
1019 cik_ctx_switch_enable(adev, false);
1020 cik_sdma_enable(adev, false);
1021
1022 return 0;
1023}
1024
1025static int cik_sdma_suspend(void *handle)
1026{
1027 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1028
1029 return cik_sdma_hw_fini(adev);
1030}
1031
1032static int cik_sdma_resume(void *handle)
1033{
1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035
1036 cik_sdma_soft_reset(handle);
1037
1038 return cik_sdma_hw_init(adev);
1039}
1040
1041static bool cik_sdma_is_idle(void *handle)
1042{
1043 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1044 u32 tmp = RREG32(mmSRBM_STATUS2);
1045
1046 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1047 SRBM_STATUS2__SDMA1_BUSY_MASK))
1048 return false;
1049
1050 return true;
1051}
1052
1053static int cik_sdma_wait_for_idle(void *handle)
1054{
1055 unsigned i;
1056 u32 tmp;
1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1058
1059 for (i = 0; i < adev->usec_timeout; i++) {
1060 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1061 SRBM_STATUS2__SDMA1_BUSY_MASK);
1062
1063 if (!tmp)
1064 return 0;
1065 udelay(1);
1066 }
1067 return -ETIMEDOUT;
1068}
1069
1070static int cik_sdma_soft_reset(void *handle)
1071{
1072 u32 srbm_soft_reset = 0;
1073 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1074 u32 tmp;
1075
1076 /* sdma0 */
1077 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1078 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1079 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1080 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1081
1082 /* sdma1 */
1083 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1084 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1085 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1086 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1087
1088 if (srbm_soft_reset) {
1089 tmp = RREG32(mmSRBM_SOFT_RESET);
1090 tmp |= srbm_soft_reset;
1091 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1092 WREG32(mmSRBM_SOFT_RESET, tmp);
1093 tmp = RREG32(mmSRBM_SOFT_RESET);
1094
1095 udelay(50);
1096
1097 tmp &= ~srbm_soft_reset;
1098 WREG32(mmSRBM_SOFT_RESET, tmp);
1099 tmp = RREG32(mmSRBM_SOFT_RESET);
1100
1101 /* Wait a little for things to settle down */
1102 udelay(50);
1103 }
1104
1105 return 0;
1106}
1107
1108static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1109 struct amdgpu_irq_src *src,
1110 unsigned type,
1111 enum amdgpu_interrupt_state state)
1112{
1113 u32 sdma_cntl;
1114
1115 switch (type) {
1116 case AMDGPU_SDMA_IRQ_INSTANCE0:
1117 switch (state) {
1118 case AMDGPU_IRQ_STATE_DISABLE:
1119 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1120 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1121 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1122 break;
1123 case AMDGPU_IRQ_STATE_ENABLE:
1124 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1125 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1126 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1127 break;
1128 default:
1129 break;
1130 }
1131 break;
1132 case AMDGPU_SDMA_IRQ_INSTANCE1:
1133 switch (state) {
1134 case AMDGPU_IRQ_STATE_DISABLE:
1135 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1136 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1137 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1138 break;
1139 case AMDGPU_IRQ_STATE_ENABLE:
1140 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1141 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1142 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1143 break;
1144 default:
1145 break;
1146 }
1147 break;
1148 default:
1149 break;
1150 }
1151 return 0;
1152}
1153
1154static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1155 struct amdgpu_irq_src *source,
1156 struct amdgpu_iv_entry *entry)
1157{
1158 u8 instance_id, queue_id;
1159
1160 instance_id = (entry->ring_id & 0x3) >> 0;
1161 queue_id = (entry->ring_id & 0xc) >> 2;
1162 DRM_DEBUG("IH: SDMA trap\n");
1163 switch (instance_id) {
1164 case 0:
1165 switch (queue_id) {
1166 case 0:
1167 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1168 break;
1169 case 1:
1170 /* XXX compute */
1171 break;
1172 case 2:
1173 /* XXX compute */
1174 break;
1175 }
1176 break;
1177 case 1:
1178 switch (queue_id) {
1179 case 0:
1180 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1181 break;
1182 case 1:
1183 /* XXX compute */
1184 break;
1185 case 2:
1186 /* XXX compute */
1187 break;
1188 }
1189 break;
1190 }
1191
1192 return 0;
1193}
1194
1195static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1196 struct amdgpu_irq_src *source,
1197 struct amdgpu_iv_entry *entry)
1198{
1199 u8 instance_id;
1200
1201 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1202 instance_id = (entry->ring_id & 0x3) >> 0;
1203 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1204 return 0;
1205}
1206
1207static int cik_sdma_set_clockgating_state(void *handle,
1208 enum amd_clockgating_state state)
1209{
1210 bool gate = false;
1211 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1212
1213 if (state == AMD_CG_STATE_GATE)
1214 gate = true;
1215
1216 cik_enable_sdma_mgcg(adev, gate);
1217 cik_enable_sdma_mgls(adev, gate);
1218
1219 return 0;
1220}
1221
1222static int cik_sdma_set_powergating_state(void *handle,
1223 enum amd_powergating_state state)
1224{
1225 return 0;
1226}
1227
1228static const struct amd_ip_funcs cik_sdma_ip_funcs = {
1229 .name = "cik_sdma",
1230 .early_init = cik_sdma_early_init,
1231 .late_init = NULL,
1232 .sw_init = cik_sdma_sw_init,
1233 .sw_fini = cik_sdma_sw_fini,
1234 .hw_init = cik_sdma_hw_init,
1235 .hw_fini = cik_sdma_hw_fini,
1236 .suspend = cik_sdma_suspend,
1237 .resume = cik_sdma_resume,
1238 .is_idle = cik_sdma_is_idle,
1239 .wait_for_idle = cik_sdma_wait_for_idle,
1240 .soft_reset = cik_sdma_soft_reset,
1241 .set_clockgating_state = cik_sdma_set_clockgating_state,
1242 .set_powergating_state = cik_sdma_set_powergating_state,
1243};
1244
1245static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1246 .type = AMDGPU_RING_TYPE_SDMA,
1247 .align_mask = 0xf,
1248 .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),
1249 .support_64bit_ptrs = false,
1250 .get_rptr = cik_sdma_ring_get_rptr,
1251 .get_wptr = cik_sdma_ring_get_wptr,
1252 .set_wptr = cik_sdma_ring_set_wptr,
1253 .emit_frame_size =
1254 6 + /* cik_sdma_ring_emit_hdp_flush */
1255 3 + /* hdp invalidate */
1256 6 + /* cik_sdma_ring_emit_pipeline_sync */
1257 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
1258 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
1259 .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
1260 .emit_ib = cik_sdma_ring_emit_ib,
1261 .emit_fence = cik_sdma_ring_emit_fence,
1262 .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1263 .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1264 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1265 .test_ring = cik_sdma_ring_test_ring,
1266 .test_ib = cik_sdma_ring_test_ib,
1267 .insert_nop = cik_sdma_ring_insert_nop,
1268 .pad_ib = cik_sdma_ring_pad_ib,
1269 .emit_wreg = cik_sdma_ring_emit_wreg,
1270};
1271
1272static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1273{
1274 int i;
1275
1276 for (i = 0; i < adev->sdma.num_instances; i++) {
1277 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1278 adev->sdma.instance[i].ring.me = i;
1279 }
1280}
1281
1282static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1283 .set = cik_sdma_set_trap_irq_state,
1284 .process = cik_sdma_process_trap_irq,
1285};
1286
1287static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1288 .process = cik_sdma_process_illegal_inst_irq,
1289};
1290
1291static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1292{
1293 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1294 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1295 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1296}
1297
1298/**
1299 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1300 *
1301 * @ib: indirect buffer to copy to
1302 * @src_offset: src GPU address
1303 * @dst_offset: dst GPU address
1304 * @byte_count: number of bytes to xfer
1305 * @tmz: is this a secure operation
1306 *
1307 * Copy GPU buffers using the DMA engine (CIK).
1308 * Used by the amdgpu ttm implementation to move pages if
1309 * registered as the asic copy callback.
1310 */
1311static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1312 uint64_t src_offset,
1313 uint64_t dst_offset,
1314 uint32_t byte_count,
1315 bool tmz)
1316{
1317 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1318 ib->ptr[ib->length_dw++] = byte_count;
1319 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1320 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1321 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1322 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1323 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1324}
1325
1326/**
1327 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1328 *
1329 * @ib: indirect buffer to fill
1330 * @src_data: value to write to buffer
1331 * @dst_offset: dst GPU address
1332 * @byte_count: number of bytes to xfer
1333 *
1334 * Fill GPU buffers using the DMA engine (CIK).
1335 */
1336static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1337 uint32_t src_data,
1338 uint64_t dst_offset,
1339 uint32_t byte_count)
1340{
1341 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1342 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1343 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1344 ib->ptr[ib->length_dw++] = src_data;
1345 ib->ptr[ib->length_dw++] = byte_count;
1346}
1347
1348static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1349 .copy_max_bytes = 0x1fffff,
1350 .copy_num_dw = 7,
1351 .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1352
1353 .fill_max_bytes = 0x1fffff,
1354 .fill_num_dw = 5,
1355 .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1356};
1357
1358static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1359{
1360 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1361 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1362}
1363
1364static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1365 .copy_pte_num_dw = 7,
1366 .copy_pte = cik_sdma_vm_copy_pte,
1367
1368 .write_pte = cik_sdma_vm_write_pte,
1369 .set_pte_pde = cik_sdma_vm_set_pte_pde,
1370};
1371
1372static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1373{
1374 unsigned i;
1375
1376 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1377 for (i = 0; i < adev->sdma.num_instances; i++) {
1378 adev->vm_manager.vm_pte_scheds[i] =
1379 &adev->sdma.instance[i].ring.sched;
1380 }
1381 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1382}
1383
1384const struct amdgpu_ip_block_version cik_sdma_ip_block =
1385{
1386 .type = AMD_IP_BLOCK_TYPE_SDMA,
1387 .major = 2,
1388 .minor = 0,
1389 .rev = 0,
1390 .funcs = &cik_sdma_ip_funcs,
1391};