Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * TI DaVinci GPIO Support
4 *
5 * Copyright (c) 2006-2007 David Brownell
6 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7 */
8
9#include <linux/gpio/driver.h>
10#include <linux/errno.h>
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/module.h>
18#include <linux/pinctrl/consumer.h>
19#include <linux/platform_device.h>
20#include <linux/property.h>
21#include <linux/irqchip/chained_irq.h>
22#include <linux/spinlock.h>
23#include <linux/pm_runtime.h>
24
25#define MAX_REGS_BANKS 5
26#define MAX_INT_PER_BANK 32
27
28struct davinci_gpio_regs {
29 u32 dir;
30 u32 out_data;
31 u32 set_data;
32 u32 clr_data;
33 u32 in_data;
34 u32 set_rising;
35 u32 clr_rising;
36 u32 set_falling;
37 u32 clr_falling;
38 u32 intstat;
39};
40
41typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
42
43#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
44
45static void __iomem *gpio_base;
46static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
47
48struct davinci_gpio_irq_data {
49 void __iomem *regs;
50 struct davinci_gpio_controller *chip;
51 int bank_num;
52};
53
54struct davinci_gpio_controller {
55 struct gpio_chip chip;
56 struct irq_domain *irq_domain;
57 /* Serialize access to GPIO registers */
58 spinlock_t lock;
59 void __iomem *regs[MAX_REGS_BANKS];
60 int gpio_unbanked;
61 int irqs[MAX_INT_PER_BANK];
62 struct davinci_gpio_regs context[MAX_REGS_BANKS];
63 u32 binten_context;
64};
65
66static inline u32 __gpio_mask(unsigned gpio)
67{
68 return 1 << (gpio % 32);
69}
70
71static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
72{
73 struct davinci_gpio_regs __iomem *g;
74
75 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
76
77 return g;
78}
79
80static int davinci_gpio_irq_setup(struct platform_device *pdev);
81
82/*--------------------------------------------------------------------------*/
83
84/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
85static inline int __davinci_direction(struct gpio_chip *chip,
86 unsigned offset, bool out, int value)
87{
88 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
89 struct davinci_gpio_regs __iomem *g;
90 unsigned long flags;
91 u32 temp;
92 int bank = offset / 32;
93 u32 mask = __gpio_mask(offset);
94
95 g = d->regs[bank];
96 spin_lock_irqsave(&d->lock, flags);
97 temp = readl_relaxed(&g->dir);
98 if (out) {
99 temp &= ~mask;
100 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
101 } else {
102 temp |= mask;
103 }
104 writel_relaxed(temp, &g->dir);
105 spin_unlock_irqrestore(&d->lock, flags);
106
107 return 0;
108}
109
110static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
111{
112 return __davinci_direction(chip, offset, false, 0);
113}
114
115static int
116davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
117{
118 return __davinci_direction(chip, offset, true, value);
119}
120
121/*
122 * Read the pin's value (works even if it's set up as output);
123 * returns zero/nonzero.
124 *
125 * Note that changes are synched to the GPIO clock, so reading values back
126 * right after you've set them may give old values.
127 */
128static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
129{
130 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
131 struct davinci_gpio_regs __iomem *g;
132 int bank = offset / 32;
133
134 g = d->regs[bank];
135
136 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
137}
138
139/*
140 * Assuming the pin is muxed as a gpio output, set its output value.
141 */
142static void
143davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
144{
145 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
146 struct davinci_gpio_regs __iomem *g;
147 int bank = offset / 32;
148
149 g = d->regs[bank];
150
151 writel_relaxed(__gpio_mask(offset),
152 value ? &g->set_data : &g->clr_data);
153}
154
155static int davinci_gpio_probe(struct platform_device *pdev)
156{
157 int bank, i, ret = 0;
158 unsigned int ngpio, nbank, nirq, gpio_unbanked;
159 struct davinci_gpio_controller *chips;
160 struct device *dev = &pdev->dev;
161
162 /*
163 * The gpio banks conceptually expose a segmented bitmap,
164 * and "ngpio" is one more than the largest zero-based
165 * bit index that's valid.
166 */
167 ret = device_property_read_u32(dev, "ti,ngpio", &ngpio);
168 if (ret)
169 return dev_err_probe(dev, ret, "Failed to get the number of GPIOs\n");
170 if (ngpio == 0)
171 return dev_err_probe(dev, -EINVAL, "How many GPIOs?\n");
172
173 /*
174 * If there are unbanked interrupts then the number of
175 * interrupts is equal to number of gpios else all are banked so
176 * number of interrupts is equal to number of banks(each with 16 gpios)
177 */
178 ret = device_property_read_u32(dev, "ti,davinci-gpio-unbanked",
179 &gpio_unbanked);
180 if (ret)
181 return dev_err_probe(dev, ret, "Failed to get the unbanked GPIOs property\n");
182
183 if (gpio_unbanked)
184 nirq = gpio_unbanked;
185 else
186 nirq = DIV_ROUND_UP(ngpio, 16);
187
188 if (nirq > MAX_INT_PER_BANK) {
189 dev_err(dev, "Too many IRQs!\n");
190 return -EINVAL;
191 }
192
193 chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
194 if (!chips)
195 return -ENOMEM;
196
197 gpio_base = devm_platform_ioremap_resource(pdev, 0);
198 if (IS_ERR(gpio_base))
199 return PTR_ERR(gpio_base);
200
201 for (i = 0; i < nirq; i++) {
202 chips->irqs[i] = platform_get_irq(pdev, i);
203 if (chips->irqs[i] < 0)
204 return chips->irqs[i];
205 }
206
207 chips->chip.label = dev_name(dev);
208
209 chips->chip.direction_input = davinci_direction_in;
210 chips->chip.get = davinci_gpio_get;
211 chips->chip.direction_output = davinci_direction_out;
212 chips->chip.set = davinci_gpio_set;
213
214 chips->chip.ngpio = ngpio;
215 chips->chip.base = -1;
216
217#ifdef CONFIG_OF_GPIO
218 chips->chip.parent = dev;
219 chips->chip.request = gpiochip_generic_request;
220 chips->chip.free = gpiochip_generic_free;
221#endif
222 spin_lock_init(&chips->lock);
223
224 chips->gpio_unbanked = gpio_unbanked;
225
226 nbank = DIV_ROUND_UP(ngpio, 32);
227 for (bank = 0; bank < nbank; bank++)
228 chips->regs[bank] = gpio_base + offset_array[bank];
229
230 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
231 if (ret)
232 return ret;
233
234 platform_set_drvdata(pdev, chips);
235 ret = davinci_gpio_irq_setup(pdev);
236 if (ret)
237 return ret;
238
239 return 0;
240}
241
242/*--------------------------------------------------------------------------*/
243/*
244 * We expect irqs will normally be set up as input pins, but they can also be
245 * used as output pins ... which is convenient for testing.
246 *
247 * NOTE: The first few GPIOs also have direct INTC hookups in addition
248 * to their GPIOBNK0 irq, with a bit less overhead.
249 *
250 * All those INTC hookups (direct, plus several IRQ banks) can also
251 * serve as EDMA event triggers.
252 */
253
254static void gpio_irq_mask(struct irq_data *d)
255{
256 struct davinci_gpio_regs __iomem *g = irq2regs(d);
257 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
258
259 writel_relaxed(mask, &g->clr_falling);
260 writel_relaxed(mask, &g->clr_rising);
261}
262
263static void gpio_irq_unmask(struct irq_data *d)
264{
265 struct davinci_gpio_regs __iomem *g = irq2regs(d);
266 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
267 unsigned status = irqd_get_trigger_type(d);
268
269 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
270 if (!status)
271 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
272
273 if (status & IRQ_TYPE_EDGE_FALLING)
274 writel_relaxed(mask, &g->set_falling);
275 if (status & IRQ_TYPE_EDGE_RISING)
276 writel_relaxed(mask, &g->set_rising);
277}
278
279static int gpio_irq_type(struct irq_data *d, unsigned trigger)
280{
281 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
282 return -EINVAL;
283
284 return 0;
285}
286
287static struct irq_chip gpio_irqchip = {
288 .name = "GPIO",
289 .irq_unmask = gpio_irq_unmask,
290 .irq_mask = gpio_irq_mask,
291 .irq_set_type = gpio_irq_type,
292 .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE,
293};
294
295static void gpio_irq_handler(struct irq_desc *desc)
296{
297 struct davinci_gpio_regs __iomem *g;
298 u32 mask = 0xffff;
299 int bank_num;
300 struct davinci_gpio_controller *d;
301 struct davinci_gpio_irq_data *irqdata;
302
303 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
304 bank_num = irqdata->bank_num;
305 g = irqdata->regs;
306 d = irqdata->chip;
307
308 /* we only care about one bank */
309 if ((bank_num % 2) == 1)
310 mask <<= 16;
311
312 /* temporarily mask (level sensitive) parent IRQ */
313 chained_irq_enter(irq_desc_get_chip(desc), desc);
314 while (1) {
315 u32 status;
316 int bit;
317 irq_hw_number_t hw_irq;
318
319 /* ack any irqs */
320 status = readl_relaxed(&g->intstat) & mask;
321 if (!status)
322 break;
323 writel_relaxed(status, &g->intstat);
324
325 /* now demux them to the right lowlevel handler */
326
327 while (status) {
328 bit = __ffs(status);
329 status &= ~BIT(bit);
330 /* Max number of gpios per controller is 144 so
331 * hw_irq will be in [0..143]
332 */
333 hw_irq = (bank_num / 2) * 32 + bit;
334
335 generic_handle_domain_irq(d->irq_domain, hw_irq);
336 }
337 }
338 chained_irq_exit(irq_desc_get_chip(desc), desc);
339 /* now it may re-trigger */
340}
341
342static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
343{
344 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
345
346 if (d->irq_domain)
347 return irq_create_mapping(d->irq_domain, offset);
348 else
349 return -ENXIO;
350}
351
352static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
353{
354 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
355
356 /*
357 * NOTE: we assume for now that only irqs in the first gpio_chip
358 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
359 */
360 if (offset < d->gpio_unbanked)
361 return d->irqs[offset];
362 else
363 return -ENODEV;
364}
365
366static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
367{
368 struct davinci_gpio_controller *d;
369 struct davinci_gpio_regs __iomem *g;
370 u32 mask, i;
371
372 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
373 g = (struct davinci_gpio_regs __iomem *)d->regs[0];
374 for (i = 0; i < MAX_INT_PER_BANK; i++)
375 if (data->irq == d->irqs[i])
376 break;
377
378 if (i == MAX_INT_PER_BANK)
379 return -EINVAL;
380
381 mask = __gpio_mask(i);
382
383 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
384 return -EINVAL;
385
386 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
387 ? &g->set_falling : &g->clr_falling);
388 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
389 ? &g->set_rising : &g->clr_rising);
390
391 return 0;
392}
393
394static int
395davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
396 irq_hw_number_t hw)
397{
398 struct davinci_gpio_controller *chips =
399 (struct davinci_gpio_controller *)d->host_data;
400 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
401
402 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
403 "davinci_gpio");
404 irq_set_irq_type(irq, IRQ_TYPE_NONE);
405 irq_set_chip_data(irq, (__force void *)g);
406 irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
407
408 return 0;
409}
410
411static const struct irq_domain_ops davinci_gpio_irq_ops = {
412 .map = davinci_gpio_irq_map,
413 .xlate = irq_domain_xlate_onetwocell,
414};
415
416static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
417{
418 static struct irq_chip_type gpio_unbanked;
419
420 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
421
422 return &gpio_unbanked.chip;
423};
424
425static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
426{
427 static struct irq_chip gpio_unbanked;
428
429 gpio_unbanked = *irq_get_chip(irq);
430 return &gpio_unbanked;
431};
432
433static const struct of_device_id davinci_gpio_ids[];
434
435/*
436 * NOTE: for suspend/resume, probably best to make a platform_device with
437 * suspend_late/resume_resume calls hooking into results of the set_wake()
438 * calls ... so if no gpios are wakeup events the clock can be disabled,
439 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
440 * (dm6446) can be set appropriately for GPIOV33 pins.
441 */
442
443static int davinci_gpio_irq_setup(struct platform_device *pdev)
444{
445 unsigned gpio, bank;
446 int irq;
447 struct clk *clk;
448 u32 binten = 0;
449 unsigned ngpio;
450 struct device *dev = &pdev->dev;
451 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
452 struct davinci_gpio_regs __iomem *g;
453 struct irq_domain *irq_domain = NULL;
454 struct irq_chip *irq_chip;
455 struct davinci_gpio_irq_data *irqdata;
456 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
457
458 /*
459 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
460 */
461 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
462 if (dev->of_node)
463 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)device_get_match_data(dev);
464
465 ngpio = chips->chip.ngpio;
466
467 clk = devm_clk_get_enabled(dev, "gpio");
468 if (IS_ERR(clk)) {
469 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
470 return PTR_ERR(clk);
471 }
472
473 if (!chips->gpio_unbanked) {
474 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
475 if (irq < 0) {
476 dev_err(dev, "Couldn't allocate IRQ numbers\n");
477 return irq;
478 }
479
480 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
481 &davinci_gpio_irq_ops,
482 chips);
483 if (!irq_domain) {
484 dev_err(dev, "Couldn't register an IRQ domain\n");
485 return -ENODEV;
486 }
487 }
488
489 /*
490 * Arrange gpiod_to_irq() support, handling either direct IRQs or
491 * banked IRQs. Having GPIOs in the first GPIO bank use direct
492 * IRQs, while the others use banked IRQs, would need some setup
493 * tweaks to recognize hardware which can do that.
494 */
495 chips->chip.to_irq = gpio_to_irq_banked;
496 chips->irq_domain = irq_domain;
497
498 /*
499 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
500 * controller only handling trigger modes. We currently assume no
501 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
502 */
503 if (chips->gpio_unbanked) {
504 /* pass "bank 0" GPIO IRQs to AINTC */
505 chips->chip.to_irq = gpio_to_irq_unbanked;
506
507 binten = GENMASK(chips->gpio_unbanked / 16, 0);
508
509 /* AINTC handles mask/unmask; GPIO handles triggering */
510 irq = chips->irqs[0];
511 irq_chip = gpio_get_irq_chip(irq);
512 irq_chip->name = "GPIO-AINTC";
513 irq_chip->irq_set_type = gpio_irq_type_unbanked;
514
515 /* default trigger: both edges */
516 g = chips->regs[0];
517 writel_relaxed(~0, &g->set_falling);
518 writel_relaxed(~0, &g->set_rising);
519
520 /* set the direct IRQs up to use that irqchip */
521 for (gpio = 0; gpio < chips->gpio_unbanked; gpio++) {
522 irq_set_chip(chips->irqs[gpio], irq_chip);
523 irq_set_handler_data(chips->irqs[gpio], chips);
524 irq_set_status_flags(chips->irqs[gpio],
525 IRQ_TYPE_EDGE_BOTH);
526 }
527
528 goto done;
529 }
530
531 /*
532 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
533 * then chain through our own handler.
534 */
535 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
536 /* disabled by default, enabled only as needed
537 * There are register sets for 32 GPIOs. 2 banks of 16
538 * GPIOs are covered by each set of registers hence divide by 2
539 */
540 g = chips->regs[bank / 2];
541 writel_relaxed(~0, &g->clr_falling);
542 writel_relaxed(~0, &g->clr_rising);
543
544 /*
545 * Each chip handles 32 gpios, and each irq bank consists of 16
546 * gpio irqs. Pass the irq bank's corresponding controller to
547 * the chained irq handler.
548 */
549 irqdata = devm_kzalloc(&pdev->dev,
550 sizeof(struct
551 davinci_gpio_irq_data),
552 GFP_KERNEL);
553 if (!irqdata)
554 return -ENOMEM;
555
556 irqdata->regs = g;
557 irqdata->bank_num = bank;
558 irqdata->chip = chips;
559
560 irq_set_chained_handler_and_data(chips->irqs[bank],
561 gpio_irq_handler, irqdata);
562
563 binten |= BIT(bank);
564 }
565
566done:
567 /*
568 * BINTEN -- per-bank interrupt enable. genirq would also let these
569 * bits be set/cleared dynamically.
570 */
571 writel_relaxed(binten, gpio_base + BINTEN);
572
573 return 0;
574}
575
576static void davinci_gpio_save_context(struct davinci_gpio_controller *chips,
577 u32 nbank)
578{
579 struct davinci_gpio_regs __iomem *g;
580 struct davinci_gpio_regs *context;
581 u32 bank;
582 void __iomem *base;
583
584 base = chips->regs[0] - offset_array[0];
585 chips->binten_context = readl_relaxed(base + BINTEN);
586
587 for (bank = 0; bank < nbank; bank++) {
588 g = chips->regs[bank];
589 context = &chips->context[bank];
590 context->dir = readl_relaxed(&g->dir);
591 context->set_data = readl_relaxed(&g->set_data);
592 context->set_rising = readl_relaxed(&g->set_rising);
593 context->set_falling = readl_relaxed(&g->set_falling);
594 }
595
596 /* Clear all interrupt status registers */
597 writel_relaxed(GENMASK(31, 0), &g->intstat);
598}
599
600static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips,
601 u32 nbank)
602{
603 struct davinci_gpio_regs __iomem *g;
604 struct davinci_gpio_regs *context;
605 u32 bank;
606 void __iomem *base;
607
608 base = chips->regs[0] - offset_array[0];
609
610 if (readl_relaxed(base + BINTEN) != chips->binten_context)
611 writel_relaxed(chips->binten_context, base + BINTEN);
612
613 for (bank = 0; bank < nbank; bank++) {
614 g = chips->regs[bank];
615 context = &chips->context[bank];
616 if (readl_relaxed(&g->dir) != context->dir)
617 writel_relaxed(context->dir, &g->dir);
618 if (readl_relaxed(&g->set_data) != context->set_data)
619 writel_relaxed(context->set_data, &g->set_data);
620 if (readl_relaxed(&g->set_rising) != context->set_rising)
621 writel_relaxed(context->set_rising, &g->set_rising);
622 if (readl_relaxed(&g->set_falling) != context->set_falling)
623 writel_relaxed(context->set_falling, &g->set_falling);
624 }
625}
626
627static int davinci_gpio_suspend(struct device *dev)
628{
629 struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
630 u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32);
631
632 davinci_gpio_save_context(chips, nbank);
633
634 return 0;
635}
636
637static int davinci_gpio_resume(struct device *dev)
638{
639 struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
640 u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32);
641
642 davinci_gpio_restore_context(chips, nbank);
643
644 return 0;
645}
646
647static DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend,
648 davinci_gpio_resume);
649
650static const struct of_device_id davinci_gpio_ids[] = {
651 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
652 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
653 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
654 { /* sentinel */ },
655};
656MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
657
658static struct platform_driver davinci_gpio_driver = {
659 .probe = davinci_gpio_probe,
660 .driver = {
661 .name = "davinci_gpio",
662 .pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops),
663 .of_match_table = davinci_gpio_ids,
664 },
665};
666
667/*
668 * GPIO driver registration needs to be done before machine_init functions
669 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
670 */
671static int __init davinci_gpio_drv_reg(void)
672{
673 return platform_driver_register(&davinci_gpio_driver);
674}
675postcore_initcall(davinci_gpio_drv_reg);
676
677static void __exit davinci_gpio_exit(void)
678{
679 platform_driver_unregister(&davinci_gpio_driver);
680}
681module_exit(davinci_gpio_exit);
682
683MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
684MODULE_DESCRIPTION("DAVINCI GPIO driver");
685MODULE_LICENSE("GPL");
686MODULE_ALIAS("platform:gpio-davinci");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * TI DaVinci GPIO Support
4 *
5 * Copyright (c) 2006-2007 David Brownell
6 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7 */
8
9#include <linux/gpio/driver.h>
10#include <linux/errno.h>
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/platform_device.h>
22#include <linux/platform_data/gpio-davinci.h>
23#include <linux/irqchip/chained_irq.h>
24#include <linux/spinlock.h>
25#include <linux/pm_runtime.h>
26
27#include <asm-generic/gpio.h>
28
29#define MAX_REGS_BANKS 5
30#define MAX_INT_PER_BANK 32
31
32struct davinci_gpio_regs {
33 u32 dir;
34 u32 out_data;
35 u32 set_data;
36 u32 clr_data;
37 u32 in_data;
38 u32 set_rising;
39 u32 clr_rising;
40 u32 set_falling;
41 u32 clr_falling;
42 u32 intstat;
43};
44
45typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
46
47#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
48
49static void __iomem *gpio_base;
50static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
51
52struct davinci_gpio_irq_data {
53 void __iomem *regs;
54 struct davinci_gpio_controller *chip;
55 int bank_num;
56};
57
58struct davinci_gpio_controller {
59 struct gpio_chip chip;
60 struct irq_domain *irq_domain;
61 /* Serialize access to GPIO registers */
62 spinlock_t lock;
63 void __iomem *regs[MAX_REGS_BANKS];
64 int gpio_unbanked;
65 int irqs[MAX_INT_PER_BANK];
66 struct davinci_gpio_regs context[MAX_REGS_BANKS];
67 u32 binten_context;
68};
69
70static inline u32 __gpio_mask(unsigned gpio)
71{
72 return 1 << (gpio % 32);
73}
74
75static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
76{
77 struct davinci_gpio_regs __iomem *g;
78
79 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
80
81 return g;
82}
83
84static int davinci_gpio_irq_setup(struct platform_device *pdev);
85
86/*--------------------------------------------------------------------------*/
87
88/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
89static inline int __davinci_direction(struct gpio_chip *chip,
90 unsigned offset, bool out, int value)
91{
92 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
93 struct davinci_gpio_regs __iomem *g;
94 unsigned long flags;
95 u32 temp;
96 int bank = offset / 32;
97 u32 mask = __gpio_mask(offset);
98
99 g = d->regs[bank];
100 spin_lock_irqsave(&d->lock, flags);
101 temp = readl_relaxed(&g->dir);
102 if (out) {
103 temp &= ~mask;
104 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
105 } else {
106 temp |= mask;
107 }
108 writel_relaxed(temp, &g->dir);
109 spin_unlock_irqrestore(&d->lock, flags);
110
111 return 0;
112}
113
114static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
115{
116 return __davinci_direction(chip, offset, false, 0);
117}
118
119static int
120davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
121{
122 return __davinci_direction(chip, offset, true, value);
123}
124
125/*
126 * Read the pin's value (works even if it's set up as output);
127 * returns zero/nonzero.
128 *
129 * Note that changes are synched to the GPIO clock, so reading values back
130 * right after you've set them may give old values.
131 */
132static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
133{
134 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
135 struct davinci_gpio_regs __iomem *g;
136 int bank = offset / 32;
137
138 g = d->regs[bank];
139
140 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
141}
142
143/*
144 * Assuming the pin is muxed as a gpio output, set its output value.
145 */
146static void
147davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
148{
149 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
150 struct davinci_gpio_regs __iomem *g;
151 int bank = offset / 32;
152
153 g = d->regs[bank];
154
155 writel_relaxed(__gpio_mask(offset),
156 value ? &g->set_data : &g->clr_data);
157}
158
159static struct davinci_gpio_platform_data *
160davinci_gpio_get_pdata(struct platform_device *pdev)
161{
162 struct device_node *dn = pdev->dev.of_node;
163 struct davinci_gpio_platform_data *pdata;
164 int ret;
165 u32 val;
166
167 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
168 return dev_get_platdata(&pdev->dev);
169
170 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
171 if (!pdata)
172 return NULL;
173
174 ret = of_property_read_u32(dn, "ti,ngpio", &val);
175 if (ret)
176 goto of_err;
177
178 pdata->ngpio = val;
179
180 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
181 if (ret)
182 goto of_err;
183
184 pdata->gpio_unbanked = val;
185
186 return pdata;
187
188of_err:
189 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
190 return NULL;
191}
192
193static int davinci_gpio_probe(struct platform_device *pdev)
194{
195 int bank, i, ret = 0;
196 unsigned int ngpio, nbank, nirq;
197 struct davinci_gpio_controller *chips;
198 struct davinci_gpio_platform_data *pdata;
199 struct device *dev = &pdev->dev;
200
201 pdata = davinci_gpio_get_pdata(pdev);
202 if (!pdata) {
203 dev_err(dev, "No platform data found\n");
204 return -EINVAL;
205 }
206
207 dev->platform_data = pdata;
208
209 /*
210 * The gpio banks conceptually expose a segmented bitmap,
211 * and "ngpio" is one more than the largest zero-based
212 * bit index that's valid.
213 */
214 ngpio = pdata->ngpio;
215 if (ngpio == 0) {
216 dev_err(dev, "How many GPIOs?\n");
217 return -EINVAL;
218 }
219
220 /*
221 * If there are unbanked interrupts then the number of
222 * interrupts is equal to number of gpios else all are banked so
223 * number of interrupts is equal to number of banks(each with 16 gpios)
224 */
225 if (pdata->gpio_unbanked)
226 nirq = pdata->gpio_unbanked;
227 else
228 nirq = DIV_ROUND_UP(ngpio, 16);
229
230 chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
231 if (!chips)
232 return -ENOMEM;
233
234 gpio_base = devm_platform_ioremap_resource(pdev, 0);
235 if (IS_ERR(gpio_base))
236 return PTR_ERR(gpio_base);
237
238 for (i = 0; i < nirq; i++) {
239 chips->irqs[i] = platform_get_irq(pdev, i);
240 if (chips->irqs[i] < 0)
241 return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n");
242 }
243
244 chips->chip.label = dev_name(dev);
245
246 chips->chip.direction_input = davinci_direction_in;
247 chips->chip.get = davinci_gpio_get;
248 chips->chip.direction_output = davinci_direction_out;
249 chips->chip.set = davinci_gpio_set;
250
251 chips->chip.ngpio = ngpio;
252 chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
253
254#ifdef CONFIG_OF_GPIO
255 chips->chip.of_gpio_n_cells = 2;
256 chips->chip.parent = dev;
257 chips->chip.request = gpiochip_generic_request;
258 chips->chip.free = gpiochip_generic_free;
259#endif
260 spin_lock_init(&chips->lock);
261
262 nbank = DIV_ROUND_UP(ngpio, 32);
263 for (bank = 0; bank < nbank; bank++)
264 chips->regs[bank] = gpio_base + offset_array[bank];
265
266 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
267 if (ret)
268 return ret;
269
270 platform_set_drvdata(pdev, chips);
271 ret = davinci_gpio_irq_setup(pdev);
272 if (ret)
273 return ret;
274
275 return 0;
276}
277
278/*--------------------------------------------------------------------------*/
279/*
280 * We expect irqs will normally be set up as input pins, but they can also be
281 * used as output pins ... which is convenient for testing.
282 *
283 * NOTE: The first few GPIOs also have direct INTC hookups in addition
284 * to their GPIOBNK0 irq, with a bit less overhead.
285 *
286 * All those INTC hookups (direct, plus several IRQ banks) can also
287 * serve as EDMA event triggers.
288 */
289
290static void gpio_irq_disable(struct irq_data *d)
291{
292 struct davinci_gpio_regs __iomem *g = irq2regs(d);
293 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
294
295 writel_relaxed(mask, &g->clr_falling);
296 writel_relaxed(mask, &g->clr_rising);
297}
298
299static void gpio_irq_enable(struct irq_data *d)
300{
301 struct davinci_gpio_regs __iomem *g = irq2regs(d);
302 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
303 unsigned status = irqd_get_trigger_type(d);
304
305 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
306 if (!status)
307 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
308
309 if (status & IRQ_TYPE_EDGE_FALLING)
310 writel_relaxed(mask, &g->set_falling);
311 if (status & IRQ_TYPE_EDGE_RISING)
312 writel_relaxed(mask, &g->set_rising);
313}
314
315static int gpio_irq_type(struct irq_data *d, unsigned trigger)
316{
317 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
318 return -EINVAL;
319
320 return 0;
321}
322
323static struct irq_chip gpio_irqchip = {
324 .name = "GPIO",
325 .irq_enable = gpio_irq_enable,
326 .irq_disable = gpio_irq_disable,
327 .irq_set_type = gpio_irq_type,
328 .flags = IRQCHIP_SET_TYPE_MASKED,
329};
330
331static void gpio_irq_handler(struct irq_desc *desc)
332{
333 struct davinci_gpio_regs __iomem *g;
334 u32 mask = 0xffff;
335 int bank_num;
336 struct davinci_gpio_controller *d;
337 struct davinci_gpio_irq_data *irqdata;
338
339 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
340 bank_num = irqdata->bank_num;
341 g = irqdata->regs;
342 d = irqdata->chip;
343
344 /* we only care about one bank */
345 if ((bank_num % 2) == 1)
346 mask <<= 16;
347
348 /* temporarily mask (level sensitive) parent IRQ */
349 chained_irq_enter(irq_desc_get_chip(desc), desc);
350 while (1) {
351 u32 status;
352 int bit;
353 irq_hw_number_t hw_irq;
354
355 /* ack any irqs */
356 status = readl_relaxed(&g->intstat) & mask;
357 if (!status)
358 break;
359 writel_relaxed(status, &g->intstat);
360
361 /* now demux them to the right lowlevel handler */
362
363 while (status) {
364 bit = __ffs(status);
365 status &= ~BIT(bit);
366 /* Max number of gpios per controller is 144 so
367 * hw_irq will be in [0..143]
368 */
369 hw_irq = (bank_num / 2) * 32 + bit;
370
371 generic_handle_domain_irq(d->irq_domain, hw_irq);
372 }
373 }
374 chained_irq_exit(irq_desc_get_chip(desc), desc);
375 /* now it may re-trigger */
376}
377
378static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
379{
380 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
381
382 if (d->irq_domain)
383 return irq_create_mapping(d->irq_domain, offset);
384 else
385 return -ENXIO;
386}
387
388static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
389{
390 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
391
392 /*
393 * NOTE: we assume for now that only irqs in the first gpio_chip
394 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
395 */
396 if (offset < d->gpio_unbanked)
397 return d->irqs[offset];
398 else
399 return -ENODEV;
400}
401
402static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
403{
404 struct davinci_gpio_controller *d;
405 struct davinci_gpio_regs __iomem *g;
406 u32 mask, i;
407
408 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
409 g = (struct davinci_gpio_regs __iomem *)d->regs[0];
410 for (i = 0; i < MAX_INT_PER_BANK; i++)
411 if (data->irq == d->irqs[i])
412 break;
413
414 if (i == MAX_INT_PER_BANK)
415 return -EINVAL;
416
417 mask = __gpio_mask(i);
418
419 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
420 return -EINVAL;
421
422 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
423 ? &g->set_falling : &g->clr_falling);
424 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
425 ? &g->set_rising : &g->clr_rising);
426
427 return 0;
428}
429
430static int
431davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
432 irq_hw_number_t hw)
433{
434 struct davinci_gpio_controller *chips =
435 (struct davinci_gpio_controller *)d->host_data;
436 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
437
438 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
439 "davinci_gpio");
440 irq_set_irq_type(irq, IRQ_TYPE_NONE);
441 irq_set_chip_data(irq, (__force void *)g);
442 irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
443
444 return 0;
445}
446
447static const struct irq_domain_ops davinci_gpio_irq_ops = {
448 .map = davinci_gpio_irq_map,
449 .xlate = irq_domain_xlate_onetwocell,
450};
451
452static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
453{
454 static struct irq_chip_type gpio_unbanked;
455
456 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
457
458 return &gpio_unbanked.chip;
459};
460
461static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
462{
463 static struct irq_chip gpio_unbanked;
464
465 gpio_unbanked = *irq_get_chip(irq);
466 return &gpio_unbanked;
467};
468
469static const struct of_device_id davinci_gpio_ids[];
470
471/*
472 * NOTE: for suspend/resume, probably best to make a platform_device with
473 * suspend_late/resume_resume calls hooking into results of the set_wake()
474 * calls ... so if no gpios are wakeup events the clock can be disabled,
475 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
476 * (dm6446) can be set appropriately for GPIOV33 pins.
477 */
478
479static int davinci_gpio_irq_setup(struct platform_device *pdev)
480{
481 unsigned gpio, bank;
482 int irq;
483 int ret;
484 struct clk *clk;
485 u32 binten = 0;
486 unsigned ngpio;
487 struct device *dev = &pdev->dev;
488 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
489 struct davinci_gpio_platform_data *pdata = dev->platform_data;
490 struct davinci_gpio_regs __iomem *g;
491 struct irq_domain *irq_domain = NULL;
492 const struct of_device_id *match;
493 struct irq_chip *irq_chip;
494 struct davinci_gpio_irq_data *irqdata;
495 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
496
497 /*
498 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
499 */
500 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
501 match = of_match_device(of_match_ptr(davinci_gpio_ids),
502 dev);
503 if (match)
504 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
505
506 ngpio = pdata->ngpio;
507
508 clk = devm_clk_get(dev, "gpio");
509 if (IS_ERR(clk)) {
510 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
511 return PTR_ERR(clk);
512 }
513
514 ret = clk_prepare_enable(clk);
515 if (ret)
516 return ret;
517
518 if (!pdata->gpio_unbanked) {
519 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
520 if (irq < 0) {
521 dev_err(dev, "Couldn't allocate IRQ numbers\n");
522 clk_disable_unprepare(clk);
523 return irq;
524 }
525
526 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
527 &davinci_gpio_irq_ops,
528 chips);
529 if (!irq_domain) {
530 dev_err(dev, "Couldn't register an IRQ domain\n");
531 clk_disable_unprepare(clk);
532 return -ENODEV;
533 }
534 }
535
536 /*
537 * Arrange gpio_to_irq() support, handling either direct IRQs or
538 * banked IRQs. Having GPIOs in the first GPIO bank use direct
539 * IRQs, while the others use banked IRQs, would need some setup
540 * tweaks to recognize hardware which can do that.
541 */
542 chips->chip.to_irq = gpio_to_irq_banked;
543 chips->irq_domain = irq_domain;
544
545 /*
546 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
547 * controller only handling trigger modes. We currently assume no
548 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
549 */
550 if (pdata->gpio_unbanked) {
551 /* pass "bank 0" GPIO IRQs to AINTC */
552 chips->chip.to_irq = gpio_to_irq_unbanked;
553 chips->gpio_unbanked = pdata->gpio_unbanked;
554 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
555
556 /* AINTC handles mask/unmask; GPIO handles triggering */
557 irq = chips->irqs[0];
558 irq_chip = gpio_get_irq_chip(irq);
559 irq_chip->name = "GPIO-AINTC";
560 irq_chip->irq_set_type = gpio_irq_type_unbanked;
561
562 /* default trigger: both edges */
563 g = chips->regs[0];
564 writel_relaxed(~0, &g->set_falling);
565 writel_relaxed(~0, &g->set_rising);
566
567 /* set the direct IRQs up to use that irqchip */
568 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
569 irq_set_chip(chips->irqs[gpio], irq_chip);
570 irq_set_handler_data(chips->irqs[gpio], chips);
571 irq_set_status_flags(chips->irqs[gpio],
572 IRQ_TYPE_EDGE_BOTH);
573 }
574
575 goto done;
576 }
577
578 /*
579 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
580 * then chain through our own handler.
581 */
582 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
583 /* disabled by default, enabled only as needed
584 * There are register sets for 32 GPIOs. 2 banks of 16
585 * GPIOs are covered by each set of registers hence divide by 2
586 */
587 g = chips->regs[bank / 2];
588 writel_relaxed(~0, &g->clr_falling);
589 writel_relaxed(~0, &g->clr_rising);
590
591 /*
592 * Each chip handles 32 gpios, and each irq bank consists of 16
593 * gpio irqs. Pass the irq bank's corresponding controller to
594 * the chained irq handler.
595 */
596 irqdata = devm_kzalloc(&pdev->dev,
597 sizeof(struct
598 davinci_gpio_irq_data),
599 GFP_KERNEL);
600 if (!irqdata) {
601 clk_disable_unprepare(clk);
602 return -ENOMEM;
603 }
604
605 irqdata->regs = g;
606 irqdata->bank_num = bank;
607 irqdata->chip = chips;
608
609 irq_set_chained_handler_and_data(chips->irqs[bank],
610 gpio_irq_handler, irqdata);
611
612 binten |= BIT(bank);
613 }
614
615done:
616 /*
617 * BINTEN -- per-bank interrupt enable. genirq would also let these
618 * bits be set/cleared dynamically.
619 */
620 writel_relaxed(binten, gpio_base + BINTEN);
621
622 return 0;
623}
624
625static void davinci_gpio_save_context(struct davinci_gpio_controller *chips,
626 u32 nbank)
627{
628 struct davinci_gpio_regs __iomem *g;
629 struct davinci_gpio_regs *context;
630 u32 bank;
631 void __iomem *base;
632
633 base = chips->regs[0] - offset_array[0];
634 chips->binten_context = readl_relaxed(base + BINTEN);
635
636 for (bank = 0; bank < nbank; bank++) {
637 g = chips->regs[bank];
638 context = &chips->context[bank];
639 context->dir = readl_relaxed(&g->dir);
640 context->set_data = readl_relaxed(&g->set_data);
641 context->set_rising = readl_relaxed(&g->set_rising);
642 context->set_falling = readl_relaxed(&g->set_falling);
643 }
644
645 /* Clear Bank interrupt enable bit */
646 writel_relaxed(0, base + BINTEN);
647
648 /* Clear all interrupt status registers */
649 writel_relaxed(GENMASK(31, 0), &g->intstat);
650}
651
652static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips,
653 u32 nbank)
654{
655 struct davinci_gpio_regs __iomem *g;
656 struct davinci_gpio_regs *context;
657 u32 bank;
658 void __iomem *base;
659
660 base = chips->regs[0] - offset_array[0];
661
662 if (readl_relaxed(base + BINTEN) != chips->binten_context)
663 writel_relaxed(chips->binten_context, base + BINTEN);
664
665 for (bank = 0; bank < nbank; bank++) {
666 g = chips->regs[bank];
667 context = &chips->context[bank];
668 if (readl_relaxed(&g->dir) != context->dir)
669 writel_relaxed(context->dir, &g->dir);
670 if (readl_relaxed(&g->set_data) != context->set_data)
671 writel_relaxed(context->set_data, &g->set_data);
672 if (readl_relaxed(&g->set_rising) != context->set_rising)
673 writel_relaxed(context->set_rising, &g->set_rising);
674 if (readl_relaxed(&g->set_falling) != context->set_falling)
675 writel_relaxed(context->set_falling, &g->set_falling);
676 }
677}
678
679static int davinci_gpio_suspend(struct device *dev)
680{
681 struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
682 struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
683 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
684
685 davinci_gpio_save_context(chips, nbank);
686
687 return 0;
688}
689
690static int davinci_gpio_resume(struct device *dev)
691{
692 struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
693 struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
694 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
695
696 davinci_gpio_restore_context(chips, nbank);
697
698 return 0;
699}
700
701DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend,
702 davinci_gpio_resume);
703
704static const struct of_device_id davinci_gpio_ids[] = {
705 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
706 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
707 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
708 { /* sentinel */ },
709};
710MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
711
712static struct platform_driver davinci_gpio_driver = {
713 .probe = davinci_gpio_probe,
714 .driver = {
715 .name = "davinci_gpio",
716 .pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops),
717 .of_match_table = of_match_ptr(davinci_gpio_ids),
718 },
719};
720
721/**
722 * GPIO driver registration needs to be done before machine_init functions
723 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
724 */
725static int __init davinci_gpio_drv_reg(void)
726{
727 return platform_driver_register(&davinci_gpio_driver);
728}
729postcore_initcall(davinci_gpio_drv_reg);
730
731static void __exit davinci_gpio_exit(void)
732{
733 platform_driver_unregister(&davinci_gpio_driver);
734}
735module_exit(davinci_gpio_exit);
736
737MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
738MODULE_DESCRIPTION("DAVINCI GPIO driver");
739MODULE_LICENSE("GPL");
740MODULE_ALIAS("platform:gpio-davinci");