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1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (C) 2015-2017 Broadcom
3
4#include <linux/bitops.h>
5#include <linux/gpio/driver.h>
6#include <linux/of.h>
7#include <linux/module.h>
8#include <linux/irqdomain.h>
9#include <linux/irqchip/chained_irq.h>
10#include <linux/interrupt.h>
11#include <linux/platform_device.h>
12
13enum gio_reg_index {
14 GIO_REG_ODEN = 0,
15 GIO_REG_DATA,
16 GIO_REG_IODIR,
17 GIO_REG_EC,
18 GIO_REG_EI,
19 GIO_REG_MASK,
20 GIO_REG_LEVEL,
21 GIO_REG_STAT,
22 NUMBER_OF_GIO_REGISTERS
23};
24
25#define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
26#define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
27#define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
28#define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
29#define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
30#define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
31#define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
32#define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
33#define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
34#define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
35
36struct brcmstb_gpio_bank {
37 struct list_head node;
38 int id;
39 struct gpio_chip gc;
40 struct brcmstb_gpio_priv *parent_priv;
41 u32 width;
42 u32 wake_active;
43 u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
44};
45
46struct brcmstb_gpio_priv {
47 struct list_head bank_list;
48 void __iomem *reg_base;
49 struct platform_device *pdev;
50 struct irq_domain *irq_domain;
51 struct irq_chip irq_chip;
52 int parent_irq;
53 int num_gpios;
54 int parent_wake_irq;
55};
56
57#define MAX_GPIO_PER_BANK 32
58#define GPIO_BANK(gpio) ((gpio) >> 5)
59/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
60#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
61
62static inline struct brcmstb_gpio_priv *
63brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
64{
65 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
66 return bank->parent_priv;
67}
68
69static unsigned long
70__brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
71{
72 void __iomem *reg_base = bank->parent_priv->reg_base;
73
74 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
75 bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
76}
77
78static unsigned long
79brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
80{
81 unsigned long status;
82 unsigned long flags;
83
84 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
85 status = __brcmstb_gpio_get_active_irqs(bank);
86 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
87
88 return status;
89}
90
91static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
92 struct brcmstb_gpio_bank *bank)
93{
94 return hwirq - bank->gc.offset;
95}
96
97static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
98 unsigned int hwirq, bool enable)
99{
100 struct gpio_chip *gc = &bank->gc;
101 struct brcmstb_gpio_priv *priv = bank->parent_priv;
102 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
103 u32 imask;
104 unsigned long flags;
105
106 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
107 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
108 if (enable)
109 imask |= mask;
110 else
111 imask &= ~mask;
112 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
113 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
114}
115
116static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
117{
118 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
119 /* gc_offset is relative to this gpio_chip; want real offset */
120 int hwirq = offset + gc->offset;
121
122 if (hwirq >= priv->num_gpios)
123 return -ENXIO;
124 return irq_create_mapping(priv->irq_domain, hwirq);
125}
126
127/* -------------------- IRQ chip functions -------------------- */
128
129static void brcmstb_gpio_irq_mask(struct irq_data *d)
130{
131 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
132 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
133
134 brcmstb_gpio_set_imask(bank, d->hwirq, false);
135}
136
137static void brcmstb_gpio_irq_unmask(struct irq_data *d)
138{
139 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
140 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
141
142 brcmstb_gpio_set_imask(bank, d->hwirq, true);
143}
144
145static void brcmstb_gpio_irq_ack(struct irq_data *d)
146{
147 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
148 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
149 struct brcmstb_gpio_priv *priv = bank->parent_priv;
150 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
151
152 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
153}
154
155static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
156{
157 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
158 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
159 struct brcmstb_gpio_priv *priv = bank->parent_priv;
160 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
161 u32 edge_insensitive, iedge_insensitive;
162 u32 edge_config, iedge_config;
163 u32 level, ilevel;
164 unsigned long flags;
165
166 switch (type) {
167 case IRQ_TYPE_LEVEL_LOW:
168 level = mask;
169 edge_config = 0;
170 edge_insensitive = 0;
171 break;
172 case IRQ_TYPE_LEVEL_HIGH:
173 level = mask;
174 edge_config = mask;
175 edge_insensitive = 0;
176 break;
177 case IRQ_TYPE_EDGE_FALLING:
178 level = 0;
179 edge_config = 0;
180 edge_insensitive = 0;
181 break;
182 case IRQ_TYPE_EDGE_RISING:
183 level = 0;
184 edge_config = mask;
185 edge_insensitive = 0;
186 break;
187 case IRQ_TYPE_EDGE_BOTH:
188 level = 0;
189 edge_config = 0; /* don't care, but want known value */
190 edge_insensitive = mask;
191 break;
192 default:
193 return -EINVAL;
194 }
195
196 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
197
198 iedge_config = bank->gc.read_reg(priv->reg_base +
199 GIO_EC(bank->id)) & ~mask;
200 iedge_insensitive = bank->gc.read_reg(priv->reg_base +
201 GIO_EI(bank->id)) & ~mask;
202 ilevel = bank->gc.read_reg(priv->reg_base +
203 GIO_LEVEL(bank->id)) & ~mask;
204
205 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
206 iedge_config | edge_config);
207 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
208 iedge_insensitive | edge_insensitive);
209 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
210 ilevel | level);
211
212 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
213 return 0;
214}
215
216static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
217 unsigned int enable)
218{
219 int ret = 0;
220
221 if (enable)
222 ret = enable_irq_wake(priv->parent_wake_irq);
223 else
224 ret = disable_irq_wake(priv->parent_wake_irq);
225 if (ret)
226 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
227 enable ? "enable" : "disable");
228 return ret;
229}
230
231static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
232{
233 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
234 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
235 struct brcmstb_gpio_priv *priv = bank->parent_priv;
236 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
237
238 /*
239 * Do not do anything specific for now, suspend/resume callbacks will
240 * configure the interrupt mask appropriately
241 */
242 if (enable)
243 bank->wake_active |= mask;
244 else
245 bank->wake_active &= ~mask;
246
247 return brcmstb_gpio_priv_set_wake(priv, enable);
248}
249
250static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
251{
252 struct brcmstb_gpio_priv *priv = data;
253
254 if (!priv || irq != priv->parent_wake_irq)
255 return IRQ_NONE;
256
257 /* Nothing to do */
258 return IRQ_HANDLED;
259}
260
261static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
262{
263 struct brcmstb_gpio_priv *priv = bank->parent_priv;
264 struct irq_domain *domain = priv->irq_domain;
265 int hwbase = bank->gc.offset;
266 unsigned long status;
267
268 while ((status = brcmstb_gpio_get_active_irqs(bank))) {
269 unsigned int offset;
270
271 for_each_set_bit(offset, &status, 32) {
272 if (offset >= bank->width)
273 dev_warn(&priv->pdev->dev,
274 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
275 bank->id, offset);
276 generic_handle_domain_irq(domain, hwbase + offset);
277 }
278 }
279}
280
281/* Each UPG GIO block has one IRQ for all banks */
282static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
283{
284 struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
285 struct irq_chip *chip = irq_desc_get_chip(desc);
286 struct brcmstb_gpio_bank *bank;
287
288 /* Interrupts weren't properly cleared during probe */
289 BUG_ON(!priv || !chip);
290
291 chained_irq_enter(chip, desc);
292 list_for_each_entry(bank, &priv->bank_list, node)
293 brcmstb_gpio_irq_bank_handler(bank);
294 chained_irq_exit(chip, desc);
295}
296
297static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
298 struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
299{
300 struct brcmstb_gpio_bank *bank;
301 int i = 0;
302
303 /* banks are in descending order */
304 list_for_each_entry_reverse(bank, &priv->bank_list, node) {
305 i += bank->gc.ngpio;
306 if (hwirq < i)
307 return bank;
308 }
309 return NULL;
310}
311
312/*
313 * This lock class tells lockdep that GPIO irqs are in a different
314 * category than their parents, so it won't report false recursion.
315 */
316static struct lock_class_key brcmstb_gpio_irq_lock_class;
317static struct lock_class_key brcmstb_gpio_irq_request_class;
318
319
320static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
321 irq_hw_number_t hwirq)
322{
323 struct brcmstb_gpio_priv *priv = d->host_data;
324 struct brcmstb_gpio_bank *bank =
325 brcmstb_gpio_hwirq_to_bank(priv, hwirq);
326 struct platform_device *pdev = priv->pdev;
327 int ret;
328
329 if (!bank)
330 return -EINVAL;
331
332 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
333 irq, (int)hwirq, bank->id);
334 ret = irq_set_chip_data(irq, &bank->gc);
335 if (ret < 0)
336 return ret;
337 irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
338 &brcmstb_gpio_irq_request_class);
339 irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
340 irq_set_noprobe(irq);
341 return 0;
342}
343
344static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
345{
346 irq_set_chip_and_handler(irq, NULL, NULL);
347 irq_set_chip_data(irq, NULL);
348}
349
350static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
351 .map = brcmstb_gpio_irq_map,
352 .unmap = brcmstb_gpio_irq_unmap,
353 .xlate = irq_domain_xlate_twocell,
354};
355
356/* Make sure that the number of banks matches up between properties */
357static int brcmstb_gpio_sanity_check_banks(struct device *dev,
358 struct device_node *np, struct resource *res)
359{
360 int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
361 int num_banks =
362 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
363
364 if (res_num_banks != num_banks) {
365 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
366 res_num_banks, num_banks);
367 return -EINVAL;
368 } else {
369 return 0;
370 }
371}
372
373static void brcmstb_gpio_remove(struct platform_device *pdev)
374{
375 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
376 struct brcmstb_gpio_bank *bank;
377 int offset, virq;
378
379 if (priv->parent_irq > 0)
380 irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
381
382 /* Remove all IRQ mappings and delete the domain */
383 if (priv->irq_domain) {
384 for (offset = 0; offset < priv->num_gpios; offset++) {
385 virq = irq_find_mapping(priv->irq_domain, offset);
386 irq_dispose_mapping(virq);
387 }
388 irq_domain_remove(priv->irq_domain);
389 }
390
391 /*
392 * You can lose return values below, but we report all errors, and it's
393 * more important to actually perform all of the steps.
394 */
395 list_for_each_entry(bank, &priv->bank_list, node)
396 gpiochip_remove(&bank->gc);
397}
398
399static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
400 const struct of_phandle_args *gpiospec, u32 *flags)
401{
402 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
403 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
404 int offset;
405
406 if (gc->of_gpio_n_cells != 2) {
407 WARN_ON(1);
408 return -EINVAL;
409 }
410
411 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
412 return -EINVAL;
413
414 offset = gpiospec->args[0] - bank->gc.offset;
415 if (offset >= gc->ngpio || offset < 0)
416 return -EINVAL;
417
418 if (unlikely(offset >= bank->width)) {
419 dev_warn_ratelimited(&priv->pdev->dev,
420 "Received request for invalid GPIO offset %d\n",
421 gpiospec->args[0]);
422 }
423
424 if (flags)
425 *flags = gpiospec->args[1];
426
427 return offset;
428}
429
430/* priv->parent_irq and priv->num_gpios must be set before calling */
431static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
432 struct brcmstb_gpio_priv *priv)
433{
434 struct device *dev = &pdev->dev;
435 struct device_node *np = dev->of_node;
436 int err;
437
438 priv->irq_domain =
439 irq_domain_add_linear(np, priv->num_gpios,
440 &brcmstb_gpio_irq_domain_ops,
441 priv);
442 if (!priv->irq_domain) {
443 dev_err(dev, "Couldn't allocate IRQ domain\n");
444 return -ENXIO;
445 }
446
447 if (of_property_read_bool(np, "wakeup-source")) {
448 priv->parent_wake_irq = platform_get_irq(pdev, 1);
449 if (priv->parent_wake_irq < 0) {
450 priv->parent_wake_irq = 0;
451 dev_warn(dev,
452 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
453 } else {
454 /*
455 * Set wakeup capability so we can process boot-time
456 * "wakeups" (e.g., from S5 cold boot)
457 */
458 device_set_wakeup_capable(dev, true);
459 device_wakeup_enable(dev);
460 err = devm_request_irq(dev, priv->parent_wake_irq,
461 brcmstb_gpio_wake_irq_handler,
462 IRQF_SHARED,
463 "brcmstb-gpio-wake", priv);
464
465 if (err < 0) {
466 dev_err(dev, "Couldn't request wake IRQ");
467 goto out_free_domain;
468 }
469 }
470 }
471
472 priv->irq_chip.name = dev_name(dev);
473 priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
474 priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
475 priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
476 priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
477 priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
478
479 if (priv->parent_wake_irq)
480 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
481
482 irq_set_chained_handler_and_data(priv->parent_irq,
483 brcmstb_gpio_irq_handler, priv);
484 irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
485
486 return 0;
487
488out_free_domain:
489 irq_domain_remove(priv->irq_domain);
490
491 return err;
492}
493
494static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
495 struct brcmstb_gpio_bank *bank)
496{
497 struct gpio_chip *gc = &bank->gc;
498 unsigned int i;
499
500 for (i = 0; i < GIO_REG_STAT; i++)
501 bank->saved_regs[i] = gc->read_reg(priv->reg_base +
502 GIO_BANK_OFF(bank->id, i));
503}
504
505static void brcmstb_gpio_quiesce(struct device *dev, bool save)
506{
507 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
508 struct brcmstb_gpio_bank *bank;
509 struct gpio_chip *gc;
510 u32 imask;
511
512 /* disable non-wake interrupt */
513 if (priv->parent_irq >= 0)
514 disable_irq(priv->parent_irq);
515
516 list_for_each_entry(bank, &priv->bank_list, node) {
517 gc = &bank->gc;
518
519 if (save)
520 brcmstb_gpio_bank_save(priv, bank);
521
522 /* Unmask GPIOs which have been flagged as wake-up sources */
523 if (priv->parent_wake_irq)
524 imask = bank->wake_active;
525 else
526 imask = 0;
527 gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
528 imask);
529 }
530}
531
532static void brcmstb_gpio_shutdown(struct platform_device *pdev)
533{
534 /* Enable GPIO for S5 cold boot */
535 brcmstb_gpio_quiesce(&pdev->dev, false);
536}
537
538#ifdef CONFIG_PM_SLEEP
539static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
540 struct brcmstb_gpio_bank *bank)
541{
542 struct gpio_chip *gc = &bank->gc;
543 unsigned int i;
544
545 for (i = 0; i < GIO_REG_STAT; i++)
546 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
547 bank->saved_regs[i]);
548}
549
550static int brcmstb_gpio_suspend(struct device *dev)
551{
552 brcmstb_gpio_quiesce(dev, true);
553 return 0;
554}
555
556static int brcmstb_gpio_resume(struct device *dev)
557{
558 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
559 struct brcmstb_gpio_bank *bank;
560 bool need_wakeup_event = false;
561
562 list_for_each_entry(bank, &priv->bank_list, node) {
563 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
564 brcmstb_gpio_bank_restore(priv, bank);
565 }
566
567 if (priv->parent_wake_irq && need_wakeup_event)
568 pm_wakeup_event(dev, 0);
569
570 /* enable non-wake interrupt */
571 if (priv->parent_irq >= 0)
572 enable_irq(priv->parent_irq);
573
574 return 0;
575}
576
577#else
578#define brcmstb_gpio_suspend NULL
579#define brcmstb_gpio_resume NULL
580#endif /* CONFIG_PM_SLEEP */
581
582static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
583 .suspend_noirq = brcmstb_gpio_suspend,
584 .resume_noirq = brcmstb_gpio_resume,
585};
586
587static int brcmstb_gpio_probe(struct platform_device *pdev)
588{
589 struct device *dev = &pdev->dev;
590 struct device_node *np = dev->of_node;
591 void __iomem *reg_base;
592 struct brcmstb_gpio_priv *priv;
593 struct resource *res;
594 u32 bank_width;
595 int num_banks = 0;
596 int num_gpios = 0;
597 int err;
598 unsigned long flags = 0;
599 bool need_wakeup_event = false;
600
601 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
602 if (!priv)
603 return -ENOMEM;
604 platform_set_drvdata(pdev, priv);
605 INIT_LIST_HEAD(&priv->bank_list);
606
607 reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
608 if (IS_ERR(reg_base))
609 return PTR_ERR(reg_base);
610
611 priv->reg_base = reg_base;
612 priv->pdev = pdev;
613
614 if (of_property_read_bool(np, "interrupt-controller")) {
615 priv->parent_irq = platform_get_irq(pdev, 0);
616 if (priv->parent_irq <= 0)
617 return -ENOENT;
618 } else {
619 priv->parent_irq = -ENOENT;
620 }
621
622 if (brcmstb_gpio_sanity_check_banks(dev, np, res))
623 return -EINVAL;
624
625 /*
626 * MIPS endianness is configured by boot strap, which also reverses all
627 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
628 * endian I/O).
629 *
630 * Other architectures (e.g., ARM) either do not support big endian, or
631 * else leave I/O in little endian mode.
632 */
633#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
634 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
635#endif
636
637 of_property_for_each_u32(np, "brcm,gpio-bank-widths", bank_width) {
638 struct brcmstb_gpio_bank *bank;
639 struct gpio_chip *gc;
640
641 /*
642 * If bank_width is 0, then there is an empty bank in the
643 * register block. Special handling for this case.
644 */
645 if (bank_width == 0) {
646 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
647 num_banks);
648 num_banks++;
649 num_gpios += MAX_GPIO_PER_BANK;
650 continue;
651 }
652
653 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
654 if (!bank) {
655 err = -ENOMEM;
656 goto fail;
657 }
658
659 bank->parent_priv = priv;
660 bank->id = num_banks;
661 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
662 dev_err(dev, "Invalid bank width %d\n", bank_width);
663 err = -EINVAL;
664 goto fail;
665 } else {
666 bank->width = bank_width;
667 }
668
669 /*
670 * Regs are 4 bytes wide, have data reg, no set/clear regs,
671 * and direction bits have 0 = output and 1 = input
672 */
673 gc = &bank->gc;
674 err = bgpio_init(gc, dev, 4,
675 reg_base + GIO_DATA(bank->id),
676 NULL, NULL, NULL,
677 reg_base + GIO_IODIR(bank->id), flags);
678 if (err) {
679 dev_err(dev, "bgpio_init() failed\n");
680 goto fail;
681 }
682
683 gc->owner = THIS_MODULE;
684 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
685 if (!gc->label) {
686 err = -ENOMEM;
687 goto fail;
688 }
689 gc->of_gpio_n_cells = 2;
690 gc->of_xlate = brcmstb_gpio_of_xlate;
691 /* not all ngpio lines are valid, will use bank width later */
692 gc->ngpio = MAX_GPIO_PER_BANK;
693 gc->offset = bank->id * MAX_GPIO_PER_BANK;
694 gc->request = gpiochip_generic_request;
695 gc->free = gpiochip_generic_free;
696 if (priv->parent_irq > 0)
697 gc->to_irq = brcmstb_gpio_to_irq;
698
699 /*
700 * Mask all interrupts by default, since wakeup interrupts may
701 * be retained from S5 cold boot
702 */
703 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
704 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
705
706 err = gpiochip_add_data(gc, bank);
707 if (err) {
708 dev_err(dev, "Could not add gpiochip for bank %d\n",
709 bank->id);
710 goto fail;
711 }
712 num_gpios += gc->ngpio;
713
714 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
715 gc->base, gc->ngpio, bank->width);
716
717 /* Everything looks good, so add bank to list */
718 list_add(&bank->node, &priv->bank_list);
719
720 num_banks++;
721 }
722
723 priv->num_gpios = num_gpios;
724 if (priv->parent_irq > 0) {
725 err = brcmstb_gpio_irq_setup(pdev, priv);
726 if (err)
727 goto fail;
728 }
729
730 if (priv->parent_wake_irq && need_wakeup_event)
731 pm_wakeup_event(dev, 0);
732
733 return 0;
734
735fail:
736 (void) brcmstb_gpio_remove(pdev);
737 return err;
738}
739
740static const struct of_device_id brcmstb_gpio_of_match[] = {
741 { .compatible = "brcm,brcmstb-gpio" },
742 {},
743};
744
745MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
746
747static struct platform_driver brcmstb_gpio_driver = {
748 .driver = {
749 .name = "brcmstb-gpio",
750 .of_match_table = brcmstb_gpio_of_match,
751 .pm = &brcmstb_gpio_pm_ops,
752 },
753 .probe = brcmstb_gpio_probe,
754 .remove = brcmstb_gpio_remove,
755 .shutdown = brcmstb_gpio_shutdown,
756};
757module_platform_driver(brcmstb_gpio_driver);
758
759MODULE_AUTHOR("Gregory Fong");
760MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
761MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (C) 2015-2017 Broadcom
3
4#include <linux/bitops.h>
5#include <linux/gpio/driver.h>
6#include <linux/of_device.h>
7#include <linux/of_irq.h>
8#include <linux/module.h>
9#include <linux/irqdomain.h>
10#include <linux/irqchip/chained_irq.h>
11#include <linux/interrupt.h>
12
13enum gio_reg_index {
14 GIO_REG_ODEN = 0,
15 GIO_REG_DATA,
16 GIO_REG_IODIR,
17 GIO_REG_EC,
18 GIO_REG_EI,
19 GIO_REG_MASK,
20 GIO_REG_LEVEL,
21 GIO_REG_STAT,
22 NUMBER_OF_GIO_REGISTERS
23};
24
25#define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
26#define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
27#define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
28#define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
29#define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
30#define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
31#define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
32#define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
33#define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
34#define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
35
36struct brcmstb_gpio_bank {
37 struct list_head node;
38 int id;
39 struct gpio_chip gc;
40 struct brcmstb_gpio_priv *parent_priv;
41 u32 width;
42 u32 wake_active;
43 u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
44};
45
46struct brcmstb_gpio_priv {
47 struct list_head bank_list;
48 void __iomem *reg_base;
49 struct platform_device *pdev;
50 struct irq_domain *irq_domain;
51 struct irq_chip irq_chip;
52 int parent_irq;
53 int gpio_base;
54 int num_gpios;
55 int parent_wake_irq;
56};
57
58#define MAX_GPIO_PER_BANK 32
59#define GPIO_BANK(gpio) ((gpio) >> 5)
60/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
61#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
62
63static inline struct brcmstb_gpio_priv *
64brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
65{
66 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
67 return bank->parent_priv;
68}
69
70static unsigned long
71__brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
72{
73 void __iomem *reg_base = bank->parent_priv->reg_base;
74
75 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
76 bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
77}
78
79static unsigned long
80brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
81{
82 unsigned long status;
83 unsigned long flags;
84
85 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
86 status = __brcmstb_gpio_get_active_irqs(bank);
87 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
88
89 return status;
90}
91
92static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
93 struct brcmstb_gpio_bank *bank)
94{
95 return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
96}
97
98static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
99 unsigned int hwirq, bool enable)
100{
101 struct gpio_chip *gc = &bank->gc;
102 struct brcmstb_gpio_priv *priv = bank->parent_priv;
103 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
104 u32 imask;
105 unsigned long flags;
106
107 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
108 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
109 if (enable)
110 imask |= mask;
111 else
112 imask &= ~mask;
113 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
114 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
115}
116
117static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
118{
119 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
120 /* gc_offset is relative to this gpio_chip; want real offset */
121 int hwirq = offset + (gc->base - priv->gpio_base);
122
123 if (hwirq >= priv->num_gpios)
124 return -ENXIO;
125 return irq_create_mapping(priv->irq_domain, hwirq);
126}
127
128/* -------------------- IRQ chip functions -------------------- */
129
130static void brcmstb_gpio_irq_mask(struct irq_data *d)
131{
132 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
133 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
134
135 brcmstb_gpio_set_imask(bank, d->hwirq, false);
136}
137
138static void brcmstb_gpio_irq_unmask(struct irq_data *d)
139{
140 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
141 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
142
143 brcmstb_gpio_set_imask(bank, d->hwirq, true);
144}
145
146static void brcmstb_gpio_irq_ack(struct irq_data *d)
147{
148 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
149 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
150 struct brcmstb_gpio_priv *priv = bank->parent_priv;
151 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
152
153 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
154}
155
156static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
157{
158 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
159 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
160 struct brcmstb_gpio_priv *priv = bank->parent_priv;
161 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
162 u32 edge_insensitive, iedge_insensitive;
163 u32 edge_config, iedge_config;
164 u32 level, ilevel;
165 unsigned long flags;
166
167 switch (type) {
168 case IRQ_TYPE_LEVEL_LOW:
169 level = mask;
170 edge_config = 0;
171 edge_insensitive = 0;
172 break;
173 case IRQ_TYPE_LEVEL_HIGH:
174 level = mask;
175 edge_config = mask;
176 edge_insensitive = 0;
177 break;
178 case IRQ_TYPE_EDGE_FALLING:
179 level = 0;
180 edge_config = 0;
181 edge_insensitive = 0;
182 break;
183 case IRQ_TYPE_EDGE_RISING:
184 level = 0;
185 edge_config = mask;
186 edge_insensitive = 0;
187 break;
188 case IRQ_TYPE_EDGE_BOTH:
189 level = 0;
190 edge_config = 0; /* don't care, but want known value */
191 edge_insensitive = mask;
192 break;
193 default:
194 return -EINVAL;
195 }
196
197 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
198
199 iedge_config = bank->gc.read_reg(priv->reg_base +
200 GIO_EC(bank->id)) & ~mask;
201 iedge_insensitive = bank->gc.read_reg(priv->reg_base +
202 GIO_EI(bank->id)) & ~mask;
203 ilevel = bank->gc.read_reg(priv->reg_base +
204 GIO_LEVEL(bank->id)) & ~mask;
205
206 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
207 iedge_config | edge_config);
208 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
209 iedge_insensitive | edge_insensitive);
210 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
211 ilevel | level);
212
213 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
214 return 0;
215}
216
217static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
218 unsigned int enable)
219{
220 int ret = 0;
221
222 if (enable)
223 ret = enable_irq_wake(priv->parent_wake_irq);
224 else
225 ret = disable_irq_wake(priv->parent_wake_irq);
226 if (ret)
227 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
228 enable ? "enable" : "disable");
229 return ret;
230}
231
232static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
233{
234 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
235 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
236 struct brcmstb_gpio_priv *priv = bank->parent_priv;
237 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
238
239 /*
240 * Do not do anything specific for now, suspend/resume callbacks will
241 * configure the interrupt mask appropriately
242 */
243 if (enable)
244 bank->wake_active |= mask;
245 else
246 bank->wake_active &= ~mask;
247
248 return brcmstb_gpio_priv_set_wake(priv, enable);
249}
250
251static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
252{
253 struct brcmstb_gpio_priv *priv = data;
254
255 if (!priv || irq != priv->parent_wake_irq)
256 return IRQ_NONE;
257
258 /* Nothing to do */
259 return IRQ_HANDLED;
260}
261
262static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
263{
264 struct brcmstb_gpio_priv *priv = bank->parent_priv;
265 struct irq_domain *domain = priv->irq_domain;
266 int hwbase = bank->gc.base - priv->gpio_base;
267 unsigned long status;
268
269 while ((status = brcmstb_gpio_get_active_irqs(bank))) {
270 unsigned int offset;
271
272 for_each_set_bit(offset, &status, 32) {
273 if (offset >= bank->width)
274 dev_warn(&priv->pdev->dev,
275 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
276 bank->id, offset);
277 generic_handle_domain_irq(domain, hwbase + offset);
278 }
279 }
280}
281
282/* Each UPG GIO block has one IRQ for all banks */
283static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
284{
285 struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
286 struct irq_chip *chip = irq_desc_get_chip(desc);
287 struct brcmstb_gpio_bank *bank;
288
289 /* Interrupts weren't properly cleared during probe */
290 BUG_ON(!priv || !chip);
291
292 chained_irq_enter(chip, desc);
293 list_for_each_entry(bank, &priv->bank_list, node)
294 brcmstb_gpio_irq_bank_handler(bank);
295 chained_irq_exit(chip, desc);
296}
297
298static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
299 struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
300{
301 struct brcmstb_gpio_bank *bank;
302 int i = 0;
303
304 /* banks are in descending order */
305 list_for_each_entry_reverse(bank, &priv->bank_list, node) {
306 i += bank->gc.ngpio;
307 if (hwirq < i)
308 return bank;
309 }
310 return NULL;
311}
312
313/*
314 * This lock class tells lockdep that GPIO irqs are in a different
315 * category than their parents, so it won't report false recursion.
316 */
317static struct lock_class_key brcmstb_gpio_irq_lock_class;
318static struct lock_class_key brcmstb_gpio_irq_request_class;
319
320
321static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
322 irq_hw_number_t hwirq)
323{
324 struct brcmstb_gpio_priv *priv = d->host_data;
325 struct brcmstb_gpio_bank *bank =
326 brcmstb_gpio_hwirq_to_bank(priv, hwirq);
327 struct platform_device *pdev = priv->pdev;
328 int ret;
329
330 if (!bank)
331 return -EINVAL;
332
333 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
334 irq, (int)hwirq, bank->id);
335 ret = irq_set_chip_data(irq, &bank->gc);
336 if (ret < 0)
337 return ret;
338 irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
339 &brcmstb_gpio_irq_request_class);
340 irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
341 irq_set_noprobe(irq);
342 return 0;
343}
344
345static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
346{
347 irq_set_chip_and_handler(irq, NULL, NULL);
348 irq_set_chip_data(irq, NULL);
349}
350
351static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
352 .map = brcmstb_gpio_irq_map,
353 .unmap = brcmstb_gpio_irq_unmap,
354 .xlate = irq_domain_xlate_twocell,
355};
356
357/* Make sure that the number of banks matches up between properties */
358static int brcmstb_gpio_sanity_check_banks(struct device *dev,
359 struct device_node *np, struct resource *res)
360{
361 int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
362 int num_banks =
363 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
364
365 if (res_num_banks != num_banks) {
366 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
367 res_num_banks, num_banks);
368 return -EINVAL;
369 } else {
370 return 0;
371 }
372}
373
374static int brcmstb_gpio_remove(struct platform_device *pdev)
375{
376 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
377 struct brcmstb_gpio_bank *bank;
378 int offset, virq;
379
380 if (priv->parent_irq > 0)
381 irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
382
383 /* Remove all IRQ mappings and delete the domain */
384 if (priv->irq_domain) {
385 for (offset = 0; offset < priv->num_gpios; offset++) {
386 virq = irq_find_mapping(priv->irq_domain, offset);
387 irq_dispose_mapping(virq);
388 }
389 irq_domain_remove(priv->irq_domain);
390 }
391
392 /*
393 * You can lose return values below, but we report all errors, and it's
394 * more important to actually perform all of the steps.
395 */
396 list_for_each_entry(bank, &priv->bank_list, node)
397 gpiochip_remove(&bank->gc);
398
399 return 0;
400}
401
402static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
403 const struct of_phandle_args *gpiospec, u32 *flags)
404{
405 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
406 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
407 int offset;
408
409 if (gc->of_gpio_n_cells != 2) {
410 WARN_ON(1);
411 return -EINVAL;
412 }
413
414 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
415 return -EINVAL;
416
417 offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
418 if (offset >= gc->ngpio || offset < 0)
419 return -EINVAL;
420
421 if (unlikely(offset >= bank->width)) {
422 dev_warn_ratelimited(&priv->pdev->dev,
423 "Received request for invalid GPIO offset %d\n",
424 gpiospec->args[0]);
425 }
426
427 if (flags)
428 *flags = gpiospec->args[1];
429
430 return offset;
431}
432
433/* priv->parent_irq and priv->num_gpios must be set before calling */
434static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
435 struct brcmstb_gpio_priv *priv)
436{
437 struct device *dev = &pdev->dev;
438 struct device_node *np = dev->of_node;
439 int err;
440
441 priv->irq_domain =
442 irq_domain_add_linear(np, priv->num_gpios,
443 &brcmstb_gpio_irq_domain_ops,
444 priv);
445 if (!priv->irq_domain) {
446 dev_err(dev, "Couldn't allocate IRQ domain\n");
447 return -ENXIO;
448 }
449
450 if (of_property_read_bool(np, "wakeup-source")) {
451 priv->parent_wake_irq = platform_get_irq(pdev, 1);
452 if (priv->parent_wake_irq < 0) {
453 priv->parent_wake_irq = 0;
454 dev_warn(dev,
455 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
456 } else {
457 /*
458 * Set wakeup capability so we can process boot-time
459 * "wakeups" (e.g., from S5 cold boot)
460 */
461 device_set_wakeup_capable(dev, true);
462 device_wakeup_enable(dev);
463 err = devm_request_irq(dev, priv->parent_wake_irq,
464 brcmstb_gpio_wake_irq_handler,
465 IRQF_SHARED,
466 "brcmstb-gpio-wake", priv);
467
468 if (err < 0) {
469 dev_err(dev, "Couldn't request wake IRQ");
470 goto out_free_domain;
471 }
472 }
473 }
474
475 priv->irq_chip.name = dev_name(dev);
476 priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
477 priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
478 priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
479 priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
480 priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
481
482 if (priv->parent_wake_irq)
483 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
484
485 irq_set_chained_handler_and_data(priv->parent_irq,
486 brcmstb_gpio_irq_handler, priv);
487 irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
488
489 return 0;
490
491out_free_domain:
492 irq_domain_remove(priv->irq_domain);
493
494 return err;
495}
496
497static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
498 struct brcmstb_gpio_bank *bank)
499{
500 struct gpio_chip *gc = &bank->gc;
501 unsigned int i;
502
503 for (i = 0; i < GIO_REG_STAT; i++)
504 bank->saved_regs[i] = gc->read_reg(priv->reg_base +
505 GIO_BANK_OFF(bank->id, i));
506}
507
508static void brcmstb_gpio_quiesce(struct device *dev, bool save)
509{
510 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
511 struct brcmstb_gpio_bank *bank;
512 struct gpio_chip *gc;
513 u32 imask;
514
515 /* disable non-wake interrupt */
516 if (priv->parent_irq >= 0)
517 disable_irq(priv->parent_irq);
518
519 list_for_each_entry(bank, &priv->bank_list, node) {
520 gc = &bank->gc;
521
522 if (save)
523 brcmstb_gpio_bank_save(priv, bank);
524
525 /* Unmask GPIOs which have been flagged as wake-up sources */
526 if (priv->parent_wake_irq)
527 imask = bank->wake_active;
528 else
529 imask = 0;
530 gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
531 imask);
532 }
533}
534
535static void brcmstb_gpio_shutdown(struct platform_device *pdev)
536{
537 /* Enable GPIO for S5 cold boot */
538 brcmstb_gpio_quiesce(&pdev->dev, false);
539}
540
541#ifdef CONFIG_PM_SLEEP
542static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
543 struct brcmstb_gpio_bank *bank)
544{
545 struct gpio_chip *gc = &bank->gc;
546 unsigned int i;
547
548 for (i = 0; i < GIO_REG_STAT; i++)
549 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
550 bank->saved_regs[i]);
551}
552
553static int brcmstb_gpio_suspend(struct device *dev)
554{
555 brcmstb_gpio_quiesce(dev, true);
556 return 0;
557}
558
559static int brcmstb_gpio_resume(struct device *dev)
560{
561 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
562 struct brcmstb_gpio_bank *bank;
563 bool need_wakeup_event = false;
564
565 list_for_each_entry(bank, &priv->bank_list, node) {
566 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
567 brcmstb_gpio_bank_restore(priv, bank);
568 }
569
570 if (priv->parent_wake_irq && need_wakeup_event)
571 pm_wakeup_event(dev, 0);
572
573 /* enable non-wake interrupt */
574 if (priv->parent_irq >= 0)
575 enable_irq(priv->parent_irq);
576
577 return 0;
578}
579
580#else
581#define brcmstb_gpio_suspend NULL
582#define brcmstb_gpio_resume NULL
583#endif /* CONFIG_PM_SLEEP */
584
585static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
586 .suspend_noirq = brcmstb_gpio_suspend,
587 .resume_noirq = brcmstb_gpio_resume,
588};
589
590static int brcmstb_gpio_probe(struct platform_device *pdev)
591{
592 struct device *dev = &pdev->dev;
593 struct device_node *np = dev->of_node;
594 void __iomem *reg_base;
595 struct brcmstb_gpio_priv *priv;
596 struct resource *res;
597 struct property *prop;
598 const __be32 *p;
599 u32 bank_width;
600 int num_banks = 0;
601 int err;
602 static int gpio_base;
603 unsigned long flags = 0;
604 bool need_wakeup_event = false;
605
606 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
607 if (!priv)
608 return -ENOMEM;
609 platform_set_drvdata(pdev, priv);
610 INIT_LIST_HEAD(&priv->bank_list);
611
612 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
613 reg_base = devm_ioremap_resource(dev, res);
614 if (IS_ERR(reg_base))
615 return PTR_ERR(reg_base);
616
617 priv->gpio_base = gpio_base;
618 priv->reg_base = reg_base;
619 priv->pdev = pdev;
620
621 if (of_property_read_bool(np, "interrupt-controller")) {
622 priv->parent_irq = platform_get_irq(pdev, 0);
623 if (priv->parent_irq <= 0)
624 return -ENOENT;
625 } else {
626 priv->parent_irq = -ENOENT;
627 }
628
629 if (brcmstb_gpio_sanity_check_banks(dev, np, res))
630 return -EINVAL;
631
632 /*
633 * MIPS endianness is configured by boot strap, which also reverses all
634 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
635 * endian I/O).
636 *
637 * Other architectures (e.g., ARM) either do not support big endian, or
638 * else leave I/O in little endian mode.
639 */
640#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
641 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
642#endif
643
644 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
645 bank_width) {
646 struct brcmstb_gpio_bank *bank;
647 struct gpio_chip *gc;
648
649 /*
650 * If bank_width is 0, then there is an empty bank in the
651 * register block. Special handling for this case.
652 */
653 if (bank_width == 0) {
654 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
655 num_banks);
656 num_banks++;
657 gpio_base += MAX_GPIO_PER_BANK;
658 continue;
659 }
660
661 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
662 if (!bank) {
663 err = -ENOMEM;
664 goto fail;
665 }
666
667 bank->parent_priv = priv;
668 bank->id = num_banks;
669 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
670 dev_err(dev, "Invalid bank width %d\n", bank_width);
671 err = -EINVAL;
672 goto fail;
673 } else {
674 bank->width = bank_width;
675 }
676
677 /*
678 * Regs are 4 bytes wide, have data reg, no set/clear regs,
679 * and direction bits have 0 = output and 1 = input
680 */
681 gc = &bank->gc;
682 err = bgpio_init(gc, dev, 4,
683 reg_base + GIO_DATA(bank->id),
684 NULL, NULL, NULL,
685 reg_base + GIO_IODIR(bank->id), flags);
686 if (err) {
687 dev_err(dev, "bgpio_init() failed\n");
688 goto fail;
689 }
690
691 gc->owner = THIS_MODULE;
692 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
693 if (!gc->label) {
694 err = -ENOMEM;
695 goto fail;
696 }
697 gc->base = gpio_base;
698 gc->of_gpio_n_cells = 2;
699 gc->of_xlate = brcmstb_gpio_of_xlate;
700 /* not all ngpio lines are valid, will use bank width later */
701 gc->ngpio = MAX_GPIO_PER_BANK;
702 gc->offset = bank->id * MAX_GPIO_PER_BANK;
703 if (priv->parent_irq > 0)
704 gc->to_irq = brcmstb_gpio_to_irq;
705
706 /*
707 * Mask all interrupts by default, since wakeup interrupts may
708 * be retained from S5 cold boot
709 */
710 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
711 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
712
713 err = gpiochip_add_data(gc, bank);
714 if (err) {
715 dev_err(dev, "Could not add gpiochip for bank %d\n",
716 bank->id);
717 goto fail;
718 }
719 gpio_base += gc->ngpio;
720
721 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
722 gc->base, gc->ngpio, bank->width);
723
724 /* Everything looks good, so add bank to list */
725 list_add(&bank->node, &priv->bank_list);
726
727 num_banks++;
728 }
729
730 priv->num_gpios = gpio_base - priv->gpio_base;
731 if (priv->parent_irq > 0) {
732 err = brcmstb_gpio_irq_setup(pdev, priv);
733 if (err)
734 goto fail;
735 }
736
737 if (priv->parent_wake_irq && need_wakeup_event)
738 pm_wakeup_event(dev, 0);
739
740 return 0;
741
742fail:
743 (void) brcmstb_gpio_remove(pdev);
744 return err;
745}
746
747static const struct of_device_id brcmstb_gpio_of_match[] = {
748 { .compatible = "brcm,brcmstb-gpio" },
749 {},
750};
751
752MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
753
754static struct platform_driver brcmstb_gpio_driver = {
755 .driver = {
756 .name = "brcmstb-gpio",
757 .of_match_table = brcmstb_gpio_of_match,
758 .pm = &brcmstb_gpio_pm_ops,
759 },
760 .probe = brcmstb_gpio_probe,
761 .remove = brcmstb_gpio_remove,
762 .shutdown = brcmstb_gpio_shutdown,
763};
764module_platform_driver(brcmstb_gpio_driver);
765
766MODULE_AUTHOR("Gregory Fong");
767MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
768MODULE_LICENSE("GPL v2");