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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
4 * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
5 */
6
7#include <linux/clk.h>
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/slab.h>
15#include <linux/spinlock.h>
16
17#include "clk-stm32-core.h"
18#include "reset-stm32.h"
19
20static DEFINE_SPINLOCK(rlock);
21
22static int stm32_rcc_clock_init(struct device *dev,
23 const struct of_device_id *match,
24 void __iomem *base)
25{
26 const struct stm32_rcc_match_data *data = match->data;
27 struct clk_hw_onecell_data *clk_data = data->hw_clks;
28 struct clk_hw **hws;
29 int n, max_binding;
30
31 max_binding = data->maxbinding;
32
33 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding), GFP_KERNEL);
34 if (!clk_data)
35 return -ENOMEM;
36
37 clk_data->num = max_binding;
38
39 hws = clk_data->hws;
40
41 for (n = 0; n < max_binding; n++)
42 hws[n] = ERR_PTR(-ENOENT);
43
44 for (n = 0; n < data->num_clocks; n++) {
45 const struct clock_config *cfg_clock = &data->tab_clocks[n];
46 struct clk_hw *hw = ERR_PTR(-ENOENT);
47
48 if (data->check_security &&
49 data->check_security(dev->of_node, base, cfg_clock))
50 continue;
51
52 if (cfg_clock->func)
53 hw = (*cfg_clock->func)(dev, data, base, &rlock,
54 cfg_clock);
55
56 if (IS_ERR(hw)) {
57 dev_err(dev, "Can't register clk %d: %ld\n", n,
58 PTR_ERR(hw));
59 return PTR_ERR(hw);
60 }
61
62 if (cfg_clock->id != NO_ID)
63 hws[cfg_clock->id] = hw;
64 }
65
66 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
67}
68
69int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
70 void __iomem *base)
71{
72 const struct stm32_rcc_match_data *rcc_match_data;
73 const struct of_device_id *match;
74 int err;
75
76 match = of_match_node(match_data, dev_of_node(dev));
77 if (!match) {
78 dev_err(dev, "match data not found\n");
79 return -ENODEV;
80 }
81
82 rcc_match_data = match->data;
83
84 /* RCC Reset Configuration */
85 err = stm32_rcc_reset_init(dev, rcc_match_data->reset_data, base);
86 if (err) {
87 pr_err("stm32 reset failed to initialize\n");
88 return err;
89 }
90
91 /* RCC Clock Configuration */
92 err = stm32_rcc_clock_init(dev, match, base);
93 if (err) {
94 pr_err("stm32 clock failed to initialize\n");
95 return err;
96 }
97
98 return 0;
99}
100
101static u8 stm32_mux_get_parent(void __iomem *base,
102 struct clk_stm32_clock_data *data,
103 u16 mux_id)
104{
105 const struct stm32_mux_cfg *mux = &data->muxes[mux_id];
106 u32 mask = BIT(mux->width) - 1;
107 u32 val;
108
109 val = readl(base + mux->offset) >> mux->shift;
110 val &= mask;
111
112 return val;
113}
114
115static int stm32_mux_set_parent(void __iomem *base,
116 struct clk_stm32_clock_data *data,
117 u16 mux_id, u8 index)
118{
119 const struct stm32_mux_cfg *mux = &data->muxes[mux_id];
120
121 u32 mask = BIT(mux->width) - 1;
122 u32 reg = readl(base + mux->offset);
123 u32 val = index << mux->shift;
124
125 reg &= ~(mask << mux->shift);
126 reg |= val;
127
128 writel(reg, base + mux->offset);
129
130 return 0;
131}
132
133static void stm32_gate_endisable(void __iomem *base,
134 struct clk_stm32_clock_data *data,
135 u16 gate_id, int enable)
136{
137 const struct stm32_gate_cfg *gate = &data->gates[gate_id];
138 void __iomem *addr = base + gate->offset;
139
140 if (enable) {
141 if (data->gate_cpt[gate_id]++ > 0)
142 return;
143
144 if (gate->set_clr != 0)
145 writel(BIT(gate->bit_idx), addr);
146 else
147 writel(readl(addr) | BIT(gate->bit_idx), addr);
148 } else {
149 if (--data->gate_cpt[gate_id] > 0)
150 return;
151
152 if (gate->set_clr != 0)
153 writel(BIT(gate->bit_idx), addr + gate->set_clr);
154 else
155 writel(readl(addr) & ~BIT(gate->bit_idx), addr);
156 }
157}
158
159static void stm32_gate_disable_unused(void __iomem *base,
160 struct clk_stm32_clock_data *data,
161 u16 gate_id)
162{
163 const struct stm32_gate_cfg *gate = &data->gates[gate_id];
164 void __iomem *addr = base + gate->offset;
165
166 if (data->gate_cpt[gate_id] > 0)
167 return;
168
169 if (gate->set_clr != 0)
170 writel(BIT(gate->bit_idx), addr + gate->set_clr);
171 else
172 writel(readl(addr) & ~BIT(gate->bit_idx), addr);
173}
174
175static int stm32_gate_is_enabled(void __iomem *base,
176 struct clk_stm32_clock_data *data,
177 u16 gate_id)
178{
179 const struct stm32_gate_cfg *gate = &data->gates[gate_id];
180
181 return (readl(base + gate->offset) & BIT(gate->bit_idx)) != 0;
182}
183
184static unsigned int _get_table_div(const struct clk_div_table *table,
185 unsigned int val)
186{
187 const struct clk_div_table *clkt;
188
189 for (clkt = table; clkt->div; clkt++)
190 if (clkt->val == val)
191 return clkt->div;
192 return 0;
193}
194
195static unsigned int _get_div(const struct clk_div_table *table,
196 unsigned int val, unsigned long flags, u8 width)
197{
198 if (flags & CLK_DIVIDER_ONE_BASED)
199 return val;
200 if (flags & CLK_DIVIDER_POWER_OF_TWO)
201 return 1 << val;
202 if (table)
203 return _get_table_div(table, val);
204 return val + 1;
205}
206
207static unsigned long stm32_divider_get_rate(void __iomem *base,
208 struct clk_stm32_clock_data *data,
209 u16 div_id,
210 unsigned long parent_rate)
211{
212 const struct stm32_div_cfg *divider = &data->dividers[div_id];
213 unsigned int val;
214 unsigned int div;
215
216 val = readl(base + divider->offset) >> divider->shift;
217 val &= clk_div_mask(divider->width);
218 div = _get_div(divider->table, val, divider->flags, divider->width);
219
220 if (!div) {
221 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
222 "%d: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
223 div_id);
224 return parent_rate;
225 }
226
227 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
228}
229
230static int stm32_divider_set_rate(void __iomem *base,
231 struct clk_stm32_clock_data *data,
232 u16 div_id, unsigned long rate,
233 unsigned long parent_rate)
234{
235 const struct stm32_div_cfg *divider = &data->dividers[div_id];
236 int value;
237 u32 val;
238
239 value = divider_get_val(rate, parent_rate, divider->table,
240 divider->width, divider->flags);
241 if (value < 0)
242 return value;
243
244 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
245 val = clk_div_mask(divider->width) << (divider->shift + 16);
246 } else {
247 val = readl(base + divider->offset);
248 val &= ~(clk_div_mask(divider->width) << divider->shift);
249 }
250
251 val |= (u32)value << divider->shift;
252
253 writel(val, base + divider->offset);
254
255 return 0;
256}
257
258static u8 clk_stm32_mux_get_parent(struct clk_hw *hw)
259{
260 struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
261
262 return stm32_mux_get_parent(mux->base, mux->clock_data, mux->mux_id);
263}
264
265static int clk_stm32_mux_set_parent(struct clk_hw *hw, u8 index)
266{
267 struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
268 unsigned long flags = 0;
269
270 spin_lock_irqsave(mux->lock, flags);
271
272 stm32_mux_set_parent(mux->base, mux->clock_data, mux->mux_id, index);
273
274 spin_unlock_irqrestore(mux->lock, flags);
275
276 return 0;
277}
278
279const struct clk_ops clk_stm32_mux_ops = {
280 .determine_rate = __clk_mux_determine_rate,
281 .get_parent = clk_stm32_mux_get_parent,
282 .set_parent = clk_stm32_mux_set_parent,
283};
284
285static void clk_stm32_gate_endisable(struct clk_hw *hw, int enable)
286{
287 struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
288 unsigned long flags = 0;
289
290 spin_lock_irqsave(gate->lock, flags);
291
292 stm32_gate_endisable(gate->base, gate->clock_data, gate->gate_id, enable);
293
294 spin_unlock_irqrestore(gate->lock, flags);
295}
296
297static int clk_stm32_gate_enable(struct clk_hw *hw)
298{
299 clk_stm32_gate_endisable(hw, 1);
300
301 return 0;
302}
303
304static void clk_stm32_gate_disable(struct clk_hw *hw)
305{
306 clk_stm32_gate_endisable(hw, 0);
307}
308
309static int clk_stm32_gate_is_enabled(struct clk_hw *hw)
310{
311 struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
312
313 return stm32_gate_is_enabled(gate->base, gate->clock_data, gate->gate_id);
314}
315
316static void clk_stm32_gate_disable_unused(struct clk_hw *hw)
317{
318 struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
319 unsigned long flags = 0;
320
321 spin_lock_irqsave(gate->lock, flags);
322
323 stm32_gate_disable_unused(gate->base, gate->clock_data, gate->gate_id);
324
325 spin_unlock_irqrestore(gate->lock, flags);
326}
327
328const struct clk_ops clk_stm32_gate_ops = {
329 .enable = clk_stm32_gate_enable,
330 .disable = clk_stm32_gate_disable,
331 .is_enabled = clk_stm32_gate_is_enabled,
332 .disable_unused = clk_stm32_gate_disable_unused,
333};
334
335static int clk_stm32_divider_set_rate(struct clk_hw *hw, unsigned long rate,
336 unsigned long parent_rate)
337{
338 struct clk_stm32_div *div = to_clk_stm32_divider(hw);
339 unsigned long flags = 0;
340 int ret;
341
342 if (div->div_id == NO_STM32_DIV)
343 return rate;
344
345 spin_lock_irqsave(div->lock, flags);
346
347 ret = stm32_divider_set_rate(div->base, div->clock_data, div->div_id, rate, parent_rate);
348
349 spin_unlock_irqrestore(div->lock, flags);
350
351 return ret;
352}
353
354static long clk_stm32_divider_round_rate(struct clk_hw *hw, unsigned long rate,
355 unsigned long *prate)
356{
357 struct clk_stm32_div *div = to_clk_stm32_divider(hw);
358 const struct stm32_div_cfg *divider;
359
360 if (div->div_id == NO_STM32_DIV)
361 return rate;
362
363 divider = &div->clock_data->dividers[div->div_id];
364
365 /* if read only, just return current value */
366 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
367 u32 val;
368
369 val = readl(div->base + divider->offset) >> divider->shift;
370 val &= clk_div_mask(divider->width);
371
372 return divider_ro_round_rate(hw, rate, prate, divider->table,
373 divider->width, divider->flags,
374 val);
375 }
376
377 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
378 rate, prate, divider->table,
379 divider->width, divider->flags);
380}
381
382static unsigned long clk_stm32_divider_recalc_rate(struct clk_hw *hw,
383 unsigned long parent_rate)
384{
385 struct clk_stm32_div *div = to_clk_stm32_divider(hw);
386
387 if (div->div_id == NO_STM32_DIV)
388 return parent_rate;
389
390 return stm32_divider_get_rate(div->base, div->clock_data, div->div_id, parent_rate);
391}
392
393const struct clk_ops clk_stm32_divider_ops = {
394 .recalc_rate = clk_stm32_divider_recalc_rate,
395 .round_rate = clk_stm32_divider_round_rate,
396 .set_rate = clk_stm32_divider_set_rate,
397};
398
399static int clk_stm32_composite_set_rate(struct clk_hw *hw, unsigned long rate,
400 unsigned long parent_rate)
401{
402 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
403 unsigned long flags = 0;
404 int ret;
405
406 if (composite->div_id == NO_STM32_DIV)
407 return rate;
408
409 spin_lock_irqsave(composite->lock, flags);
410
411 ret = stm32_divider_set_rate(composite->base, composite->clock_data,
412 composite->div_id, rate, parent_rate);
413
414 spin_unlock_irqrestore(composite->lock, flags);
415
416 return ret;
417}
418
419static unsigned long clk_stm32_composite_recalc_rate(struct clk_hw *hw,
420 unsigned long parent_rate)
421{
422 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
423
424 if (composite->div_id == NO_STM32_DIV)
425 return parent_rate;
426
427 return stm32_divider_get_rate(composite->base, composite->clock_data,
428 composite->div_id, parent_rate);
429}
430
431static int clk_stm32_composite_determine_rate(struct clk_hw *hw,
432 struct clk_rate_request *req)
433{
434 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
435 const struct stm32_div_cfg *divider;
436 long rate;
437
438 if (composite->div_id == NO_STM32_DIV)
439 return 0;
440
441 divider = &composite->clock_data->dividers[composite->div_id];
442
443 /* if read only, just return current value */
444 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
445 u32 val;
446
447 val = readl(composite->base + divider->offset) >> divider->shift;
448 val &= clk_div_mask(divider->width);
449
450 rate = divider_ro_round_rate(hw, req->rate, &req->best_parent_rate,
451 divider->table, divider->width, divider->flags,
452 val);
453 if (rate < 0)
454 return rate;
455
456 req->rate = rate;
457 return 0;
458 }
459
460 rate = divider_round_rate_parent(hw, clk_hw_get_parent(hw),
461 req->rate, &req->best_parent_rate,
462 divider->table, divider->width, divider->flags);
463 if (rate < 0)
464 return rate;
465
466 req->rate = rate;
467 return 0;
468}
469
470static u8 clk_stm32_composite_get_parent(struct clk_hw *hw)
471{
472 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
473
474 return stm32_mux_get_parent(composite->base, composite->clock_data, composite->mux_id);
475}
476
477static int clk_stm32_composite_set_parent(struct clk_hw *hw, u8 index)
478{
479 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
480 unsigned long flags = 0;
481
482 spin_lock_irqsave(composite->lock, flags);
483
484 stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, index);
485
486 spin_unlock_irqrestore(composite->lock, flags);
487
488 if (composite->clock_data->is_multi_mux) {
489 struct clk_hw *other_mux_hw = composite->clock_data->is_multi_mux(hw);
490
491 if (other_mux_hw) {
492 struct clk_hw *hwp = clk_hw_get_parent_by_index(hw, index);
493
494 clk_hw_reparent(other_mux_hw, hwp);
495 }
496 }
497
498 return 0;
499}
500
501static int clk_stm32_composite_is_enabled(struct clk_hw *hw)
502{
503 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
504
505 if (composite->gate_id == NO_STM32_GATE)
506 return (__clk_get_enable_count(hw->clk) > 0);
507
508 return stm32_gate_is_enabled(composite->base, composite->clock_data, composite->gate_id);
509}
510
511#define MUX_SAFE_POSITION 0
512
513static int clk_stm32_has_safe_mux(struct clk_hw *hw)
514{
515 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
516 const struct stm32_mux_cfg *mux = &composite->clock_data->muxes[composite->mux_id];
517
518 return !!(mux->flags & MUX_SAFE);
519}
520
521static void clk_stm32_set_safe_position_mux(struct clk_hw *hw)
522{
523 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
524
525 if (!clk_stm32_composite_is_enabled(hw)) {
526 unsigned long flags = 0;
527
528 if (composite->clock_data->is_multi_mux) {
529 struct clk_hw *other_mux_hw = NULL;
530
531 other_mux_hw = composite->clock_data->is_multi_mux(hw);
532
533 if (!other_mux_hw || clk_stm32_composite_is_enabled(other_mux_hw))
534 return;
535 }
536
537 spin_lock_irqsave(composite->lock, flags);
538
539 stm32_mux_set_parent(composite->base, composite->clock_data,
540 composite->mux_id, MUX_SAFE_POSITION);
541
542 spin_unlock_irqrestore(composite->lock, flags);
543 }
544}
545
546static void clk_stm32_safe_restore_position_mux(struct clk_hw *hw)
547{
548 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
549 int sel = clk_hw_get_parent_index(hw);
550 unsigned long flags = 0;
551
552 spin_lock_irqsave(composite->lock, flags);
553
554 stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, sel);
555
556 spin_unlock_irqrestore(composite->lock, flags);
557}
558
559static void clk_stm32_composite_gate_endisable(struct clk_hw *hw, int enable)
560{
561 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
562 unsigned long flags = 0;
563
564 spin_lock_irqsave(composite->lock, flags);
565
566 stm32_gate_endisable(composite->base, composite->clock_data, composite->gate_id, enable);
567
568 spin_unlock_irqrestore(composite->lock, flags);
569}
570
571static int clk_stm32_composite_gate_enable(struct clk_hw *hw)
572{
573 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
574
575 if (composite->gate_id == NO_STM32_GATE)
576 return 0;
577
578 clk_stm32_composite_gate_endisable(hw, 1);
579
580 if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))
581 clk_stm32_safe_restore_position_mux(hw);
582
583 return 0;
584}
585
586static void clk_stm32_composite_gate_disable(struct clk_hw *hw)
587{
588 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
589
590 if (composite->gate_id == NO_STM32_GATE)
591 return;
592
593 clk_stm32_composite_gate_endisable(hw, 0);
594
595 if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))
596 clk_stm32_set_safe_position_mux(hw);
597}
598
599static void clk_stm32_composite_disable_unused(struct clk_hw *hw)
600{
601 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
602 unsigned long flags = 0;
603
604 if (composite->gate_id == NO_STM32_GATE)
605 return;
606
607 spin_lock_irqsave(composite->lock, flags);
608
609 stm32_gate_disable_unused(composite->base, composite->clock_data, composite->gate_id);
610
611 spin_unlock_irqrestore(composite->lock, flags);
612}
613
614const struct clk_ops clk_stm32_composite_ops = {
615 .set_rate = clk_stm32_composite_set_rate,
616 .recalc_rate = clk_stm32_composite_recalc_rate,
617 .determine_rate = clk_stm32_composite_determine_rate,
618 .get_parent = clk_stm32_composite_get_parent,
619 .set_parent = clk_stm32_composite_set_parent,
620 .enable = clk_stm32_composite_gate_enable,
621 .disable = clk_stm32_composite_gate_disable,
622 .is_enabled = clk_stm32_composite_is_enabled,
623 .disable_unused = clk_stm32_composite_disable_unused,
624};
625
626struct clk_hw *clk_stm32_mux_register(struct device *dev,
627 const struct stm32_rcc_match_data *data,
628 void __iomem *base,
629 spinlock_t *lock,
630 const struct clock_config *cfg)
631{
632 struct clk_stm32_mux *mux = cfg->clock_cfg;
633 struct clk_hw *hw = &mux->hw;
634 int err;
635
636 mux->base = base;
637 mux->lock = lock;
638 mux->clock_data = data->clock_data;
639
640 err = devm_clk_hw_register(dev, hw);
641 if (err)
642 return ERR_PTR(err);
643
644 return hw;
645}
646
647struct clk_hw *clk_stm32_gate_register(struct device *dev,
648 const struct stm32_rcc_match_data *data,
649 void __iomem *base,
650 spinlock_t *lock,
651 const struct clock_config *cfg)
652{
653 struct clk_stm32_gate *gate = cfg->clock_cfg;
654 struct clk_hw *hw = &gate->hw;
655 int err;
656
657 gate->base = base;
658 gate->lock = lock;
659 gate->clock_data = data->clock_data;
660
661 err = devm_clk_hw_register(dev, hw);
662 if (err)
663 return ERR_PTR(err);
664
665 return hw;
666}
667
668struct clk_hw *clk_stm32_div_register(struct device *dev,
669 const struct stm32_rcc_match_data *data,
670 void __iomem *base,
671 spinlock_t *lock,
672 const struct clock_config *cfg)
673{
674 struct clk_stm32_div *div = cfg->clock_cfg;
675 struct clk_hw *hw = &div->hw;
676 int err;
677
678 div->base = base;
679 div->lock = lock;
680 div->clock_data = data->clock_data;
681
682 err = devm_clk_hw_register(dev, hw);
683 if (err)
684 return ERR_PTR(err);
685
686 return hw;
687}
688
689struct clk_hw *clk_stm32_composite_register(struct device *dev,
690 const struct stm32_rcc_match_data *data,
691 void __iomem *base,
692 spinlock_t *lock,
693 const struct clock_config *cfg)
694{
695 struct clk_stm32_composite *composite = cfg->clock_cfg;
696 struct clk_hw *hw = &composite->hw;
697 int err;
698
699 composite->base = base;
700 composite->lock = lock;
701 composite->clock_data = data->clock_data;
702
703 err = devm_clk_hw_register(dev, hw);
704 if (err)
705 return ERR_PTR(err);
706
707 return hw;
708}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
4 * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
5 */
6
7#include <linux/clk.h>
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/slab.h>
15#include <linux/spinlock.h>
16
17#include "clk-stm32-core.h"
18#include "reset-stm32.h"
19
20static DEFINE_SPINLOCK(rlock);
21
22static int stm32_rcc_clock_init(struct device *dev,
23 const struct of_device_id *match,
24 void __iomem *base)
25{
26 const struct stm32_rcc_match_data *data = match->data;
27 struct clk_hw_onecell_data *clk_data = data->hw_clks;
28 struct device_node *np = dev_of_node(dev);
29 struct clk_hw **hws;
30 int n, max_binding;
31
32 max_binding = data->maxbinding;
33
34 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding), GFP_KERNEL);
35 if (!clk_data)
36 return -ENOMEM;
37
38 clk_data->num = max_binding;
39
40 hws = clk_data->hws;
41
42 for (n = 0; n < max_binding; n++)
43 hws[n] = ERR_PTR(-ENOENT);
44
45 for (n = 0; n < data->num_clocks; n++) {
46 const struct clock_config *cfg_clock = &data->tab_clocks[n];
47 struct clk_hw *hw = ERR_PTR(-ENOENT);
48
49 if (data->check_security &&
50 data->check_security(base, cfg_clock))
51 continue;
52
53 if (cfg_clock->func)
54 hw = (*cfg_clock->func)(dev, data, base, &rlock,
55 cfg_clock);
56
57 if (IS_ERR(hw)) {
58 dev_err(dev, "Can't register clk %d: %ld\n", n,
59 PTR_ERR(hw));
60 return PTR_ERR(hw);
61 }
62
63 if (cfg_clock->id != NO_ID)
64 hws[cfg_clock->id] = hw;
65 }
66
67 return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
68}
69
70int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
71 void __iomem *base)
72{
73 const struct of_device_id *match;
74 int err;
75
76 match = of_match_node(match_data, dev_of_node(dev));
77 if (!match) {
78 dev_err(dev, "match data not found\n");
79 return -ENODEV;
80 }
81
82 /* RCC Reset Configuration */
83 err = stm32_rcc_reset_init(dev, match, base);
84 if (err) {
85 pr_err("stm32 reset failed to initialize\n");
86 return err;
87 }
88
89 /* RCC Clock Configuration */
90 err = stm32_rcc_clock_init(dev, match, base);
91 if (err) {
92 pr_err("stm32 clock failed to initialize\n");
93 return err;
94 }
95
96 return 0;
97}
98
99static u8 stm32_mux_get_parent(void __iomem *base,
100 struct clk_stm32_clock_data *data,
101 u16 mux_id)
102{
103 const struct stm32_mux_cfg *mux = &data->muxes[mux_id];
104 u32 mask = BIT(mux->width) - 1;
105 u32 val;
106
107 val = readl(base + mux->offset) >> mux->shift;
108 val &= mask;
109
110 return val;
111}
112
113static int stm32_mux_set_parent(void __iomem *base,
114 struct clk_stm32_clock_data *data,
115 u16 mux_id, u8 index)
116{
117 const struct stm32_mux_cfg *mux = &data->muxes[mux_id];
118
119 u32 mask = BIT(mux->width) - 1;
120 u32 reg = readl(base + mux->offset);
121 u32 val = index << mux->shift;
122
123 reg &= ~(mask << mux->shift);
124 reg |= val;
125
126 writel(reg, base + mux->offset);
127
128 return 0;
129}
130
131static void stm32_gate_endisable(void __iomem *base,
132 struct clk_stm32_clock_data *data,
133 u16 gate_id, int enable)
134{
135 const struct stm32_gate_cfg *gate = &data->gates[gate_id];
136 void __iomem *addr = base + gate->offset;
137
138 if (enable) {
139 if (data->gate_cpt[gate_id]++ > 0)
140 return;
141
142 if (gate->set_clr != 0)
143 writel(BIT(gate->bit_idx), addr);
144 else
145 writel(readl(addr) | BIT(gate->bit_idx), addr);
146 } else {
147 if (--data->gate_cpt[gate_id] > 0)
148 return;
149
150 if (gate->set_clr != 0)
151 writel(BIT(gate->bit_idx), addr + gate->set_clr);
152 else
153 writel(readl(addr) & ~BIT(gate->bit_idx), addr);
154 }
155}
156
157static void stm32_gate_disable_unused(void __iomem *base,
158 struct clk_stm32_clock_data *data,
159 u16 gate_id)
160{
161 const struct stm32_gate_cfg *gate = &data->gates[gate_id];
162 void __iomem *addr = base + gate->offset;
163
164 if (data->gate_cpt[gate_id] > 0)
165 return;
166
167 if (gate->set_clr != 0)
168 writel(BIT(gate->bit_idx), addr + gate->set_clr);
169 else
170 writel(readl(addr) & ~BIT(gate->bit_idx), addr);
171}
172
173static int stm32_gate_is_enabled(void __iomem *base,
174 struct clk_stm32_clock_data *data,
175 u16 gate_id)
176{
177 const struct stm32_gate_cfg *gate = &data->gates[gate_id];
178
179 return (readl(base + gate->offset) & BIT(gate->bit_idx)) != 0;
180}
181
182static unsigned int _get_table_div(const struct clk_div_table *table,
183 unsigned int val)
184{
185 const struct clk_div_table *clkt;
186
187 for (clkt = table; clkt->div; clkt++)
188 if (clkt->val == val)
189 return clkt->div;
190 return 0;
191}
192
193static unsigned int _get_div(const struct clk_div_table *table,
194 unsigned int val, unsigned long flags, u8 width)
195{
196 if (flags & CLK_DIVIDER_ONE_BASED)
197 return val;
198 if (flags & CLK_DIVIDER_POWER_OF_TWO)
199 return 1 << val;
200 if (table)
201 return _get_table_div(table, val);
202 return val + 1;
203}
204
205static unsigned long stm32_divider_get_rate(void __iomem *base,
206 struct clk_stm32_clock_data *data,
207 u16 div_id,
208 unsigned long parent_rate)
209{
210 const struct stm32_div_cfg *divider = &data->dividers[div_id];
211 unsigned int val;
212 unsigned int div;
213
214 val = readl(base + divider->offset) >> divider->shift;
215 val &= clk_div_mask(divider->width);
216 div = _get_div(divider->table, val, divider->flags, divider->width);
217
218 if (!div) {
219 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
220 "%d: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
221 div_id);
222 return parent_rate;
223 }
224
225 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
226}
227
228static int stm32_divider_set_rate(void __iomem *base,
229 struct clk_stm32_clock_data *data,
230 u16 div_id, unsigned long rate,
231 unsigned long parent_rate)
232{
233 const struct stm32_div_cfg *divider = &data->dividers[div_id];
234 int value;
235 u32 val;
236
237 value = divider_get_val(rate, parent_rate, divider->table,
238 divider->width, divider->flags);
239 if (value < 0)
240 return value;
241
242 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
243 val = clk_div_mask(divider->width) << (divider->shift + 16);
244 } else {
245 val = readl(base + divider->offset);
246 val &= ~(clk_div_mask(divider->width) << divider->shift);
247 }
248
249 val |= (u32)value << divider->shift;
250
251 writel(val, base + divider->offset);
252
253 return 0;
254}
255
256static u8 clk_stm32_mux_get_parent(struct clk_hw *hw)
257{
258 struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
259
260 return stm32_mux_get_parent(mux->base, mux->clock_data, mux->mux_id);
261}
262
263static int clk_stm32_mux_set_parent(struct clk_hw *hw, u8 index)
264{
265 struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
266 unsigned long flags = 0;
267
268 spin_lock_irqsave(mux->lock, flags);
269
270 stm32_mux_set_parent(mux->base, mux->clock_data, mux->mux_id, index);
271
272 spin_unlock_irqrestore(mux->lock, flags);
273
274 return 0;
275}
276
277const struct clk_ops clk_stm32_mux_ops = {
278 .get_parent = clk_stm32_mux_get_parent,
279 .set_parent = clk_stm32_mux_set_parent,
280};
281
282static void clk_stm32_gate_endisable(struct clk_hw *hw, int enable)
283{
284 struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
285 unsigned long flags = 0;
286
287 spin_lock_irqsave(gate->lock, flags);
288
289 stm32_gate_endisable(gate->base, gate->clock_data, gate->gate_id, enable);
290
291 spin_unlock_irqrestore(gate->lock, flags);
292}
293
294static int clk_stm32_gate_enable(struct clk_hw *hw)
295{
296 clk_stm32_gate_endisable(hw, 1);
297
298 return 0;
299}
300
301static void clk_stm32_gate_disable(struct clk_hw *hw)
302{
303 clk_stm32_gate_endisable(hw, 0);
304}
305
306static int clk_stm32_gate_is_enabled(struct clk_hw *hw)
307{
308 struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
309
310 return stm32_gate_is_enabled(gate->base, gate->clock_data, gate->gate_id);
311}
312
313static void clk_stm32_gate_disable_unused(struct clk_hw *hw)
314{
315 struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
316 unsigned long flags = 0;
317
318 spin_lock_irqsave(gate->lock, flags);
319
320 stm32_gate_disable_unused(gate->base, gate->clock_data, gate->gate_id);
321
322 spin_unlock_irqrestore(gate->lock, flags);
323}
324
325const struct clk_ops clk_stm32_gate_ops = {
326 .enable = clk_stm32_gate_enable,
327 .disable = clk_stm32_gate_disable,
328 .is_enabled = clk_stm32_gate_is_enabled,
329 .disable_unused = clk_stm32_gate_disable_unused,
330};
331
332static int clk_stm32_divider_set_rate(struct clk_hw *hw, unsigned long rate,
333 unsigned long parent_rate)
334{
335 struct clk_stm32_div *div = to_clk_stm32_divider(hw);
336 unsigned long flags = 0;
337 int ret;
338
339 if (div->div_id == NO_STM32_DIV)
340 return rate;
341
342 spin_lock_irqsave(div->lock, flags);
343
344 ret = stm32_divider_set_rate(div->base, div->clock_data, div->div_id, rate, parent_rate);
345
346 spin_unlock_irqrestore(div->lock, flags);
347
348 return ret;
349}
350
351static long clk_stm32_divider_round_rate(struct clk_hw *hw, unsigned long rate,
352 unsigned long *prate)
353{
354 struct clk_stm32_div *div = to_clk_stm32_divider(hw);
355 const struct stm32_div_cfg *divider;
356
357 if (div->div_id == NO_STM32_DIV)
358 return rate;
359
360 divider = &div->clock_data->dividers[div->div_id];
361
362 /* if read only, just return current value */
363 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
364 u32 val;
365
366 val = readl(div->base + divider->offset) >> divider->shift;
367 val &= clk_div_mask(divider->width);
368
369 return divider_ro_round_rate(hw, rate, prate, divider->table,
370 divider->width, divider->flags,
371 val);
372 }
373
374 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
375 rate, prate, divider->table,
376 divider->width, divider->flags);
377}
378
379static unsigned long clk_stm32_divider_recalc_rate(struct clk_hw *hw,
380 unsigned long parent_rate)
381{
382 struct clk_stm32_div *div = to_clk_stm32_divider(hw);
383
384 if (div->div_id == NO_STM32_DIV)
385 return parent_rate;
386
387 return stm32_divider_get_rate(div->base, div->clock_data, div->div_id, parent_rate);
388}
389
390const struct clk_ops clk_stm32_divider_ops = {
391 .recalc_rate = clk_stm32_divider_recalc_rate,
392 .round_rate = clk_stm32_divider_round_rate,
393 .set_rate = clk_stm32_divider_set_rate,
394};
395
396static int clk_stm32_composite_set_rate(struct clk_hw *hw, unsigned long rate,
397 unsigned long parent_rate)
398{
399 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
400 unsigned long flags = 0;
401 int ret;
402
403 if (composite->div_id == NO_STM32_DIV)
404 return rate;
405
406 spin_lock_irqsave(composite->lock, flags);
407
408 ret = stm32_divider_set_rate(composite->base, composite->clock_data,
409 composite->div_id, rate, parent_rate);
410
411 spin_unlock_irqrestore(composite->lock, flags);
412
413 return ret;
414}
415
416static unsigned long clk_stm32_composite_recalc_rate(struct clk_hw *hw,
417 unsigned long parent_rate)
418{
419 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
420
421 if (composite->div_id == NO_STM32_DIV)
422 return parent_rate;
423
424 return stm32_divider_get_rate(composite->base, composite->clock_data,
425 composite->div_id, parent_rate);
426}
427
428static long clk_stm32_composite_round_rate(struct clk_hw *hw, unsigned long rate,
429 unsigned long *prate)
430{
431 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
432
433 const struct stm32_div_cfg *divider;
434
435 if (composite->div_id == NO_STM32_DIV)
436 return rate;
437
438 divider = &composite->clock_data->dividers[composite->div_id];
439
440 /* if read only, just return current value */
441 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
442 u32 val;
443
444 val = readl(composite->base + divider->offset) >> divider->shift;
445 val &= clk_div_mask(divider->width);
446
447 return divider_ro_round_rate(hw, rate, prate, divider->table,
448 divider->width, divider->flags,
449 val);
450 }
451
452 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
453 rate, prate, divider->table,
454 divider->width, divider->flags);
455}
456
457static u8 clk_stm32_composite_get_parent(struct clk_hw *hw)
458{
459 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
460
461 return stm32_mux_get_parent(composite->base, composite->clock_data, composite->mux_id);
462}
463
464static int clk_stm32_composite_set_parent(struct clk_hw *hw, u8 index)
465{
466 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
467 unsigned long flags = 0;
468
469 spin_lock_irqsave(composite->lock, flags);
470
471 stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, index);
472
473 spin_unlock_irqrestore(composite->lock, flags);
474
475 if (composite->clock_data->is_multi_mux) {
476 struct clk_hw *other_mux_hw = composite->clock_data->is_multi_mux(hw);
477
478 if (other_mux_hw) {
479 struct clk_hw *hwp = clk_hw_get_parent_by_index(hw, index);
480
481 clk_hw_reparent(other_mux_hw, hwp);
482 }
483 }
484
485 return 0;
486}
487
488static int clk_stm32_composite_is_enabled(struct clk_hw *hw)
489{
490 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
491
492 if (composite->gate_id == NO_STM32_GATE)
493 return (__clk_get_enable_count(hw->clk) > 0);
494
495 return stm32_gate_is_enabled(composite->base, composite->clock_data, composite->gate_id);
496}
497
498#define MUX_SAFE_POSITION 0
499
500static int clk_stm32_has_safe_mux(struct clk_hw *hw)
501{
502 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
503 const struct stm32_mux_cfg *mux = &composite->clock_data->muxes[composite->mux_id];
504
505 return !!(mux->flags & MUX_SAFE);
506}
507
508static void clk_stm32_set_safe_position_mux(struct clk_hw *hw)
509{
510 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
511
512 if (!clk_stm32_composite_is_enabled(hw)) {
513 unsigned long flags = 0;
514
515 if (composite->clock_data->is_multi_mux) {
516 struct clk_hw *other_mux_hw = NULL;
517
518 other_mux_hw = composite->clock_data->is_multi_mux(hw);
519
520 if (!other_mux_hw || clk_stm32_composite_is_enabled(other_mux_hw))
521 return;
522 }
523
524 spin_lock_irqsave(composite->lock, flags);
525
526 stm32_mux_set_parent(composite->base, composite->clock_data,
527 composite->mux_id, MUX_SAFE_POSITION);
528
529 spin_unlock_irqrestore(composite->lock, flags);
530 }
531}
532
533static void clk_stm32_safe_restore_position_mux(struct clk_hw *hw)
534{
535 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
536 int sel = clk_hw_get_parent_index(hw);
537 unsigned long flags = 0;
538
539 spin_lock_irqsave(composite->lock, flags);
540
541 stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, sel);
542
543 spin_unlock_irqrestore(composite->lock, flags);
544}
545
546static void clk_stm32_composite_gate_endisable(struct clk_hw *hw, int enable)
547{
548 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
549 unsigned long flags = 0;
550
551 spin_lock_irqsave(composite->lock, flags);
552
553 stm32_gate_endisable(composite->base, composite->clock_data, composite->gate_id, enable);
554
555 spin_unlock_irqrestore(composite->lock, flags);
556}
557
558static int clk_stm32_composite_gate_enable(struct clk_hw *hw)
559{
560 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
561
562 if (composite->gate_id == NO_STM32_GATE)
563 return 0;
564
565 clk_stm32_composite_gate_endisable(hw, 1);
566
567 if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))
568 clk_stm32_safe_restore_position_mux(hw);
569
570 return 0;
571}
572
573static void clk_stm32_composite_gate_disable(struct clk_hw *hw)
574{
575 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
576
577 if (composite->gate_id == NO_STM32_GATE)
578 return;
579
580 clk_stm32_composite_gate_endisable(hw, 0);
581
582 if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))
583 clk_stm32_set_safe_position_mux(hw);
584}
585
586static void clk_stm32_composite_disable_unused(struct clk_hw *hw)
587{
588 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
589 unsigned long flags = 0;
590
591 if (composite->gate_id == NO_STM32_GATE)
592 return;
593
594 spin_lock_irqsave(composite->lock, flags);
595
596 stm32_gate_disable_unused(composite->base, composite->clock_data, composite->gate_id);
597
598 spin_unlock_irqrestore(composite->lock, flags);
599}
600
601const struct clk_ops clk_stm32_composite_ops = {
602 .set_rate = clk_stm32_composite_set_rate,
603 .recalc_rate = clk_stm32_composite_recalc_rate,
604 .round_rate = clk_stm32_composite_round_rate,
605 .get_parent = clk_stm32_composite_get_parent,
606 .set_parent = clk_stm32_composite_set_parent,
607 .enable = clk_stm32_composite_gate_enable,
608 .disable = clk_stm32_composite_gate_disable,
609 .is_enabled = clk_stm32_composite_is_enabled,
610 .disable_unused = clk_stm32_composite_disable_unused,
611};
612
613struct clk_hw *clk_stm32_mux_register(struct device *dev,
614 const struct stm32_rcc_match_data *data,
615 void __iomem *base,
616 spinlock_t *lock,
617 const struct clock_config *cfg)
618{
619 struct clk_stm32_mux *mux = cfg->clock_cfg;
620 struct clk_hw *hw = &mux->hw;
621 int err;
622
623 mux->base = base;
624 mux->lock = lock;
625 mux->clock_data = data->clock_data;
626
627 err = clk_hw_register(dev, hw);
628 if (err)
629 return ERR_PTR(err);
630
631 return hw;
632}
633
634struct clk_hw *clk_stm32_gate_register(struct device *dev,
635 const struct stm32_rcc_match_data *data,
636 void __iomem *base,
637 spinlock_t *lock,
638 const struct clock_config *cfg)
639{
640 struct clk_stm32_gate *gate = cfg->clock_cfg;
641 struct clk_hw *hw = &gate->hw;
642 int err;
643
644 gate->base = base;
645 gate->lock = lock;
646 gate->clock_data = data->clock_data;
647
648 err = clk_hw_register(dev, hw);
649 if (err)
650 return ERR_PTR(err);
651
652 return hw;
653}
654
655struct clk_hw *clk_stm32_div_register(struct device *dev,
656 const struct stm32_rcc_match_data *data,
657 void __iomem *base,
658 spinlock_t *lock,
659 const struct clock_config *cfg)
660{
661 struct clk_stm32_div *div = cfg->clock_cfg;
662 struct clk_hw *hw = &div->hw;
663 int err;
664
665 div->base = base;
666 div->lock = lock;
667 div->clock_data = data->clock_data;
668
669 err = clk_hw_register(dev, hw);
670 if (err)
671 return ERR_PTR(err);
672
673 return hw;
674}
675
676struct clk_hw *clk_stm32_composite_register(struct device *dev,
677 const struct stm32_rcc_match_data *data,
678 void __iomem *base,
679 spinlock_t *lock,
680 const struct clock_config *cfg)
681{
682 struct clk_stm32_composite *composite = cfg->clock_cfg;
683 struct clk_hw *hw = &composite->hw;
684 int err;
685
686 composite->base = base;
687 composite->lock = lock;
688 composite->clock_data = data->clock_data;
689
690 err = clk_hw_register(dev, hw);
691 if (err)
692 return ERR_PTR(err);
693
694 return hw;
695}