1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Kernel-based Virtual Machine driver for Linux
  4 *
  5 * AMD SVM support
  6 *
  7 * Copyright (C) 2006 Qumranet, Inc.
  8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  9 *
 10 * Authors:
 11 *   Yaniv Kamay  <yaniv@qumranet.com>
 12 *   Avi Kivity   <avi@qumranet.com>
 13 */
 14
 15#ifndef __SVM_SVM_H
 16#define __SVM_SVM_H
 17
 18#include <linux/kvm_types.h>
 19#include <linux/kvm_host.h>
 20#include <linux/bits.h>
 21
 22#include <asm/svm.h>
 23#include <asm/sev-common.h>
 24
 25#include "cpuid.h"
 26#include "kvm_cache_regs.h"
 27
 28/*
 29 * Helpers to convert to/from physical addresses for pages whose address is
 30 * consumed directly by hardware.  Even though it's a physical address, SVM
 31 * often restricts the address to the natural width, hence 'unsigned long'
 32 * instead of 'hpa_t'.
 33 */
 34static inline unsigned long __sme_page_pa(struct page *page)
 35{
 36	return __sme_set(page_to_pfn(page) << PAGE_SHIFT);
 37}
 38
 39static inline struct page *__sme_pa_to_page(unsigned long pa)
 40{
 41	return pfn_to_page(__sme_clr(pa) >> PAGE_SHIFT);
 42}
 43
 44#define	IOPM_SIZE PAGE_SIZE * 3
 45#define	MSRPM_SIZE PAGE_SIZE * 2
 46
 47#define MAX_DIRECT_ACCESS_MSRS	48
 48#define MSRPM_OFFSETS	32
 49extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 50extern bool npt_enabled;
 51extern int nrips;
 52extern int vgif;
 53extern bool intercept_smi;
 54extern bool x2avic_enabled;
 55extern bool vnmi;
 56extern int lbrv;
 
 
 
 
 
 57
 58/*
 59 * Clean bits in VMCB.
 60 * VMCB_ALL_CLEAN_MASK might also need to
 61 * be updated if this enum is modified.
 62 */
 63enum {
 64	VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 65			    pause filter count */
 66	VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 67	VMCB_ASID,	 /* ASID */
 68	VMCB_INTR,	 /* int_ctl, int_vector */
 69	VMCB_NPT,        /* npt_en, nCR3, gPAT */
 70	VMCB_CR,	 /* CR0, CR3, CR4, EFER */
 71	VMCB_DR,         /* DR6, DR7 */
 72	VMCB_DT,         /* GDT, IDT */
 73	VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 74	VMCB_CR2,        /* CR2 only */
 75	VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 76	VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 77			  * AVIC PHYSICAL_TABLE pointer,
 78			  * AVIC LOGICAL_TABLE pointer
 79			  */
 80	VMCB_SW = 31,    /* Reserved for hypervisor/software use */
 81};
 82
 83#define VMCB_ALL_CLEAN_MASK (					\
 84	(1U << VMCB_INTERCEPTS) | (1U << VMCB_PERM_MAP) |	\
 85	(1U << VMCB_ASID) | (1U << VMCB_INTR) |			\
 86	(1U << VMCB_NPT) | (1U << VMCB_CR) | (1U << VMCB_DR) |	\
 87	(1U << VMCB_DT) | (1U << VMCB_SEG) | (1U << VMCB_CR2) |	\
 88	(1U << VMCB_LBR) | (1U << VMCB_AVIC) |			\
 89	(1U << VMCB_SW))
 90
 91/* TPR and CR2 are always written before VMRUN */
 92#define VMCB_ALWAYS_DIRTY_MASK	((1U << VMCB_INTR) | (1U << VMCB_CR2))
 93
 94struct kvm_sev_info {
 95	bool active;		/* SEV enabled guest */
 96	bool es_active;		/* SEV-ES enabled guest */
 97	bool need_init;		/* waiting for SEV_INIT2 */
 98	unsigned int asid;	/* ASID used for this guest */
 99	unsigned int handle;	/* SEV firmware handle */
100	int fd;			/* SEV device fd */
101	unsigned long pages_locked; /* Number of pages locked */
102	struct list_head regions_list;  /* List of registered regions */
103	u64 ap_jump_table;	/* SEV-ES AP Jump Table address */
104	u64 vmsa_features;
105	u16 ghcb_version;	/* Highest guest GHCB protocol version allowed */
106	struct kvm *enc_context_owner; /* Owner of copied encryption context */
107	struct list_head mirror_vms; /* List of VMs mirroring */
108	struct list_head mirror_entry; /* Use as a list entry of mirrors */
109	struct misc_cg *misc_cg; /* For misc cgroup accounting */
110	atomic_t migration_in_progress;
111	void *snp_context;      /* SNP guest context page */
112	void *guest_req_buf;    /* Bounce buffer for SNP Guest Request input */
113	void *guest_resp_buf;   /* Bounce buffer for SNP Guest Request output */
114	struct mutex guest_req_mutex; /* Must acquire before using bounce buffers */
115};
116
117struct kvm_svm {
118	struct kvm kvm;
119
120	/* Struct members for AVIC */
121	u32 avic_vm_id;
122	struct page *avic_logical_id_table_page;
123	struct page *avic_physical_id_table_page;
124	struct hlist_node hnode;
125
126	struct kvm_sev_info sev_info;
127};
128
129struct kvm_vcpu;
130
131struct kvm_vmcb_info {
132	struct vmcb *ptr;
133	unsigned long pa;
134	int cpu;
135	uint64_t asid_generation;
136};
137
138struct vmcb_save_area_cached {
139	u64 efer;
140	u64 cr4;
141	u64 cr3;
142	u64 cr0;
143	u64 dr7;
144	u64 dr6;
145};
146
147struct vmcb_ctrl_area_cached {
148	u32 intercepts[MAX_INTERCEPT];
149	u16 pause_filter_thresh;
150	u16 pause_filter_count;
151	u64 iopm_base_pa;
152	u64 msrpm_base_pa;
153	u64 tsc_offset;
154	u32 asid;
155	u8 tlb_ctl;
156	u32 int_ctl;
157	u32 int_vector;
158	u32 int_state;
159	u32 exit_code;
160	u32 exit_code_hi;
161	u64 exit_info_1;
162	u64 exit_info_2;
163	u32 exit_int_info;
164	u32 exit_int_info_err;
165	u64 nested_ctl;
166	u32 event_inj;
167	u32 event_inj_err;
168	u64 next_rip;
169	u64 nested_cr3;
170	u64 virt_ext;
171	u32 clean;
172	union {
173#if IS_ENABLED(CONFIG_HYPERV) || IS_ENABLED(CONFIG_KVM_HYPERV)
174		struct hv_vmcb_enlightenments hv_enlightenments;
175#endif
176		u8 reserved_sw[32];
177	};
178};
179
180struct svm_nested_state {
181	struct kvm_vmcb_info vmcb02;
182	u64 hsave_msr;
183	u64 vm_cr_msr;
184	u64 vmcb12_gpa;
185	u64 last_vmcb12_gpa;
186
187	/* These are the merged vectors */
188	u32 *msrpm;
189
190	/* A VMRUN has started but has not yet been performed, so
191	 * we cannot inject a nested vmexit yet.  */
192	bool nested_run_pending;
193
194	/* cache for control fields of the guest */
195	struct vmcb_ctrl_area_cached ctl;
196
197	/*
198	 * Note: this struct is not kept up-to-date while L2 runs; it is only
199	 * valid within nested_svm_vmrun.
200	 */
201	struct vmcb_save_area_cached save;
202
203	bool initialized;
204
205	/*
206	 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to
207	 * changes in MSR bitmap for L1 or switching to a different L2. Note,
208	 * this flag can only be used reliably in conjunction with a paravirt L1
209	 * which informs L0 whether any changes to MSR bitmap for L2 were done
210	 * on its side.
211	 */
212	bool force_msr_bitmap_recalc;
213};
214
215struct vcpu_sev_es_state {
216	/* SEV-ES support */
217	struct sev_es_save_area *vmsa;
218	struct ghcb *ghcb;
219	u8 valid_bitmap[16];
220	struct kvm_host_map ghcb_map;
221	bool received_first_sipi;
222	unsigned int ap_reset_hold_type;
223
224	/* SEV-ES scratch area support */
225	u64 sw_scratch;
226	void *ghcb_sa;
227	u32 ghcb_sa_len;
228	bool ghcb_sa_sync;
229	bool ghcb_sa_free;
230
231	/* SNP Page-State-Change buffer entries currently being processed */
232	u16 psc_idx;
233	u16 psc_inflight;
234	bool psc_2m;
235
236	u64 ghcb_registered_gpa;
237
238	struct mutex snp_vmsa_mutex; /* Used to handle concurrent updates of VMSA. */
239	gpa_t snp_vmsa_gpa;
240	bool snp_ap_waiting_for_reset;
241	bool snp_has_guest_vmsa;
242};
243
244struct vcpu_svm {
245	struct kvm_vcpu vcpu;
246	/* vmcb always points at current_vmcb->ptr, it's purely a shorthand. */
247	struct vmcb *vmcb;
248	struct kvm_vmcb_info vmcb01;
249	struct kvm_vmcb_info *current_vmcb;
250	u32 asid;
251	u32 sysenter_esp_hi;
252	u32 sysenter_eip_hi;
253	uint64_t tsc_aux;
254
255	u64 msr_decfg;
256
257	u64 next_rip;
258
259	u64 spec_ctrl;
260
261	u64 tsc_ratio_msr;
262	/*
263	 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
264	 * translated into the appropriate L2_CFG bits on the host to
265	 * perform speculative control.
266	 */
267	u64 virt_spec_ctrl;
268
269	u32 *msrpm;
270
271	ulong nmi_iret_rip;
272
273	struct svm_nested_state nested;
274
275	/* NMI mask value, used when vNMI is not enabled */
276	bool nmi_masked;
277
278	/*
279	 * True when NMIs are still masked but guest IRET was just intercepted
280	 * and KVM is waiting for RIP to change, which will signal that the
281	 * intercepted IRET was retired and thus NMI can be unmasked.
282	 */
283	bool awaiting_iret_completion;
284
285	/*
286	 * Set when KVM is awaiting IRET completion and needs to inject NMIs as
287	 * soon as the IRET completes (e.g. NMI is pending injection).  KVM
288	 * temporarily steals RFLAGS.TF to single-step the guest in this case
289	 * in order to regain control as soon as the NMI-blocking condition
290	 * goes away.
291	 */
292	bool nmi_singlestep;
293	u64 nmi_singlestep_guest_rflags;
294
295	bool nmi_l1_to_l2;
296
297	unsigned long soft_int_csbase;
298	unsigned long soft_int_old_rip;
299	unsigned long soft_int_next_rip;
300	bool soft_int_injected;
301
 
 
 
 
 
 
 
 
 
302	u32 ldr_reg;
303	u32 dfr_reg;
304	struct page *avic_backing_page;
305	u64 *avic_physical_id_cache;
306
307	/*
308	 * Per-vcpu list of struct amd_svm_iommu_ir:
309	 * This is used mainly to store interrupt remapping information used
310	 * when update the vcpu affinity. This avoids the need to scan for
311	 * IRTE and try to match ga_tag in the IOMMU driver.
312	 */
313	struct list_head ir_list;
314	spinlock_t ir_list_lock;
315
316	/* Save desired MSR intercept (read: pass-through) state */
317	struct {
318		DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS);
319		DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS);
320	} shadow_msr_intercept;
321
322	struct vcpu_sev_es_state sev_es;
323
324	bool guest_state_loaded;
325
326	bool x2avic_msrs_intercepted;
327
328	/* Guest GIF value, used when vGIF is not enabled */
329	bool guest_gif;
330};
331
332struct svm_cpu_data {
333	u64 asid_generation;
334	u32 max_asid;
335	u32 next_asid;
336	u32 min_asid;
 
337
338	struct vmcb *save_area;
339	unsigned long save_area_pa;
340
341	struct vmcb *current_vmcb;
342
343	/* index = sev_asid, value = vmcb pointer */
344	struct vmcb **sev_vmcbs;
345};
346
347DECLARE_PER_CPU(struct svm_cpu_data, svm_data);
348
349void recalc_intercepts(struct vcpu_svm *svm);
350
351static __always_inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
352{
353	return container_of(kvm, struct kvm_svm, kvm);
354}
355
356static __always_inline struct kvm_sev_info *to_kvm_sev_info(struct kvm *kvm)
357{
358	return &to_kvm_svm(kvm)->sev_info;
359}
360
361static __always_inline bool sev_guest(struct kvm *kvm)
362{
363#ifdef CONFIG_KVM_AMD_SEV
364	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
365
366	return sev->active;
367#else
368	return false;
369#endif
370}
371
372static __always_inline bool sev_es_guest(struct kvm *kvm)
373{
374#ifdef CONFIG_KVM_AMD_SEV
375	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
376
377	return sev->es_active && !WARN_ON_ONCE(!sev->active);
378#else
379	return false;
380#endif
381}
382
383static __always_inline bool sev_snp_guest(struct kvm *kvm)
384{
385#ifdef CONFIG_KVM_AMD_SEV
386	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
387
388	return (sev->vmsa_features & SVM_SEV_FEAT_SNP_ACTIVE) &&
389	       !WARN_ON_ONCE(!sev_es_guest(kvm));
390#else
391	return false;
392#endif
393}
394
395static inline bool ghcb_gpa_is_registered(struct vcpu_svm *svm, u64 val)
396{
397	return svm->sev_es.ghcb_registered_gpa == val;
398}
399
400static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)
401{
402	vmcb->control.clean = 0;
403}
404
405static inline void vmcb_mark_all_clean(struct vmcb *vmcb)
406{
407	vmcb->control.clean = VMCB_ALL_CLEAN_MASK
408			       & ~VMCB_ALWAYS_DIRTY_MASK;
409}
410
411static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit)
412{
413	vmcb->control.clean &= ~(1 << bit);
414}
415
416static inline bool vmcb_is_dirty(struct vmcb *vmcb, int bit)
417{
418        return !test_bit(bit, (unsigned long *)&vmcb->control.clean);
419}
420
421static __always_inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
422{
423	return container_of(vcpu, struct vcpu_svm, vcpu);
424}
425
426/*
427 * Only the PDPTRs are loaded on demand into the shadow MMU.  All other
428 * fields are synchronized on VM-Exit, because accessing the VMCB is cheap.
429 *
430 * CR3 might be out of date in the VMCB but it is not marked dirty; instead,
431 * KVM_REQ_LOAD_MMU_PGD is always requested when the cached vcpu->arch.cr3
432 * is changed.  svm_load_mmu_pgd() then syncs the new CR3 value into the VMCB.
433 */
434#define SVM_REGS_LAZY_LOAD_SET	(1 << VCPU_EXREG_PDPTR)
435
436static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit)
437{
438	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
439	__set_bit(bit, (unsigned long *)&control->intercepts);
440}
441
442static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit)
443{
444	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
445	__clear_bit(bit, (unsigned long *)&control->intercepts);
446}
447
448static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit)
449{
450	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
451	return test_bit(bit, (unsigned long *)&control->intercepts);
452}
453
454static inline bool vmcb12_is_intercept(struct vmcb_ctrl_area_cached *control, u32 bit)
455{
456	WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
457	return test_bit(bit, (unsigned long *)&control->intercepts);
458}
459
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
460static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit)
461{
462	struct vmcb *vmcb = svm->vmcb01.ptr;
463
464	WARN_ON_ONCE(bit >= 32);
465	vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
466
467	recalc_intercepts(svm);
468}
469
470static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit)
471{
472	struct vmcb *vmcb = svm->vmcb01.ptr;
473
474	WARN_ON_ONCE(bit >= 32);
475	vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
476
477	recalc_intercepts(svm);
478}
479
480static inline void svm_set_intercept(struct vcpu_svm *svm, int bit)
481{
482	struct vmcb *vmcb = svm->vmcb01.ptr;
483
484	vmcb_set_intercept(&vmcb->control, bit);
485
486	recalc_intercepts(svm);
487}
488
489static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit)
490{
491	struct vmcb *vmcb = svm->vmcb01.ptr;
492
493	vmcb_clr_intercept(&vmcb->control, bit);
494
495	recalc_intercepts(svm);
496}
497
498static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit)
499{
500	return vmcb_is_intercept(&svm->vmcb->control, bit);
501}
502
503static inline bool nested_vgif_enabled(struct vcpu_svm *svm)
504{
505	return guest_can_use(&svm->vcpu, X86_FEATURE_VGIF) &&
506	       (svm->nested.ctl.int_ctl & V_GIF_ENABLE_MASK);
507}
508
509static inline struct vmcb *get_vgif_vmcb(struct vcpu_svm *svm)
510{
511	if (!vgif)
512		return NULL;
513
514	if (is_guest_mode(&svm->vcpu) && !nested_vgif_enabled(svm))
515		return svm->nested.vmcb02.ptr;
516	else
517		return svm->vmcb01.ptr;
518}
519
520static inline void enable_gif(struct vcpu_svm *svm)
521{
522	struct vmcb *vmcb = get_vgif_vmcb(svm);
523
524	if (vmcb)
525		vmcb->control.int_ctl |= V_GIF_MASK;
526	else
527		svm->guest_gif = true;
528}
529
530static inline void disable_gif(struct vcpu_svm *svm)
531{
532	struct vmcb *vmcb = get_vgif_vmcb(svm);
533
534	if (vmcb)
535		vmcb->control.int_ctl &= ~V_GIF_MASK;
536	else
537		svm->guest_gif = false;
538}
539
540static inline bool gif_set(struct vcpu_svm *svm)
541{
542	struct vmcb *vmcb = get_vgif_vmcb(svm);
543
544	if (vmcb)
545		return !!(vmcb->control.int_ctl & V_GIF_MASK);
546	else
547		return svm->guest_gif;
548}
549
550static inline bool nested_npt_enabled(struct vcpu_svm *svm)
551{
552	return svm->nested.ctl.nested_ctl & SVM_NESTED_CTL_NP_ENABLE;
553}
554
555static inline bool nested_vnmi_enabled(struct vcpu_svm *svm)
556{
557	return guest_can_use(&svm->vcpu, X86_FEATURE_VNMI) &&
558	       (svm->nested.ctl.int_ctl & V_NMI_ENABLE_MASK);
559}
560
561static inline bool is_x2apic_msrpm_offset(u32 offset)
562{
563	/* 4 msrs per u8, and 4 u8 in u32 */
564	u32 msr = offset * 16;
565
566	return (msr >= APIC_BASE_MSR) &&
567	       (msr < (APIC_BASE_MSR + 0x100));
568}
569
570static inline struct vmcb *get_vnmi_vmcb_l1(struct vcpu_svm *svm)
571{
572	if (!vnmi)
573		return NULL;
574
575	if (is_guest_mode(&svm->vcpu))
576		return NULL;
577	else
578		return svm->vmcb01.ptr;
579}
580
581static inline bool is_vnmi_enabled(struct vcpu_svm *svm)
582{
583	struct vmcb *vmcb = get_vnmi_vmcb_l1(svm);
584
585	if (vmcb)
586		return !!(vmcb->control.int_ctl & V_NMI_ENABLE_MASK);
587	else
588		return false;
589}
590
591/* svm.c */
592#define MSR_INVALID				0xffffffffU
593
594#define DEBUGCTL_RESERVED_BITS (~DEBUGCTLMSR_LBR)
595
596extern bool dump_invalid_vmcb;
597
598u32 svm_msrpm_offset(u32 msr);
599u32 *svm_vcpu_alloc_msrpm(void);
600void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm);
601void svm_vcpu_free_msrpm(u32 *msrpm);
602void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb);
603void svm_enable_lbrv(struct kvm_vcpu *vcpu);
604void svm_update_lbrv(struct kvm_vcpu *vcpu);
605
606int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
607void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
608void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
609void disable_nmi_singlestep(struct vcpu_svm *svm);
610bool svm_smi_blocked(struct kvm_vcpu *vcpu);
611bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
612bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
613void svm_set_gif(struct vcpu_svm *svm, bool value);
614int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code);
615void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
616			  int read, int write);
617void svm_set_x2apic_msr_interception(struct vcpu_svm *svm, bool disable);
618void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode,
619				     int trig_mode, int vec);
620
621/* nested.c */
622
623#define NESTED_EXIT_HOST	0	/* Exit handled on host level */
624#define NESTED_EXIT_DONE	1	/* Exit caused nested vmexit  */
625#define NESTED_EXIT_CONTINUE	2	/* Further checks needed      */
626
627static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu)
628{
629	struct vcpu_svm *svm = to_svm(vcpu);
630
631	return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK);
632}
633
634static inline bool nested_exit_on_smi(struct vcpu_svm *svm)
635{
636	return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SMI);
637}
638
639static inline bool nested_exit_on_intr(struct vcpu_svm *svm)
640{
641	return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_INTR);
642}
643
644static inline bool nested_exit_on_nmi(struct vcpu_svm *svm)
645{
646	return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_NMI);
647}
648
649int enter_svm_guest_mode(struct kvm_vcpu *vcpu,
650			 u64 vmcb_gpa, struct vmcb *vmcb12, bool from_vmrun);
651void svm_leave_nested(struct kvm_vcpu *vcpu);
652void svm_free_nested(struct vcpu_svm *svm);
653int svm_allocate_nested(struct vcpu_svm *svm);
654int nested_svm_vmrun(struct kvm_vcpu *vcpu);
655void svm_copy_vmrun_state(struct vmcb_save_area *to_save,
656			  struct vmcb_save_area *from_save);
657void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb);
658int nested_svm_vmexit(struct vcpu_svm *svm);
659
660static inline int nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code)
661{
662	svm->vmcb->control.exit_code   = exit_code;
663	svm->vmcb->control.exit_info_1 = 0;
664	svm->vmcb->control.exit_info_2 = 0;
665	return nested_svm_vmexit(svm);
666}
667
668int nested_svm_exit_handled(struct vcpu_svm *svm);
669int nested_svm_check_permissions(struct kvm_vcpu *vcpu);
670int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
671			       bool has_error_code, u32 error_code);
672int nested_svm_exit_special(struct vcpu_svm *svm);
673void nested_svm_update_tsc_ratio_msr(struct kvm_vcpu *vcpu);
674void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu);
675void nested_copy_vmcb_control_to_cache(struct vcpu_svm *svm,
676				       struct vmcb_control_area *control);
677void nested_copy_vmcb_save_to_cache(struct vcpu_svm *svm,
678				    struct vmcb_save_area *save);
679void nested_sync_control_from_vmcb02(struct vcpu_svm *svm);
680void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm);
681void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb);
682
683extern struct kvm_x86_nested_ops svm_nested_ops;
684
685/* avic.c */
686#define AVIC_REQUIRED_APICV_INHIBITS			\
687(							\
688	BIT(APICV_INHIBIT_REASON_DISABLED) |		\
689	BIT(APICV_INHIBIT_REASON_ABSENT) |		\
690	BIT(APICV_INHIBIT_REASON_HYPERV) |		\
691	BIT(APICV_INHIBIT_REASON_NESTED) |		\
692	BIT(APICV_INHIBIT_REASON_IRQWIN) |		\
693	BIT(APICV_INHIBIT_REASON_PIT_REINJ) |		\
694	BIT(APICV_INHIBIT_REASON_BLOCKIRQ) |		\
695	BIT(APICV_INHIBIT_REASON_SEV)      |		\
696	BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) |	\
697	BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) |	\
698	BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) |	\
699	BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED)	\
700)
701
702bool avic_hardware_setup(void);
703int avic_ga_log_notifier(u32 ga_tag);
704void avic_vm_destroy(struct kvm *kvm);
705int avic_vm_init(struct kvm *kvm);
706void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb);
707int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu);
708int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu);
709int avic_init_vcpu(struct vcpu_svm *svm);
710void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
711void avic_vcpu_put(struct kvm_vcpu *vcpu);
712void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu);
713void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
 
714int avic_pi_update_irte(struct kvm *kvm, unsigned int host_irq,
715			uint32_t guest_irq, bool set);
716void avic_vcpu_blocking(struct kvm_vcpu *vcpu);
717void avic_vcpu_unblocking(struct kvm_vcpu *vcpu);
718void avic_ring_doorbell(struct kvm_vcpu *vcpu);
719unsigned long avic_vcpu_get_apicv_inhibit_reasons(struct kvm_vcpu *vcpu);
720void avic_refresh_virtual_apic_mode(struct kvm_vcpu *vcpu);
721
722
723/* sev.c */
724
725void pre_sev_run(struct vcpu_svm *svm, int cpu);
726void sev_init_vmcb(struct vcpu_svm *svm);
727void sev_vcpu_after_set_cpuid(struct vcpu_svm *svm);
728int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in);
729void sev_es_vcpu_reset(struct vcpu_svm *svm);
730void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
731void sev_es_prepare_switch_to_guest(struct vcpu_svm *svm, struct sev_es_save_area *hostsa);
732void sev_es_unmap_ghcb(struct vcpu_svm *svm);
733
734#ifdef CONFIG_KVM_AMD_SEV
 
 
 
735int sev_mem_enc_ioctl(struct kvm *kvm, void __user *argp);
736int sev_mem_enc_register_region(struct kvm *kvm,
737				struct kvm_enc_region *range);
738int sev_mem_enc_unregister_region(struct kvm *kvm,
739				  struct kvm_enc_region *range);
740int sev_vm_copy_enc_context_from(struct kvm *kvm, unsigned int source_fd);
741int sev_vm_move_enc_context_from(struct kvm *kvm, unsigned int source_fd);
742void sev_guest_memory_reclaimed(struct kvm *kvm);
743int sev_handle_vmgexit(struct kvm_vcpu *vcpu);
744
745/* These symbols are used in common code and are stubbed below.  */
746
747struct page *snp_safe_alloc_page_node(int node, gfp_t gfp);
748static inline struct page *snp_safe_alloc_page(void)
749{
750	return snp_safe_alloc_page_node(numa_node_id(), GFP_KERNEL_ACCOUNT);
751}
752
753void sev_free_vcpu(struct kvm_vcpu *vcpu);
754void sev_vm_destroy(struct kvm *kvm);
755void __init sev_set_cpu_caps(void);
756void __init sev_hardware_setup(void);
757void sev_hardware_unsetup(void);
758int sev_cpu_init(struct svm_cpu_data *sd);
759int sev_dev_get_attr(u32 group, u64 attr, u64 *val);
760extern unsigned int max_sev_asid;
761void sev_handle_rmp_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code);
762void sev_snp_init_protected_guest_state(struct kvm_vcpu *vcpu);
763int sev_gmem_prepare(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, int max_order);
764void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t end);
765int sev_private_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn);
766#else
767static inline struct page *snp_safe_alloc_page_node(int node, gfp_t gfp)
768{
769	return alloc_pages_node(node, gfp | __GFP_ZERO, 0);
770}
771
772static inline struct page *snp_safe_alloc_page(void)
773{
774	return snp_safe_alloc_page_node(numa_node_id(), GFP_KERNEL_ACCOUNT);
775}
776
777static inline void sev_free_vcpu(struct kvm_vcpu *vcpu) {}
778static inline void sev_vm_destroy(struct kvm *kvm) {}
779static inline void __init sev_set_cpu_caps(void) {}
780static inline void __init sev_hardware_setup(void) {}
781static inline void sev_hardware_unsetup(void) {}
782static inline int sev_cpu_init(struct svm_cpu_data *sd) { return 0; }
783static inline int sev_dev_get_attr(u32 group, u64 attr, u64 *val) { return -ENXIO; }
784#define max_sev_asid 0
785static inline void sev_handle_rmp_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code) {}
786static inline void sev_snp_init_protected_guest_state(struct kvm_vcpu *vcpu) {}
787static inline int sev_gmem_prepare(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, int max_order)
788{
789	return 0;
790}
791static inline void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t end) {}
792static inline int sev_private_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn)
793{
794	return 0;
795}
796
797#endif
798
799/* vmenter.S */
800
801void __svm_sev_es_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted,
802			   struct sev_es_save_area *hostsa);
803void __svm_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted);
804
805#define DEFINE_KVM_GHCB_ACCESSORS(field)						\
806	static __always_inline bool kvm_ghcb_##field##_is_valid(const struct vcpu_svm *svm) \
807	{									\
808		return test_bit(GHCB_BITMAP_IDX(field),				\
809				(unsigned long *)&svm->sev_es.valid_bitmap);	\
810	}									\
811										\
812	static __always_inline u64 kvm_ghcb_get_##field##_if_valid(struct vcpu_svm *svm, struct ghcb *ghcb) \
813	{									\
814		return kvm_ghcb_##field##_is_valid(svm) ? ghcb->save.field : 0;	\
815	}									\
816
817DEFINE_KVM_GHCB_ACCESSORS(cpl)
818DEFINE_KVM_GHCB_ACCESSORS(rax)
819DEFINE_KVM_GHCB_ACCESSORS(rcx)
820DEFINE_KVM_GHCB_ACCESSORS(rdx)
821DEFINE_KVM_GHCB_ACCESSORS(rbx)
822DEFINE_KVM_GHCB_ACCESSORS(rsi)
823DEFINE_KVM_GHCB_ACCESSORS(sw_exit_code)
824DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_1)
825DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_2)
826DEFINE_KVM_GHCB_ACCESSORS(sw_scratch)
827DEFINE_KVM_GHCB_ACCESSORS(xcr0)
828
829#endif