Loading...
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
7 *
8 * MMU support
9 *
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 *
13 * Authors:
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
16 */
17
18/*
19 * The MMU needs to be able to access/walk 32-bit and 64-bit guest page tables,
20 * as well as guest EPT tables, so the code in this file is compiled thrice,
21 * once per guest PTE type. The per-type defines are #undef'd at the end.
22 */
23
24#if PTTYPE == 64
25 #define pt_element_t u64
26 #define guest_walker guest_walker64
27 #define FNAME(name) paging##64_##name
28 #define PT_LEVEL_BITS 9
29 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
30 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
31 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
32 #ifdef CONFIG_X86_64
33 #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL
34 #else
35 #define PT_MAX_FULL_LEVELS 2
36 #endif
37#elif PTTYPE == 32
38 #define pt_element_t u32
39 #define guest_walker guest_walker32
40 #define FNAME(name) paging##32_##name
41 #define PT_LEVEL_BITS 10
42 #define PT_MAX_FULL_LEVELS 2
43 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
44 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
45 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
46
47 #define PT32_DIR_PSE36_SIZE 4
48 #define PT32_DIR_PSE36_SHIFT 13
49 #define PT32_DIR_PSE36_MASK \
50 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
51#elif PTTYPE == PTTYPE_EPT
52 #define pt_element_t u64
53 #define guest_walker guest_walkerEPT
54 #define FNAME(name) ept_##name
55 #define PT_LEVEL_BITS 9
56 #define PT_GUEST_DIRTY_SHIFT 9
57 #define PT_GUEST_ACCESSED_SHIFT 8
58 #define PT_HAVE_ACCESSED_DIRTY(mmu) (!(mmu)->cpu_role.base.ad_disabled)
59 #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL
60#else
61 #error Invalid PTTYPE value
62#endif
63
64/* Common logic, but per-type values. These also need to be undefined. */
65#define PT_BASE_ADDR_MASK ((pt_element_t)__PT_BASE_ADDR_MASK)
66#define PT_LVL_ADDR_MASK(lvl) __PT_LVL_ADDR_MASK(PT_BASE_ADDR_MASK, lvl, PT_LEVEL_BITS)
67#define PT_LVL_OFFSET_MASK(lvl) __PT_LVL_OFFSET_MASK(PT_BASE_ADDR_MASK, lvl, PT_LEVEL_BITS)
68#define PT_INDEX(addr, lvl) __PT_INDEX(addr, lvl, PT_LEVEL_BITS)
69
70#define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT)
71#define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT)
72
73#define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
74#define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PG_LEVEL_4K)
75
76/*
77 * The guest_walker structure emulates the behavior of the hardware page
78 * table walker.
79 */
80struct guest_walker {
81 int level;
82 unsigned max_level;
83 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
84 pt_element_t ptes[PT_MAX_FULL_LEVELS];
85 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
86 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
87 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
88 bool pte_writable[PT_MAX_FULL_LEVELS];
89 unsigned int pt_access[PT_MAX_FULL_LEVELS];
90 unsigned int pte_access;
91 gfn_t gfn;
92 struct x86_exception fault;
93};
94
95#if PTTYPE == 32
96static inline gfn_t pse36_gfn_delta(u32 gpte)
97{
98 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
99
100 return (gpte & PT32_DIR_PSE36_MASK) << shift;
101}
102#endif
103
104static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
105{
106 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
107}
108
109static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access,
110 unsigned gpte)
111{
112 unsigned mask;
113
114 /* dirty bit is not supported, so no need to track it */
115 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
116 return;
117
118 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
119
120 mask = (unsigned)~ACC_WRITE_MASK;
121 /* Allow write access to dirty gptes */
122 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
123 PT_WRITABLE_MASK;
124 *access &= mask;
125}
126
127static inline int FNAME(is_present_gpte)(unsigned long pte)
128{
129#if PTTYPE != PTTYPE_EPT
130 return pte & PT_PRESENT_MASK;
131#else
132 return pte & 7;
133#endif
134}
135
136static bool FNAME(is_bad_mt_xwr)(struct rsvd_bits_validate *rsvd_check, u64 gpte)
137{
138#if PTTYPE != PTTYPE_EPT
139 return false;
140#else
141 return __is_bad_mt_xwr(rsvd_check, gpte);
142#endif
143}
144
145static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level)
146{
147 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level) ||
148 FNAME(is_bad_mt_xwr)(&mmu->guest_rsvd_check, gpte);
149}
150
151static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
152 struct kvm_mmu_page *sp, u64 *spte,
153 u64 gpte)
154{
155 if (!FNAME(is_present_gpte)(gpte))
156 goto no_present;
157
158 /* Prefetch only accessed entries (unless A/D bits are disabled). */
159 if (PT_HAVE_ACCESSED_DIRTY(vcpu->arch.mmu) &&
160 !(gpte & PT_GUEST_ACCESSED_MASK))
161 goto no_present;
162
163 if (FNAME(is_rsvd_bits_set)(vcpu->arch.mmu, gpte, PG_LEVEL_4K))
164 goto no_present;
165
166 return false;
167
168no_present:
169 drop_spte(vcpu->kvm, spte);
170 return true;
171}
172
173/*
174 * For PTTYPE_EPT, a page table can be executable but not readable
175 * on supported processors. Therefore, set_spte does not automatically
176 * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
177 * to signify readability since it isn't used in the EPT case
178 */
179static inline unsigned FNAME(gpte_access)(u64 gpte)
180{
181 unsigned access;
182#if PTTYPE == PTTYPE_EPT
183 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
184 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
185 ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0);
186#else
187 BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK);
188 BUILD_BUG_ON(ACC_EXEC_MASK != 1);
189 access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK);
190 /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */
191 access ^= (gpte >> PT64_NX_SHIFT);
192#endif
193
194 return access;
195}
196
197static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
198 struct kvm_mmu *mmu,
199 struct guest_walker *walker,
200 gpa_t addr, int write_fault)
201{
202 unsigned level, index;
203 pt_element_t pte, orig_pte;
204 pt_element_t __user *ptep_user;
205 gfn_t table_gfn;
206 int ret;
207
208 /* dirty/accessed bits are not supported, so no need to update them */
209 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
210 return 0;
211
212 for (level = walker->max_level; level >= walker->level; --level) {
213 pte = orig_pte = walker->ptes[level - 1];
214 table_gfn = walker->table_gfn[level - 1];
215 ptep_user = walker->ptep_user[level - 1];
216 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
217 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
218 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
219 pte |= PT_GUEST_ACCESSED_MASK;
220 }
221 if (level == walker->level && write_fault &&
222 !(pte & PT_GUEST_DIRTY_MASK)) {
223 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
224#if PTTYPE == PTTYPE_EPT
225 if (kvm_x86_ops.nested_ops->write_log_dirty(vcpu, addr))
226 return -EINVAL;
227#endif
228 pte |= PT_GUEST_DIRTY_MASK;
229 }
230 if (pte == orig_pte)
231 continue;
232
233 /*
234 * If the slot is read-only, simply do not process the accessed
235 * and dirty bits. This is the correct thing to do if the slot
236 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
237 * are only supported if the accessed and dirty bits are already
238 * set in the ROM (so that MMIO writes are never needed).
239 *
240 * Note that NPT does not allow this at all and faults, since
241 * it always wants nested page table entries for the guest
242 * page tables to be writable. And EPT works but will simply
243 * overwrite the read-only memory to set the accessed and dirty
244 * bits.
245 */
246 if (unlikely(!walker->pte_writable[level - 1]))
247 continue;
248
249 ret = __try_cmpxchg_user(ptep_user, &orig_pte, pte, fault);
250 if (ret)
251 return ret;
252
253 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
254 walker->ptes[level - 1] = pte;
255 }
256 return 0;
257}
258
259static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
260{
261 unsigned pkeys = 0;
262#if PTTYPE == 64
263 pte_t pte = {.pte = gpte};
264
265 pkeys = pte_flags_pkey(pte_flags(pte));
266#endif
267 return pkeys;
268}
269
270static inline bool FNAME(is_last_gpte)(struct kvm_mmu *mmu,
271 unsigned int level, unsigned int gpte)
272{
273 /*
274 * For EPT and PAE paging (both variants), bit 7 is either reserved at
275 * all level or indicates a huge page (ignoring CR3/EPTP). In either
276 * case, bit 7 being set terminates the walk.
277 */
278#if PTTYPE == 32
279 /*
280 * 32-bit paging requires special handling because bit 7 is ignored if
281 * CR4.PSE=0, not reserved. Clear bit 7 in the gpte if the level is
282 * greater than the last level for which bit 7 is the PAGE_SIZE bit.
283 *
284 * The RHS has bit 7 set iff level < (2 + PSE). If it is clear, bit 7
285 * is not reserved and does not indicate a large page at this level,
286 * so clear PT_PAGE_SIZE_MASK in gpte if that is the case.
287 */
288 gpte &= level - (PT32_ROOT_LEVEL + mmu->cpu_role.ext.cr4_pse);
289#endif
290 /*
291 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
292 * iff level <= PG_LEVEL_4K, which for our purpose means
293 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
294 */
295 gpte |= level - PG_LEVEL_4K - 1;
296
297 return gpte & PT_PAGE_SIZE_MASK;
298}
299/*
300 * Fetch a guest pte for a guest virtual address, or for an L2's GPA.
301 */
302static int FNAME(walk_addr_generic)(struct guest_walker *walker,
303 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
304 gpa_t addr, u64 access)
305{
306 int ret;
307 pt_element_t pte;
308 pt_element_t __user *ptep_user;
309 gfn_t table_gfn;
310 u64 pt_access, pte_access;
311 unsigned index, accessed_dirty, pte_pkey;
312 u64 nested_access;
313 gpa_t pte_gpa;
314 bool have_ad;
315 int offset;
316 u64 walk_nx_mask = 0;
317 const int write_fault = access & PFERR_WRITE_MASK;
318 const int user_fault = access & PFERR_USER_MASK;
319 const int fetch_fault = access & PFERR_FETCH_MASK;
320 u16 errcode = 0;
321 gpa_t real_gpa;
322 gfn_t gfn;
323
324 trace_kvm_mmu_pagetable_walk(addr, access);
325retry_walk:
326 walker->level = mmu->cpu_role.base.level;
327 pte = kvm_mmu_get_guest_pgd(vcpu, mmu);
328 have_ad = PT_HAVE_ACCESSED_DIRTY(mmu);
329
330#if PTTYPE == 64
331 walk_nx_mask = 1ULL << PT64_NX_SHIFT;
332 if (walker->level == PT32E_ROOT_LEVEL) {
333 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
334 trace_kvm_mmu_paging_element(pte, walker->level);
335 if (!FNAME(is_present_gpte)(pte))
336 goto error;
337 --walker->level;
338 }
339#endif
340 walker->max_level = walker->level;
341
342 /*
343 * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging
344 * by the MOV to CR instruction are treated as reads and do not cause the
345 * processor to set the dirty flag in any EPT paging-structure entry.
346 */
347 nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK;
348
349 pte_access = ~0;
350
351 /*
352 * Queue a page fault for injection if this assertion fails, as callers
353 * assume that walker.fault contains sane info on a walk failure. I.e.
354 * avoid making the situation worse by inducing even worse badness
355 * between when the assertion fails and when KVM kicks the vCPU out to
356 * userspace (because the VM is bugged).
357 */
358 if (KVM_BUG_ON(is_long_mode(vcpu) && !is_pae(vcpu), vcpu->kvm))
359 goto error;
360
361 ++walker->level;
362
363 do {
364 struct kvm_memory_slot *slot;
365 unsigned long host_addr;
366
367 pt_access = pte_access;
368 --walker->level;
369
370 index = PT_INDEX(addr, walker->level);
371 table_gfn = gpte_to_gfn(pte);
372 offset = index * sizeof(pt_element_t);
373 pte_gpa = gfn_to_gpa(table_gfn) + offset;
374
375 BUG_ON(walker->level < 1);
376 walker->table_gfn[walker->level - 1] = table_gfn;
377 walker->pte_gpa[walker->level - 1] = pte_gpa;
378
379 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(table_gfn),
380 nested_access, &walker->fault);
381
382 /*
383 * FIXME: This can happen if emulation (for of an INS/OUTS
384 * instruction) triggers a nested page fault. The exit
385 * qualification / exit info field will incorrectly have
386 * "guest page access" as the nested page fault's cause,
387 * instead of "guest page structure access". To fix this,
388 * the x86_exception struct should be augmented with enough
389 * information to fix the exit_qualification or exit_info_1
390 * fields.
391 */
392 if (unlikely(real_gpa == INVALID_GPA))
393 return 0;
394
395 slot = kvm_vcpu_gfn_to_memslot(vcpu, gpa_to_gfn(real_gpa));
396 if (!kvm_is_visible_memslot(slot))
397 goto error;
398
399 host_addr = gfn_to_hva_memslot_prot(slot, gpa_to_gfn(real_gpa),
400 &walker->pte_writable[walker->level - 1]);
401 if (unlikely(kvm_is_error_hva(host_addr)))
402 goto error;
403
404 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
405 if (unlikely(__get_user(pte, ptep_user)))
406 goto error;
407 walker->ptep_user[walker->level - 1] = ptep_user;
408
409 trace_kvm_mmu_paging_element(pte, walker->level);
410
411 /*
412 * Inverting the NX it lets us AND it like other
413 * permission bits.
414 */
415 pte_access = pt_access & (pte ^ walk_nx_mask);
416
417 if (unlikely(!FNAME(is_present_gpte)(pte)))
418 goto error;
419
420 if (unlikely(FNAME(is_rsvd_bits_set)(mmu, pte, walker->level))) {
421 errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
422 goto error;
423 }
424
425 walker->ptes[walker->level - 1] = pte;
426
427 /* Convert to ACC_*_MASK flags for struct guest_walker. */
428 walker->pt_access[walker->level - 1] = FNAME(gpte_access)(pt_access ^ walk_nx_mask);
429 } while (!FNAME(is_last_gpte)(mmu, walker->level, pte));
430
431 pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
432 accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0;
433
434 /* Convert to ACC_*_MASK flags for struct guest_walker. */
435 walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask);
436 errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access);
437 if (unlikely(errcode))
438 goto error;
439
440 gfn = gpte_to_gfn_lvl(pte, walker->level);
441 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
442
443#if PTTYPE == 32
444 if (walker->level > PG_LEVEL_4K && is_cpuid_PSE36())
445 gfn += pse36_gfn_delta(pte);
446#endif
447
448 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(gfn), access, &walker->fault);
449 if (real_gpa == INVALID_GPA)
450 return 0;
451
452 walker->gfn = real_gpa >> PAGE_SHIFT;
453
454 if (!write_fault)
455 FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte);
456 else
457 /*
458 * On a write fault, fold the dirty bit into accessed_dirty.
459 * For modes without A/D bits support accessed_dirty will be
460 * always clear.
461 */
462 accessed_dirty &= pte >>
463 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
464
465 if (unlikely(!accessed_dirty)) {
466 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker,
467 addr, write_fault);
468 if (unlikely(ret < 0))
469 goto error;
470 else if (ret)
471 goto retry_walk;
472 }
473
474 return 1;
475
476error:
477 errcode |= write_fault | user_fault;
478 if (fetch_fault && (is_efer_nx(mmu) || is_cr4_smep(mmu)))
479 errcode |= PFERR_FETCH_MASK;
480
481 walker->fault.vector = PF_VECTOR;
482 walker->fault.error_code_valid = true;
483 walker->fault.error_code = errcode;
484
485#if PTTYPE == PTTYPE_EPT
486 /*
487 * Use PFERR_RSVD_MASK in error_code to tell if EPT
488 * misconfiguration requires to be injected. The detection is
489 * done by is_rsvd_bits_set() above.
490 *
491 * We set up the value of exit_qualification to inject:
492 * [2:0] - Derive from the access bits. The exit_qualification might be
493 * out of date if it is serving an EPT misconfiguration.
494 * [5:3] - Calculated by the page walk of the guest EPT page tables
495 * [7:8] - Derived from [7:8] of real exit_qualification
496 *
497 * The other bits are set to 0.
498 */
499 if (!(errcode & PFERR_RSVD_MASK)) {
500 walker->fault.exit_qualification = 0;
501
502 if (write_fault)
503 walker->fault.exit_qualification |= EPT_VIOLATION_ACC_WRITE;
504 if (user_fault)
505 walker->fault.exit_qualification |= EPT_VIOLATION_ACC_READ;
506 if (fetch_fault)
507 walker->fault.exit_qualification |= EPT_VIOLATION_ACC_INSTR;
508
509 /*
510 * Note, pte_access holds the raw RWX bits from the EPTE, not
511 * ACC_*_MASK flags!
512 */
513 walker->fault.exit_qualification |= (pte_access & VMX_EPT_RWX_MASK) <<
514 EPT_VIOLATION_RWX_SHIFT;
515 }
516#endif
517 walker->fault.address = addr;
518 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
519 walker->fault.async_page_fault = false;
520
521 trace_kvm_mmu_walker_error(walker->fault.error_code);
522 return 0;
523}
524
525static int FNAME(walk_addr)(struct guest_walker *walker,
526 struct kvm_vcpu *vcpu, gpa_t addr, u64 access)
527{
528 return FNAME(walk_addr_generic)(walker, vcpu, vcpu->arch.mmu, addr,
529 access);
530}
531
532static bool
533FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
534 u64 *spte, pt_element_t gpte)
535{
536 unsigned pte_access;
537 gfn_t gfn;
538
539 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
540 return false;
541
542 gfn = gpte_to_gfn(gpte);
543 pte_access = sp->role.access & FNAME(gpte_access)(gpte);
544 FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
545
546 return kvm_mmu_prefetch_sptes(vcpu, gfn, spte, 1, pte_access);
547}
548
549static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
550 struct guest_walker *gw, int level)
551{
552 pt_element_t curr_pte;
553 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
554 u64 mask;
555 int r, index;
556
557 if (level == PG_LEVEL_4K) {
558 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
559 base_gpa = pte_gpa & ~mask;
560 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
561
562 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
563 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
564 curr_pte = gw->prefetch_ptes[index];
565 } else
566 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
567 &curr_pte, sizeof(curr_pte));
568
569 return r || curr_pte != gw->ptes[level - 1];
570}
571
572static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
573 u64 *sptep)
574{
575 struct kvm_mmu_page *sp;
576 pt_element_t *gptep = gw->prefetch_ptes;
577 u64 *spte;
578 int i;
579
580 sp = sptep_to_sp(sptep);
581
582 if (sp->role.level > PG_LEVEL_4K)
583 return;
584
585 /*
586 * If addresses are being invalidated, skip prefetching to avoid
587 * accidentally prefetching those addresses.
588 */
589 if (unlikely(vcpu->kvm->mmu_invalidate_in_progress))
590 return;
591
592 if (sp->role.direct)
593 return __direct_pte_prefetch(vcpu, sp, sptep);
594
595 i = spte_index(sptep) & ~(PTE_PREFETCH_NUM - 1);
596 spte = sp->spt + i;
597
598 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
599 if (spte == sptep)
600 continue;
601
602 if (is_shadow_present_pte(*spte))
603 continue;
604
605 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i]))
606 break;
607 }
608}
609
610/*
611 * Fetch a shadow pte for a specific level in the paging hierarchy.
612 * If the guest tries to write a write-protected page, we need to
613 * emulate this operation, return 1 to indicate this case.
614 */
615static int FNAME(fetch)(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault,
616 struct guest_walker *gw)
617{
618 struct kvm_mmu_page *sp = NULL;
619 struct kvm_shadow_walk_iterator it;
620 unsigned int direct_access, access;
621 int top_level, ret;
622 gfn_t base_gfn = fault->gfn;
623
624 WARN_ON_ONCE(gw->gfn != base_gfn);
625 direct_access = gw->pte_access;
626
627 top_level = vcpu->arch.mmu->cpu_role.base.level;
628 if (top_level == PT32E_ROOT_LEVEL)
629 top_level = PT32_ROOT_LEVEL;
630 /*
631 * Verify that the top-level gpte is still there. Since the page
632 * is a root page, it is either write protected (and cannot be
633 * changed from now on) or it is invalid (in which case, we don't
634 * really care if it changes underneath us after this point).
635 */
636 if (FNAME(gpte_changed)(vcpu, gw, top_level))
637 return RET_PF_RETRY;
638
639 if (WARN_ON_ONCE(!VALID_PAGE(vcpu->arch.mmu->root.hpa)))
640 return RET_PF_RETRY;
641
642 /*
643 * Load a new root and retry the faulting instruction in the extremely
644 * unlikely scenario that the guest root gfn became visible between
645 * loading a dummy root and handling the resulting page fault, e.g. if
646 * userspace create a memslot in the interim.
647 */
648 if (unlikely(kvm_mmu_is_dummy_root(vcpu->arch.mmu->root.hpa))) {
649 kvm_make_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu);
650 return RET_PF_RETRY;
651 }
652
653 for_each_shadow_entry(vcpu, fault->addr, it) {
654 gfn_t table_gfn;
655
656 clear_sp_write_flooding_count(it.sptep);
657 if (it.level == gw->level)
658 break;
659
660 table_gfn = gw->table_gfn[it.level - 2];
661 access = gw->pt_access[it.level - 2];
662 sp = kvm_mmu_get_child_sp(vcpu, it.sptep, table_gfn,
663 false, access);
664
665 /*
666 * Synchronize the new page before linking it, as the CPU (KVM)
667 * is architecturally disallowed from inserting non-present
668 * entries into the TLB, i.e. the guest isn't required to flush
669 * the TLB when changing the gPTE from non-present to present.
670 *
671 * For PG_LEVEL_4K, kvm_mmu_find_shadow_page() has already
672 * synchronized the page via kvm_sync_page().
673 *
674 * For higher level pages, which cannot be unsync themselves
675 * but can have unsync children, synchronize via the slower
676 * mmu_sync_children(). If KVM needs to drop mmu_lock due to
677 * contention or to reschedule, instruct the caller to retry
678 * the #PF (mmu_sync_children() ensures forward progress will
679 * be made).
680 */
681 if (sp != ERR_PTR(-EEXIST) && sp->unsync_children &&
682 mmu_sync_children(vcpu, sp, false))
683 return RET_PF_RETRY;
684
685 /*
686 * Verify that the gpte in the page, which is now either
687 * write-protected or unsync, wasn't modified between the fault
688 * and acquiring mmu_lock. This needs to be done even when
689 * reusing an existing shadow page to ensure the information
690 * gathered by the walker matches the information stored in the
691 * shadow page (which could have been modified by a different
692 * vCPU even if the page was already linked). Holding mmu_lock
693 * prevents the shadow page from changing after this point.
694 */
695 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
696 return RET_PF_RETRY;
697
698 if (sp != ERR_PTR(-EEXIST))
699 link_shadow_page(vcpu, it.sptep, sp);
700
701 if (fault->write && table_gfn == fault->gfn)
702 fault->write_fault_to_shadow_pgtable = true;
703 }
704
705 /*
706 * Adjust the hugepage size _after_ resolving indirect shadow pages.
707 * KVM doesn't support mapping hugepages into the guest for gfns that
708 * are being shadowed by KVM, i.e. allocating a new shadow page may
709 * affect the allowed hugepage size.
710 */
711 kvm_mmu_hugepage_adjust(vcpu, fault);
712
713 trace_kvm_mmu_spte_requested(fault);
714
715 for (; shadow_walk_okay(&it); shadow_walk_next(&it)) {
716 /*
717 * We cannot overwrite existing page tables with an NX
718 * large page, as the leaf could be executable.
719 */
720 if (fault->nx_huge_page_workaround_enabled)
721 disallowed_hugepage_adjust(fault, *it.sptep, it.level);
722
723 base_gfn = gfn_round_for_level(fault->gfn, it.level);
724 if (it.level == fault->goal_level)
725 break;
726
727 validate_direct_spte(vcpu, it.sptep, direct_access);
728
729 sp = kvm_mmu_get_child_sp(vcpu, it.sptep, base_gfn,
730 true, direct_access);
731 if (sp == ERR_PTR(-EEXIST))
732 continue;
733
734 link_shadow_page(vcpu, it.sptep, sp);
735 if (fault->huge_page_disallowed)
736 account_nx_huge_page(vcpu->kvm, sp,
737 fault->req_level >= it.level);
738 }
739
740 if (WARN_ON_ONCE(it.level != fault->goal_level))
741 return -EFAULT;
742
743 ret = mmu_set_spte(vcpu, fault->slot, it.sptep, gw->pte_access,
744 base_gfn, fault->pfn, fault);
745 if (ret == RET_PF_SPURIOUS)
746 return ret;
747
748 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
749 return ret;
750}
751
752/*
753 * Page fault handler. There are several causes for a page fault:
754 * - there is no shadow pte for the guest pte
755 * - write access through a shadow pte marked read only so that we can set
756 * the dirty bit
757 * - write access to a shadow pte marked read only so we can update the page
758 * dirty bitmap, when userspace requests it
759 * - mmio access; in this case we will never install a present shadow pte
760 * - normal guest page fault due to the guest pte marked not present, not
761 * writable, or not executable
762 *
763 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
764 * a negative value on error.
765 */
766static int FNAME(page_fault)(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
767{
768 struct guest_walker walker;
769 int r;
770
771 WARN_ON_ONCE(fault->is_tdp);
772
773 /*
774 * Look up the guest pte for the faulting address.
775 * If PFEC.RSVD is set, this is a shadow page fault.
776 * The bit needs to be cleared before walking guest page tables.
777 */
778 r = FNAME(walk_addr)(&walker, vcpu, fault->addr,
779 fault->error_code & ~PFERR_RSVD_MASK);
780
781 /*
782 * The page is not mapped by the guest. Let the guest handle it.
783 */
784 if (!r) {
785 if (!fault->prefetch)
786 kvm_inject_emulated_page_fault(vcpu, &walker.fault);
787
788 return RET_PF_RETRY;
789 }
790
791 fault->gfn = walker.gfn;
792 fault->max_level = walker.level;
793 fault->slot = kvm_vcpu_gfn_to_memslot(vcpu, fault->gfn);
794
795 if (page_fault_handle_page_track(vcpu, fault)) {
796 shadow_page_table_clear_flood(vcpu, fault->addr);
797 return RET_PF_WRITE_PROTECTED;
798 }
799
800 r = mmu_topup_memory_caches(vcpu, true);
801 if (r)
802 return r;
803
804 r = kvm_mmu_faultin_pfn(vcpu, fault, walker.pte_access);
805 if (r != RET_PF_CONTINUE)
806 return r;
807
808 /*
809 * Do not change pte_access if the pfn is a mmio page, otherwise
810 * we will cache the incorrect access into mmio spte.
811 */
812 if (fault->write && !(walker.pte_access & ACC_WRITE_MASK) &&
813 !is_cr0_wp(vcpu->arch.mmu) && !fault->user && fault->slot) {
814 walker.pte_access |= ACC_WRITE_MASK;
815 walker.pte_access &= ~ACC_USER_MASK;
816
817 /*
818 * If we converted a user page to a kernel page,
819 * so that the kernel can write to it when cr0.wp=0,
820 * then we should prevent the kernel from executing it
821 * if SMEP is enabled.
822 */
823 if (is_cr4_smep(vcpu->arch.mmu))
824 walker.pte_access &= ~ACC_EXEC_MASK;
825 }
826
827 r = RET_PF_RETRY;
828 write_lock(&vcpu->kvm->mmu_lock);
829
830 if (is_page_fault_stale(vcpu, fault))
831 goto out_unlock;
832
833 r = make_mmu_pages_available(vcpu);
834 if (r)
835 goto out_unlock;
836 r = FNAME(fetch)(vcpu, fault, &walker);
837
838out_unlock:
839 kvm_mmu_finish_page_fault(vcpu, fault, r);
840 write_unlock(&vcpu->kvm->mmu_lock);
841 return r;
842}
843
844static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
845{
846 int offset = 0;
847
848 WARN_ON_ONCE(sp->role.level != PG_LEVEL_4K);
849
850 if (PTTYPE == 32)
851 offset = sp->role.quadrant << SPTE_LEVEL_BITS;
852
853 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
854}
855
856/* Note, @addr is a GPA when gva_to_gpa() translates an L2 GPA to an L1 GPA. */
857static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
858 gpa_t addr, u64 access,
859 struct x86_exception *exception)
860{
861 struct guest_walker walker;
862 gpa_t gpa = INVALID_GPA;
863 int r;
864
865#ifndef CONFIG_X86_64
866 /* A 64-bit GVA should be impossible on 32-bit KVM. */
867 WARN_ON_ONCE((addr >> 32) && mmu == vcpu->arch.walk_mmu);
868#endif
869
870 r = FNAME(walk_addr_generic)(&walker, vcpu, mmu, addr, access);
871
872 if (r) {
873 gpa = gfn_to_gpa(walker.gfn);
874 gpa |= addr & ~PAGE_MASK;
875 } else if (exception)
876 *exception = walker.fault;
877
878 return gpa;
879}
880
881/*
882 * Using the information in sp->shadowed_translation (kvm_mmu_page_get_gfn()) is
883 * safe because SPTEs are protected by mmu_notifiers and memslot generations, so
884 * the pfn for a given gfn can't change unless all SPTEs pointing to the gfn are
885 * nuked first.
886 *
887 * Returns
888 * < 0: failed to sync spte
889 * 0: the spte is synced and no tlb flushing is required
890 * > 0: the spte is synced and tlb flushing is required
891 */
892static int FNAME(sync_spte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, int i)
893{
894 bool host_writable;
895 gpa_t first_pte_gpa;
896 u64 *sptep, spte;
897 struct kvm_memory_slot *slot;
898 unsigned pte_access;
899 pt_element_t gpte;
900 gpa_t pte_gpa;
901 gfn_t gfn;
902
903 if (WARN_ON_ONCE(sp->spt[i] == SHADOW_NONPRESENT_VALUE ||
904 !sp->shadowed_translation))
905 return 0;
906
907 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
908 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
909
910 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
911 sizeof(pt_element_t)))
912 return -1;
913
914 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte))
915 return 1;
916
917 gfn = gpte_to_gfn(gpte);
918 pte_access = sp->role.access;
919 pte_access &= FNAME(gpte_access)(gpte);
920 FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
921
922 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access))
923 return 0;
924
925 /*
926 * Drop the SPTE if the new protections result in no effective
927 * "present" bit or if the gfn is changing. The former case
928 * only affects EPT with execute-only support with pte_access==0;
929 * all other paging modes will create a read-only SPTE if
930 * pte_access is zero.
931 */
932 if ((pte_access | shadow_present_mask) == SHADOW_NONPRESENT_VALUE ||
933 gfn != kvm_mmu_page_get_gfn(sp, i)) {
934 drop_spte(vcpu->kvm, &sp->spt[i]);
935 return 1;
936 }
937 /*
938 * Do nothing if the permissions are unchanged. The existing SPTE is
939 * still, and prefetch_invalid_gpte() has verified that the A/D bits
940 * are set in the "new" gPTE, i.e. there is no danger of missing an A/D
941 * update due to A/D bits being set in the SPTE but not the gPTE.
942 */
943 if (kvm_mmu_page_get_access(sp, i) == pte_access)
944 return 0;
945
946 /* Update the shadowed access bits in case they changed. */
947 kvm_mmu_page_set_access(sp, i, pte_access);
948
949 sptep = &sp->spt[i];
950 spte = *sptep;
951 host_writable = spte & shadow_host_writable_mask;
952 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
953 make_spte(vcpu, sp, slot, pte_access, gfn,
954 spte_to_pfn(spte), spte, true, true,
955 host_writable, &spte);
956
957 /*
958 * There is no need to mark the pfn dirty, as the new protections must
959 * be a subset of the old protections, i.e. synchronizing a SPTE cannot
960 * change the SPTE from read-only to writable.
961 */
962 return mmu_spte_update(sptep, spte);
963}
964
965#undef pt_element_t
966#undef guest_walker
967#undef FNAME
968#undef PT_BASE_ADDR_MASK
969#undef PT_INDEX
970#undef PT_LVL_ADDR_MASK
971#undef PT_LVL_OFFSET_MASK
972#undef PT_LEVEL_BITS
973#undef PT_MAX_FULL_LEVELS
974#undef gpte_to_gfn
975#undef gpte_to_gfn_lvl
976#undef PT_GUEST_ACCESSED_MASK
977#undef PT_GUEST_DIRTY_MASK
978#undef PT_GUEST_DIRTY_SHIFT
979#undef PT_GUEST_ACCESSED_SHIFT
980#undef PT_HAVE_ACCESSED_DIRTY
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
7 *
8 * MMU support
9 *
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 *
13 * Authors:
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
16 */
17
18/*
19 * The MMU needs to be able to access/walk 32-bit and 64-bit guest page tables,
20 * as well as guest EPT tables, so the code in this file is compiled thrice,
21 * once per guest PTE type. The per-type defines are #undef'd at the end.
22 */
23
24#if PTTYPE == 64
25 #define pt_element_t u64
26 #define guest_walker guest_walker64
27 #define FNAME(name) paging##64_##name
28 #define PT_LEVEL_BITS 9
29 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
30 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
31 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
32 #ifdef CONFIG_X86_64
33 #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL
34 #else
35 #define PT_MAX_FULL_LEVELS 2
36 #endif
37#elif PTTYPE == 32
38 #define pt_element_t u32
39 #define guest_walker guest_walker32
40 #define FNAME(name) paging##32_##name
41 #define PT_LEVEL_BITS 10
42 #define PT_MAX_FULL_LEVELS 2
43 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
44 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
45 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
46
47 #define PT32_DIR_PSE36_SIZE 4
48 #define PT32_DIR_PSE36_SHIFT 13
49 #define PT32_DIR_PSE36_MASK \
50 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
51#elif PTTYPE == PTTYPE_EPT
52 #define pt_element_t u64
53 #define guest_walker guest_walkerEPT
54 #define FNAME(name) ept_##name
55 #define PT_LEVEL_BITS 9
56 #define PT_GUEST_DIRTY_SHIFT 9
57 #define PT_GUEST_ACCESSED_SHIFT 8
58 #define PT_HAVE_ACCESSED_DIRTY(mmu) (!(mmu)->cpu_role.base.ad_disabled)
59 #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL
60#else
61 #error Invalid PTTYPE value
62#endif
63
64/* Common logic, but per-type values. These also need to be undefined. */
65#define PT_BASE_ADDR_MASK ((pt_element_t)(((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)))
66#define PT_LVL_ADDR_MASK(lvl) __PT_LVL_ADDR_MASK(PT_BASE_ADDR_MASK, lvl, PT_LEVEL_BITS)
67#define PT_LVL_OFFSET_MASK(lvl) __PT_LVL_OFFSET_MASK(PT_BASE_ADDR_MASK, lvl, PT_LEVEL_BITS)
68#define PT_INDEX(addr, lvl) __PT_INDEX(addr, lvl, PT_LEVEL_BITS)
69
70#define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT)
71#define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT)
72
73#define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
74#define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PG_LEVEL_4K)
75
76/*
77 * The guest_walker structure emulates the behavior of the hardware page
78 * table walker.
79 */
80struct guest_walker {
81 int level;
82 unsigned max_level;
83 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
84 pt_element_t ptes[PT_MAX_FULL_LEVELS];
85 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
86 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
87 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
88 bool pte_writable[PT_MAX_FULL_LEVELS];
89 unsigned int pt_access[PT_MAX_FULL_LEVELS];
90 unsigned int pte_access;
91 gfn_t gfn;
92 struct x86_exception fault;
93};
94
95#if PTTYPE == 32
96static inline gfn_t pse36_gfn_delta(u32 gpte)
97{
98 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
99
100 return (gpte & PT32_DIR_PSE36_MASK) << shift;
101}
102#endif
103
104static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
105{
106 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
107}
108
109static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access,
110 unsigned gpte)
111{
112 unsigned mask;
113
114 /* dirty bit is not supported, so no need to track it */
115 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
116 return;
117
118 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
119
120 mask = (unsigned)~ACC_WRITE_MASK;
121 /* Allow write access to dirty gptes */
122 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
123 PT_WRITABLE_MASK;
124 *access &= mask;
125}
126
127static inline int FNAME(is_present_gpte)(unsigned long pte)
128{
129#if PTTYPE != PTTYPE_EPT
130 return pte & PT_PRESENT_MASK;
131#else
132 return pte & 7;
133#endif
134}
135
136static bool FNAME(is_bad_mt_xwr)(struct rsvd_bits_validate *rsvd_check, u64 gpte)
137{
138#if PTTYPE != PTTYPE_EPT
139 return false;
140#else
141 return __is_bad_mt_xwr(rsvd_check, gpte);
142#endif
143}
144
145static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level)
146{
147 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level) ||
148 FNAME(is_bad_mt_xwr)(&mmu->guest_rsvd_check, gpte);
149}
150
151static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
152 struct kvm_mmu_page *sp, u64 *spte,
153 u64 gpte)
154{
155 if (!FNAME(is_present_gpte)(gpte))
156 goto no_present;
157
158 /* Prefetch only accessed entries (unless A/D bits are disabled). */
159 if (PT_HAVE_ACCESSED_DIRTY(vcpu->arch.mmu) &&
160 !(gpte & PT_GUEST_ACCESSED_MASK))
161 goto no_present;
162
163 if (FNAME(is_rsvd_bits_set)(vcpu->arch.mmu, gpte, PG_LEVEL_4K))
164 goto no_present;
165
166 return false;
167
168no_present:
169 drop_spte(vcpu->kvm, spte);
170 return true;
171}
172
173/*
174 * For PTTYPE_EPT, a page table can be executable but not readable
175 * on supported processors. Therefore, set_spte does not automatically
176 * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
177 * to signify readability since it isn't used in the EPT case
178 */
179static inline unsigned FNAME(gpte_access)(u64 gpte)
180{
181 unsigned access;
182#if PTTYPE == PTTYPE_EPT
183 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
184 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
185 ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0);
186#else
187 BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK);
188 BUILD_BUG_ON(ACC_EXEC_MASK != 1);
189 access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK);
190 /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */
191 access ^= (gpte >> PT64_NX_SHIFT);
192#endif
193
194 return access;
195}
196
197static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
198 struct kvm_mmu *mmu,
199 struct guest_walker *walker,
200 gpa_t addr, int write_fault)
201{
202 unsigned level, index;
203 pt_element_t pte, orig_pte;
204 pt_element_t __user *ptep_user;
205 gfn_t table_gfn;
206 int ret;
207
208 /* dirty/accessed bits are not supported, so no need to update them */
209 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
210 return 0;
211
212 for (level = walker->max_level; level >= walker->level; --level) {
213 pte = orig_pte = walker->ptes[level - 1];
214 table_gfn = walker->table_gfn[level - 1];
215 ptep_user = walker->ptep_user[level - 1];
216 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
217 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
218 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
219 pte |= PT_GUEST_ACCESSED_MASK;
220 }
221 if (level == walker->level && write_fault &&
222 !(pte & PT_GUEST_DIRTY_MASK)) {
223 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
224#if PTTYPE == PTTYPE_EPT
225 if (kvm_x86_ops.nested_ops->write_log_dirty(vcpu, addr))
226 return -EINVAL;
227#endif
228 pte |= PT_GUEST_DIRTY_MASK;
229 }
230 if (pte == orig_pte)
231 continue;
232
233 /*
234 * If the slot is read-only, simply do not process the accessed
235 * and dirty bits. This is the correct thing to do if the slot
236 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
237 * are only supported if the accessed and dirty bits are already
238 * set in the ROM (so that MMIO writes are never needed).
239 *
240 * Note that NPT does not allow this at all and faults, since
241 * it always wants nested page table entries for the guest
242 * page tables to be writable. And EPT works but will simply
243 * overwrite the read-only memory to set the accessed and dirty
244 * bits.
245 */
246 if (unlikely(!walker->pte_writable[level - 1]))
247 continue;
248
249 ret = __try_cmpxchg_user(ptep_user, &orig_pte, pte, fault);
250 if (ret)
251 return ret;
252
253 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
254 walker->ptes[level - 1] = pte;
255 }
256 return 0;
257}
258
259static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
260{
261 unsigned pkeys = 0;
262#if PTTYPE == 64
263 pte_t pte = {.pte = gpte};
264
265 pkeys = pte_flags_pkey(pte_flags(pte));
266#endif
267 return pkeys;
268}
269
270static inline bool FNAME(is_last_gpte)(struct kvm_mmu *mmu,
271 unsigned int level, unsigned int gpte)
272{
273 /*
274 * For EPT and PAE paging (both variants), bit 7 is either reserved at
275 * all level or indicates a huge page (ignoring CR3/EPTP). In either
276 * case, bit 7 being set terminates the walk.
277 */
278#if PTTYPE == 32
279 /*
280 * 32-bit paging requires special handling because bit 7 is ignored if
281 * CR4.PSE=0, not reserved. Clear bit 7 in the gpte if the level is
282 * greater than the last level for which bit 7 is the PAGE_SIZE bit.
283 *
284 * The RHS has bit 7 set iff level < (2 + PSE). If it is clear, bit 7
285 * is not reserved and does not indicate a large page at this level,
286 * so clear PT_PAGE_SIZE_MASK in gpte if that is the case.
287 */
288 gpte &= level - (PT32_ROOT_LEVEL + mmu->cpu_role.ext.cr4_pse);
289#endif
290 /*
291 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
292 * iff level <= PG_LEVEL_4K, which for our purpose means
293 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
294 */
295 gpte |= level - PG_LEVEL_4K - 1;
296
297 return gpte & PT_PAGE_SIZE_MASK;
298}
299/*
300 * Fetch a guest pte for a guest virtual address, or for an L2's GPA.
301 */
302static int FNAME(walk_addr_generic)(struct guest_walker *walker,
303 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
304 gpa_t addr, u64 access)
305{
306 int ret;
307 pt_element_t pte;
308 pt_element_t __user *ptep_user;
309 gfn_t table_gfn;
310 u64 pt_access, pte_access;
311 unsigned index, accessed_dirty, pte_pkey;
312 u64 nested_access;
313 gpa_t pte_gpa;
314 bool have_ad;
315 int offset;
316 u64 walk_nx_mask = 0;
317 const int write_fault = access & PFERR_WRITE_MASK;
318 const int user_fault = access & PFERR_USER_MASK;
319 const int fetch_fault = access & PFERR_FETCH_MASK;
320 u16 errcode = 0;
321 gpa_t real_gpa;
322 gfn_t gfn;
323
324 trace_kvm_mmu_pagetable_walk(addr, access);
325retry_walk:
326 walker->level = mmu->cpu_role.base.level;
327 pte = mmu->get_guest_pgd(vcpu);
328 have_ad = PT_HAVE_ACCESSED_DIRTY(mmu);
329
330#if PTTYPE == 64
331 walk_nx_mask = 1ULL << PT64_NX_SHIFT;
332 if (walker->level == PT32E_ROOT_LEVEL) {
333 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
334 trace_kvm_mmu_paging_element(pte, walker->level);
335 if (!FNAME(is_present_gpte)(pte))
336 goto error;
337 --walker->level;
338 }
339#endif
340 walker->max_level = walker->level;
341 ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
342
343 /*
344 * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging
345 * by the MOV to CR instruction are treated as reads and do not cause the
346 * processor to set the dirty flag in any EPT paging-structure entry.
347 */
348 nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK;
349
350 pte_access = ~0;
351 ++walker->level;
352
353 do {
354 unsigned long host_addr;
355
356 pt_access = pte_access;
357 --walker->level;
358
359 index = PT_INDEX(addr, walker->level);
360 table_gfn = gpte_to_gfn(pte);
361 offset = index * sizeof(pt_element_t);
362 pte_gpa = gfn_to_gpa(table_gfn) + offset;
363
364 BUG_ON(walker->level < 1);
365 walker->table_gfn[walker->level - 1] = table_gfn;
366 walker->pte_gpa[walker->level - 1] = pte_gpa;
367
368 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(table_gfn),
369 nested_access, &walker->fault);
370
371 /*
372 * FIXME: This can happen if emulation (for of an INS/OUTS
373 * instruction) triggers a nested page fault. The exit
374 * qualification / exit info field will incorrectly have
375 * "guest page access" as the nested page fault's cause,
376 * instead of "guest page structure access". To fix this,
377 * the x86_exception struct should be augmented with enough
378 * information to fix the exit_qualification or exit_info_1
379 * fields.
380 */
381 if (unlikely(real_gpa == INVALID_GPA))
382 return 0;
383
384 host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, gpa_to_gfn(real_gpa),
385 &walker->pte_writable[walker->level - 1]);
386 if (unlikely(kvm_is_error_hva(host_addr)))
387 goto error;
388
389 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
390 if (unlikely(__get_user(pte, ptep_user)))
391 goto error;
392 walker->ptep_user[walker->level - 1] = ptep_user;
393
394 trace_kvm_mmu_paging_element(pte, walker->level);
395
396 /*
397 * Inverting the NX it lets us AND it like other
398 * permission bits.
399 */
400 pte_access = pt_access & (pte ^ walk_nx_mask);
401
402 if (unlikely(!FNAME(is_present_gpte)(pte)))
403 goto error;
404
405 if (unlikely(FNAME(is_rsvd_bits_set)(mmu, pte, walker->level))) {
406 errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
407 goto error;
408 }
409
410 walker->ptes[walker->level - 1] = pte;
411
412 /* Convert to ACC_*_MASK flags for struct guest_walker. */
413 walker->pt_access[walker->level - 1] = FNAME(gpte_access)(pt_access ^ walk_nx_mask);
414 } while (!FNAME(is_last_gpte)(mmu, walker->level, pte));
415
416 pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
417 accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0;
418
419 /* Convert to ACC_*_MASK flags for struct guest_walker. */
420 walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask);
421 errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access);
422 if (unlikely(errcode))
423 goto error;
424
425 gfn = gpte_to_gfn_lvl(pte, walker->level);
426 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
427
428#if PTTYPE == 32
429 if (walker->level > PG_LEVEL_4K && is_cpuid_PSE36())
430 gfn += pse36_gfn_delta(pte);
431#endif
432
433 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(gfn), access, &walker->fault);
434 if (real_gpa == INVALID_GPA)
435 return 0;
436
437 walker->gfn = real_gpa >> PAGE_SHIFT;
438
439 if (!write_fault)
440 FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte);
441 else
442 /*
443 * On a write fault, fold the dirty bit into accessed_dirty.
444 * For modes without A/D bits support accessed_dirty will be
445 * always clear.
446 */
447 accessed_dirty &= pte >>
448 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
449
450 if (unlikely(!accessed_dirty)) {
451 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker,
452 addr, write_fault);
453 if (unlikely(ret < 0))
454 goto error;
455 else if (ret)
456 goto retry_walk;
457 }
458
459 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
460 __func__, (u64)pte, walker->pte_access,
461 walker->pt_access[walker->level - 1]);
462 return 1;
463
464error:
465 errcode |= write_fault | user_fault;
466 if (fetch_fault && (is_efer_nx(mmu) || is_cr4_smep(mmu)))
467 errcode |= PFERR_FETCH_MASK;
468
469 walker->fault.vector = PF_VECTOR;
470 walker->fault.error_code_valid = true;
471 walker->fault.error_code = errcode;
472
473#if PTTYPE == PTTYPE_EPT
474 /*
475 * Use PFERR_RSVD_MASK in error_code to tell if EPT
476 * misconfiguration requires to be injected. The detection is
477 * done by is_rsvd_bits_set() above.
478 *
479 * We set up the value of exit_qualification to inject:
480 * [2:0] - Derive from the access bits. The exit_qualification might be
481 * out of date if it is serving an EPT misconfiguration.
482 * [5:3] - Calculated by the page walk of the guest EPT page tables
483 * [7:8] - Derived from [7:8] of real exit_qualification
484 *
485 * The other bits are set to 0.
486 */
487 if (!(errcode & PFERR_RSVD_MASK)) {
488 vcpu->arch.exit_qualification &= (EPT_VIOLATION_GVA_IS_VALID |
489 EPT_VIOLATION_GVA_TRANSLATED);
490 if (write_fault)
491 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE;
492 if (user_fault)
493 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ;
494 if (fetch_fault)
495 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR;
496
497 /*
498 * Note, pte_access holds the raw RWX bits from the EPTE, not
499 * ACC_*_MASK flags!
500 */
501 vcpu->arch.exit_qualification |= (pte_access & VMX_EPT_RWX_MASK) <<
502 EPT_VIOLATION_RWX_SHIFT;
503 }
504#endif
505 walker->fault.address = addr;
506 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
507 walker->fault.async_page_fault = false;
508
509 trace_kvm_mmu_walker_error(walker->fault.error_code);
510 return 0;
511}
512
513static int FNAME(walk_addr)(struct guest_walker *walker,
514 struct kvm_vcpu *vcpu, gpa_t addr, u64 access)
515{
516 return FNAME(walk_addr_generic)(walker, vcpu, vcpu->arch.mmu, addr,
517 access);
518}
519
520static bool
521FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
522 u64 *spte, pt_element_t gpte, bool no_dirty_log)
523{
524 struct kvm_memory_slot *slot;
525 unsigned pte_access;
526 gfn_t gfn;
527 kvm_pfn_t pfn;
528
529 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
530 return false;
531
532 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
533
534 gfn = gpte_to_gfn(gpte);
535 pte_access = sp->role.access & FNAME(gpte_access)(gpte);
536 FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
537
538 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn,
539 no_dirty_log && (pte_access & ACC_WRITE_MASK));
540 if (!slot)
541 return false;
542
543 pfn = gfn_to_pfn_memslot_atomic(slot, gfn);
544 if (is_error_pfn(pfn))
545 return false;
546
547 mmu_set_spte(vcpu, slot, spte, pte_access, gfn, pfn, NULL);
548 kvm_release_pfn_clean(pfn);
549 return true;
550}
551
552static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
553 struct guest_walker *gw, int level)
554{
555 pt_element_t curr_pte;
556 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
557 u64 mask;
558 int r, index;
559
560 if (level == PG_LEVEL_4K) {
561 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
562 base_gpa = pte_gpa & ~mask;
563 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
564
565 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
566 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
567 curr_pte = gw->prefetch_ptes[index];
568 } else
569 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
570 &curr_pte, sizeof(curr_pte));
571
572 return r || curr_pte != gw->ptes[level - 1];
573}
574
575static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
576 u64 *sptep)
577{
578 struct kvm_mmu_page *sp;
579 pt_element_t *gptep = gw->prefetch_ptes;
580 u64 *spte;
581 int i;
582
583 sp = sptep_to_sp(sptep);
584
585 if (sp->role.level > PG_LEVEL_4K)
586 return;
587
588 /*
589 * If addresses are being invalidated, skip prefetching to avoid
590 * accidentally prefetching those addresses.
591 */
592 if (unlikely(vcpu->kvm->mmu_invalidate_in_progress))
593 return;
594
595 if (sp->role.direct)
596 return __direct_pte_prefetch(vcpu, sp, sptep);
597
598 i = spte_index(sptep) & ~(PTE_PREFETCH_NUM - 1);
599 spte = sp->spt + i;
600
601 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
602 if (spte == sptep)
603 continue;
604
605 if (is_shadow_present_pte(*spte))
606 continue;
607
608 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
609 break;
610 }
611}
612
613/*
614 * Fetch a shadow pte for a specific level in the paging hierarchy.
615 * If the guest tries to write a write-protected page, we need to
616 * emulate this operation, return 1 to indicate this case.
617 */
618static int FNAME(fetch)(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault,
619 struct guest_walker *gw)
620{
621 struct kvm_mmu_page *sp = NULL;
622 struct kvm_shadow_walk_iterator it;
623 unsigned int direct_access, access;
624 int top_level, ret;
625 gfn_t base_gfn = fault->gfn;
626
627 WARN_ON_ONCE(gw->gfn != base_gfn);
628 direct_access = gw->pte_access;
629
630 top_level = vcpu->arch.mmu->cpu_role.base.level;
631 if (top_level == PT32E_ROOT_LEVEL)
632 top_level = PT32_ROOT_LEVEL;
633 /*
634 * Verify that the top-level gpte is still there. Since the page
635 * is a root page, it is either write protected (and cannot be
636 * changed from now on) or it is invalid (in which case, we don't
637 * really care if it changes underneath us after this point).
638 */
639 if (FNAME(gpte_changed)(vcpu, gw, top_level))
640 goto out_gpte_changed;
641
642 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root.hpa)))
643 goto out_gpte_changed;
644
645 for (shadow_walk_init(&it, vcpu, fault->addr);
646 shadow_walk_okay(&it) && it.level > gw->level;
647 shadow_walk_next(&it)) {
648 gfn_t table_gfn;
649
650 clear_sp_write_flooding_count(it.sptep);
651
652 table_gfn = gw->table_gfn[it.level - 2];
653 access = gw->pt_access[it.level - 2];
654 sp = kvm_mmu_get_child_sp(vcpu, it.sptep, table_gfn,
655 false, access);
656
657 if (sp != ERR_PTR(-EEXIST)) {
658 /*
659 * We must synchronize the pagetable before linking it
660 * because the guest doesn't need to flush tlb when
661 * the gpte is changed from non-present to present.
662 * Otherwise, the guest may use the wrong mapping.
663 *
664 * For PG_LEVEL_4K, kvm_mmu_get_page() has already
665 * synchronized it transiently via kvm_sync_page().
666 *
667 * For higher level pagetable, we synchronize it via
668 * the slower mmu_sync_children(). If it needs to
669 * break, some progress has been made; return
670 * RET_PF_RETRY and retry on the next #PF.
671 * KVM_REQ_MMU_SYNC is not necessary but it
672 * expedites the process.
673 */
674 if (sp->unsync_children &&
675 mmu_sync_children(vcpu, sp, false))
676 return RET_PF_RETRY;
677 }
678
679 /*
680 * Verify that the gpte in the page we've just write
681 * protected is still there.
682 */
683 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
684 goto out_gpte_changed;
685
686 if (sp != ERR_PTR(-EEXIST))
687 link_shadow_page(vcpu, it.sptep, sp);
688 }
689
690 kvm_mmu_hugepage_adjust(vcpu, fault);
691
692 trace_kvm_mmu_spte_requested(fault);
693
694 for (; shadow_walk_okay(&it); shadow_walk_next(&it)) {
695 clear_sp_write_flooding_count(it.sptep);
696
697 /*
698 * We cannot overwrite existing page tables with an NX
699 * large page, as the leaf could be executable.
700 */
701 if (fault->nx_huge_page_workaround_enabled)
702 disallowed_hugepage_adjust(fault, *it.sptep, it.level);
703
704 base_gfn = fault->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
705 if (it.level == fault->goal_level)
706 break;
707
708 validate_direct_spte(vcpu, it.sptep, direct_access);
709
710 sp = kvm_mmu_get_child_sp(vcpu, it.sptep, base_gfn,
711 true, direct_access);
712 if (sp == ERR_PTR(-EEXIST))
713 continue;
714
715 link_shadow_page(vcpu, it.sptep, sp);
716 if (fault->huge_page_disallowed)
717 account_nx_huge_page(vcpu->kvm, sp,
718 fault->req_level >= it.level);
719 }
720
721 if (WARN_ON_ONCE(it.level != fault->goal_level))
722 return -EFAULT;
723
724 ret = mmu_set_spte(vcpu, fault->slot, it.sptep, gw->pte_access,
725 base_gfn, fault->pfn, fault);
726 if (ret == RET_PF_SPURIOUS)
727 return ret;
728
729 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
730 return ret;
731
732out_gpte_changed:
733 return RET_PF_RETRY;
734}
735
736 /*
737 * To see whether the mapped gfn can write its page table in the current
738 * mapping.
739 *
740 * It is the helper function of FNAME(page_fault). When guest uses large page
741 * size to map the writable gfn which is used as current page table, we should
742 * force kvm to use small page size to map it because new shadow page will be
743 * created when kvm establishes shadow page table that stop kvm using large
744 * page size. Do it early can avoid unnecessary #PF and emulation.
745 *
746 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
747 * currently used as its page table.
748 *
749 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
750 * since the PDPT is always shadowed, that means, we can not use large page
751 * size to map the gfn which is used as PDPT.
752 */
753static bool
754FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
755 struct guest_walker *walker, bool user_fault,
756 bool *write_fault_to_shadow_pgtable)
757{
758 int level;
759 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
760 bool self_changed = false;
761
762 if (!(walker->pte_access & ACC_WRITE_MASK ||
763 (!is_cr0_wp(vcpu->arch.mmu) && !user_fault)))
764 return false;
765
766 for (level = walker->level; level <= walker->max_level; level++) {
767 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
768
769 self_changed |= !(gfn & mask);
770 *write_fault_to_shadow_pgtable |= !gfn;
771 }
772
773 return self_changed;
774}
775
776/*
777 * Page fault handler. There are several causes for a page fault:
778 * - there is no shadow pte for the guest pte
779 * - write access through a shadow pte marked read only so that we can set
780 * the dirty bit
781 * - write access to a shadow pte marked read only so we can update the page
782 * dirty bitmap, when userspace requests it
783 * - mmio access; in this case we will never install a present shadow pte
784 * - normal guest page fault due to the guest pte marked not present, not
785 * writable, or not executable
786 *
787 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
788 * a negative value on error.
789 */
790static int FNAME(page_fault)(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
791{
792 struct guest_walker walker;
793 int r;
794 unsigned long mmu_seq;
795 bool is_self_change_mapping;
796
797 pgprintk("%s: addr %lx err %x\n", __func__, fault->addr, fault->error_code);
798 WARN_ON_ONCE(fault->is_tdp);
799
800 /*
801 * Look up the guest pte for the faulting address.
802 * If PFEC.RSVD is set, this is a shadow page fault.
803 * The bit needs to be cleared before walking guest page tables.
804 */
805 r = FNAME(walk_addr)(&walker, vcpu, fault->addr,
806 fault->error_code & ~PFERR_RSVD_MASK);
807
808 /*
809 * The page is not mapped by the guest. Let the guest handle it.
810 */
811 if (!r) {
812 pgprintk("%s: guest page fault\n", __func__);
813 if (!fault->prefetch)
814 kvm_inject_emulated_page_fault(vcpu, &walker.fault);
815
816 return RET_PF_RETRY;
817 }
818
819 fault->gfn = walker.gfn;
820 fault->slot = kvm_vcpu_gfn_to_memslot(vcpu, fault->gfn);
821
822 if (page_fault_handle_page_track(vcpu, fault)) {
823 shadow_page_table_clear_flood(vcpu, fault->addr);
824 return RET_PF_EMULATE;
825 }
826
827 r = mmu_topup_memory_caches(vcpu, true);
828 if (r)
829 return r;
830
831 vcpu->arch.write_fault_to_shadow_pgtable = false;
832
833 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
834 &walker, fault->user, &vcpu->arch.write_fault_to_shadow_pgtable);
835
836 if (is_self_change_mapping)
837 fault->max_level = PG_LEVEL_4K;
838 else
839 fault->max_level = walker.level;
840
841 mmu_seq = vcpu->kvm->mmu_invalidate_seq;
842 smp_rmb();
843
844 r = kvm_faultin_pfn(vcpu, fault);
845 if (r != RET_PF_CONTINUE)
846 return r;
847
848 r = handle_abnormal_pfn(vcpu, fault, walker.pte_access);
849 if (r != RET_PF_CONTINUE)
850 return r;
851
852 /*
853 * Do not change pte_access if the pfn is a mmio page, otherwise
854 * we will cache the incorrect access into mmio spte.
855 */
856 if (fault->write && !(walker.pte_access & ACC_WRITE_MASK) &&
857 !is_cr0_wp(vcpu->arch.mmu) && !fault->user && fault->slot) {
858 walker.pte_access |= ACC_WRITE_MASK;
859 walker.pte_access &= ~ACC_USER_MASK;
860
861 /*
862 * If we converted a user page to a kernel page,
863 * so that the kernel can write to it when cr0.wp=0,
864 * then we should prevent the kernel from executing it
865 * if SMEP is enabled.
866 */
867 if (is_cr4_smep(vcpu->arch.mmu))
868 walker.pte_access &= ~ACC_EXEC_MASK;
869 }
870
871 r = RET_PF_RETRY;
872 write_lock(&vcpu->kvm->mmu_lock);
873
874 if (is_page_fault_stale(vcpu, fault, mmu_seq))
875 goto out_unlock;
876
877 r = make_mmu_pages_available(vcpu);
878 if (r)
879 goto out_unlock;
880 r = FNAME(fetch)(vcpu, fault, &walker);
881
882out_unlock:
883 write_unlock(&vcpu->kvm->mmu_lock);
884 kvm_release_pfn_clean(fault->pfn);
885 return r;
886}
887
888static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
889{
890 int offset = 0;
891
892 WARN_ON(sp->role.level != PG_LEVEL_4K);
893
894 if (PTTYPE == 32)
895 offset = sp->role.quadrant << SPTE_LEVEL_BITS;
896
897 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
898}
899
900static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa)
901{
902 struct kvm_shadow_walk_iterator iterator;
903 struct kvm_mmu_page *sp;
904 u64 old_spte;
905 int level;
906 u64 *sptep;
907
908 vcpu_clear_mmio_info(vcpu, gva);
909
910 /*
911 * No need to check return value here, rmap_can_add() can
912 * help us to skip pte prefetch later.
913 */
914 mmu_topup_memory_caches(vcpu, true);
915
916 if (!VALID_PAGE(root_hpa)) {
917 WARN_ON(1);
918 return;
919 }
920
921 write_lock(&vcpu->kvm->mmu_lock);
922 for_each_shadow_entry_using_root(vcpu, root_hpa, gva, iterator) {
923 level = iterator.level;
924 sptep = iterator.sptep;
925
926 sp = sptep_to_sp(sptep);
927 old_spte = *sptep;
928 if (is_last_spte(old_spte, level)) {
929 pt_element_t gpte;
930 gpa_t pte_gpa;
931
932 if (!sp->unsync)
933 break;
934
935 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
936 pte_gpa += spte_index(sptep) * sizeof(pt_element_t);
937
938 mmu_page_zap_pte(vcpu->kvm, sp, sptep, NULL);
939 if (is_shadow_present_pte(old_spte))
940 kvm_flush_remote_tlbs_with_address(vcpu->kvm,
941 sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level));
942
943 if (!rmap_can_add(vcpu))
944 break;
945
946 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
947 sizeof(pt_element_t)))
948 break;
949
950 FNAME(prefetch_gpte)(vcpu, sp, sptep, gpte, false);
951 }
952
953 if (!sp->unsync_children)
954 break;
955 }
956 write_unlock(&vcpu->kvm->mmu_lock);
957}
958
959/* Note, @addr is a GPA when gva_to_gpa() translates an L2 GPA to an L1 GPA. */
960static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
961 gpa_t addr, u64 access,
962 struct x86_exception *exception)
963{
964 struct guest_walker walker;
965 gpa_t gpa = INVALID_GPA;
966 int r;
967
968#ifndef CONFIG_X86_64
969 /* A 64-bit GVA should be impossible on 32-bit KVM. */
970 WARN_ON_ONCE((addr >> 32) && mmu == vcpu->arch.walk_mmu);
971#endif
972
973 r = FNAME(walk_addr_generic)(&walker, vcpu, mmu, addr, access);
974
975 if (r) {
976 gpa = gfn_to_gpa(walker.gfn);
977 gpa |= addr & ~PAGE_MASK;
978 } else if (exception)
979 *exception = walker.fault;
980
981 return gpa;
982}
983
984/*
985 * Using the information in sp->shadowed_translation (kvm_mmu_page_get_gfn()) is
986 * safe because:
987 * - The spte has a reference to the struct page, so the pfn for a given gfn
988 * can't change unless all sptes pointing to it are nuked first.
989 *
990 * Returns
991 * < 0: the sp should be zapped
992 * 0: the sp is synced and no tlb flushing is required
993 * > 0: the sp is synced and tlb flushing is required
994 */
995static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
996{
997 union kvm_mmu_page_role root_role = vcpu->arch.mmu->root_role;
998 int i;
999 bool host_writable;
1000 gpa_t first_pte_gpa;
1001 bool flush = false;
1002
1003 /*
1004 * Ignore various flags when verifying that it's safe to sync a shadow
1005 * page using the current MMU context.
1006 *
1007 * - level: not part of the overall MMU role and will never match as the MMU's
1008 * level tracks the root level
1009 * - access: updated based on the new guest PTE
1010 * - quadrant: not part of the overall MMU role (similar to level)
1011 */
1012 const union kvm_mmu_page_role sync_role_ign = {
1013 .level = 0xf,
1014 .access = 0x7,
1015 .quadrant = 0x3,
1016 .passthrough = 0x1,
1017 };
1018
1019 /*
1020 * Direct pages can never be unsync, and KVM should never attempt to
1021 * sync a shadow page for a different MMU context, e.g. if the role
1022 * differs then the memslot lookup (SMM vs. non-SMM) will be bogus, the
1023 * reserved bits checks will be wrong, etc...
1024 */
1025 if (WARN_ON_ONCE(sp->role.direct ||
1026 (sp->role.word ^ root_role.word) & ~sync_role_ign.word))
1027 return -1;
1028
1029 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
1030
1031 for (i = 0; i < SPTE_ENT_PER_PAGE; i++) {
1032 u64 *sptep, spte;
1033 struct kvm_memory_slot *slot;
1034 unsigned pte_access;
1035 pt_element_t gpte;
1036 gpa_t pte_gpa;
1037 gfn_t gfn;
1038
1039 if (!sp->spt[i])
1040 continue;
1041
1042 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
1043
1044 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
1045 sizeof(pt_element_t)))
1046 return -1;
1047
1048 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
1049 flush = true;
1050 continue;
1051 }
1052
1053 gfn = gpte_to_gfn(gpte);
1054 pte_access = sp->role.access;
1055 pte_access &= FNAME(gpte_access)(gpte);
1056 FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
1057
1058 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access))
1059 continue;
1060
1061 /*
1062 * Drop the SPTE if the new protections would result in a RWX=0
1063 * SPTE or if the gfn is changing. The RWX=0 case only affects
1064 * EPT with execute-only support, i.e. EPT without an effective
1065 * "present" bit, as all other paging modes will create a
1066 * read-only SPTE if pte_access is zero.
1067 */
1068 if ((!pte_access && !shadow_present_mask) ||
1069 gfn != kvm_mmu_page_get_gfn(sp, i)) {
1070 drop_spte(vcpu->kvm, &sp->spt[i]);
1071 flush = true;
1072 continue;
1073 }
1074
1075 /* Update the shadowed access bits in case they changed. */
1076 kvm_mmu_page_set_access(sp, i, pte_access);
1077
1078 sptep = &sp->spt[i];
1079 spte = *sptep;
1080 host_writable = spte & shadow_host_writable_mask;
1081 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1082 make_spte(vcpu, sp, slot, pte_access, gfn,
1083 spte_to_pfn(spte), spte, true, false,
1084 host_writable, &spte);
1085
1086 flush |= mmu_spte_update(sptep, spte);
1087 }
1088
1089 /*
1090 * Note, any flush is purely for KVM's correctness, e.g. when dropping
1091 * an existing SPTE or clearing W/A/D bits to ensure an mmu_notifier
1092 * unmap or dirty logging event doesn't fail to flush. The guest is
1093 * responsible for flushing the TLB to ensure any changes in protection
1094 * bits are recognized, i.e. until the guest flushes or page faults on
1095 * a relevant address, KVM is architecturally allowed to let vCPUs use
1096 * cached translations with the old protection bits.
1097 */
1098 return flush;
1099}
1100
1101#undef pt_element_t
1102#undef guest_walker
1103#undef FNAME
1104#undef PT_BASE_ADDR_MASK
1105#undef PT_INDEX
1106#undef PT_LVL_ADDR_MASK
1107#undef PT_LVL_OFFSET_MASK
1108#undef PT_LEVEL_BITS
1109#undef PT_MAX_FULL_LEVELS
1110#undef gpte_to_gfn
1111#undef gpte_to_gfn_lvl
1112#undef PT_GUEST_ACCESSED_MASK
1113#undef PT_GUEST_DIRTY_MASK
1114#undef PT_GUEST_DIRTY_SHIFT
1115#undef PT_GUEST_ACCESSED_SHIFT
1116#undef PT_HAVE_ACCESSED_DIRTY