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1// SPDX-License-Identifier: GPL-2.0-only
2#include <linux/export.h>
3#include <linux/bitops.h>
4#include <linux/elf.h>
5#include <linux/mm.h>
6
7#include <linux/io.h>
8#include <linux/sched.h>
9#include <linux/sched/clock.h>
10#include <linux/random.h>
11#include <linux/topology.h>
12#include <asm/processor.h>
13#include <asm/apic.h>
14#include <asm/cacheinfo.h>
15#include <asm/cpu.h>
16#include <asm/cpu_device_id.h>
17#include <asm/spec-ctrl.h>
18#include <asm/smp.h>
19#include <asm/numa.h>
20#include <asm/pci-direct.h>
21#include <asm/delay.h>
22#include <asm/debugreg.h>
23#include <asm/resctrl.h>
24#include <asm/sev.h>
25
26#ifdef CONFIG_X86_64
27# include <asm/mmconfig.h>
28#endif
29
30#include "cpu.h"
31
32static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
33{
34 u32 gprs[8] = { 0 };
35 int err;
36
37 WARN_ONCE((boot_cpu_data.x86 != 0xf),
38 "%s should only be used on K8!\n", __func__);
39
40 gprs[1] = msr;
41 gprs[7] = 0x9c5a203a;
42
43 err = rdmsr_safe_regs(gprs);
44
45 *p = gprs[0] | ((u64)gprs[2] << 32);
46
47 return err;
48}
49
50static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
51{
52 u32 gprs[8] = { 0 };
53
54 WARN_ONCE((boot_cpu_data.x86 != 0xf),
55 "%s should only be used on K8!\n", __func__);
56
57 gprs[0] = (u32)val;
58 gprs[1] = msr;
59 gprs[2] = val >> 32;
60 gprs[7] = 0x9c5a203a;
61
62 return wrmsr_safe_regs(gprs);
63}
64
65/*
66 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
67 * misexecution of code under Linux. Owners of such processors should
68 * contact AMD for precise details and a CPU swap.
69 *
70 * See http://www.multimania.com/poulot/k6bug.html
71 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
72 * (Publication # 21266 Issue Date: August 1998)
73 *
74 * The following test is erm.. interesting. AMD neglected to up
75 * the chip setting when fixing the bug but they also tweaked some
76 * performance at the same time..
77 */
78
79#ifdef CONFIG_X86_32
80extern __visible void vide(void);
81__asm__(".text\n"
82 ".globl vide\n"
83 ".type vide, @function\n"
84 ".align 4\n"
85 "vide: ret\n");
86#endif
87
88static void init_amd_k5(struct cpuinfo_x86 *c)
89{
90#ifdef CONFIG_X86_32
91/*
92 * General Systems BIOSen alias the cpu frequency registers
93 * of the Elan at 0x000df000. Unfortunately, one of the Linux
94 * drivers subsequently pokes it, and changes the CPU speed.
95 * Workaround : Remove the unneeded alias.
96 */
97#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
98#define CBAR_ENB (0x80000000)
99#define CBAR_KEY (0X000000CB)
100 if (c->x86_model == 9 || c->x86_model == 10) {
101 if (inl(CBAR) & CBAR_ENB)
102 outl(0 | CBAR_KEY, CBAR);
103 }
104#endif
105}
106
107static void init_amd_k6(struct cpuinfo_x86 *c)
108{
109#ifdef CONFIG_X86_32
110 u32 l, h;
111 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
112
113 if (c->x86_model < 6) {
114 /* Based on AMD doc 20734R - June 2000 */
115 if (c->x86_model == 0) {
116 clear_cpu_cap(c, X86_FEATURE_APIC);
117 set_cpu_cap(c, X86_FEATURE_PGE);
118 }
119 return;
120 }
121
122 if (c->x86_model == 6 && c->x86_stepping == 1) {
123 const int K6_BUG_LOOP = 1000000;
124 int n;
125 void (*f_vide)(void);
126 u64 d, d2;
127
128 pr_info("AMD K6 stepping B detected - ");
129
130 /*
131 * It looks like AMD fixed the 2.6.2 bug and improved indirect
132 * calls at the same time.
133 */
134
135 n = K6_BUG_LOOP;
136 f_vide = vide;
137 OPTIMIZER_HIDE_VAR(f_vide);
138 d = rdtsc();
139 while (n--)
140 f_vide();
141 d2 = rdtsc();
142 d = d2-d;
143
144 if (d > 20*K6_BUG_LOOP)
145 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
146 else
147 pr_cont("probably OK (after B9730xxxx).\n");
148 }
149
150 /* K6 with old style WHCR */
151 if (c->x86_model < 8 ||
152 (c->x86_model == 8 && c->x86_stepping < 8)) {
153 /* We can only write allocate on the low 508Mb */
154 if (mbytes > 508)
155 mbytes = 508;
156
157 rdmsr(MSR_K6_WHCR, l, h);
158 if ((l&0x0000FFFF) == 0) {
159 unsigned long flags;
160 l = (1<<0)|((mbytes/4)<<1);
161 local_irq_save(flags);
162 wbinvd();
163 wrmsr(MSR_K6_WHCR, l, h);
164 local_irq_restore(flags);
165 pr_info("Enabling old style K6 write allocation for %d Mb\n",
166 mbytes);
167 }
168 return;
169 }
170
171 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
172 c->x86_model == 9 || c->x86_model == 13) {
173 /* The more serious chips .. */
174
175 if (mbytes > 4092)
176 mbytes = 4092;
177
178 rdmsr(MSR_K6_WHCR, l, h);
179 if ((l&0xFFFF0000) == 0) {
180 unsigned long flags;
181 l = ((mbytes>>2)<<22)|(1<<16);
182 local_irq_save(flags);
183 wbinvd();
184 wrmsr(MSR_K6_WHCR, l, h);
185 local_irq_restore(flags);
186 pr_info("Enabling new style K6 write allocation for %d Mb\n",
187 mbytes);
188 }
189
190 return;
191 }
192
193 if (c->x86_model == 10) {
194 /* AMD Geode LX is model 10 */
195 /* placeholder for any needed mods */
196 return;
197 }
198#endif
199}
200
201static void init_amd_k7(struct cpuinfo_x86 *c)
202{
203#ifdef CONFIG_X86_32
204 u32 l, h;
205
206 /*
207 * Bit 15 of Athlon specific MSR 15, needs to be 0
208 * to enable SSE on Palomino/Morgan/Barton CPU's.
209 * If the BIOS didn't enable it already, enable it here.
210 */
211 if (c->x86_model >= 6 && c->x86_model <= 10) {
212 if (!cpu_has(c, X86_FEATURE_XMM)) {
213 pr_info("Enabling disabled K7/SSE Support.\n");
214 msr_clear_bit(MSR_K7_HWCR, 15);
215 set_cpu_cap(c, X86_FEATURE_XMM);
216 }
217 }
218
219 /*
220 * It's been determined by AMD that Athlons since model 8 stepping 1
221 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
222 * As per AMD technical note 27212 0.2
223 */
224 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
225 rdmsr(MSR_K7_CLK_CTL, l, h);
226 if ((l & 0xfff00000) != 0x20000000) {
227 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
228 l, ((l & 0x000fffff)|0x20000000));
229 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
230 }
231 }
232
233 /* calling is from identify_secondary_cpu() ? */
234 if (!c->cpu_index)
235 return;
236
237 /*
238 * Certain Athlons might work (for various values of 'work') in SMP
239 * but they are not certified as MP capable.
240 */
241 /* Athlon 660/661 is valid. */
242 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
243 (c->x86_stepping == 1)))
244 return;
245
246 /* Duron 670 is valid */
247 if ((c->x86_model == 7) && (c->x86_stepping == 0))
248 return;
249
250 /*
251 * Athlon 662, Duron 671, and Athlon >model 7 have capability
252 * bit. It's worth noting that the A5 stepping (662) of some
253 * Athlon XP's have the MP bit set.
254 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
255 * more.
256 */
257 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
258 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
259 (c->x86_model > 7))
260 if (cpu_has(c, X86_FEATURE_MP))
261 return;
262
263 /* If we get here, not a certified SMP capable AMD system. */
264
265 /*
266 * Don't taint if we are running SMP kernel on a single non-MP
267 * approved Athlon
268 */
269 WARN_ONCE(1, "WARNING: This combination of AMD"
270 " processors is not suitable for SMP.\n");
271 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
272#endif
273}
274
275#ifdef CONFIG_NUMA
276/*
277 * To workaround broken NUMA config. Read the comment in
278 * srat_detect_node().
279 */
280static int nearby_node(int apicid)
281{
282 int i, node;
283
284 for (i = apicid - 1; i >= 0; i--) {
285 node = __apicid_to_node[i];
286 if (node != NUMA_NO_NODE && node_online(node))
287 return node;
288 }
289 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
290 node = __apicid_to_node[i];
291 if (node != NUMA_NO_NODE && node_online(node))
292 return node;
293 }
294 return first_node(node_online_map); /* Shouldn't happen */
295}
296#endif
297
298static void srat_detect_node(struct cpuinfo_x86 *c)
299{
300#ifdef CONFIG_NUMA
301 int cpu = smp_processor_id();
302 int node;
303 unsigned apicid = c->topo.apicid;
304
305 node = numa_cpu_node(cpu);
306 if (node == NUMA_NO_NODE)
307 node = per_cpu_llc_id(cpu);
308
309 /*
310 * On multi-fabric platform (e.g. Numascale NumaChip) a
311 * platform-specific handler needs to be called to fixup some
312 * IDs of the CPU.
313 */
314 if (x86_cpuinit.fixup_cpu_id)
315 x86_cpuinit.fixup_cpu_id(c, node);
316
317 if (!node_online(node)) {
318 /*
319 * Two possibilities here:
320 *
321 * - The CPU is missing memory and no node was created. In
322 * that case try picking one from a nearby CPU.
323 *
324 * - The APIC IDs differ from the HyperTransport node IDs
325 * which the K8 northbridge parsing fills in. Assume
326 * they are all increased by a constant offset, but in
327 * the same order as the HT nodeids. If that doesn't
328 * result in a usable node fall back to the path for the
329 * previous case.
330 *
331 * This workaround operates directly on the mapping between
332 * APIC ID and NUMA node, assuming certain relationship
333 * between APIC ID, HT node ID and NUMA topology. As going
334 * through CPU mapping may alter the outcome, directly
335 * access __apicid_to_node[].
336 */
337 int ht_nodeid = c->topo.initial_apicid;
338
339 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
340 node = __apicid_to_node[ht_nodeid];
341 /* Pick a nearby node */
342 if (!node_online(node))
343 node = nearby_node(apicid);
344 }
345 numa_set_node(cpu, node);
346#endif
347}
348
349static void bsp_determine_snp(struct cpuinfo_x86 *c)
350{
351#ifdef CONFIG_ARCH_HAS_CC_PLATFORM
352 cc_vendor = CC_VENDOR_AMD;
353
354 if (cpu_has(c, X86_FEATURE_SEV_SNP)) {
355 /*
356 * RMP table entry format is not architectural and is defined by the
357 * per-processor PPR. Restrict SNP support on the known CPU models
358 * for which the RMP table entry format is currently defined for.
359 */
360 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
361 c->x86 >= 0x19 && snp_probe_rmptable_info()) {
362 cc_platform_set(CC_ATTR_HOST_SEV_SNP);
363 } else {
364 setup_clear_cpu_cap(X86_FEATURE_SEV_SNP);
365 cc_platform_clear(CC_ATTR_HOST_SEV_SNP);
366 }
367 }
368#endif
369}
370
371static void bsp_init_amd(struct cpuinfo_x86 *c)
372{
373 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
374
375 if (c->x86 > 0x10 ||
376 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
377 u64 val;
378
379 rdmsrl(MSR_K7_HWCR, val);
380 if (!(val & BIT(24)))
381 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
382 }
383 }
384
385 if (c->x86 == 0x15) {
386 unsigned long upperbit;
387 u32 cpuid, assoc;
388
389 cpuid = cpuid_edx(0x80000005);
390 assoc = cpuid >> 16 & 0xff;
391 upperbit = ((cpuid >> 24) << 10) / assoc;
392
393 va_align.mask = (upperbit - 1) & PAGE_MASK;
394 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
395
396 /* A random value per boot for bit slice [12:upper_bit) */
397 va_align.bits = get_random_u32() & va_align.mask;
398 }
399
400 if (cpu_has(c, X86_FEATURE_MWAITX))
401 use_mwaitx_delay();
402
403 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
404 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
405 c->x86 >= 0x15 && c->x86 <= 0x17) {
406 unsigned int bit;
407
408 switch (c->x86) {
409 case 0x15: bit = 54; break;
410 case 0x16: bit = 33; break;
411 case 0x17: bit = 10; break;
412 default: return;
413 }
414 /*
415 * Try to cache the base value so further operations can
416 * avoid RMW. If that faults, do not enable SSBD.
417 */
418 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
419 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
420 setup_force_cpu_cap(X86_FEATURE_SSBD);
421 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
422 }
423 }
424
425 resctrl_cpu_detect(c);
426
427 /* Figure out Zen generations: */
428 switch (c->x86) {
429 case 0x17:
430 switch (c->x86_model) {
431 case 0x00 ... 0x2f:
432 case 0x50 ... 0x5f:
433 setup_force_cpu_cap(X86_FEATURE_ZEN1);
434 break;
435 case 0x30 ... 0x4f:
436 case 0x60 ... 0x7f:
437 case 0x90 ... 0x91:
438 case 0xa0 ... 0xaf:
439 setup_force_cpu_cap(X86_FEATURE_ZEN2);
440 break;
441 default:
442 goto warn;
443 }
444 break;
445
446 case 0x19:
447 switch (c->x86_model) {
448 case 0x00 ... 0x0f:
449 case 0x20 ... 0x5f:
450 setup_force_cpu_cap(X86_FEATURE_ZEN3);
451 break;
452 case 0x10 ... 0x1f:
453 case 0x60 ... 0xaf:
454 setup_force_cpu_cap(X86_FEATURE_ZEN4);
455 break;
456 default:
457 goto warn;
458 }
459 break;
460
461 case 0x1a:
462 switch (c->x86_model) {
463 case 0x00 ... 0x2f:
464 case 0x40 ... 0x4f:
465 case 0x60 ... 0x7f:
466 setup_force_cpu_cap(X86_FEATURE_ZEN5);
467 break;
468 default:
469 goto warn;
470 }
471 break;
472
473 default:
474 break;
475 }
476
477 bsp_determine_snp(c);
478 return;
479
480warn:
481 WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model);
482}
483
484static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
485{
486 u64 msr;
487
488 /*
489 * BIOS support is required for SME and SEV.
490 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by
491 * the SME physical address space reduction value.
492 * If BIOS has not enabled SME then don't advertise the
493 * SME feature (set in scattered.c).
494 * If the kernel has not enabled SME via any means then
495 * don't advertise the SME feature.
496 * For SEV: If BIOS has not enabled SEV then don't advertise SEV and
497 * any additional functionality based on it.
498 *
499 * In all cases, since support for SME and SEV requires long mode,
500 * don't advertise the feature under CONFIG_X86_32.
501 */
502 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
503 /* Check if memory encryption is enabled */
504 rdmsrl(MSR_AMD64_SYSCFG, msr);
505 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
506 goto clear_all;
507
508 /*
509 * Always adjust physical address bits. Even though this
510 * will be a value above 32-bits this is still done for
511 * CONFIG_X86_32 so that accurate values are reported.
512 */
513 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
514
515 if (IS_ENABLED(CONFIG_X86_32))
516 goto clear_all;
517
518 if (!sme_me_mask)
519 setup_clear_cpu_cap(X86_FEATURE_SME);
520
521 rdmsrl(MSR_K7_HWCR, msr);
522 if (!(msr & MSR_K7_HWCR_SMMLOCK))
523 goto clear_sev;
524
525 return;
526
527clear_all:
528 setup_clear_cpu_cap(X86_FEATURE_SME);
529clear_sev:
530 setup_clear_cpu_cap(X86_FEATURE_SEV);
531 setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
532 setup_clear_cpu_cap(X86_FEATURE_SEV_SNP);
533 }
534}
535
536static void early_init_amd(struct cpuinfo_x86 *c)
537{
538 u32 dummy;
539
540 if (c->x86 >= 0xf)
541 set_cpu_cap(c, X86_FEATURE_K8);
542
543 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
544
545 /*
546 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
547 * with P/T states and does not stop in deep C-states
548 */
549 if (c->x86_power & (1 << 8)) {
550 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
551 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
552 }
553
554 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
555 if (c->x86_power & BIT(12))
556 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
557
558 /* Bit 14 indicates the Runtime Average Power Limit interface. */
559 if (c->x86_power & BIT(14))
560 set_cpu_cap(c, X86_FEATURE_RAPL);
561
562#ifdef CONFIG_X86_64
563 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
564#else
565 /* Set MTRR capability flag if appropriate */
566 if (c->x86 == 5)
567 if (c->x86_model == 13 || c->x86_model == 9 ||
568 (c->x86_model == 8 && c->x86_stepping >= 8))
569 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
570#endif
571#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
572 /*
573 * ApicID can always be treated as an 8-bit value for AMD APIC versions
574 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
575 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
576 * after 16h.
577 */
578 if (boot_cpu_has(X86_FEATURE_APIC)) {
579 if (c->x86 > 0x16)
580 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
581 else if (c->x86 >= 0xf) {
582 /* check CPU config space for extended APIC ID */
583 unsigned int val;
584
585 val = read_pci_config(0, 24, 0, 0x68);
586 if ((val >> 17 & 0x3) == 0x3)
587 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
588 }
589 }
590#endif
591
592 /*
593 * This is only needed to tell the kernel whether to use VMCALL
594 * and VMMCALL. VMMCALL is never executed except under virt, so
595 * we can set it unconditionally.
596 */
597 set_cpu_cap(c, X86_FEATURE_VMMCALL);
598
599 /* F16h erratum 793, CVE-2013-6885 */
600 if (c->x86 == 0x16 && c->x86_model <= 0xf)
601 msr_set_bit(MSR_AMD64_LS_CFG, 15);
602
603 early_detect_mem_encrypt(c);
604
605 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_IBPB_BRTYPE)) {
606 if (c->x86 == 0x17 && boot_cpu_has(X86_FEATURE_AMD_IBPB))
607 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE);
608 else if (c->x86 >= 0x19 && !wrmsrl_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) {
609 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE);
610 setup_force_cpu_cap(X86_FEATURE_SBPB);
611 }
612 }
613}
614
615static void init_amd_k8(struct cpuinfo_x86 *c)
616{
617 u32 level;
618 u64 value;
619
620 /* On C+ stepping K8 rep microcode works well for copy/memset */
621 level = cpuid_eax(1);
622 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
623 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
624
625 /*
626 * Some BIOSes incorrectly force this feature, but only K8 revision D
627 * (model = 0x14) and later actually support it.
628 * (AMD Erratum #110, docId: 25759).
629 */
630 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
631 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
632 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
633 value &= ~BIT_64(32);
634 wrmsrl_amd_safe(0xc001100d, value);
635 }
636 }
637
638 if (!c->x86_model_id[0])
639 strcpy(c->x86_model_id, "Hammer");
640
641#ifdef CONFIG_SMP
642 /*
643 * Disable TLB flush filter by setting HWCR.FFDIS on K8
644 * bit 6 of msr C001_0015
645 *
646 * Errata 63 for SH-B3 steppings
647 * Errata 122 for all steppings (F+ have it disabled by default)
648 */
649 msr_set_bit(MSR_K7_HWCR, 6);
650#endif
651 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
652
653 /*
654 * Check models and steppings affected by erratum 400. This is
655 * used to select the proper idle routine and to enable the
656 * check whether the machine is affected in arch_post_acpi_subsys_init()
657 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
658 */
659 if (c->x86_model > 0x41 ||
660 (c->x86_model == 0x41 && c->x86_stepping >= 0x2))
661 setup_force_cpu_bug(X86_BUG_AMD_E400);
662}
663
664static void init_amd_gh(struct cpuinfo_x86 *c)
665{
666#ifdef CONFIG_MMCONF_FAM10H
667 /* do this for boot cpu */
668 if (c == &boot_cpu_data)
669 check_enable_amd_mmconf_dmi();
670
671 fam10h_check_enable_mmcfg();
672#endif
673
674 /*
675 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
676 * is always needed when GART is enabled, even in a kernel which has no
677 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
678 * If it doesn't, we do it here as suggested by the BKDG.
679 *
680 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
681 */
682 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
683
684 /*
685 * On family 10h BIOS may not have properly enabled WC+ support, causing
686 * it to be converted to CD memtype. This may result in performance
687 * degradation for certain nested-paging guests. Prevent this conversion
688 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
689 *
690 * NOTE: we want to use the _safe accessors so as not to #GP kvm
691 * guests on older kvm hosts.
692 */
693 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
694
695 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
696
697 /*
698 * Check models and steppings affected by erratum 400. This is
699 * used to select the proper idle routine and to enable the
700 * check whether the machine is affected in arch_post_acpi_subsys_init()
701 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
702 */
703 if (c->x86_model > 0x2 ||
704 (c->x86_model == 0x2 && c->x86_stepping >= 0x1))
705 setup_force_cpu_bug(X86_BUG_AMD_E400);
706}
707
708static void init_amd_ln(struct cpuinfo_x86 *c)
709{
710 /*
711 * Apply erratum 665 fix unconditionally so machines without a BIOS
712 * fix work.
713 */
714 msr_set_bit(MSR_AMD64_DE_CFG, 31);
715}
716
717static bool rdrand_force;
718
719static int __init rdrand_cmdline(char *str)
720{
721 if (!str)
722 return -EINVAL;
723
724 if (!strcmp(str, "force"))
725 rdrand_force = true;
726 else
727 return -EINVAL;
728
729 return 0;
730}
731early_param("rdrand", rdrand_cmdline);
732
733static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
734{
735 /*
736 * Saving of the MSR used to hide the RDRAND support during
737 * suspend/resume is done by arch/x86/power/cpu.c, which is
738 * dependent on CONFIG_PM_SLEEP.
739 */
740 if (!IS_ENABLED(CONFIG_PM_SLEEP))
741 return;
742
743 /*
744 * The self-test can clear X86_FEATURE_RDRAND, so check for
745 * RDRAND support using the CPUID function directly.
746 */
747 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force)
748 return;
749
750 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62);
751
752 /*
753 * Verify that the CPUID change has occurred in case the kernel is
754 * running virtualized and the hypervisor doesn't support the MSR.
755 */
756 if (cpuid_ecx(1) & BIT(30)) {
757 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n");
758 return;
759 }
760
761 clear_cpu_cap(c, X86_FEATURE_RDRAND);
762 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n");
763}
764
765static void init_amd_jg(struct cpuinfo_x86 *c)
766{
767 /*
768 * Some BIOS implementations do not restore proper RDRAND support
769 * across suspend and resume. Check on whether to hide the RDRAND
770 * instruction support via CPUID.
771 */
772 clear_rdrand_cpuid_bit(c);
773}
774
775static void init_amd_bd(struct cpuinfo_x86 *c)
776{
777 u64 value;
778
779 /*
780 * The way access filter has a performance penalty on some workloads.
781 * Disable it on the affected CPUs.
782 */
783 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
784 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
785 value |= 0x1E;
786 wrmsrl_safe(MSR_F15H_IC_CFG, value);
787 }
788 }
789
790 /*
791 * Some BIOS implementations do not restore proper RDRAND support
792 * across suspend and resume. Check on whether to hide the RDRAND
793 * instruction support via CPUID.
794 */
795 clear_rdrand_cpuid_bit(c);
796}
797
798static const struct x86_cpu_desc erratum_1386_microcode[] = {
799 AMD_CPU_DESC(0x17, 0x1, 0x2, 0x0800126e),
800 AMD_CPU_DESC(0x17, 0x31, 0x0, 0x08301052),
801 {},
802};
803
804static void fix_erratum_1386(struct cpuinfo_x86 *c)
805{
806 /*
807 * Work around Erratum 1386. The XSAVES instruction malfunctions in
808 * certain circumstances on Zen1/2 uarch, and not all parts have had
809 * updated microcode at the time of writing (March 2023).
810 *
811 * Affected parts all have no supervisor XSAVE states, meaning that
812 * the XSAVEC instruction (which works fine) is equivalent.
813 *
814 * Clear the feature flag only on microcode revisions which
815 * don't have the fix.
816 */
817 if (x86_cpu_has_min_microcode_rev(erratum_1386_microcode))
818 return;
819
820 clear_cpu_cap(c, X86_FEATURE_XSAVES);
821}
822
823void init_spectral_chicken(struct cpuinfo_x86 *c)
824{
825#ifdef CONFIG_MITIGATION_UNRET_ENTRY
826 u64 value;
827
828 /*
829 * On Zen2 we offer this chicken (bit) on the altar of Speculation.
830 *
831 * This suppresses speculation from the middle of a basic block, i.e. it
832 * suppresses non-branch predictions.
833 */
834 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
835 if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) {
836 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT;
837 wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value);
838 }
839 }
840#endif
841}
842
843static void init_amd_zen_common(void)
844{
845 setup_force_cpu_cap(X86_FEATURE_ZEN);
846#ifdef CONFIG_NUMA
847 node_reclaim_distance = 32;
848#endif
849}
850
851static void init_amd_zen1(struct cpuinfo_x86 *c)
852{
853 fix_erratum_1386(c);
854
855 /* Fix up CPUID bits, but only if not virtualised. */
856 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
857
858 /* Erratum 1076: CPB feature bit not being set in CPUID. */
859 if (!cpu_has(c, X86_FEATURE_CPB))
860 set_cpu_cap(c, X86_FEATURE_CPB);
861 }
862
863 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
864 setup_force_cpu_bug(X86_BUG_DIV0);
865}
866
867static bool cpu_has_zenbleed_microcode(void)
868{
869 u32 good_rev = 0;
870
871 switch (boot_cpu_data.x86_model) {
872 case 0x30 ... 0x3f: good_rev = 0x0830107b; break;
873 case 0x60 ... 0x67: good_rev = 0x0860010c; break;
874 case 0x68 ... 0x6f: good_rev = 0x08608107; break;
875 case 0x70 ... 0x7f: good_rev = 0x08701033; break;
876 case 0xa0 ... 0xaf: good_rev = 0x08a00009; break;
877
878 default:
879 return false;
880 }
881
882 if (boot_cpu_data.microcode < good_rev)
883 return false;
884
885 return true;
886}
887
888static void zen2_zenbleed_check(struct cpuinfo_x86 *c)
889{
890 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
891 return;
892
893 if (!cpu_has(c, X86_FEATURE_AVX))
894 return;
895
896 if (!cpu_has_zenbleed_microcode()) {
897 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
898 msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
899 } else {
900 msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
901 }
902}
903
904static void init_amd_zen2(struct cpuinfo_x86 *c)
905{
906 init_spectral_chicken(c);
907 fix_erratum_1386(c);
908 zen2_zenbleed_check(c);
909}
910
911static void init_amd_zen3(struct cpuinfo_x86 *c)
912{
913 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
914 /*
915 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
916 * Branch Type Confusion, but predate the allocation of the
917 * BTC_NO bit.
918 */
919 if (!cpu_has(c, X86_FEATURE_BTC_NO))
920 set_cpu_cap(c, X86_FEATURE_BTC_NO);
921 }
922}
923
924static void init_amd_zen4(struct cpuinfo_x86 *c)
925{
926 if (!cpu_has(c, X86_FEATURE_HYPERVISOR))
927 msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
928
929 /*
930 * These Zen4 SoCs advertise support for virtualized VMLOAD/VMSAVE
931 * in some BIOS versions but they can lead to random host reboots.
932 */
933 switch (c->x86_model) {
934 case 0x18 ... 0x1f:
935 case 0x60 ... 0x7f:
936 clear_cpu_cap(c, X86_FEATURE_V_VMSAVE_VMLOAD);
937 break;
938 }
939}
940
941static void init_amd_zen5(struct cpuinfo_x86 *c)
942{
943}
944
945static void init_amd(struct cpuinfo_x86 *c)
946{
947 u64 vm_cr;
948
949 early_init_amd(c);
950
951 /*
952 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
953 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
954 */
955 clear_cpu_cap(c, 0*32+31);
956
957 if (c->x86 >= 0x10)
958 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
959
960 /* AMD FSRM also implies FSRS */
961 if (cpu_has(c, X86_FEATURE_FSRM))
962 set_cpu_cap(c, X86_FEATURE_FSRS);
963
964 /* K6s reports MCEs but don't actually have all the MSRs */
965 if (c->x86 < 6)
966 clear_cpu_cap(c, X86_FEATURE_MCE);
967
968 switch (c->x86) {
969 case 4: init_amd_k5(c); break;
970 case 5: init_amd_k6(c); break;
971 case 6: init_amd_k7(c); break;
972 case 0xf: init_amd_k8(c); break;
973 case 0x10: init_amd_gh(c); break;
974 case 0x12: init_amd_ln(c); break;
975 case 0x15: init_amd_bd(c); break;
976 case 0x16: init_amd_jg(c); break;
977 }
978
979 /*
980 * Save up on some future enablement work and do common Zen
981 * settings.
982 */
983 if (c->x86 >= 0x17)
984 init_amd_zen_common();
985
986 if (boot_cpu_has(X86_FEATURE_ZEN1))
987 init_amd_zen1(c);
988 else if (boot_cpu_has(X86_FEATURE_ZEN2))
989 init_amd_zen2(c);
990 else if (boot_cpu_has(X86_FEATURE_ZEN3))
991 init_amd_zen3(c);
992 else if (boot_cpu_has(X86_FEATURE_ZEN4))
993 init_amd_zen4(c);
994 else if (boot_cpu_has(X86_FEATURE_ZEN5))
995 init_amd_zen5(c);
996
997 /*
998 * Enable workaround for FXSAVE leak on CPUs
999 * without a XSaveErPtr feature
1000 */
1001 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
1002 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
1003
1004 cpu_detect_cache_sizes(c);
1005
1006 srat_detect_node(c);
1007
1008 init_amd_cacheinfo(c);
1009
1010 if (cpu_has(c, X86_FEATURE_SVM)) {
1011 rdmsrl(MSR_VM_CR, vm_cr);
1012 if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) {
1013 pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n");
1014 clear_cpu_cap(c, X86_FEATURE_SVM);
1015 }
1016 }
1017
1018 if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) {
1019 /*
1020 * Use LFENCE for execution serialization. On families which
1021 * don't have that MSR, LFENCE is already serializing.
1022 * msr_set_bit() uses the safe accessors, too, even if the MSR
1023 * is not present.
1024 */
1025 msr_set_bit(MSR_AMD64_DE_CFG,
1026 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
1027
1028 /* A serializing LFENCE stops RDTSC speculation */
1029 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
1030 }
1031
1032 /*
1033 * Family 0x12 and above processors have APIC timer
1034 * running in deep C states.
1035 */
1036 if (c->x86 > 0x11)
1037 set_cpu_cap(c, X86_FEATURE_ARAT);
1038
1039 /* 3DNow or LM implies PREFETCHW */
1040 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
1041 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
1042 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
1043
1044 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
1045 if (!cpu_feature_enabled(X86_FEATURE_XENPV))
1046 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
1047
1048 /*
1049 * Turn on the Instructions Retired free counter on machines not
1050 * susceptible to erratum #1054 "Instructions Retired Performance
1051 * Counter May Be Inaccurate".
1052 */
1053 if (cpu_has(c, X86_FEATURE_IRPERF) &&
1054 (boot_cpu_has(X86_FEATURE_ZEN1) && c->x86_model > 0x2f))
1055 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
1056
1057 check_null_seg_clears_base(c);
1058
1059 /*
1060 * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up
1061 * using the trampoline code and as part of it, MSR_EFER gets prepared there in
1062 * order to be replicated onto them. Regardless, set it here again, if not set,
1063 * to protect against any future refactoring/code reorganization which might
1064 * miss setting this important bit.
1065 */
1066 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
1067 cpu_has(c, X86_FEATURE_AUTOIBRS))
1068 WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS) < 0);
1069
1070 /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */
1071 clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
1072}
1073
1074#ifdef CONFIG_X86_32
1075static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1076{
1077 /* AMD errata T13 (order #21922) */
1078 if (c->x86 == 6) {
1079 /* Duron Rev A0 */
1080 if (c->x86_model == 3 && c->x86_stepping == 0)
1081 size = 64;
1082 /* Tbird rev A1/A2 */
1083 if (c->x86_model == 4 &&
1084 (c->x86_stepping == 0 || c->x86_stepping == 1))
1085 size = 256;
1086 }
1087 return size;
1088}
1089#endif
1090
1091static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
1092{
1093 u32 ebx, eax, ecx, edx;
1094 u16 mask = 0xfff;
1095
1096 if (c->x86 < 0xf)
1097 return;
1098
1099 if (c->extended_cpuid_level < 0x80000006)
1100 return;
1101
1102 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1103
1104 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
1105 tlb_lli_4k[ENTRIES] = ebx & mask;
1106
1107 /*
1108 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
1109 * characteristics from the CPUID function 0x80000005 instead.
1110 */
1111 if (c->x86 == 0xf) {
1112 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1113 mask = 0xff;
1114 }
1115
1116 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1117 if (!((eax >> 16) & mask))
1118 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
1119 else
1120 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
1121
1122 /* a 4M entry uses two 2M entries */
1123 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
1124
1125 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1126 if (!(eax & mask)) {
1127 /* Erratum 658 */
1128 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
1129 tlb_lli_2m[ENTRIES] = 1024;
1130 } else {
1131 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1132 tlb_lli_2m[ENTRIES] = eax & 0xff;
1133 }
1134 } else
1135 tlb_lli_2m[ENTRIES] = eax & mask;
1136
1137 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
1138}
1139
1140static const struct cpu_dev amd_cpu_dev = {
1141 .c_vendor = "AMD",
1142 .c_ident = { "AuthenticAMD" },
1143#ifdef CONFIG_X86_32
1144 .legacy_models = {
1145 { .family = 4, .model_names =
1146 {
1147 [3] = "486 DX/2",
1148 [7] = "486 DX/2-WB",
1149 [8] = "486 DX/4",
1150 [9] = "486 DX/4-WB",
1151 [14] = "Am5x86-WT",
1152 [15] = "Am5x86-WB"
1153 }
1154 },
1155 },
1156 .legacy_cache_size = amd_size_cache,
1157#endif
1158 .c_early_init = early_init_amd,
1159 .c_detect_tlb = cpu_detect_tlb_amd,
1160 .c_bsp_init = bsp_init_amd,
1161 .c_init = init_amd,
1162 .c_x86_vendor = X86_VENDOR_AMD,
1163};
1164
1165cpu_dev_register(amd_cpu_dev);
1166
1167static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask);
1168
1169static unsigned int amd_msr_dr_addr_masks[] = {
1170 MSR_F16H_DR0_ADDR_MASK,
1171 MSR_F16H_DR1_ADDR_MASK,
1172 MSR_F16H_DR1_ADDR_MASK + 1,
1173 MSR_F16H_DR1_ADDR_MASK + 2
1174};
1175
1176void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr)
1177{
1178 int cpu = smp_processor_id();
1179
1180 if (!cpu_feature_enabled(X86_FEATURE_BPEXT))
1181 return;
1182
1183 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks)))
1184 return;
1185
1186 if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask)
1187 return;
1188
1189 wrmsr(amd_msr_dr_addr_masks[dr], mask, 0);
1190 per_cpu(amd_dr_addr_mask, cpu)[dr] = mask;
1191}
1192
1193unsigned long amd_get_dr_addr_mask(unsigned int dr)
1194{
1195 if (!cpu_feature_enabled(X86_FEATURE_BPEXT))
1196 return 0;
1197
1198 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks)))
1199 return 0;
1200
1201 return per_cpu(amd_dr_addr_mask[dr], smp_processor_id());
1202}
1203EXPORT_SYMBOL_GPL(amd_get_dr_addr_mask);
1204
1205static void zenbleed_check_cpu(void *unused)
1206{
1207 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
1208
1209 zen2_zenbleed_check(c);
1210}
1211
1212void amd_check_microcode(void)
1213{
1214 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
1215 return;
1216
1217 if (cpu_feature_enabled(X86_FEATURE_ZEN2))
1218 on_each_cpu(zenbleed_check_cpu, NULL, 1);
1219}
1// SPDX-License-Identifier: GPL-2.0-only
2#include <linux/export.h>
3#include <linux/bitops.h>
4#include <linux/elf.h>
5#include <linux/mm.h>
6
7#include <linux/io.h>
8#include <linux/sched.h>
9#include <linux/sched/clock.h>
10#include <linux/random.h>
11#include <linux/topology.h>
12#include <asm/processor.h>
13#include <asm/apic.h>
14#include <asm/cacheinfo.h>
15#include <asm/cpu.h>
16#include <asm/spec-ctrl.h>
17#include <asm/smp.h>
18#include <asm/numa.h>
19#include <asm/pci-direct.h>
20#include <asm/delay.h>
21#include <asm/debugreg.h>
22#include <asm/resctrl.h>
23
24#ifdef CONFIG_X86_64
25# include <asm/mmconfig.h>
26#endif
27
28#include "cpu.h"
29
30static const int amd_erratum_383[];
31static const int amd_erratum_400[];
32static const int amd_erratum_1054[];
33static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
34
35/*
36 * nodes_per_socket: Stores the number of nodes per socket.
37 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
38 * Node Identifiers[10:8]
39 */
40static u32 nodes_per_socket = 1;
41
42static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
43{
44 u32 gprs[8] = { 0 };
45 int err;
46
47 WARN_ONCE((boot_cpu_data.x86 != 0xf),
48 "%s should only be used on K8!\n", __func__);
49
50 gprs[1] = msr;
51 gprs[7] = 0x9c5a203a;
52
53 err = rdmsr_safe_regs(gprs);
54
55 *p = gprs[0] | ((u64)gprs[2] << 32);
56
57 return err;
58}
59
60static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
61{
62 u32 gprs[8] = { 0 };
63
64 WARN_ONCE((boot_cpu_data.x86 != 0xf),
65 "%s should only be used on K8!\n", __func__);
66
67 gprs[0] = (u32)val;
68 gprs[1] = msr;
69 gprs[2] = val >> 32;
70 gprs[7] = 0x9c5a203a;
71
72 return wrmsr_safe_regs(gprs);
73}
74
75/*
76 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
77 * misexecution of code under Linux. Owners of such processors should
78 * contact AMD for precise details and a CPU swap.
79 *
80 * See http://www.multimania.com/poulot/k6bug.html
81 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
82 * (Publication # 21266 Issue Date: August 1998)
83 *
84 * The following test is erm.. interesting. AMD neglected to up
85 * the chip setting when fixing the bug but they also tweaked some
86 * performance at the same time..
87 */
88
89#ifdef CONFIG_X86_32
90extern __visible void vide(void);
91__asm__(".text\n"
92 ".globl vide\n"
93 ".type vide, @function\n"
94 ".align 4\n"
95 "vide: ret\n");
96#endif
97
98static void init_amd_k5(struct cpuinfo_x86 *c)
99{
100#ifdef CONFIG_X86_32
101/*
102 * General Systems BIOSen alias the cpu frequency registers
103 * of the Elan at 0x000df000. Unfortunately, one of the Linux
104 * drivers subsequently pokes it, and changes the CPU speed.
105 * Workaround : Remove the unneeded alias.
106 */
107#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
108#define CBAR_ENB (0x80000000)
109#define CBAR_KEY (0X000000CB)
110 if (c->x86_model == 9 || c->x86_model == 10) {
111 if (inl(CBAR) & CBAR_ENB)
112 outl(0 | CBAR_KEY, CBAR);
113 }
114#endif
115}
116
117static void init_amd_k6(struct cpuinfo_x86 *c)
118{
119#ifdef CONFIG_X86_32
120 u32 l, h;
121 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
122
123 if (c->x86_model < 6) {
124 /* Based on AMD doc 20734R - June 2000 */
125 if (c->x86_model == 0) {
126 clear_cpu_cap(c, X86_FEATURE_APIC);
127 set_cpu_cap(c, X86_FEATURE_PGE);
128 }
129 return;
130 }
131
132 if (c->x86_model == 6 && c->x86_stepping == 1) {
133 const int K6_BUG_LOOP = 1000000;
134 int n;
135 void (*f_vide)(void);
136 u64 d, d2;
137
138 pr_info("AMD K6 stepping B detected - ");
139
140 /*
141 * It looks like AMD fixed the 2.6.2 bug and improved indirect
142 * calls at the same time.
143 */
144
145 n = K6_BUG_LOOP;
146 f_vide = vide;
147 OPTIMIZER_HIDE_VAR(f_vide);
148 d = rdtsc();
149 while (n--)
150 f_vide();
151 d2 = rdtsc();
152 d = d2-d;
153
154 if (d > 20*K6_BUG_LOOP)
155 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
156 else
157 pr_cont("probably OK (after B9730xxxx).\n");
158 }
159
160 /* K6 with old style WHCR */
161 if (c->x86_model < 8 ||
162 (c->x86_model == 8 && c->x86_stepping < 8)) {
163 /* We can only write allocate on the low 508Mb */
164 if (mbytes > 508)
165 mbytes = 508;
166
167 rdmsr(MSR_K6_WHCR, l, h);
168 if ((l&0x0000FFFF) == 0) {
169 unsigned long flags;
170 l = (1<<0)|((mbytes/4)<<1);
171 local_irq_save(flags);
172 wbinvd();
173 wrmsr(MSR_K6_WHCR, l, h);
174 local_irq_restore(flags);
175 pr_info("Enabling old style K6 write allocation for %d Mb\n",
176 mbytes);
177 }
178 return;
179 }
180
181 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
182 c->x86_model == 9 || c->x86_model == 13) {
183 /* The more serious chips .. */
184
185 if (mbytes > 4092)
186 mbytes = 4092;
187
188 rdmsr(MSR_K6_WHCR, l, h);
189 if ((l&0xFFFF0000) == 0) {
190 unsigned long flags;
191 l = ((mbytes>>2)<<22)|(1<<16);
192 local_irq_save(flags);
193 wbinvd();
194 wrmsr(MSR_K6_WHCR, l, h);
195 local_irq_restore(flags);
196 pr_info("Enabling new style K6 write allocation for %d Mb\n",
197 mbytes);
198 }
199
200 return;
201 }
202
203 if (c->x86_model == 10) {
204 /* AMD Geode LX is model 10 */
205 /* placeholder for any needed mods */
206 return;
207 }
208#endif
209}
210
211static void init_amd_k7(struct cpuinfo_x86 *c)
212{
213#ifdef CONFIG_X86_32
214 u32 l, h;
215
216 /*
217 * Bit 15 of Athlon specific MSR 15, needs to be 0
218 * to enable SSE on Palomino/Morgan/Barton CPU's.
219 * If the BIOS didn't enable it already, enable it here.
220 */
221 if (c->x86_model >= 6 && c->x86_model <= 10) {
222 if (!cpu_has(c, X86_FEATURE_XMM)) {
223 pr_info("Enabling disabled K7/SSE Support.\n");
224 msr_clear_bit(MSR_K7_HWCR, 15);
225 set_cpu_cap(c, X86_FEATURE_XMM);
226 }
227 }
228
229 /*
230 * It's been determined by AMD that Athlons since model 8 stepping 1
231 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
232 * As per AMD technical note 27212 0.2
233 */
234 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
235 rdmsr(MSR_K7_CLK_CTL, l, h);
236 if ((l & 0xfff00000) != 0x20000000) {
237 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
238 l, ((l & 0x000fffff)|0x20000000));
239 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
240 }
241 }
242
243 /* calling is from identify_secondary_cpu() ? */
244 if (!c->cpu_index)
245 return;
246
247 /*
248 * Certain Athlons might work (for various values of 'work') in SMP
249 * but they are not certified as MP capable.
250 */
251 /* Athlon 660/661 is valid. */
252 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
253 (c->x86_stepping == 1)))
254 return;
255
256 /* Duron 670 is valid */
257 if ((c->x86_model == 7) && (c->x86_stepping == 0))
258 return;
259
260 /*
261 * Athlon 662, Duron 671, and Athlon >model 7 have capability
262 * bit. It's worth noting that the A5 stepping (662) of some
263 * Athlon XP's have the MP bit set.
264 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
265 * more.
266 */
267 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
268 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
269 (c->x86_model > 7))
270 if (cpu_has(c, X86_FEATURE_MP))
271 return;
272
273 /* If we get here, not a certified SMP capable AMD system. */
274
275 /*
276 * Don't taint if we are running SMP kernel on a single non-MP
277 * approved Athlon
278 */
279 WARN_ONCE(1, "WARNING: This combination of AMD"
280 " processors is not suitable for SMP.\n");
281 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
282#endif
283}
284
285#ifdef CONFIG_NUMA
286/*
287 * To workaround broken NUMA config. Read the comment in
288 * srat_detect_node().
289 */
290static int nearby_node(int apicid)
291{
292 int i, node;
293
294 for (i = apicid - 1; i >= 0; i--) {
295 node = __apicid_to_node[i];
296 if (node != NUMA_NO_NODE && node_online(node))
297 return node;
298 }
299 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
300 node = __apicid_to_node[i];
301 if (node != NUMA_NO_NODE && node_online(node))
302 return node;
303 }
304 return first_node(node_online_map); /* Shouldn't happen */
305}
306#endif
307
308/*
309 * Fix up cpu_core_id for pre-F17h systems to be in the
310 * [0 .. cores_per_node - 1] range. Not really needed but
311 * kept so as not to break existing setups.
312 */
313static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
314{
315 u32 cus_per_node;
316
317 if (c->x86 >= 0x17)
318 return;
319
320 cus_per_node = c->x86_max_cores / nodes_per_socket;
321 c->cpu_core_id %= cus_per_node;
322}
323
324/*
325 * Fixup core topology information for
326 * (1) AMD multi-node processors
327 * Assumption: Number of cores in each internal node is the same.
328 * (2) AMD processors supporting compute units
329 */
330static void amd_get_topology(struct cpuinfo_x86 *c)
331{
332 int cpu = smp_processor_id();
333
334 /* get information required for multi-node processors */
335 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
336 int err;
337 u32 eax, ebx, ecx, edx;
338
339 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
340
341 c->cpu_die_id = ecx & 0xff;
342
343 if (c->x86 == 0x15)
344 c->cu_id = ebx & 0xff;
345
346 if (c->x86 >= 0x17) {
347 c->cpu_core_id = ebx & 0xff;
348
349 if (smp_num_siblings > 1)
350 c->x86_max_cores /= smp_num_siblings;
351 }
352
353 /*
354 * In case leaf B is available, use it to derive
355 * topology information.
356 */
357 err = detect_extended_topology(c);
358 if (!err)
359 c->x86_coreid_bits = get_count_order(c->x86_max_cores);
360
361 cacheinfo_amd_init_llc_id(c, cpu);
362
363 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
364 u64 value;
365
366 rdmsrl(MSR_FAM10H_NODE_ID, value);
367 c->cpu_die_id = value & 7;
368
369 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
370 } else
371 return;
372
373 if (nodes_per_socket > 1) {
374 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
375 legacy_fixup_core_id(c);
376 }
377}
378
379/*
380 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
381 * Assumes number of cores is a power of two.
382 */
383static void amd_detect_cmp(struct cpuinfo_x86 *c)
384{
385 unsigned bits;
386 int cpu = smp_processor_id();
387
388 bits = c->x86_coreid_bits;
389 /* Low order bits define the core id (index of core in socket) */
390 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
391 /* Convert the initial APIC ID into the socket ID */
392 c->phys_proc_id = c->initial_apicid >> bits;
393 /* use socket ID also for last level cache */
394 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
395}
396
397u32 amd_get_nodes_per_socket(void)
398{
399 return nodes_per_socket;
400}
401EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
402
403static void srat_detect_node(struct cpuinfo_x86 *c)
404{
405#ifdef CONFIG_NUMA
406 int cpu = smp_processor_id();
407 int node;
408 unsigned apicid = c->apicid;
409
410 node = numa_cpu_node(cpu);
411 if (node == NUMA_NO_NODE)
412 node = get_llc_id(cpu);
413
414 /*
415 * On multi-fabric platform (e.g. Numascale NumaChip) a
416 * platform-specific handler needs to be called to fixup some
417 * IDs of the CPU.
418 */
419 if (x86_cpuinit.fixup_cpu_id)
420 x86_cpuinit.fixup_cpu_id(c, node);
421
422 if (!node_online(node)) {
423 /*
424 * Two possibilities here:
425 *
426 * - The CPU is missing memory and no node was created. In
427 * that case try picking one from a nearby CPU.
428 *
429 * - The APIC IDs differ from the HyperTransport node IDs
430 * which the K8 northbridge parsing fills in. Assume
431 * they are all increased by a constant offset, but in
432 * the same order as the HT nodeids. If that doesn't
433 * result in a usable node fall back to the path for the
434 * previous case.
435 *
436 * This workaround operates directly on the mapping between
437 * APIC ID and NUMA node, assuming certain relationship
438 * between APIC ID, HT node ID and NUMA topology. As going
439 * through CPU mapping may alter the outcome, directly
440 * access __apicid_to_node[].
441 */
442 int ht_nodeid = c->initial_apicid;
443
444 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
445 node = __apicid_to_node[ht_nodeid];
446 /* Pick a nearby node */
447 if (!node_online(node))
448 node = nearby_node(apicid);
449 }
450 numa_set_node(cpu, node);
451#endif
452}
453
454static void early_init_amd_mc(struct cpuinfo_x86 *c)
455{
456#ifdef CONFIG_SMP
457 unsigned bits, ecx;
458
459 /* Multi core CPU? */
460 if (c->extended_cpuid_level < 0x80000008)
461 return;
462
463 ecx = cpuid_ecx(0x80000008);
464
465 c->x86_max_cores = (ecx & 0xff) + 1;
466
467 /* CPU telling us the core id bits shift? */
468 bits = (ecx >> 12) & 0xF;
469
470 /* Otherwise recompute */
471 if (bits == 0) {
472 while ((1 << bits) < c->x86_max_cores)
473 bits++;
474 }
475
476 c->x86_coreid_bits = bits;
477#endif
478}
479
480static void bsp_init_amd(struct cpuinfo_x86 *c)
481{
482 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
483
484 if (c->x86 > 0x10 ||
485 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
486 u64 val;
487
488 rdmsrl(MSR_K7_HWCR, val);
489 if (!(val & BIT(24)))
490 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
491 }
492 }
493
494 if (c->x86 == 0x15) {
495 unsigned long upperbit;
496 u32 cpuid, assoc;
497
498 cpuid = cpuid_edx(0x80000005);
499 assoc = cpuid >> 16 & 0xff;
500 upperbit = ((cpuid >> 24) << 10) / assoc;
501
502 va_align.mask = (upperbit - 1) & PAGE_MASK;
503 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
504
505 /* A random value per boot for bit slice [12:upper_bit) */
506 va_align.bits = get_random_u32() & va_align.mask;
507 }
508
509 if (cpu_has(c, X86_FEATURE_MWAITX))
510 use_mwaitx_delay();
511
512 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
513 u32 ecx;
514
515 ecx = cpuid_ecx(0x8000001e);
516 __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1;
517 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
518 u64 value;
519
520 rdmsrl(MSR_FAM10H_NODE_ID, value);
521 __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1;
522 }
523
524 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
525 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
526 c->x86 >= 0x15 && c->x86 <= 0x17) {
527 unsigned int bit;
528
529 switch (c->x86) {
530 case 0x15: bit = 54; break;
531 case 0x16: bit = 33; break;
532 case 0x17: bit = 10; break;
533 default: return;
534 }
535 /*
536 * Try to cache the base value so further operations can
537 * avoid RMW. If that faults, do not enable SSBD.
538 */
539 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
540 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
541 setup_force_cpu_cap(X86_FEATURE_SSBD);
542 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
543 }
544 }
545
546 resctrl_cpu_detect(c);
547}
548
549static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
550{
551 u64 msr;
552
553 /*
554 * BIOS support is required for SME and SEV.
555 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by
556 * the SME physical address space reduction value.
557 * If BIOS has not enabled SME then don't advertise the
558 * SME feature (set in scattered.c).
559 * If the kernel has not enabled SME via any means then
560 * don't advertise the SME feature.
561 * For SEV: If BIOS has not enabled SEV then don't advertise the
562 * SEV and SEV_ES feature (set in scattered.c).
563 *
564 * In all cases, since support for SME and SEV requires long mode,
565 * don't advertise the feature under CONFIG_X86_32.
566 */
567 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
568 /* Check if memory encryption is enabled */
569 rdmsrl(MSR_AMD64_SYSCFG, msr);
570 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
571 goto clear_all;
572
573 /*
574 * Always adjust physical address bits. Even though this
575 * will be a value above 32-bits this is still done for
576 * CONFIG_X86_32 so that accurate values are reported.
577 */
578 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
579
580 if (IS_ENABLED(CONFIG_X86_32))
581 goto clear_all;
582
583 if (!sme_me_mask)
584 setup_clear_cpu_cap(X86_FEATURE_SME);
585
586 rdmsrl(MSR_K7_HWCR, msr);
587 if (!(msr & MSR_K7_HWCR_SMMLOCK))
588 goto clear_sev;
589
590 return;
591
592clear_all:
593 setup_clear_cpu_cap(X86_FEATURE_SME);
594clear_sev:
595 setup_clear_cpu_cap(X86_FEATURE_SEV);
596 setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
597 }
598}
599
600static void early_init_amd(struct cpuinfo_x86 *c)
601{
602 u64 value;
603 u32 dummy;
604
605 early_init_amd_mc(c);
606
607 if (c->x86 >= 0xf)
608 set_cpu_cap(c, X86_FEATURE_K8);
609
610 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
611
612 /*
613 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
614 * with P/T states and does not stop in deep C-states
615 */
616 if (c->x86_power & (1 << 8)) {
617 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
618 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
619 }
620
621 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
622 if (c->x86_power & BIT(12))
623 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
624
625 /* Bit 14 indicates the Runtime Average Power Limit interface. */
626 if (c->x86_power & BIT(14))
627 set_cpu_cap(c, X86_FEATURE_RAPL);
628
629#ifdef CONFIG_X86_64
630 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
631#else
632 /* Set MTRR capability flag if appropriate */
633 if (c->x86 == 5)
634 if (c->x86_model == 13 || c->x86_model == 9 ||
635 (c->x86_model == 8 && c->x86_stepping >= 8))
636 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
637#endif
638#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
639 /*
640 * ApicID can always be treated as an 8-bit value for AMD APIC versions
641 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
642 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
643 * after 16h.
644 */
645 if (boot_cpu_has(X86_FEATURE_APIC)) {
646 if (c->x86 > 0x16)
647 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
648 else if (c->x86 >= 0xf) {
649 /* check CPU config space for extended APIC ID */
650 unsigned int val;
651
652 val = read_pci_config(0, 24, 0, 0x68);
653 if ((val >> 17 & 0x3) == 0x3)
654 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
655 }
656 }
657#endif
658
659 /*
660 * This is only needed to tell the kernel whether to use VMCALL
661 * and VMMCALL. VMMCALL is never executed except under virt, so
662 * we can set it unconditionally.
663 */
664 set_cpu_cap(c, X86_FEATURE_VMMCALL);
665
666 /* F16h erratum 793, CVE-2013-6885 */
667 if (c->x86 == 0x16 && c->x86_model <= 0xf)
668 msr_set_bit(MSR_AMD64_LS_CFG, 15);
669
670 /*
671 * Check whether the machine is affected by erratum 400. This is
672 * used to select the proper idle routine and to enable the check
673 * whether the machine is affected in arch_post_acpi_init(), which
674 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
675 */
676 if (cpu_has_amd_erratum(c, amd_erratum_400))
677 set_cpu_bug(c, X86_BUG_AMD_E400);
678
679 early_detect_mem_encrypt(c);
680
681 /* Re-enable TopologyExtensions if switched off by BIOS */
682 if (c->x86 == 0x15 &&
683 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&
684 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
685
686 if (msr_set_bit(0xc0011005, 54) > 0) {
687 rdmsrl(0xc0011005, value);
688 if (value & BIT_64(54)) {
689 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
690 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
691 }
692 }
693 }
694
695 if (cpu_has(c, X86_FEATURE_TOPOEXT))
696 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
697}
698
699static void init_amd_k8(struct cpuinfo_x86 *c)
700{
701 u32 level;
702 u64 value;
703
704 /* On C+ stepping K8 rep microcode works well for copy/memset */
705 level = cpuid_eax(1);
706 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
707 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
708
709 /*
710 * Some BIOSes incorrectly force this feature, but only K8 revision D
711 * (model = 0x14) and later actually support it.
712 * (AMD Erratum #110, docId: 25759).
713 */
714 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
715 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
716 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
717 value &= ~BIT_64(32);
718 wrmsrl_amd_safe(0xc001100d, value);
719 }
720 }
721
722 if (!c->x86_model_id[0])
723 strcpy(c->x86_model_id, "Hammer");
724
725#ifdef CONFIG_SMP
726 /*
727 * Disable TLB flush filter by setting HWCR.FFDIS on K8
728 * bit 6 of msr C001_0015
729 *
730 * Errata 63 for SH-B3 steppings
731 * Errata 122 for all steppings (F+ have it disabled by default)
732 */
733 msr_set_bit(MSR_K7_HWCR, 6);
734#endif
735 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
736}
737
738static void init_amd_gh(struct cpuinfo_x86 *c)
739{
740#ifdef CONFIG_MMCONF_FAM10H
741 /* do this for boot cpu */
742 if (c == &boot_cpu_data)
743 check_enable_amd_mmconf_dmi();
744
745 fam10h_check_enable_mmcfg();
746#endif
747
748 /*
749 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
750 * is always needed when GART is enabled, even in a kernel which has no
751 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
752 * If it doesn't, we do it here as suggested by the BKDG.
753 *
754 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
755 */
756 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
757
758 /*
759 * On family 10h BIOS may not have properly enabled WC+ support, causing
760 * it to be converted to CD memtype. This may result in performance
761 * degradation for certain nested-paging guests. Prevent this conversion
762 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
763 *
764 * NOTE: we want to use the _safe accessors so as not to #GP kvm
765 * guests on older kvm hosts.
766 */
767 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
768
769 if (cpu_has_amd_erratum(c, amd_erratum_383))
770 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
771}
772
773static void init_amd_ln(struct cpuinfo_x86 *c)
774{
775 /*
776 * Apply erratum 665 fix unconditionally so machines without a BIOS
777 * fix work.
778 */
779 msr_set_bit(MSR_AMD64_DE_CFG, 31);
780}
781
782static bool rdrand_force;
783
784static int __init rdrand_cmdline(char *str)
785{
786 if (!str)
787 return -EINVAL;
788
789 if (!strcmp(str, "force"))
790 rdrand_force = true;
791 else
792 return -EINVAL;
793
794 return 0;
795}
796early_param("rdrand", rdrand_cmdline);
797
798static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
799{
800 /*
801 * Saving of the MSR used to hide the RDRAND support during
802 * suspend/resume is done by arch/x86/power/cpu.c, which is
803 * dependent on CONFIG_PM_SLEEP.
804 */
805 if (!IS_ENABLED(CONFIG_PM_SLEEP))
806 return;
807
808 /*
809 * The self-test can clear X86_FEATURE_RDRAND, so check for
810 * RDRAND support using the CPUID function directly.
811 */
812 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force)
813 return;
814
815 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62);
816
817 /*
818 * Verify that the CPUID change has occurred in case the kernel is
819 * running virtualized and the hypervisor doesn't support the MSR.
820 */
821 if (cpuid_ecx(1) & BIT(30)) {
822 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n");
823 return;
824 }
825
826 clear_cpu_cap(c, X86_FEATURE_RDRAND);
827 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n");
828}
829
830static void init_amd_jg(struct cpuinfo_x86 *c)
831{
832 /*
833 * Some BIOS implementations do not restore proper RDRAND support
834 * across suspend and resume. Check on whether to hide the RDRAND
835 * instruction support via CPUID.
836 */
837 clear_rdrand_cpuid_bit(c);
838}
839
840static void init_amd_bd(struct cpuinfo_x86 *c)
841{
842 u64 value;
843
844 /*
845 * The way access filter has a performance penalty on some workloads.
846 * Disable it on the affected CPUs.
847 */
848 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
849 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
850 value |= 0x1E;
851 wrmsrl_safe(MSR_F15H_IC_CFG, value);
852 }
853 }
854
855 /*
856 * Some BIOS implementations do not restore proper RDRAND support
857 * across suspend and resume. Check on whether to hide the RDRAND
858 * instruction support via CPUID.
859 */
860 clear_rdrand_cpuid_bit(c);
861}
862
863void init_spectral_chicken(struct cpuinfo_x86 *c)
864{
865#ifdef CONFIG_CPU_UNRET_ENTRY
866 u64 value;
867
868 /*
869 * On Zen2 we offer this chicken (bit) on the altar of Speculation.
870 *
871 * This suppresses speculation from the middle of a basic block, i.e. it
872 * suppresses non-branch predictions.
873 *
874 * We use STIBP as a heuristic to filter out Zen2 from the rest of F17H
875 */
876 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_AMD_STIBP)) {
877 if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) {
878 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT;
879 wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value);
880 }
881 }
882#endif
883}
884
885static void init_amd_zn(struct cpuinfo_x86 *c)
886{
887 set_cpu_cap(c, X86_FEATURE_ZEN);
888
889#ifdef CONFIG_NUMA
890 node_reclaim_distance = 32;
891#endif
892
893 /* Fix up CPUID bits, but only if not virtualised. */
894 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
895
896 /* Erratum 1076: CPB feature bit not being set in CPUID. */
897 if (!cpu_has(c, X86_FEATURE_CPB))
898 set_cpu_cap(c, X86_FEATURE_CPB);
899
900 /*
901 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
902 * Branch Type Confusion, but predate the allocation of the
903 * BTC_NO bit.
904 */
905 if (c->x86 == 0x19 && !cpu_has(c, X86_FEATURE_BTC_NO))
906 set_cpu_cap(c, X86_FEATURE_BTC_NO);
907 }
908}
909
910static void init_amd(struct cpuinfo_x86 *c)
911{
912 early_init_amd(c);
913
914 /*
915 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
916 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
917 */
918 clear_cpu_cap(c, 0*32+31);
919
920 if (c->x86 >= 0x10)
921 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
922
923 /* get apicid instead of initial apic id from cpuid */
924 c->apicid = hard_smp_processor_id();
925
926 /* K6s reports MCEs but don't actually have all the MSRs */
927 if (c->x86 < 6)
928 clear_cpu_cap(c, X86_FEATURE_MCE);
929
930 switch (c->x86) {
931 case 4: init_amd_k5(c); break;
932 case 5: init_amd_k6(c); break;
933 case 6: init_amd_k7(c); break;
934 case 0xf: init_amd_k8(c); break;
935 case 0x10: init_amd_gh(c); break;
936 case 0x12: init_amd_ln(c); break;
937 case 0x15: init_amd_bd(c); break;
938 case 0x16: init_amd_jg(c); break;
939 case 0x17: init_spectral_chicken(c);
940 fallthrough;
941 case 0x19: init_amd_zn(c); break;
942 }
943
944 /*
945 * Enable workaround for FXSAVE leak on CPUs
946 * without a XSaveErPtr feature
947 */
948 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
949 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
950
951 cpu_detect_cache_sizes(c);
952
953 amd_detect_cmp(c);
954 amd_get_topology(c);
955 srat_detect_node(c);
956
957 init_amd_cacheinfo(c);
958
959 if (cpu_has(c, X86_FEATURE_XMM2)) {
960 /*
961 * Use LFENCE for execution serialization. On families which
962 * don't have that MSR, LFENCE is already serializing.
963 * msr_set_bit() uses the safe accessors, too, even if the MSR
964 * is not present.
965 */
966 msr_set_bit(MSR_AMD64_DE_CFG,
967 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
968
969 /* A serializing LFENCE stops RDTSC speculation */
970 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
971 }
972
973 /*
974 * Family 0x12 and above processors have APIC timer
975 * running in deep C states.
976 */
977 if (c->x86 > 0x11)
978 set_cpu_cap(c, X86_FEATURE_ARAT);
979
980 /* 3DNow or LM implies PREFETCHW */
981 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
982 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
983 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
984
985 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
986 if (!cpu_feature_enabled(X86_FEATURE_XENPV))
987 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
988
989 /*
990 * Turn on the Instructions Retired free counter on machines not
991 * susceptible to erratum #1054 "Instructions Retired Performance
992 * Counter May Be Inaccurate".
993 */
994 if (cpu_has(c, X86_FEATURE_IRPERF) &&
995 !cpu_has_amd_erratum(c, amd_erratum_1054))
996 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
997
998 check_null_seg_clears_base(c);
999}
1000
1001#ifdef CONFIG_X86_32
1002static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1003{
1004 /* AMD errata T13 (order #21922) */
1005 if (c->x86 == 6) {
1006 /* Duron Rev A0 */
1007 if (c->x86_model == 3 && c->x86_stepping == 0)
1008 size = 64;
1009 /* Tbird rev A1/A2 */
1010 if (c->x86_model == 4 &&
1011 (c->x86_stepping == 0 || c->x86_stepping == 1))
1012 size = 256;
1013 }
1014 return size;
1015}
1016#endif
1017
1018static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
1019{
1020 u32 ebx, eax, ecx, edx;
1021 u16 mask = 0xfff;
1022
1023 if (c->x86 < 0xf)
1024 return;
1025
1026 if (c->extended_cpuid_level < 0x80000006)
1027 return;
1028
1029 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1030
1031 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
1032 tlb_lli_4k[ENTRIES] = ebx & mask;
1033
1034 /*
1035 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
1036 * characteristics from the CPUID function 0x80000005 instead.
1037 */
1038 if (c->x86 == 0xf) {
1039 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1040 mask = 0xff;
1041 }
1042
1043 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1044 if (!((eax >> 16) & mask))
1045 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
1046 else
1047 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
1048
1049 /* a 4M entry uses two 2M entries */
1050 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
1051
1052 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1053 if (!(eax & mask)) {
1054 /* Erratum 658 */
1055 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
1056 tlb_lli_2m[ENTRIES] = 1024;
1057 } else {
1058 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1059 tlb_lli_2m[ENTRIES] = eax & 0xff;
1060 }
1061 } else
1062 tlb_lli_2m[ENTRIES] = eax & mask;
1063
1064 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
1065}
1066
1067static const struct cpu_dev amd_cpu_dev = {
1068 .c_vendor = "AMD",
1069 .c_ident = { "AuthenticAMD" },
1070#ifdef CONFIG_X86_32
1071 .legacy_models = {
1072 { .family = 4, .model_names =
1073 {
1074 [3] = "486 DX/2",
1075 [7] = "486 DX/2-WB",
1076 [8] = "486 DX/4",
1077 [9] = "486 DX/4-WB",
1078 [14] = "Am5x86-WT",
1079 [15] = "Am5x86-WB"
1080 }
1081 },
1082 },
1083 .legacy_cache_size = amd_size_cache,
1084#endif
1085 .c_early_init = early_init_amd,
1086 .c_detect_tlb = cpu_detect_tlb_amd,
1087 .c_bsp_init = bsp_init_amd,
1088 .c_init = init_amd,
1089 .c_x86_vendor = X86_VENDOR_AMD,
1090};
1091
1092cpu_dev_register(amd_cpu_dev);
1093
1094/*
1095 * AMD errata checking
1096 *
1097 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
1098 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
1099 * have an OSVW id assigned, which it takes as first argument. Both take a
1100 * variable number of family-specific model-stepping ranges created by
1101 * AMD_MODEL_RANGE().
1102 *
1103 * Example:
1104 *
1105 * const int amd_erratum_319[] =
1106 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
1107 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
1108 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
1109 */
1110
1111#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1112#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1113#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1114 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1115#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1116#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1117#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1118
1119static const int amd_erratum_400[] =
1120 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
1121 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
1122
1123static const int amd_erratum_383[] =
1124 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
1125
1126/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
1127static const int amd_erratum_1054[] =
1128 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
1129
1130static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
1131{
1132 int osvw_id = *erratum++;
1133 u32 range;
1134 u32 ms;
1135
1136 if (osvw_id >= 0 && osvw_id < 65536 &&
1137 cpu_has(cpu, X86_FEATURE_OSVW)) {
1138 u64 osvw_len;
1139
1140 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
1141 if (osvw_id < osvw_len) {
1142 u64 osvw_bits;
1143
1144 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
1145 osvw_bits);
1146 return osvw_bits & (1ULL << (osvw_id & 0x3f));
1147 }
1148 }
1149
1150 /* OSVW unavailable or ID unknown, match family-model-stepping range */
1151 ms = (cpu->x86_model << 4) | cpu->x86_stepping;
1152 while ((range = *erratum++))
1153 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
1154 (ms >= AMD_MODEL_RANGE_START(range)) &&
1155 (ms <= AMD_MODEL_RANGE_END(range)))
1156 return true;
1157
1158 return false;
1159}
1160
1161void set_dr_addr_mask(unsigned long mask, int dr)
1162{
1163 if (!boot_cpu_has(X86_FEATURE_BPEXT))
1164 return;
1165
1166 switch (dr) {
1167 case 0:
1168 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
1169 break;
1170 case 1:
1171 case 2:
1172 case 3:
1173 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
1174 break;
1175 default:
1176 break;
1177 }
1178}
1179
1180u32 amd_get_highest_perf(void)
1181{
1182 struct cpuinfo_x86 *c = &boot_cpu_data;
1183
1184 if (c->x86 == 0x17 && ((c->x86_model >= 0x30 && c->x86_model < 0x40) ||
1185 (c->x86_model >= 0x70 && c->x86_model < 0x80)))
1186 return 166;
1187
1188 if (c->x86 == 0x19 && ((c->x86_model >= 0x20 && c->x86_model < 0x30) ||
1189 (c->x86_model >= 0x40 && c->x86_model < 0x70)))
1190 return 166;
1191
1192 return 255;
1193}
1194EXPORT_SYMBOL_GPL(amd_get_highest_perf);