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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * wm0010.c -- WM0010 DSP Driver
4 *
5 * Copyright 2012 Wolfson Microelectronics PLC.
6 *
7 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
9 * Scott Ling <sl@opensource.wolfsonmicro.com>
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/interrupt.h>
15#include <linux/irqreturn.h>
16#include <linux/init.h>
17#include <linux/spi/spi.h>
18#include <linux/firmware.h>
19#include <linux/delay.h>
20#include <linux/fs.h>
21#include <linux/gpio/consumer.h>
22#include <linux/regulator/consumer.h>
23#include <linux/mutex.h>
24#include <linux/workqueue.h>
25
26#include <sound/soc.h>
27#include <sound/wm0010.h>
28
29#define DEVICE_ID_WM0010 10
30
31/* We only support v1 of the .dfw INFO record */
32#define INFO_VERSION 1
33
34enum dfw_cmd {
35 DFW_CMD_FUSE = 0x01,
36 DFW_CMD_CODE_HDR,
37 DFW_CMD_CODE_DATA,
38 DFW_CMD_PLL,
39 DFW_CMD_INFO = 0xff
40};
41
42struct dfw_binrec {
43 u8 command;
44 u32 length:24;
45 u32 address;
46 uint8_t data[];
47} __packed;
48
49struct dfw_inforec {
50 u8 info_version;
51 u8 tool_major_version;
52 u8 tool_minor_version;
53 u8 dsp_target;
54};
55
56struct dfw_pllrec {
57 u8 command;
58 u32 length:24;
59 u32 address;
60 u32 clkctrl1;
61 u32 clkctrl2;
62 u32 clkctrl3;
63 u32 ldetctrl;
64 u32 uart_div;
65 u32 spi_div;
66} __packed;
67
68static struct pll_clock_map {
69 int max_sysclk;
70 int max_pll_spi_speed;
71 u32 pll_clkctrl1;
72} pll_clock_map[] = { /* Dividers */
73 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */
74 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */
75 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */
76 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */
77 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */
78 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */
79};
80
81enum wm0010_state {
82 WM0010_POWER_OFF,
83 WM0010_OUT_OF_RESET,
84 WM0010_BOOTROM,
85 WM0010_STAGE2,
86 WM0010_FIRMWARE,
87};
88
89struct wm0010_priv {
90 struct snd_soc_component *component;
91
92 struct mutex lock;
93 struct device *dev;
94
95 struct wm0010_pdata pdata;
96
97 struct gpio_desc *reset;
98
99 struct regulator_bulk_data core_supplies[2];
100 struct regulator *dbvdd;
101
102 int sysclk;
103
104 enum wm0010_state state;
105 bool boot_failed;
106 bool ready;
107 bool pll_running;
108 int max_spi_freq;
109 int board_max_spi_speed;
110 u32 pll_clkctrl1;
111
112 spinlock_t irq_lock;
113 int irq;
114
115 struct completion boot_completion;
116};
117
118static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
119SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
120};
121
122static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
123 { "SDI2 Capture", NULL, "SDI1 Playback" },
124 { "SDI1 Capture", NULL, "SDI2 Playback" },
125
126 { "SDI1 Capture", NULL, "CLKIN" },
127 { "SDI2 Capture", NULL, "CLKIN" },
128 { "SDI1 Playback", NULL, "CLKIN" },
129 { "SDI2 Playback", NULL, "CLKIN" },
130};
131
132static const char *wm0010_state_to_str(enum wm0010_state state)
133{
134 static const char * const state_to_str[] = {
135 "Power off",
136 "Out of reset",
137 "Boot ROM",
138 "Stage2",
139 "Firmware"
140 };
141
142 if (state < 0 || state >= ARRAY_SIZE(state_to_str))
143 return "null";
144 return state_to_str[state];
145}
146
147/* Called with wm0010->lock held */
148static void wm0010_halt(struct snd_soc_component *component)
149{
150 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
151 unsigned long flags;
152 enum wm0010_state state;
153
154 /* Fetch the wm0010 state */
155 spin_lock_irqsave(&wm0010->irq_lock, flags);
156 state = wm0010->state;
157 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
158
159 switch (state) {
160 case WM0010_POWER_OFF:
161 /* If there's nothing to do, bail out */
162 return;
163 case WM0010_OUT_OF_RESET:
164 case WM0010_BOOTROM:
165 case WM0010_STAGE2:
166 case WM0010_FIRMWARE:
167 /* Remember to put chip back into reset */
168 gpiod_set_value_cansleep(wm0010->reset, 1);
169 /* Disable the regulators */
170 regulator_disable(wm0010->dbvdd);
171 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
172 wm0010->core_supplies);
173 break;
174 }
175
176 spin_lock_irqsave(&wm0010->irq_lock, flags);
177 wm0010->state = WM0010_POWER_OFF;
178 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
179}
180
181struct wm0010_boot_xfer {
182 struct list_head list;
183 struct snd_soc_component *component;
184 struct completion *done;
185 struct spi_message m;
186 struct spi_transfer t;
187};
188
189/* Called with wm0010->lock held */
190static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
191{
192 enum wm0010_state state;
193 unsigned long flags;
194
195 spin_lock_irqsave(&wm0010->irq_lock, flags);
196 state = wm0010->state;
197 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
198
199 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
200 wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
201
202 wm0010->boot_failed = true;
203}
204
205static void wm0010_boot_xfer_complete(void *data)
206{
207 struct wm0010_boot_xfer *xfer = data;
208 struct snd_soc_component *component = xfer->component;
209 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
210 u32 *out32 = xfer->t.rx_buf;
211 int i;
212
213 if (xfer->m.status != 0) {
214 dev_err(component->dev, "SPI transfer failed: %d\n",
215 xfer->m.status);
216 wm0010_mark_boot_failure(wm0010);
217 if (xfer->done)
218 complete(xfer->done);
219 return;
220 }
221
222 for (i = 0; i < xfer->t.len / 4; i++) {
223 dev_dbg(component->dev, "%d: %04x\n", i, out32[i]);
224
225 switch (be32_to_cpu(out32[i])) {
226 case 0xe0e0e0e0:
227 dev_err(component->dev,
228 "%d: ROM error reported in stage 2\n", i);
229 wm0010_mark_boot_failure(wm0010);
230 break;
231
232 case 0x55555555:
233 if (wm0010->state < WM0010_STAGE2)
234 break;
235 dev_err(component->dev,
236 "%d: ROM bootloader running in stage 2\n", i);
237 wm0010_mark_boot_failure(wm0010);
238 break;
239
240 case 0x0fed0000:
241 dev_dbg(component->dev, "Stage2 loader running\n");
242 break;
243
244 case 0x0fed0007:
245 dev_dbg(component->dev, "CODE_HDR packet received\n");
246 break;
247
248 case 0x0fed0008:
249 dev_dbg(component->dev, "CODE_DATA packet received\n");
250 break;
251
252 case 0x0fed0009:
253 dev_dbg(component->dev, "Download complete\n");
254 break;
255
256 case 0x0fed000c:
257 dev_dbg(component->dev, "Application start\n");
258 break;
259
260 case 0x0fed000e:
261 dev_dbg(component->dev, "PLL packet received\n");
262 wm0010->pll_running = true;
263 break;
264
265 case 0x0fed0025:
266 dev_err(component->dev, "Device reports image too long\n");
267 wm0010_mark_boot_failure(wm0010);
268 break;
269
270 case 0x0fed002c:
271 dev_err(component->dev, "Device reports bad SPI packet\n");
272 wm0010_mark_boot_failure(wm0010);
273 break;
274
275 case 0x0fed0031:
276 dev_err(component->dev, "Device reports SPI read overflow\n");
277 wm0010_mark_boot_failure(wm0010);
278 break;
279
280 case 0x0fed0032:
281 dev_err(component->dev, "Device reports SPI underclock\n");
282 wm0010_mark_boot_failure(wm0010);
283 break;
284
285 case 0x0fed0033:
286 dev_err(component->dev, "Device reports bad header packet\n");
287 wm0010_mark_boot_failure(wm0010);
288 break;
289
290 case 0x0fed0034:
291 dev_err(component->dev, "Device reports invalid packet type\n");
292 wm0010_mark_boot_failure(wm0010);
293 break;
294
295 case 0x0fed0035:
296 dev_err(component->dev, "Device reports data before header error\n");
297 wm0010_mark_boot_failure(wm0010);
298 break;
299
300 case 0x0fed0038:
301 dev_err(component->dev, "Device reports invalid PLL packet\n");
302 break;
303
304 case 0x0fed003a:
305 dev_err(component->dev, "Device reports packet alignment error\n");
306 wm0010_mark_boot_failure(wm0010);
307 break;
308
309 default:
310 dev_err(component->dev, "Unrecognised return 0x%x\n",
311 be32_to_cpu(out32[i]));
312 wm0010_mark_boot_failure(wm0010);
313 break;
314 }
315
316 if (wm0010->boot_failed)
317 break;
318 }
319
320 if (xfer->done)
321 complete(xfer->done);
322}
323
324static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
325{
326 int i;
327
328 for (i = 0; i < len / 8; i++)
329 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
330}
331
332static int wm0010_firmware_load(const char *name, struct snd_soc_component *component)
333{
334 struct spi_device *spi = to_spi_device(component->dev);
335 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
336 struct list_head xfer_list;
337 struct wm0010_boot_xfer *xfer;
338 int ret;
339 DECLARE_COMPLETION_ONSTACK(done);
340 const struct firmware *fw;
341 const struct dfw_binrec *rec;
342 const struct dfw_inforec *inforec;
343 u64 *img;
344 u8 *out, dsp;
345 u32 len, offset;
346
347 INIT_LIST_HEAD(&xfer_list);
348
349 ret = request_firmware(&fw, name, component->dev);
350 if (ret != 0) {
351 dev_err(component->dev, "Failed to request application(%s): %d\n",
352 name, ret);
353 return ret;
354 }
355
356 rec = (const struct dfw_binrec *)fw->data;
357 inforec = (const struct dfw_inforec *)rec->data;
358 offset = 0;
359 dsp = inforec->dsp_target;
360 wm0010->boot_failed = false;
361 if (WARN_ON(!list_empty(&xfer_list)))
362 return -EINVAL;
363
364 /* First record should be INFO */
365 if (rec->command != DFW_CMD_INFO) {
366 dev_err(component->dev, "First record not INFO\r\n");
367 ret = -EINVAL;
368 goto abort;
369 }
370
371 if (inforec->info_version != INFO_VERSION) {
372 dev_err(component->dev,
373 "Unsupported version (%02d) of INFO record\r\n",
374 inforec->info_version);
375 ret = -EINVAL;
376 goto abort;
377 }
378
379 dev_dbg(component->dev, "Version v%02d INFO record found\r\n",
380 inforec->info_version);
381
382 /* Check it's a DSP file */
383 if (dsp != DEVICE_ID_WM0010) {
384 dev_err(component->dev, "Not a WM0010 firmware file.\r\n");
385 ret = -EINVAL;
386 goto abort;
387 }
388
389 /* Skip the info record as we don't need to send it */
390 offset += ((rec->length) + 8);
391 rec = (void *)&rec->data[rec->length];
392
393 while (offset < fw->size) {
394 dev_dbg(component->dev,
395 "Packet: command %d, data length = 0x%x\r\n",
396 rec->command, rec->length);
397 len = rec->length + 8;
398
399 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
400 if (!xfer) {
401 ret = -ENOMEM;
402 goto abort;
403 }
404
405 xfer->component = component;
406 list_add_tail(&xfer->list, &xfer_list);
407
408 out = kzalloc(len, GFP_KERNEL | GFP_DMA);
409 if (!out) {
410 ret = -ENOMEM;
411 goto abort1;
412 }
413 xfer->t.rx_buf = out;
414
415 img = kzalloc(len, GFP_KERNEL | GFP_DMA);
416 if (!img) {
417 ret = -ENOMEM;
418 goto abort1;
419 }
420 xfer->t.tx_buf = img;
421
422 byte_swap_64((u64 *)&rec->command, img, len);
423
424 spi_message_init(&xfer->m);
425 xfer->m.complete = wm0010_boot_xfer_complete;
426 xfer->m.context = xfer;
427 xfer->t.len = len;
428 xfer->t.bits_per_word = 8;
429
430 if (!wm0010->pll_running) {
431 xfer->t.speed_hz = wm0010->sysclk / 6;
432 } else {
433 xfer->t.speed_hz = wm0010->max_spi_freq;
434
435 if (wm0010->board_max_spi_speed &&
436 (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
437 xfer->t.speed_hz = wm0010->board_max_spi_speed;
438 }
439
440 /* Store max usable spi frequency for later use */
441 wm0010->max_spi_freq = xfer->t.speed_hz;
442
443 spi_message_add_tail(&xfer->t, &xfer->m);
444
445 offset += ((rec->length) + 8);
446 rec = (void *)&rec->data[rec->length];
447
448 if (offset >= fw->size) {
449 dev_dbg(component->dev, "All transfers scheduled\n");
450 xfer->done = &done;
451 }
452
453 ret = spi_async(spi, &xfer->m);
454 if (ret != 0) {
455 dev_err(component->dev, "Write failed: %d\n", ret);
456 goto abort1;
457 }
458
459 if (wm0010->boot_failed) {
460 dev_dbg(component->dev, "Boot fail!\n");
461 ret = -EINVAL;
462 goto abort1;
463 }
464 }
465
466 wait_for_completion(&done);
467
468 ret = 0;
469
470abort1:
471 while (!list_empty(&xfer_list)) {
472 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
473 list);
474 kfree(xfer->t.rx_buf);
475 kfree(xfer->t.tx_buf);
476 list_del(&xfer->list);
477 kfree(xfer);
478 }
479
480abort:
481 release_firmware(fw);
482 return ret;
483}
484
485static int wm0010_stage2_load(struct snd_soc_component *component)
486{
487 struct spi_device *spi = to_spi_device(component->dev);
488 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
489 const struct firmware *fw;
490 struct spi_message m;
491 struct spi_transfer t;
492 u32 *img;
493 u8 *out;
494 int i;
495 int ret = 0;
496
497 ret = request_firmware(&fw, "wm0010_stage2.bin", component->dev);
498 if (ret != 0) {
499 dev_err(component->dev, "Failed to request stage2 loader: %d\n",
500 ret);
501 return ret;
502 }
503
504 dev_dbg(component->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
505
506 /* Copy to local buffer first as vmalloc causes problems for dma */
507 img = kmemdup(&fw->data[0], fw->size, GFP_KERNEL | GFP_DMA);
508 if (!img) {
509 ret = -ENOMEM;
510 goto abort2;
511 }
512
513 out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA);
514 if (!out) {
515 ret = -ENOMEM;
516 goto abort1;
517 }
518
519 spi_message_init(&m);
520 memset(&t, 0, sizeof(t));
521 t.rx_buf = out;
522 t.tx_buf = img;
523 t.len = fw->size;
524 t.bits_per_word = 8;
525 t.speed_hz = wm0010->sysclk / 10;
526 spi_message_add_tail(&t, &m);
527
528 dev_dbg(component->dev, "Starting initial download at %dHz\n",
529 t.speed_hz);
530
531 ret = spi_sync(spi, &m);
532 if (ret != 0) {
533 dev_err(component->dev, "Initial download failed: %d\n", ret);
534 goto abort;
535 }
536
537 /* Look for errors from the boot ROM */
538 for (i = 0; i < fw->size; i++) {
539 if (out[i] != 0x55) {
540 dev_err(component->dev, "Boot ROM error: %x in %d\n",
541 out[i], i);
542 wm0010_mark_boot_failure(wm0010);
543 ret = -EBUSY;
544 goto abort;
545 }
546 }
547abort:
548 kfree(out);
549abort1:
550 kfree(img);
551abort2:
552 release_firmware(fw);
553
554 return ret;
555}
556
557static int wm0010_boot(struct snd_soc_component *component)
558{
559 struct spi_device *spi = to_spi_device(component->dev);
560 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
561 unsigned long flags;
562 int ret;
563 struct spi_message m;
564 struct spi_transfer t;
565 struct dfw_pllrec pll_rec;
566 u32 *p, len;
567 u64 *img_swap;
568 u8 *out;
569 int i;
570
571 spin_lock_irqsave(&wm0010->irq_lock, flags);
572 if (wm0010->state != WM0010_POWER_OFF)
573 dev_warn(wm0010->dev, "DSP already powered up!\n");
574 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
575
576 if (wm0010->sysclk > 26000000) {
577 dev_err(component->dev, "Max DSP clock frequency is 26MHz\n");
578 ret = -ECANCELED;
579 goto err;
580 }
581
582 mutex_lock(&wm0010->lock);
583 wm0010->pll_running = false;
584
585 dev_dbg(component->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
586
587 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
588 wm0010->core_supplies);
589 if (ret != 0) {
590 dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
591 ret);
592 mutex_unlock(&wm0010->lock);
593 goto err;
594 }
595
596 ret = regulator_enable(wm0010->dbvdd);
597 if (ret != 0) {
598 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
599 goto err_core;
600 }
601
602 /* Release reset */
603 gpiod_set_value_cansleep(wm0010->reset, 0);
604 spin_lock_irqsave(&wm0010->irq_lock, flags);
605 wm0010->state = WM0010_OUT_OF_RESET;
606 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
607
608 if (!wait_for_completion_timeout(&wm0010->boot_completion,
609 msecs_to_jiffies(20)))
610 dev_err(component->dev, "Failed to get interrupt from DSP\n");
611
612 spin_lock_irqsave(&wm0010->irq_lock, flags);
613 wm0010->state = WM0010_BOOTROM;
614 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
615
616 ret = wm0010_stage2_load(component);
617 if (ret)
618 goto abort;
619
620 if (!wait_for_completion_timeout(&wm0010->boot_completion,
621 msecs_to_jiffies(20)))
622 dev_err(component->dev, "Failed to get interrupt from DSP loader.\n");
623
624 spin_lock_irqsave(&wm0010->irq_lock, flags);
625 wm0010->state = WM0010_STAGE2;
626 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
627
628 /* Only initialise PLL if max_spi_freq initialised */
629 if (wm0010->max_spi_freq) {
630
631 /* Initialise a PLL record */
632 memset(&pll_rec, 0, sizeof(pll_rec));
633 pll_rec.command = DFW_CMD_PLL;
634 pll_rec.length = (sizeof(pll_rec) - 8);
635
636 /* On wm0010 only the CLKCTRL1 value is used */
637 pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
638
639 ret = -ENOMEM;
640 len = pll_rec.length + 8;
641 out = kzalloc(len, GFP_KERNEL | GFP_DMA);
642 if (!out)
643 goto abort;
644
645 img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA);
646 if (!img_swap)
647 goto abort_out;
648
649 /* We need to re-order for 0010 */
650 byte_swap_64((u64 *)&pll_rec, img_swap, len);
651
652 spi_message_init(&m);
653 memset(&t, 0, sizeof(t));
654 t.rx_buf = out;
655 t.tx_buf = img_swap;
656 t.len = len;
657 t.bits_per_word = 8;
658 t.speed_hz = wm0010->sysclk / 6;
659 spi_message_add_tail(&t, &m);
660
661 ret = spi_sync(spi, &m);
662 if (ret) {
663 dev_err(component->dev, "First PLL write failed: %d\n", ret);
664 goto abort_swap;
665 }
666
667 /* Use a second send of the message to get the return status */
668 ret = spi_sync(spi, &m);
669 if (ret) {
670 dev_err(component->dev, "Second PLL write failed: %d\n", ret);
671 goto abort_swap;
672 }
673
674 p = (u32 *)out;
675
676 /* Look for PLL active code from the DSP */
677 for (i = 0; i < len / 4; i++) {
678 if (*p == 0x0e00ed0f) {
679 dev_dbg(component->dev, "PLL packet received\n");
680 wm0010->pll_running = true;
681 break;
682 }
683 p++;
684 }
685
686 kfree(img_swap);
687 kfree(out);
688 } else
689 dev_dbg(component->dev, "Not enabling DSP PLL.");
690
691 ret = wm0010_firmware_load("wm0010.dfw", component);
692
693 if (ret != 0)
694 goto abort;
695
696 spin_lock_irqsave(&wm0010->irq_lock, flags);
697 wm0010->state = WM0010_FIRMWARE;
698 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
699
700 mutex_unlock(&wm0010->lock);
701
702 return 0;
703
704abort_swap:
705 kfree(img_swap);
706abort_out:
707 kfree(out);
708abort:
709 /* Put the chip back into reset */
710 wm0010_halt(component);
711 mutex_unlock(&wm0010->lock);
712 return ret;
713
714err_core:
715 mutex_unlock(&wm0010->lock);
716 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
717 wm0010->core_supplies);
718err:
719 return ret;
720}
721
722static int wm0010_set_bias_level(struct snd_soc_component *component,
723 enum snd_soc_bias_level level)
724{
725 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
726
727 switch (level) {
728 case SND_SOC_BIAS_ON:
729 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE)
730 wm0010_boot(component);
731 break;
732 case SND_SOC_BIAS_PREPARE:
733 break;
734 case SND_SOC_BIAS_STANDBY:
735 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {
736 mutex_lock(&wm0010->lock);
737 wm0010_halt(component);
738 mutex_unlock(&wm0010->lock);
739 }
740 break;
741 case SND_SOC_BIAS_OFF:
742 break;
743 }
744
745 return 0;
746}
747
748static int wm0010_set_sysclk(struct snd_soc_component *component, int source,
749 int clk_id, unsigned int freq, int dir)
750{
751 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
752 unsigned int i;
753
754 wm0010->sysclk = freq;
755
756 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
757 wm0010->max_spi_freq = 0;
758 } else {
759 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
760 if (freq >= pll_clock_map[i].max_sysclk) {
761 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
762 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
763 break;
764 }
765 }
766
767 return 0;
768}
769
770static int wm0010_probe(struct snd_soc_component *component);
771
772static const struct snd_soc_component_driver soc_component_dev_wm0010 = {
773 .probe = wm0010_probe,
774 .set_bias_level = wm0010_set_bias_level,
775 .set_sysclk = wm0010_set_sysclk,
776 .dapm_widgets = wm0010_dapm_widgets,
777 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets),
778 .dapm_routes = wm0010_dapm_routes,
779 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
780 .use_pmdown_time = 1,
781 .endianness = 1,
782};
783
784#define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
785#define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
786 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
787 SNDRV_PCM_FMTBIT_S32_LE)
788
789static struct snd_soc_dai_driver wm0010_dai[] = {
790 {
791 .name = "wm0010-sdi1",
792 .playback = {
793 .stream_name = "SDI1 Playback",
794 .channels_min = 1,
795 .channels_max = 2,
796 .rates = WM0010_RATES,
797 .formats = WM0010_FORMATS,
798 },
799 .capture = {
800 .stream_name = "SDI1 Capture",
801 .channels_min = 1,
802 .channels_max = 2,
803 .rates = WM0010_RATES,
804 .formats = WM0010_FORMATS,
805 },
806 },
807 {
808 .name = "wm0010-sdi2",
809 .playback = {
810 .stream_name = "SDI2 Playback",
811 .channels_min = 1,
812 .channels_max = 2,
813 .rates = WM0010_RATES,
814 .formats = WM0010_FORMATS,
815 },
816 .capture = {
817 .stream_name = "SDI2 Capture",
818 .channels_min = 1,
819 .channels_max = 2,
820 .rates = WM0010_RATES,
821 .formats = WM0010_FORMATS,
822 },
823 },
824};
825
826static irqreturn_t wm0010_irq(int irq, void *data)
827{
828 struct wm0010_priv *wm0010 = data;
829
830 switch (wm0010->state) {
831 case WM0010_OUT_OF_RESET:
832 case WM0010_BOOTROM:
833 case WM0010_STAGE2:
834 spin_lock(&wm0010->irq_lock);
835 complete(&wm0010->boot_completion);
836 spin_unlock(&wm0010->irq_lock);
837 return IRQ_HANDLED;
838 default:
839 return IRQ_NONE;
840 }
841
842 return IRQ_NONE;
843}
844
845static int wm0010_probe(struct snd_soc_component *component)
846{
847 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
848
849 wm0010->component = component;
850
851 return 0;
852}
853
854static int wm0010_spi_probe(struct spi_device *spi)
855{
856 int ret;
857 int trigger;
858 int irq;
859 struct wm0010_priv *wm0010;
860
861 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
862 GFP_KERNEL);
863 if (!wm0010)
864 return -ENOMEM;
865
866 mutex_init(&wm0010->lock);
867 spin_lock_init(&wm0010->irq_lock);
868
869 spi_set_drvdata(spi, wm0010);
870 wm0010->dev = &spi->dev;
871
872 if (dev_get_platdata(&spi->dev))
873 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
874 sizeof(wm0010->pdata));
875
876 init_completion(&wm0010->boot_completion);
877
878 wm0010->core_supplies[0].supply = "AVDD";
879 wm0010->core_supplies[1].supply = "DCVDD";
880 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
881 wm0010->core_supplies);
882 if (ret != 0) {
883 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
884 ret);
885 return ret;
886 }
887
888 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
889 if (IS_ERR(wm0010->dbvdd)) {
890 ret = PTR_ERR(wm0010->dbvdd);
891 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
892 return ret;
893 }
894
895 wm0010->reset = devm_gpiod_get(wm0010->dev, "reset", GPIOD_OUT_HIGH);
896 if (IS_ERR(wm0010->reset))
897 return dev_err_probe(wm0010->dev, PTR_ERR(wm0010->reset),
898 "could not get RESET GPIO\n");
899 gpiod_set_consumer_name(wm0010->reset, "wm0010 reset");
900
901 wm0010->state = WM0010_POWER_OFF;
902
903 irq = spi->irq;
904 if (wm0010->pdata.irq_flags)
905 trigger = wm0010->pdata.irq_flags;
906 else
907 trigger = IRQF_TRIGGER_FALLING;
908 trigger |= IRQF_ONESHOT;
909
910 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger,
911 "wm0010", wm0010);
912 if (ret) {
913 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
914 irq, ret);
915 return ret;
916 }
917 wm0010->irq = irq;
918
919 ret = irq_set_irq_wake(irq, 1);
920 if (ret) {
921 dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n",
922 irq, ret);
923 return ret;
924 }
925
926 if (spi->max_speed_hz)
927 wm0010->board_max_spi_speed = spi->max_speed_hz;
928 else
929 wm0010->board_max_spi_speed = 0;
930
931 ret = devm_snd_soc_register_component(&spi->dev,
932 &soc_component_dev_wm0010, wm0010_dai,
933 ARRAY_SIZE(wm0010_dai));
934 if (ret < 0)
935 return ret;
936
937 return 0;
938}
939
940static void wm0010_spi_remove(struct spi_device *spi)
941{
942 struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
943
944 gpiod_set_value_cansleep(wm0010->reset, 1);
945
946 irq_set_irq_wake(wm0010->irq, 0);
947
948 if (wm0010->irq)
949 free_irq(wm0010->irq, wm0010);
950}
951
952static struct spi_driver wm0010_spi_driver = {
953 .driver = {
954 .name = "wm0010",
955 },
956 .probe = wm0010_spi_probe,
957 .remove = wm0010_spi_remove,
958};
959
960module_spi_driver(wm0010_spi_driver);
961
962MODULE_DESCRIPTION("ASoC WM0010 driver");
963MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
964MODULE_LICENSE("GPL");
965
966MODULE_FIRMWARE("wm0010.dfw");
967MODULE_FIRMWARE("wm0010_stage2.bin");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * wm0010.c -- WM0010 DSP Driver
4 *
5 * Copyright 2012 Wolfson Microelectronics PLC.
6 *
7 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
9 * Scott Ling <sl@opensource.wolfsonmicro.com>
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/interrupt.h>
15#include <linux/irqreturn.h>
16#include <linux/init.h>
17#include <linux/spi/spi.h>
18#include <linux/firmware.h>
19#include <linux/delay.h>
20#include <linux/fs.h>
21#include <linux/gpio.h>
22#include <linux/regulator/consumer.h>
23#include <linux/mutex.h>
24#include <linux/workqueue.h>
25
26#include <sound/soc.h>
27#include <sound/wm0010.h>
28
29#define DEVICE_ID_WM0010 10
30
31/* We only support v1 of the .dfw INFO record */
32#define INFO_VERSION 1
33
34enum dfw_cmd {
35 DFW_CMD_FUSE = 0x01,
36 DFW_CMD_CODE_HDR,
37 DFW_CMD_CODE_DATA,
38 DFW_CMD_PLL,
39 DFW_CMD_INFO = 0xff
40};
41
42struct dfw_binrec {
43 u8 command;
44 u32 length:24;
45 u32 address;
46 uint8_t data[];
47} __packed;
48
49struct dfw_inforec {
50 u8 info_version;
51 u8 tool_major_version;
52 u8 tool_minor_version;
53 u8 dsp_target;
54};
55
56struct dfw_pllrec {
57 u8 command;
58 u32 length:24;
59 u32 address;
60 u32 clkctrl1;
61 u32 clkctrl2;
62 u32 clkctrl3;
63 u32 ldetctrl;
64 u32 uart_div;
65 u32 spi_div;
66} __packed;
67
68static struct pll_clock_map {
69 int max_sysclk;
70 int max_pll_spi_speed;
71 u32 pll_clkctrl1;
72} pll_clock_map[] = { /* Dividers */
73 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */
74 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */
75 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */
76 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */
77 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */
78 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */
79};
80
81enum wm0010_state {
82 WM0010_POWER_OFF,
83 WM0010_OUT_OF_RESET,
84 WM0010_BOOTROM,
85 WM0010_STAGE2,
86 WM0010_FIRMWARE,
87};
88
89struct wm0010_priv {
90 struct snd_soc_component *component;
91
92 struct mutex lock;
93 struct device *dev;
94
95 struct wm0010_pdata pdata;
96
97 int gpio_reset;
98 int gpio_reset_value;
99
100 struct regulator_bulk_data core_supplies[2];
101 struct regulator *dbvdd;
102
103 int sysclk;
104
105 enum wm0010_state state;
106 bool boot_failed;
107 bool ready;
108 bool pll_running;
109 int max_spi_freq;
110 int board_max_spi_speed;
111 u32 pll_clkctrl1;
112
113 spinlock_t irq_lock;
114 int irq;
115
116 struct completion boot_completion;
117};
118
119struct wm0010_spi_msg {
120 struct spi_message m;
121 struct spi_transfer t;
122 u8 *tx_buf;
123 u8 *rx_buf;
124 size_t len;
125};
126
127static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
128SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
129};
130
131static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
132 { "SDI2 Capture", NULL, "SDI1 Playback" },
133 { "SDI1 Capture", NULL, "SDI2 Playback" },
134
135 { "SDI1 Capture", NULL, "CLKIN" },
136 { "SDI2 Capture", NULL, "CLKIN" },
137 { "SDI1 Playback", NULL, "CLKIN" },
138 { "SDI2 Playback", NULL, "CLKIN" },
139};
140
141static const char *wm0010_state_to_str(enum wm0010_state state)
142{
143 static const char * const state_to_str[] = {
144 "Power off",
145 "Out of reset",
146 "Boot ROM",
147 "Stage2",
148 "Firmware"
149 };
150
151 if (state < 0 || state >= ARRAY_SIZE(state_to_str))
152 return "null";
153 return state_to_str[state];
154}
155
156/* Called with wm0010->lock held */
157static void wm0010_halt(struct snd_soc_component *component)
158{
159 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
160 unsigned long flags;
161 enum wm0010_state state;
162
163 /* Fetch the wm0010 state */
164 spin_lock_irqsave(&wm0010->irq_lock, flags);
165 state = wm0010->state;
166 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
167
168 switch (state) {
169 case WM0010_POWER_OFF:
170 /* If there's nothing to do, bail out */
171 return;
172 case WM0010_OUT_OF_RESET:
173 case WM0010_BOOTROM:
174 case WM0010_STAGE2:
175 case WM0010_FIRMWARE:
176 /* Remember to put chip back into reset */
177 gpio_set_value_cansleep(wm0010->gpio_reset,
178 wm0010->gpio_reset_value);
179 /* Disable the regulators */
180 regulator_disable(wm0010->dbvdd);
181 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
182 wm0010->core_supplies);
183 break;
184 }
185
186 spin_lock_irqsave(&wm0010->irq_lock, flags);
187 wm0010->state = WM0010_POWER_OFF;
188 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
189}
190
191struct wm0010_boot_xfer {
192 struct list_head list;
193 struct snd_soc_component *component;
194 struct completion *done;
195 struct spi_message m;
196 struct spi_transfer t;
197};
198
199/* Called with wm0010->lock held */
200static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
201{
202 enum wm0010_state state;
203 unsigned long flags;
204
205 spin_lock_irqsave(&wm0010->irq_lock, flags);
206 state = wm0010->state;
207 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
208
209 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
210 wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
211
212 wm0010->boot_failed = true;
213}
214
215static void wm0010_boot_xfer_complete(void *data)
216{
217 struct wm0010_boot_xfer *xfer = data;
218 struct snd_soc_component *component = xfer->component;
219 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
220 u32 *out32 = xfer->t.rx_buf;
221 int i;
222
223 if (xfer->m.status != 0) {
224 dev_err(component->dev, "SPI transfer failed: %d\n",
225 xfer->m.status);
226 wm0010_mark_boot_failure(wm0010);
227 if (xfer->done)
228 complete(xfer->done);
229 return;
230 }
231
232 for (i = 0; i < xfer->t.len / 4; i++) {
233 dev_dbg(component->dev, "%d: %04x\n", i, out32[i]);
234
235 switch (be32_to_cpu(out32[i])) {
236 case 0xe0e0e0e0:
237 dev_err(component->dev,
238 "%d: ROM error reported in stage 2\n", i);
239 wm0010_mark_boot_failure(wm0010);
240 break;
241
242 case 0x55555555:
243 if (wm0010->state < WM0010_STAGE2)
244 break;
245 dev_err(component->dev,
246 "%d: ROM bootloader running in stage 2\n", i);
247 wm0010_mark_boot_failure(wm0010);
248 break;
249
250 case 0x0fed0000:
251 dev_dbg(component->dev, "Stage2 loader running\n");
252 break;
253
254 case 0x0fed0007:
255 dev_dbg(component->dev, "CODE_HDR packet received\n");
256 break;
257
258 case 0x0fed0008:
259 dev_dbg(component->dev, "CODE_DATA packet received\n");
260 break;
261
262 case 0x0fed0009:
263 dev_dbg(component->dev, "Download complete\n");
264 break;
265
266 case 0x0fed000c:
267 dev_dbg(component->dev, "Application start\n");
268 break;
269
270 case 0x0fed000e:
271 dev_dbg(component->dev, "PLL packet received\n");
272 wm0010->pll_running = true;
273 break;
274
275 case 0x0fed0025:
276 dev_err(component->dev, "Device reports image too long\n");
277 wm0010_mark_boot_failure(wm0010);
278 break;
279
280 case 0x0fed002c:
281 dev_err(component->dev, "Device reports bad SPI packet\n");
282 wm0010_mark_boot_failure(wm0010);
283 break;
284
285 case 0x0fed0031:
286 dev_err(component->dev, "Device reports SPI read overflow\n");
287 wm0010_mark_boot_failure(wm0010);
288 break;
289
290 case 0x0fed0032:
291 dev_err(component->dev, "Device reports SPI underclock\n");
292 wm0010_mark_boot_failure(wm0010);
293 break;
294
295 case 0x0fed0033:
296 dev_err(component->dev, "Device reports bad header packet\n");
297 wm0010_mark_boot_failure(wm0010);
298 break;
299
300 case 0x0fed0034:
301 dev_err(component->dev, "Device reports invalid packet type\n");
302 wm0010_mark_boot_failure(wm0010);
303 break;
304
305 case 0x0fed0035:
306 dev_err(component->dev, "Device reports data before header error\n");
307 wm0010_mark_boot_failure(wm0010);
308 break;
309
310 case 0x0fed0038:
311 dev_err(component->dev, "Device reports invalid PLL packet\n");
312 break;
313
314 case 0x0fed003a:
315 dev_err(component->dev, "Device reports packet alignment error\n");
316 wm0010_mark_boot_failure(wm0010);
317 break;
318
319 default:
320 dev_err(component->dev, "Unrecognised return 0x%x\n",
321 be32_to_cpu(out32[i]));
322 wm0010_mark_boot_failure(wm0010);
323 break;
324 }
325
326 if (wm0010->boot_failed)
327 break;
328 }
329
330 if (xfer->done)
331 complete(xfer->done);
332}
333
334static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
335{
336 int i;
337
338 for (i = 0; i < len / 8; i++)
339 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
340}
341
342static int wm0010_firmware_load(const char *name, struct snd_soc_component *component)
343{
344 struct spi_device *spi = to_spi_device(component->dev);
345 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
346 struct list_head xfer_list;
347 struct wm0010_boot_xfer *xfer;
348 int ret;
349 struct completion done;
350 const struct firmware *fw;
351 const struct dfw_binrec *rec;
352 const struct dfw_inforec *inforec;
353 u64 *img;
354 u8 *out, dsp;
355 u32 len, offset;
356
357 INIT_LIST_HEAD(&xfer_list);
358
359 ret = request_firmware(&fw, name, component->dev);
360 if (ret != 0) {
361 dev_err(component->dev, "Failed to request application(%s): %d\n",
362 name, ret);
363 return ret;
364 }
365
366 rec = (const struct dfw_binrec *)fw->data;
367 inforec = (const struct dfw_inforec *)rec->data;
368 offset = 0;
369 dsp = inforec->dsp_target;
370 wm0010->boot_failed = false;
371 if (WARN_ON(!list_empty(&xfer_list)))
372 return -EINVAL;
373 init_completion(&done);
374
375 /* First record should be INFO */
376 if (rec->command != DFW_CMD_INFO) {
377 dev_err(component->dev, "First record not INFO\r\n");
378 ret = -EINVAL;
379 goto abort;
380 }
381
382 if (inforec->info_version != INFO_VERSION) {
383 dev_err(component->dev,
384 "Unsupported version (%02d) of INFO record\r\n",
385 inforec->info_version);
386 ret = -EINVAL;
387 goto abort;
388 }
389
390 dev_dbg(component->dev, "Version v%02d INFO record found\r\n",
391 inforec->info_version);
392
393 /* Check it's a DSP file */
394 if (dsp != DEVICE_ID_WM0010) {
395 dev_err(component->dev, "Not a WM0010 firmware file.\r\n");
396 ret = -EINVAL;
397 goto abort;
398 }
399
400 /* Skip the info record as we don't need to send it */
401 offset += ((rec->length) + 8);
402 rec = (void *)&rec->data[rec->length];
403
404 while (offset < fw->size) {
405 dev_dbg(component->dev,
406 "Packet: command %d, data length = 0x%x\r\n",
407 rec->command, rec->length);
408 len = rec->length + 8;
409
410 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
411 if (!xfer) {
412 ret = -ENOMEM;
413 goto abort;
414 }
415
416 xfer->component = component;
417 list_add_tail(&xfer->list, &xfer_list);
418
419 out = kzalloc(len, GFP_KERNEL | GFP_DMA);
420 if (!out) {
421 ret = -ENOMEM;
422 goto abort1;
423 }
424 xfer->t.rx_buf = out;
425
426 img = kzalloc(len, GFP_KERNEL | GFP_DMA);
427 if (!img) {
428 ret = -ENOMEM;
429 goto abort1;
430 }
431 xfer->t.tx_buf = img;
432
433 byte_swap_64((u64 *)&rec->command, img, len);
434
435 spi_message_init(&xfer->m);
436 xfer->m.complete = wm0010_boot_xfer_complete;
437 xfer->m.context = xfer;
438 xfer->t.len = len;
439 xfer->t.bits_per_word = 8;
440
441 if (!wm0010->pll_running) {
442 xfer->t.speed_hz = wm0010->sysclk / 6;
443 } else {
444 xfer->t.speed_hz = wm0010->max_spi_freq;
445
446 if (wm0010->board_max_spi_speed &&
447 (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
448 xfer->t.speed_hz = wm0010->board_max_spi_speed;
449 }
450
451 /* Store max usable spi frequency for later use */
452 wm0010->max_spi_freq = xfer->t.speed_hz;
453
454 spi_message_add_tail(&xfer->t, &xfer->m);
455
456 offset += ((rec->length) + 8);
457 rec = (void *)&rec->data[rec->length];
458
459 if (offset >= fw->size) {
460 dev_dbg(component->dev, "All transfers scheduled\n");
461 xfer->done = &done;
462 }
463
464 ret = spi_async(spi, &xfer->m);
465 if (ret != 0) {
466 dev_err(component->dev, "Write failed: %d\n", ret);
467 goto abort1;
468 }
469
470 if (wm0010->boot_failed) {
471 dev_dbg(component->dev, "Boot fail!\n");
472 ret = -EINVAL;
473 goto abort1;
474 }
475 }
476
477 wait_for_completion(&done);
478
479 ret = 0;
480
481abort1:
482 while (!list_empty(&xfer_list)) {
483 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
484 list);
485 kfree(xfer->t.rx_buf);
486 kfree(xfer->t.tx_buf);
487 list_del(&xfer->list);
488 kfree(xfer);
489 }
490
491abort:
492 release_firmware(fw);
493 return ret;
494}
495
496static int wm0010_stage2_load(struct snd_soc_component *component)
497{
498 struct spi_device *spi = to_spi_device(component->dev);
499 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
500 const struct firmware *fw;
501 struct spi_message m;
502 struct spi_transfer t;
503 u32 *img;
504 u8 *out;
505 int i;
506 int ret = 0;
507
508 ret = request_firmware(&fw, "wm0010_stage2.bin", component->dev);
509 if (ret != 0) {
510 dev_err(component->dev, "Failed to request stage2 loader: %d\n",
511 ret);
512 return ret;
513 }
514
515 dev_dbg(component->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
516
517 /* Copy to local buffer first as vmalloc causes problems for dma */
518 img = kmemdup(&fw->data[0], fw->size, GFP_KERNEL | GFP_DMA);
519 if (!img) {
520 ret = -ENOMEM;
521 goto abort2;
522 }
523
524 out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA);
525 if (!out) {
526 ret = -ENOMEM;
527 goto abort1;
528 }
529
530 spi_message_init(&m);
531 memset(&t, 0, sizeof(t));
532 t.rx_buf = out;
533 t.tx_buf = img;
534 t.len = fw->size;
535 t.bits_per_word = 8;
536 t.speed_hz = wm0010->sysclk / 10;
537 spi_message_add_tail(&t, &m);
538
539 dev_dbg(component->dev, "Starting initial download at %dHz\n",
540 t.speed_hz);
541
542 ret = spi_sync(spi, &m);
543 if (ret != 0) {
544 dev_err(component->dev, "Initial download failed: %d\n", ret);
545 goto abort;
546 }
547
548 /* Look for errors from the boot ROM */
549 for (i = 0; i < fw->size; i++) {
550 if (out[i] != 0x55) {
551 dev_err(component->dev, "Boot ROM error: %x in %d\n",
552 out[i], i);
553 wm0010_mark_boot_failure(wm0010);
554 ret = -EBUSY;
555 goto abort;
556 }
557 }
558abort:
559 kfree(out);
560abort1:
561 kfree(img);
562abort2:
563 release_firmware(fw);
564
565 return ret;
566}
567
568static int wm0010_boot(struct snd_soc_component *component)
569{
570 struct spi_device *spi = to_spi_device(component->dev);
571 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
572 unsigned long flags;
573 int ret;
574 struct spi_message m;
575 struct spi_transfer t;
576 struct dfw_pllrec pll_rec;
577 u32 *p, len;
578 u64 *img_swap;
579 u8 *out;
580 int i;
581
582 spin_lock_irqsave(&wm0010->irq_lock, flags);
583 if (wm0010->state != WM0010_POWER_OFF)
584 dev_warn(wm0010->dev, "DSP already powered up!\n");
585 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
586
587 if (wm0010->sysclk > 26000000) {
588 dev_err(component->dev, "Max DSP clock frequency is 26MHz\n");
589 ret = -ECANCELED;
590 goto err;
591 }
592
593 mutex_lock(&wm0010->lock);
594 wm0010->pll_running = false;
595
596 dev_dbg(component->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
597
598 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
599 wm0010->core_supplies);
600 if (ret != 0) {
601 dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
602 ret);
603 mutex_unlock(&wm0010->lock);
604 goto err;
605 }
606
607 ret = regulator_enable(wm0010->dbvdd);
608 if (ret != 0) {
609 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
610 goto err_core;
611 }
612
613 /* Release reset */
614 gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value);
615 spin_lock_irqsave(&wm0010->irq_lock, flags);
616 wm0010->state = WM0010_OUT_OF_RESET;
617 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
618
619 if (!wait_for_completion_timeout(&wm0010->boot_completion,
620 msecs_to_jiffies(20)))
621 dev_err(component->dev, "Failed to get interrupt from DSP\n");
622
623 spin_lock_irqsave(&wm0010->irq_lock, flags);
624 wm0010->state = WM0010_BOOTROM;
625 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
626
627 ret = wm0010_stage2_load(component);
628 if (ret)
629 goto abort;
630
631 if (!wait_for_completion_timeout(&wm0010->boot_completion,
632 msecs_to_jiffies(20)))
633 dev_err(component->dev, "Failed to get interrupt from DSP loader.\n");
634
635 spin_lock_irqsave(&wm0010->irq_lock, flags);
636 wm0010->state = WM0010_STAGE2;
637 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
638
639 /* Only initialise PLL if max_spi_freq initialised */
640 if (wm0010->max_spi_freq) {
641
642 /* Initialise a PLL record */
643 memset(&pll_rec, 0, sizeof(pll_rec));
644 pll_rec.command = DFW_CMD_PLL;
645 pll_rec.length = (sizeof(pll_rec) - 8);
646
647 /* On wm0010 only the CLKCTRL1 value is used */
648 pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
649
650 ret = -ENOMEM;
651 len = pll_rec.length + 8;
652 out = kzalloc(len, GFP_KERNEL | GFP_DMA);
653 if (!out)
654 goto abort;
655
656 img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA);
657 if (!img_swap)
658 goto abort_out;
659
660 /* We need to re-order for 0010 */
661 byte_swap_64((u64 *)&pll_rec, img_swap, len);
662
663 spi_message_init(&m);
664 memset(&t, 0, sizeof(t));
665 t.rx_buf = out;
666 t.tx_buf = img_swap;
667 t.len = len;
668 t.bits_per_word = 8;
669 t.speed_hz = wm0010->sysclk / 6;
670 spi_message_add_tail(&t, &m);
671
672 ret = spi_sync(spi, &m);
673 if (ret) {
674 dev_err(component->dev, "First PLL write failed: %d\n", ret);
675 goto abort_swap;
676 }
677
678 /* Use a second send of the message to get the return status */
679 ret = spi_sync(spi, &m);
680 if (ret) {
681 dev_err(component->dev, "Second PLL write failed: %d\n", ret);
682 goto abort_swap;
683 }
684
685 p = (u32 *)out;
686
687 /* Look for PLL active code from the DSP */
688 for (i = 0; i < len / 4; i++) {
689 if (*p == 0x0e00ed0f) {
690 dev_dbg(component->dev, "PLL packet received\n");
691 wm0010->pll_running = true;
692 break;
693 }
694 p++;
695 }
696
697 kfree(img_swap);
698 kfree(out);
699 } else
700 dev_dbg(component->dev, "Not enabling DSP PLL.");
701
702 ret = wm0010_firmware_load("wm0010.dfw", component);
703
704 if (ret != 0)
705 goto abort;
706
707 spin_lock_irqsave(&wm0010->irq_lock, flags);
708 wm0010->state = WM0010_FIRMWARE;
709 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
710
711 mutex_unlock(&wm0010->lock);
712
713 return 0;
714
715abort_swap:
716 kfree(img_swap);
717abort_out:
718 kfree(out);
719abort:
720 /* Put the chip back into reset */
721 wm0010_halt(component);
722 mutex_unlock(&wm0010->lock);
723 return ret;
724
725err_core:
726 mutex_unlock(&wm0010->lock);
727 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
728 wm0010->core_supplies);
729err:
730 return ret;
731}
732
733static int wm0010_set_bias_level(struct snd_soc_component *component,
734 enum snd_soc_bias_level level)
735{
736 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
737
738 switch (level) {
739 case SND_SOC_BIAS_ON:
740 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE)
741 wm0010_boot(component);
742 break;
743 case SND_SOC_BIAS_PREPARE:
744 break;
745 case SND_SOC_BIAS_STANDBY:
746 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {
747 mutex_lock(&wm0010->lock);
748 wm0010_halt(component);
749 mutex_unlock(&wm0010->lock);
750 }
751 break;
752 case SND_SOC_BIAS_OFF:
753 break;
754 }
755
756 return 0;
757}
758
759static int wm0010_set_sysclk(struct snd_soc_component *component, int source,
760 int clk_id, unsigned int freq, int dir)
761{
762 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
763 unsigned int i;
764
765 wm0010->sysclk = freq;
766
767 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
768 wm0010->max_spi_freq = 0;
769 } else {
770 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
771 if (freq >= pll_clock_map[i].max_sysclk) {
772 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
773 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
774 break;
775 }
776 }
777
778 return 0;
779}
780
781static int wm0010_probe(struct snd_soc_component *component);
782
783static const struct snd_soc_component_driver soc_component_dev_wm0010 = {
784 .probe = wm0010_probe,
785 .set_bias_level = wm0010_set_bias_level,
786 .set_sysclk = wm0010_set_sysclk,
787 .dapm_widgets = wm0010_dapm_widgets,
788 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets),
789 .dapm_routes = wm0010_dapm_routes,
790 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
791 .use_pmdown_time = 1,
792 .endianness = 1,
793 .non_legacy_dai_naming = 1,
794};
795
796#define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
797#define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
798 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
799 SNDRV_PCM_FMTBIT_S32_LE)
800
801static struct snd_soc_dai_driver wm0010_dai[] = {
802 {
803 .name = "wm0010-sdi1",
804 .playback = {
805 .stream_name = "SDI1 Playback",
806 .channels_min = 1,
807 .channels_max = 2,
808 .rates = WM0010_RATES,
809 .formats = WM0010_FORMATS,
810 },
811 .capture = {
812 .stream_name = "SDI1 Capture",
813 .channels_min = 1,
814 .channels_max = 2,
815 .rates = WM0010_RATES,
816 .formats = WM0010_FORMATS,
817 },
818 },
819 {
820 .name = "wm0010-sdi2",
821 .playback = {
822 .stream_name = "SDI2 Playback",
823 .channels_min = 1,
824 .channels_max = 2,
825 .rates = WM0010_RATES,
826 .formats = WM0010_FORMATS,
827 },
828 .capture = {
829 .stream_name = "SDI2 Capture",
830 .channels_min = 1,
831 .channels_max = 2,
832 .rates = WM0010_RATES,
833 .formats = WM0010_FORMATS,
834 },
835 },
836};
837
838static irqreturn_t wm0010_irq(int irq, void *data)
839{
840 struct wm0010_priv *wm0010 = data;
841
842 switch (wm0010->state) {
843 case WM0010_OUT_OF_RESET:
844 case WM0010_BOOTROM:
845 case WM0010_STAGE2:
846 spin_lock(&wm0010->irq_lock);
847 complete(&wm0010->boot_completion);
848 spin_unlock(&wm0010->irq_lock);
849 return IRQ_HANDLED;
850 default:
851 return IRQ_NONE;
852 }
853
854 return IRQ_NONE;
855}
856
857static int wm0010_probe(struct snd_soc_component *component)
858{
859 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
860
861 wm0010->component = component;
862
863 return 0;
864}
865
866static int wm0010_spi_probe(struct spi_device *spi)
867{
868 unsigned long gpio_flags;
869 int ret;
870 int trigger;
871 int irq;
872 struct wm0010_priv *wm0010;
873
874 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
875 GFP_KERNEL);
876 if (!wm0010)
877 return -ENOMEM;
878
879 mutex_init(&wm0010->lock);
880 spin_lock_init(&wm0010->irq_lock);
881
882 spi_set_drvdata(spi, wm0010);
883 wm0010->dev = &spi->dev;
884
885 if (dev_get_platdata(&spi->dev))
886 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
887 sizeof(wm0010->pdata));
888
889 init_completion(&wm0010->boot_completion);
890
891 wm0010->core_supplies[0].supply = "AVDD";
892 wm0010->core_supplies[1].supply = "DCVDD";
893 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
894 wm0010->core_supplies);
895 if (ret != 0) {
896 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
897 ret);
898 return ret;
899 }
900
901 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
902 if (IS_ERR(wm0010->dbvdd)) {
903 ret = PTR_ERR(wm0010->dbvdd);
904 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
905 return ret;
906 }
907
908 if (wm0010->pdata.gpio_reset) {
909 wm0010->gpio_reset = wm0010->pdata.gpio_reset;
910
911 if (wm0010->pdata.reset_active_high)
912 wm0010->gpio_reset_value = 1;
913 else
914 wm0010->gpio_reset_value = 0;
915
916 if (wm0010->gpio_reset_value)
917 gpio_flags = GPIOF_OUT_INIT_HIGH;
918 else
919 gpio_flags = GPIOF_OUT_INIT_LOW;
920
921 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
922 gpio_flags, "wm0010 reset");
923 if (ret < 0) {
924 dev_err(wm0010->dev,
925 "Failed to request GPIO for DSP reset: %d\n",
926 ret);
927 return ret;
928 }
929 } else {
930 dev_err(wm0010->dev, "No reset GPIO configured\n");
931 return -EINVAL;
932 }
933
934 wm0010->state = WM0010_POWER_OFF;
935
936 irq = spi->irq;
937 if (wm0010->pdata.irq_flags)
938 trigger = wm0010->pdata.irq_flags;
939 else
940 trigger = IRQF_TRIGGER_FALLING;
941 trigger |= IRQF_ONESHOT;
942
943 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger,
944 "wm0010", wm0010);
945 if (ret) {
946 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
947 irq, ret);
948 return ret;
949 }
950 wm0010->irq = irq;
951
952 ret = irq_set_irq_wake(irq, 1);
953 if (ret) {
954 dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n",
955 irq, ret);
956 return ret;
957 }
958
959 if (spi->max_speed_hz)
960 wm0010->board_max_spi_speed = spi->max_speed_hz;
961 else
962 wm0010->board_max_spi_speed = 0;
963
964 ret = devm_snd_soc_register_component(&spi->dev,
965 &soc_component_dev_wm0010, wm0010_dai,
966 ARRAY_SIZE(wm0010_dai));
967 if (ret < 0)
968 return ret;
969
970 return 0;
971}
972
973static int wm0010_spi_remove(struct spi_device *spi)
974{
975 struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
976
977 gpio_set_value_cansleep(wm0010->gpio_reset,
978 wm0010->gpio_reset_value);
979
980 irq_set_irq_wake(wm0010->irq, 0);
981
982 if (wm0010->irq)
983 free_irq(wm0010->irq, wm0010);
984
985 return 0;
986}
987
988static struct spi_driver wm0010_spi_driver = {
989 .driver = {
990 .name = "wm0010",
991 },
992 .probe = wm0010_spi_probe,
993 .remove = wm0010_spi_remove,
994};
995
996module_spi_driver(wm0010_spi_driver);
997
998MODULE_DESCRIPTION("ASoC WM0010 driver");
999MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1000MODULE_LICENSE("GPL");