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1/* SPDX-License-Identifier: GPL-2.0-or-later
2 * sma1307.h -- sma1307 ALSA SoC Audio driver
3 *
4 * Copyright 2024 Iron Device Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef _SMA1307_H
12#define _SMA1307_H
13
14#include <sound/soc.h>
15
16enum sma1307_fault {
17 SMA1307_FAULT_OT1,
18 SMA1307_FAULT_OT2,
19 SMA1307_FAULT_UVLO,
20 SMA1307_FAULT_OVP_BST,
21 SMA1307_FAULT_OCP_SPK,
22 SMA1307_FAULT_OCP_BST,
23 SMA1307_FAULT_CLK
24};
25
26enum sma1307_mode {
27 SMA1307_MONO_MODE,
28 SMA1307_LEFT_MODE,
29 SMA1307_RIGHT_MODE,
30};
31
32enum sma1307_sdo_mode {
33 SMA1307_OUT_DATA_ONE_48K,
34 SMA1307_OUT_DATA_TWO_48K,
35 SMA1307_OUT_DATA_TWO_24K,
36 SMA1307_OUT_CLK_PLL,
37 SMA1307_OUT_CLK_OSC
38};
39
40enum sma1307_sdo_source {
41 SMA1307_OUT_DISABLE,
42 SMA1307_OUT_FORMAT_C,
43 SMA1307_OUT_MIXER_OUT,
44 SMA1307_OUT_AFTER_DSP,
45 SMA1307_OUT_VRMS2_AVG,
46 SMA1307_OUT_BATTERY,
47 SMA1307_OUT_TEMP,
48 SMA1307_OUT_AFTER_DELAY
49};
50
51struct sma1307_setting_file {
52 bool status;
53 char *header;
54 int *def;
55 int *mode_set[5];
56 int checksum;
57 int num_mode;
58 size_t header_size;
59 size_t def_size;
60 size_t mode_size;
61};
62
63#define SMA1307_I2C_ADDR_00 0x1e
64#define SMA1307_I2C_ADDR_01 0x3e
65#define SMA1307_I2C_ADDR_10 0x5e
66#define SMA1307_I2C_ADDR_11 0x7e
67
68#define DEVICE_NAME_SMA1307A "sma1307a"
69#define DEVICE_NAME_SMA1307AQ "sma1307aq"
70
71#define SMA1307_EXTERNAL_CLOCK_19_2 0x00
72#define SMA1307_EXTERNAL_CLOCK_24_576 0x01
73#define SMA1307_PLL_CLKIN_MCLK 0x02
74#define SMA1307_PLL_CLKIN_BCLK 0x03
75
76#define SMA1307_OFFSET_DEFAULT_MODE 0x00
77#define SMA1307_OFFSET_BURNING_MODE 0x01
78
79#define SMA1307_SETTING_HEADER_SIZE 0x08
80#define SMA1307_SETTING_DEFAULT_SIZE 0xC0
81
82#define SMA1307_DEFAULT_SET 0x00
83#define SMA1307_BINARY_FILE_SET 0x01
84
85/* Controls Name */
86#define SMA1307_REG_CTRL_NAME "Register Byte Control"
87#define SMA1307_VOL_CTRL_NAME "Speaker Volume"
88#define SMA1307_FORCE_MUTE_CTRL_NAME "Force Mute Switch"
89#define SMA1307_TDM_RX0_POS_NAME "TDM RX Slot0 Position"
90#define SMA1307_TDM_RX1_POS_NAME "TDM RX Slot1 Position"
91#define SMA1307_TDM_TX0_POS_NAME "TDM TX Slot0 Position"
92#define SMA1307_TDM_TX1_POS_NAME "TDM TX Slot1 Position"
93#define SMA1307_OT1_SW_PROT_CTRL_NAME "OT1 SW Protection Switch"
94#define SMA1307_RESET_CTRL_NAME "Reset Switch"
95#define SMA1307_CHECK_FAULT_STATUS_NAME "Check Fault Status"
96#define SMA1307_CHECK_FAULT_PERIOD_NAME "Check Fault Period"
97
98/* DAPM Name */
99#define SMA1307_AIF_IN_NAME "AIF IN Source"
100#define SMA1307_AIF_OUT0_NAME "AIF OUT0 Source"
101#define SMA1307_AIF_OUT1_NAME "AIF OUT1 Source"
102
103/*
104 * SMA1307 Register Definition
105 */
106
107/* SMA1307 Register Addresses */
108#define SMA1307_00_SYSTEM_CTRL 0x00
109#define SMA1307_01_INPUT_CTRL1 0x01
110#define SMA1307_02_BROWN_OUT_PROT1 0x02
111#define SMA1307_03_BROWN_OUT_PROT2 0x03
112#define SMA1307_04_BROWN_OUT_PROT3 0x04
113#define SMA1307_05_BROWN_OUT_PROT8 0x05
114#define SMA1307_06_BROWN_OUT_PROT9 0x06
115#define SMA1307_07_BROWN_OUT_PROT10 0x07
116#define SMA1307_08_BROWN_OUT_PROT11 0x08
117#define SMA1307_09_OUTPUT_CTRL 0x09
118#define SMA1307_0A_SPK_VOL 0x0A
119#define SMA1307_0B_BST_TEST 0x0B
120#define SMA1307_0C_BOOST_CTRL8 0x0C
121#define SMA1307_0D_SPK_TEST 0x0D
122#define SMA1307_0E_MUTE_VOL_CTRL 0x0E
123#define SMA1307_0F_VBAT_TEMP_SENSING 0x0F
124
125#define SMA1307_10_SYSTEM_CTRL1 0x10
126#define SMA1307_11_SYSTEM_CTRL2 0x11
127#define SMA1307_12_SYSTEM_CTRL3 0x12
128#define SMA1307_13_DELAY 0x13
129#define SMA1307_14_MODULATOR 0x14
130#define SMA1307_15_BASS_SPK1 0x15
131#define SMA1307_16_BASS_SPK2 0x16
132#define SMA1307_17_BASS_SPK3 0x17
133#define SMA1307_18_BASS_SPK4 0x18
134#define SMA1307_19_BASS_SPK5 0x19
135#define SMA1307_1A_BASS_SPK6 0x1A
136#define SMA1307_1B_BASS_SPK7 0x1B
137#define SMA1307_1C_BROWN_OUT_PROT20 0x1C
138#define SMA1307_1D_BROWN_OUT_PROT0 0x1D
139#define SMA1307_1E_TONE_GENERATOR 0x1E
140#define SMA1307_1F_TONE_FINE_VOLUME 0x1F
141
142#define SMA1307_22_COMP_HYS_SEL 0x22
143#define SMA1307_23_COMPLIM1 0x23
144#define SMA1307_24_COMPLIM2 0x24
145#define SMA1307_25_COMPLIM3 0x25
146#define SMA1307_26_COMPLIM4 0x26
147#define SMA1307_27_BROWN_OUT_PROT4 0x27
148#define SMA1307_28_BROWN_OUT_PROT5 0x28
149#define SMA1307_29_BROWN_OUT_PROT12 0x29
150#define SMA1307_2A_BROWN_OUT_PROT13 0x2A
151#define SMA1307_2B_BROWN_OUT_PROT14 0x2B
152#define SMA1307_2C_BROWN_OUT_PROT15 0x2C
153#define SMA1307_2D_BROWN_OUT_PROT6 0x2D
154#define SMA1307_2E_BROWN_OUT_PROT7 0x2E
155#define SMA1307_2F_BROWN_OUT_PROT16 0x2F
156
157#define SMA1307_30_BROWN_OUT_PROT17 0x30
158#define SMA1307_31_BROWN_OUT_PROT18 0x31
159#define SMA1307_32_BROWN_OUT_PROT19 0x32
160#define SMA1307_34_OCP_SPK 0x34
161#define SMA1307_35_FDPEC_CTRL0 0x35
162#define SMA1307_36_PROTECTION 0x36
163#define SMA1307_37_SLOPECTRL 0x37
164#define SMA1307_38_POWER_METER 0x38
165#define SMA1307_39_PMT_NZ_VAL 0x39
166#define SMA1307_3B_TEST1 0x3B
167#define SMA1307_3C_TEST2 0x3C
168#define SMA1307_3D_TEST3 0x3D
169#define SMA1307_3E_IDLE_MODE_CTRL 0x3E
170#define SMA1307_3F_ATEST2 0x3F
171#define SMA1307_8B_PLL_POST_N 0x8B
172#define SMA1307_8C_PLL_N 0x8C
173#define SMA1307_8D_PLL_A_SETTING 0x8D
174#define SMA1307_8E_PLL_P_CP 0x8E
175#define SMA1307_8F_ANALOG_TEST 0x8F
176
177#define SMA1307_90_CRESTLIM1 0x90
178#define SMA1307_91_CRESTLIM2 0x91
179#define SMA1307_92_FDPEC_CTRL1 0x92
180#define SMA1307_93_INT_CTRL 0x93
181#define SMA1307_94_BOOST_CTRL9 0x94
182#define SMA1307_95_BOOST_CTRL10 0x95
183#define SMA1307_96_BOOST_CTRL11 0x96
184#define SMA1307_97_OTP_TRM0 0x97
185#define SMA1307_98_OTP_TRM1 0x98
186#define SMA1307_99_OTP_TRM2 0x99
187#define SMA1307_9A_OTP_TRM3 0x9A
188
189#define SMA1307_A0_PAD_CTRL0 0xA0
190#define SMA1307_A1_PAD_CTRL1 0xA1
191#define SMA1307_A2_TOP_MAN1 0xA2
192#define SMA1307_A3_TOP_MAN2 0xA3
193#define SMA1307_A4_TOP_MAN3 0xA4
194#define SMA1307_A5_TDM1 0xA5
195#define SMA1307_A6_TDM2 0xA6
196#define SMA1307_A7_CLK_MON 0xA7
197#define SMA1307_A8_BOOST_CTRL1 0xA8
198#define SMA1307_A9_BOOST_CTRL2 0xA9
199#define SMA1307_AA_BOOST_CTRL3 0xAA
200#define SMA1307_AB_BOOST_CTRL4 0xAB
201#define SMA1307_AC_BOOST_CTRL5 0xAC
202#define SMA1307_AD_BOOST_CTRL6 0xAD
203#define SMA1307_AE_BOOST_CTRL7 0xAE
204#define SMA1307_AF_LPF 0xAF
205
206#define SMA1307_B0_RMS_TC1 0xB0
207#define SMA1307_B1_RMS_TC2 0xB1
208#define SMA1307_B2_AVG_TC1 0xB2
209#define SMA1307_B3_AVG_TC2 0xB3
210#define SMA1307_B4_PRVALUE1 0xB4
211#define SMA1307_B5_PRVALUE2 0xB5
212#define SMA1307_B8_SPK_NG_CTRL1 0xB8
213#define SMA1307_B9_SPK_NG_CTRL2 0xB9
214#define SMA1307_BA_DGC1 0xBA
215#define SMA1307_BB_DGC2 0xBB
216#define SMA1307_BC_DGC3 0xBC
217#define SMA1307_BD_MCBS_CTRL1 0xBD
218#define SMA1307_BE_MCBS_CTRL2 0xBE
219
220/* Status Register Read Only */
221#define SMA1307_F5_READY_FOR_V_SAR 0xF5
222#define SMA1307_F7_READY_FOR_T_SAR 0xF7
223#define SMA1307_F8_STATUS_T1 0xF8
224#define SMA1307_F9_STATUS_T2 0xF9
225#define SMA1307_FA_STATUS1 0xFA
226#define SMA1307_FB_STATUS2 0xFB
227#define SMA1307_FC_STATUS3 0xFC
228#define SMA1307_FD_STATUS4 0xFD
229#define SMA1307_FE_STATUS5 0xFE
230#define SMA1307_FF_DEVICE_INDEX 0xFF
231
232/* SMA1307 Registers Bit Fields */
233/* Power On/Off */
234#define SMA1307_POWER_MASK BIT(0)
235#define SMA1307_POWER_OFF 0
236#define SMA1307_POWER_ON BIT(0)
237
238/* Reset */
239#define SMA1307_RESET_MASK BIT(1)
240#define SMA1307_RESET_ON BIT(1)
241
242/* Left Polarity */
243#define SMA1307_LEFTPOL_MASK BIT(3)
244#define SMA1307_LOW_FIRST_CH 0
245#define SMA1307_HIGH_FIRST_CH BIT(3)
246
247/* SCK Falling/Rising */
248#define SMA1307_SCK_RISING_MASK BIT(2)
249#define SMA1307_SCK_FALLING_EDGE 0
250#define SMA1307_SCK_RISING_EDGE BIT(2)
251
252/* SPK Mute */
253#define SMA1307_SPK_MUTE_MASK BIT(0)
254#define SMA1307_SPK_UNMUTE 0
255#define SMA1307_SPK_MUTE BIT(0)
256
257/* SPK Mode */
258#define SMA1307_SPK_MODE_MASK (BIT(2)|BIT(3)|BIT(4))
259#define SMA1307_SPK_OFF 0
260#define SMA1307_SPK_MONO BIT(2)
261#define SMA1307_SPK_STEREO BIT(4)
262
263/* Mono Mix */
264#define SMA1307_MONOMIX_MASK BIT(0)
265#define SMA1307_MONOMIX_OFF 0
266#define SMA1307_MONOMIX_ON BIT(0)
267
268/* LR Data Swap */
269#define SMA1307_LR_DATA_SW_MASK BIT(4)
270#define SMA1307_LR_DATA_SW_NORMAL 0
271#define SMA1307_LR_DATA_SW_SWAP BIT(4)
272
273/* PLL On/Off */
274#define SMA1307_PLL_MASK BIT(6)
275#define SMA1307_PLL_ON 0
276#define SMA1307_PLL_OFF BIT(6)
277
278/* Input Format */
279#define SMA1307_I2S_MODE_MASK (BIT(4)|BIT(5)|BIT(6))
280#define SMA1307_STANDARD_I2S 0
281#define SMA1307_LJ BIT(4)
282#define SMA1307_RJ_16BIT BIT(6)
283#define SMA1307_RJ_18BIT (BIT(4)|BIT(6))
284#define SMA1307_RJ_20BIT (BIT(5)|BIT(6))
285#define SMA1307_RJ_24BIT (BIT(4)|BIT(5)|BIT(6))
286
287/* Controller / Device Setting */
288#define SMA1307_CONTROLLER_DEVICE_MASK BIT(7)
289#define SMA1307_DEVICE_MODE 0
290#define SMA1307_CONTROLLER_MODE BIT(7)
291
292/* Port Config */
293#define SMA1307_PORT_CONFIG_MASK (BIT(6)|BIT(7))
294#define SMA1307_INPUT_PORT_ONLY 0
295#define SMA1307_OUTPUT_PORT_ENABLE BIT(7)
296
297/* SDO Output */
298#define SMA1307_SDO_OUTPUT_MASK BIT(3)
299#define SMA1307_LOGIC_OUTPUT 0
300#define SMA1307_HIGH_Z_OUTPUT BIT(3)
301
302#define SMA1307_DATA_CLK_SEL_MASK (BIT(6)|BIT(7))
303#define SMA1307_SDO_DATA 0
304#define SMA1307_SDO_CLK_PLL BIT(6)
305#define SMA1307_SDO_CLK_OSC (BIT(6)|BIT(7))
306
307/* SDO Output2 */
308#define SMA1307_SDO_OUTPUT2_MASK BIT(0)
309#define SMA1307_ONE_SDO_PER_CH 0
310#define SMA1307_TWO_SDO_PER_CH BIT(0)
311
312/* SDO Output3 */
313#define SMA1307_SDO_OUTPUT3_MASK BIT(2)
314#define SMA1307_SDO_OUTPUT3_DIS 0
315#define SMA1307_TWO_SDO_PER_CH_24K BIT(2)
316
317/* SDO OUT1 Select*/
318#define SMA1307_SDO_OUT1_SEL_MASK (BIT(3)|BIT(4)|BIT(5))
319#define SMA1307_SDO1_DISABLE 0
320#define SMA1307_SDO1_FORMAT_C BIT(3)
321#define SMA1307_SDO1_MONO_MIX BIT(4)
322#define SMA1307_SDO1_AFTER_DSP (BIT(3)|BIT(4))
323#define SMA1307_SDO1_VRMS2_AVG BIT(5)
324#define SMA1307_SDO1_VBAT_MON (BIT(3)|BIT(5))
325#define SMA1307_SDO1_TEMP_MON (BIT(4)|BIT(5))
326#define SMA1307_SDO1_AFTER_DELAY (BIT(3)|BIT(4)|BIT(5))
327
328/* SDO OUT0 Select*/
329#define SMA1307_SDO_OUT0_SEL_MASK (BIT(0)|BIT(1)|BIT(2))
330#define SMA1307_SDO0_DISABLE 0
331#define SMA1307_SDO0_FORMAT_C BIT(0)
332#define SMA1307_SDO0_MONO_MIX BIT(1)
333#define SMA1307_SDO0_AFTER_DSP (BIT(0)|BIT(1))
334#define SMA1307_SDO0_VRMS2_AVG BIT(2)
335#define SMA1307_SDO0_VBAT_MON (BIT(0)|BIT(2))
336#define SMA1307_SDO0_TEMP_MON (BIT(1)|BIT(2))
337#define SMA1307_SDO0_AFTER_DELAY (BIT(0)|BIT(1)|BIT(2))
338
339/* INTERRUPT Operation */
340#define SMA1307_SEL_INT_MASK BIT(2)
341#define SMA1307_INT_CLEAR_AUTO 0
342#define SMA1307_INT_CLEAR_MANUAL BIT(2)
343
344/* INTERRUPT CLEAR */
345#define SMA1307_CLR_INT_MASK BIT(1)
346#define SMA1307_INT_READY 0
347#define SMA1307_INT_CLEAR BIT(1)
348
349/* INTERRUPT Disable */
350#define SMA1307_DIS_INT_MASK BIT(0)
351#define SMA1307_NORMAL_INT 0
352#define SMA1307_HIGH_Z_INT BIT(0)
353
354/* Interface Control */
355#define SMA1307_INTERFACE_MASK (BIT(5)|BIT(6)|BIT(7))
356#define SMA1307_LJ_FORMAT BIT(5)
357#define SMA1307_I2S_FORMAT (BIT(5)|BIT(6))
358#define SMA1307_TDM_FORMAT BIT(7)
359
360#define SMA1307_SCK_RATE_MASK (BIT(3)|BIT(4))
361#define SMA1307_SCK_64FS 0
362#define SMA1307_SCK_32FS BIT(4)
363
364#define SMA1307_DATA_WIDTH_MASK (BIT(1)|BIT(2))
365#define SMA1307_DATA_24BIT 0
366#define SMA1307_DATA_16BIT (BIT(1)|BIT(2))
367
368#define SMA1307_TDM_TX_MODE_MASK BIT(6)
369#define SMA1307_TDM_TX_MONO 0
370#define SMA1307_TDM_TX_STEREO BIT(6)
371
372#define SMA1307_TDM_SLOT0_RX_POS_MASK (BIT(3)|BIT(4)|BIT(5))
373#define SMA1307_TDM_SLOT0_RX_POS_0 0
374#define SMA1307_TDM_SLOT0_RX_POS_1 BIT(3)
375#define SMA1307_TDM_SLOT0_RX_POS_2 BIT(4)
376#define SMA1307_TDM_SLOT0_RX_POS_3 (BIT(3)|BIT(4))
377#define SMA1307_TDM_SLOT0_RX_POS_4 BIT(5)
378#define SMA1307_TDM_SLOT0_RX_POS_5 (BIT(3)|BIT(5))
379#define SMA1307_TDM_SLOT0_RX_POS_6 (BIT(4)|BIT(5))
380#define SMA1307_TDM_SLOT0_RX_POS_7 (BIT(3)|BIT(4)|BIT(5))
381
382#define SMA1307_TDM_SLOT1_RX_POS_MASK (BIT(0)|BIT(1)|BIT(2))
383#define SMA1307_TDM_SLOT1_RX_POS_0 0
384#define SMA1307_TDM_SLOT1_RX_POS_1 BIT(0)
385#define SMA1307_TDM_SLOT1_RX_POS_2 BIT(1)
386#define SMA1307_TDM_SLOT1_RX_POS_3 (BIT(0)|BIT(1))
387#define SMA1307_TDM_SLOT1_RX_POS_4 BIT(2)
388#define SMA1307_TDM_SLOT1_RX_POS_5 (BIT(0)|BIT(2))
389#define SMA1307_TDM_SLOT1_RX_POS_6 (BIT(1)|BIT(2))
390#define SMA1307_TDM_SLOT1_RX_POS_7 (BIT(0)|BIT(1)|BIT(2))
391
392/* TDM2 FORMAT : 0xA6 */
393#define SMA1307_TDM_DL_MASK BIT(7)
394#define SMA1307_TDM_DL_16 0
395#define SMA1307_TDM_DL_32 BIT(7)
396
397#define SMA1307_TDM_N_SLOT_MASK BIT(6)
398#define SMA1307_TDM_N_SLOT_4 0
399#define SMA1307_TDM_N_SLOT_8 BIT(6)
400
401#define SMA1307_TDM_SLOT0_TX_POS_MASK (BIT(3)|BIT(4)|BIT(5))
402#define SMA1307_TDM_SLOT0_TX_POS_0 0
403#define SMA1307_TDM_SLOT0_TX_POS_1 BIT(3)
404#define SMA1307_TDM_SLOT0_TX_POS_2 BIT(4)
405#define SMA1307_TDM_SLOT0_TX_POS_3 (BIT(3)|BIT(4))
406#define SMA1307_TDM_SLOT0_TX_POS_4 BIT(5)
407#define SMA1307_TDM_SLOT0_TX_POS_5 (BIT(3)|BIT(5))
408#define SMA1307_TDM_SLOT0_TX_POS_6 (BIT(4)|BIT(5))
409#define SMA1307_TDM_SLOT0_TX_POS_7 (BIT(3)|BIT(4)|BIT(5))
410
411#define SMA1307_TDM_SLOT1_TX_POS_MASK (BIT(0)|BIT(1)|BIT(2))
412#define SMA1307_TDM_SLOT1_TX_POS_0 0
413#define SMA1307_TDM_SLOT1_TX_POS_1 BIT(0)
414#define SMA1307_TDM_SLOT1_TX_POS_2 BIT(1)
415#define SMA1307_TDM_SLOT1_TX_POS_3 (BIT(0)|BIT(1))
416#define SMA1307_TDM_SLOT1_TX_POS_4 BIT(2)
417#define SMA1307_TDM_SLOT1_TX_POS_5 (BIT(0)|BIT(2))
418#define SMA1307_TDM_SLOT1_TX_POS_6 (BIT(1)|BIT(2))
419#define SMA1307_TDM_SLOT1_TX_POS_7 (BIT(0)|BIT(1)|BIT(2))
420
421/* OTP STATUS */
422#define SMA1307_OTP_STAT_MASK BIT(6)
423#define SMA1307_OTP_STAT_0 0
424#define SMA1307_OTP_STAT_1 BIT(6)
425
426/* STATUS */
427#define SMA1307_OT1_OK_STATUS BIT(7)
428#define SMA1307_OT2_OK_STATUS BIT(6)
429#define SMA1307_UVLO_STATUS BIT(5)
430#define SMA1307_OVP_BST_STATUS BIT(4)
431#define SMA1307_POWER_FLAG BIT(3)
432
433#define SMA1307_SCAN_CHK BIT(7)
434#define SMA1307_OCP_SPK_STATUS BIT(5)
435#define SMA1307_OCP_BST_STATUS BIT(4)
436#define SMA1307_BOP_STATE (BIT(1)|BIT(2)|BIT(3))
437#define SMA1307_CLK_MON_STATUS BIT(0)
438
439#define SMA1307_DEVICE_ID (BIT(3)|BIT(4))
440#define SMA1307_REV_NUM_STATUS (BIT(0)|BIT(1))
441#define SMA1307_REV_NUM_REV0 0
442#define SMA1307_REV_NUM_REV1 BIT(0)
443
444#endif