Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * cs42l51.c
4 *
5 * ASoC Driver for Cirrus Logic CS42L51 codecs
6 *
7 * Copyright (c) 2010 Arnaud Patard <apatard@mandriva.com>
8 *
9 * Based on cs4270.c - Copyright (c) Freescale Semiconductor
10 *
11 * For now:
12 * - Only I2C is support. Not SPI
13 * - master mode *NOT* supported
14 */
15
16#include <linux/clk.h>
17#include <linux/module.h>
18#include <linux/slab.h>
19#include <sound/core.h>
20#include <sound/soc.h>
21#include <sound/tlv.h>
22#include <sound/initval.h>
23#include <sound/pcm_params.h>
24#include <sound/pcm.h>
25#include <linux/gpio/consumer.h>
26#include <linux/regmap.h>
27#include <linux/regulator/consumer.h>
28
29#include "cs42l51.h"
30
31enum master_slave_mode {
32 MODE_SLAVE,
33 MODE_SLAVE_AUTO,
34 MODE_MASTER,
35};
36
37static const char * const cs42l51_supply_names[] = {
38 "VL",
39 "VD",
40 "VA",
41 "VAHP",
42};
43
44struct cs42l51_private {
45 unsigned int mclk;
46 struct clk *mclk_handle;
47 unsigned int audio_mode; /* The mode (I2S or left-justified) */
48 enum master_slave_mode func;
49 struct regulator_bulk_data supplies[ARRAY_SIZE(cs42l51_supply_names)];
50 struct gpio_desc *reset_gpio;
51 struct regmap *regmap;
52};
53
54#define CS42L51_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
55 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE)
56
57static int cs42l51_get_chan_mix(struct snd_kcontrol *kcontrol,
58 struct snd_ctl_elem_value *ucontrol)
59{
60 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
61 unsigned long value = snd_soc_component_read(component, CS42L51_PCM_MIXER)&3;
62
63 switch (value) {
64 default:
65 case 0:
66 ucontrol->value.enumerated.item[0] = 0;
67 break;
68 /* same value : (L+R)/2 and (R+L)/2 */
69 case 1:
70 case 2:
71 ucontrol->value.enumerated.item[0] = 1;
72 break;
73 case 3:
74 ucontrol->value.enumerated.item[0] = 2;
75 break;
76 }
77
78 return 0;
79}
80
81#define CHAN_MIX_NORMAL 0x00
82#define CHAN_MIX_BOTH 0x55
83#define CHAN_MIX_SWAP 0xFF
84
85static int cs42l51_set_chan_mix(struct snd_kcontrol *kcontrol,
86 struct snd_ctl_elem_value *ucontrol)
87{
88 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
89 unsigned char val;
90
91 switch (ucontrol->value.enumerated.item[0]) {
92 default:
93 case 0:
94 val = CHAN_MIX_NORMAL;
95 break;
96 case 1:
97 val = CHAN_MIX_BOTH;
98 break;
99 case 2:
100 val = CHAN_MIX_SWAP;
101 break;
102 }
103
104 snd_soc_component_write(component, CS42L51_PCM_MIXER, val);
105
106 return 1;
107}
108
109static const DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -5150, 50, 0);
110static const DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 150, 0);
111
112static const DECLARE_TLV_DB_SCALE(aout_tlv, -10200, 50, 0);
113
114static const DECLARE_TLV_DB_SCALE(boost_tlv, 1600, 1600, 0);
115static const DECLARE_TLV_DB_SCALE(adc_boost_tlv, 2000, 2000, 0);
116static const char *chan_mix[] = {
117 "L R",
118 "L+R",
119 "R L",
120};
121
122static const DECLARE_TLV_DB_SCALE(pga_tlv, -300, 50, 0);
123static const DECLARE_TLV_DB_SCALE(adc_att_tlv, -9600, 100, 0);
124
125static SOC_ENUM_SINGLE_EXT_DECL(cs42l51_chan_mix, chan_mix);
126
127static const struct snd_kcontrol_new cs42l51_snd_controls[] = {
128 SOC_DOUBLE_R_SX_TLV("PCM Playback Volume",
129 CS42L51_PCMA_VOL, CS42L51_PCMB_VOL,
130 0, 0x19, 0x7F, adc_pcm_tlv),
131 SOC_DOUBLE_R("PCM Playback Switch",
132 CS42L51_PCMA_VOL, CS42L51_PCMB_VOL, 7, 1, 1),
133 SOC_DOUBLE_R_SX_TLV("Analog Playback Volume",
134 CS42L51_AOUTA_VOL, CS42L51_AOUTB_VOL,
135 0, 0x34, 0xE4, aout_tlv),
136 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
137 CS42L51_ADCA_VOL, CS42L51_ADCB_VOL,
138 0, 0x19, 0x7F, adc_pcm_tlv),
139 SOC_DOUBLE_R("ADC Mixer Switch",
140 CS42L51_ADCA_VOL, CS42L51_ADCB_VOL, 7, 1, 1),
141 SOC_DOUBLE_R_SX_TLV("ADC Attenuator Volume",
142 CS42L51_ADCA_ATT, CS42L51_ADCB_ATT,
143 0, 0xA0, 96, adc_att_tlv),
144 SOC_DOUBLE_R_SX_TLV("PGA Volume",
145 CS42L51_ALC_PGA_CTL, CS42L51_ALC_PGB_CTL,
146 0, 0x1A, 30, pga_tlv),
147 SOC_SINGLE("Playback Deemphasis Switch", CS42L51_DAC_CTL, 3, 1, 0),
148 SOC_SINGLE("Auto-Mute Switch", CS42L51_DAC_CTL, 2, 1, 0),
149 SOC_SINGLE("Soft Ramp Switch", CS42L51_DAC_CTL, 1, 1, 0),
150 SOC_SINGLE("Zero Cross Switch", CS42L51_DAC_CTL, 0, 0, 0),
151 SOC_DOUBLE_TLV("Mic Boost Volume",
152 CS42L51_MIC_CTL, 0, 1, 1, 0, boost_tlv),
153 SOC_DOUBLE_TLV("ADC Boost Volume",
154 CS42L51_MIC_CTL, 5, 6, 1, 0, adc_boost_tlv),
155 SOC_SINGLE_TLV("Bass Volume", CS42L51_TONE_CTL, 0, 0xf, 1, tone_tlv),
156 SOC_SINGLE_TLV("Treble Volume", CS42L51_TONE_CTL, 4, 0xf, 1, tone_tlv),
157 SOC_ENUM_EXT("PCM channel mixer",
158 cs42l51_chan_mix,
159 cs42l51_get_chan_mix, cs42l51_set_chan_mix),
160};
161
162/*
163 * to power down, one must:
164 * 1.) Enable the PDN bit
165 * 2.) enable power-down for the select channels
166 * 3.) disable the PDN bit.
167 */
168static int cs42l51_pdn_event(struct snd_soc_dapm_widget *w,
169 struct snd_kcontrol *kcontrol, int event)
170{
171 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
172
173 switch (event) {
174 case SND_SOC_DAPM_PRE_PMD:
175 snd_soc_component_update_bits(component, CS42L51_POWER_CTL1,
176 CS42L51_POWER_CTL1_PDN,
177 CS42L51_POWER_CTL1_PDN);
178 break;
179 default:
180 case SND_SOC_DAPM_POST_PMD:
181 snd_soc_component_update_bits(component, CS42L51_POWER_CTL1,
182 CS42L51_POWER_CTL1_PDN, 0);
183 break;
184 }
185
186 return 0;
187}
188
189static const char *cs42l51_dac_names[] = {"Direct PCM",
190 "DSP PCM", "ADC"};
191static SOC_ENUM_SINGLE_DECL(cs42l51_dac_mux_enum,
192 CS42L51_DAC_CTL, 6, cs42l51_dac_names);
193static const struct snd_kcontrol_new cs42l51_dac_mux_controls =
194 SOC_DAPM_ENUM("Route", cs42l51_dac_mux_enum);
195
196static const char *cs42l51_adcl_names[] = {"AIN1 Left", "AIN2 Left",
197 "MIC Left", "MIC+preamp Left"};
198static SOC_ENUM_SINGLE_DECL(cs42l51_adcl_mux_enum,
199 CS42L51_ADC_INPUT, 4, cs42l51_adcl_names);
200static const struct snd_kcontrol_new cs42l51_adcl_mux_controls =
201 SOC_DAPM_ENUM("Route", cs42l51_adcl_mux_enum);
202
203static const char *cs42l51_adcr_names[] = {"AIN1 Right", "AIN2 Right",
204 "MIC Right", "MIC+preamp Right"};
205static SOC_ENUM_SINGLE_DECL(cs42l51_adcr_mux_enum,
206 CS42L51_ADC_INPUT, 6, cs42l51_adcr_names);
207static const struct snd_kcontrol_new cs42l51_adcr_mux_controls =
208 SOC_DAPM_ENUM("Route", cs42l51_adcr_mux_enum);
209
210static const struct snd_soc_dapm_widget cs42l51_dapm_widgets[] = {
211 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L51_MIC_POWER_CTL, 1, 1, NULL,
212 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
213 SND_SOC_DAPM_PGA_E("Left PGA", CS42L51_POWER_CTL1, 3, 1, NULL, 0,
214 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
215 SND_SOC_DAPM_PGA_E("Right PGA", CS42L51_POWER_CTL1, 4, 1, NULL, 0,
216 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
217 SND_SOC_DAPM_ADC_E("Left ADC", "Left HiFi Capture",
218 CS42L51_POWER_CTL1, 1, 1,
219 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
220 SND_SOC_DAPM_ADC_E("Right ADC", "Right HiFi Capture",
221 CS42L51_POWER_CTL1, 2, 1,
222 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
223 SND_SOC_DAPM_DAC_E("Left DAC", NULL, CS42L51_POWER_CTL1, 5, 1,
224 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
225 SND_SOC_DAPM_DAC_E("Right DAC", NULL, CS42L51_POWER_CTL1, 6, 1,
226 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
227
228 /* analog/mic */
229 SND_SOC_DAPM_INPUT("AIN1L"),
230 SND_SOC_DAPM_INPUT("AIN1R"),
231 SND_SOC_DAPM_INPUT("AIN2L"),
232 SND_SOC_DAPM_INPUT("AIN2R"),
233 SND_SOC_DAPM_INPUT("MICL"),
234 SND_SOC_DAPM_INPUT("MICR"),
235
236 SND_SOC_DAPM_MIXER("Mic Preamp Left",
237 CS42L51_MIC_POWER_CTL, 2, 1, NULL, 0),
238 SND_SOC_DAPM_MIXER("Mic Preamp Right",
239 CS42L51_MIC_POWER_CTL, 3, 1, NULL, 0),
240
241 /* HP */
242 SND_SOC_DAPM_OUTPUT("HPL"),
243 SND_SOC_DAPM_OUTPUT("HPR"),
244
245 /* mux */
246 SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
247 &cs42l51_dac_mux_controls),
248 SND_SOC_DAPM_MUX("PGA-ADC Mux Left", SND_SOC_NOPM, 0, 0,
249 &cs42l51_adcl_mux_controls),
250 SND_SOC_DAPM_MUX("PGA-ADC Mux Right", SND_SOC_NOPM, 0, 0,
251 &cs42l51_adcr_mux_controls),
252};
253
254static int mclk_event(struct snd_soc_dapm_widget *w,
255 struct snd_kcontrol *kcontrol, int event)
256{
257 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
258 struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(comp);
259
260 switch (event) {
261 case SND_SOC_DAPM_PRE_PMU:
262 return clk_prepare_enable(cs42l51->mclk_handle);
263 case SND_SOC_DAPM_POST_PMD:
264 /* Delay mclk shutdown to fulfill power-down sequence requirements */
265 msleep(20);
266 clk_disable_unprepare(cs42l51->mclk_handle);
267 break;
268 }
269
270 return 0;
271}
272
273static const struct snd_soc_dapm_widget cs42l51_dapm_mclk_widgets[] = {
274 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, mclk_event,
275 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
276};
277
278static const struct snd_soc_dapm_route cs42l51_routes[] = {
279 {"HPL", NULL, "Left DAC"},
280 {"HPR", NULL, "Right DAC"},
281
282 {"Right DAC", NULL, "DAC Mux"},
283 {"Left DAC", NULL, "DAC Mux"},
284
285 {"DAC Mux", "Direct PCM", "Playback"},
286 {"DAC Mux", "DSP PCM", "Playback"},
287
288 {"Left ADC", NULL, "Left PGA"},
289 {"Right ADC", NULL, "Right PGA"},
290
291 {"Mic Preamp Left", NULL, "MICL"},
292 {"Mic Preamp Right", NULL, "MICR"},
293
294 {"PGA-ADC Mux Left", "AIN1 Left", "AIN1L" },
295 {"PGA-ADC Mux Left", "AIN2 Left", "AIN2L" },
296 {"PGA-ADC Mux Left", "MIC Left", "MICL" },
297 {"PGA-ADC Mux Left", "MIC+preamp Left", "Mic Preamp Left" },
298 {"PGA-ADC Mux Right", "AIN1 Right", "AIN1R" },
299 {"PGA-ADC Mux Right", "AIN2 Right", "AIN2R" },
300 {"PGA-ADC Mux Right", "MIC Right", "MICR" },
301 {"PGA-ADC Mux Right", "MIC+preamp Right", "Mic Preamp Right" },
302
303 {"Left PGA", NULL, "PGA-ADC Mux Left"},
304 {"Right PGA", NULL, "PGA-ADC Mux Right"},
305};
306
307static int cs42l51_set_dai_fmt(struct snd_soc_dai *codec_dai,
308 unsigned int format)
309{
310 struct snd_soc_component *component = codec_dai->component;
311 struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
312
313 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
314 case SND_SOC_DAIFMT_I2S:
315 case SND_SOC_DAIFMT_LEFT_J:
316 case SND_SOC_DAIFMT_RIGHT_J:
317 cs42l51->audio_mode = format & SND_SOC_DAIFMT_FORMAT_MASK;
318 break;
319 default:
320 dev_err(component->dev, "invalid DAI format\n");
321 return -EINVAL;
322 }
323
324 switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
325 case SND_SOC_DAIFMT_CBM_CFM:
326 cs42l51->func = MODE_MASTER;
327 break;
328 case SND_SOC_DAIFMT_CBS_CFS:
329 cs42l51->func = MODE_SLAVE_AUTO;
330 break;
331 default:
332 dev_err(component->dev, "Unknown master/slave configuration\n");
333 return -EINVAL;
334 }
335
336 return 0;
337}
338
339struct cs42l51_ratios {
340 unsigned int ratio;
341 unsigned char speed_mode;
342 unsigned char mclk;
343};
344
345static struct cs42l51_ratios slave_ratios[] = {
346 { 512, CS42L51_QSM_MODE, 0 }, { 768, CS42L51_QSM_MODE, 0 },
347 { 1024, CS42L51_QSM_MODE, 0 }, { 1536, CS42L51_QSM_MODE, 0 },
348 { 2048, CS42L51_QSM_MODE, 0 }, { 3072, CS42L51_QSM_MODE, 0 },
349 { 256, CS42L51_HSM_MODE, 0 }, { 384, CS42L51_HSM_MODE, 0 },
350 { 512, CS42L51_HSM_MODE, 0 }, { 768, CS42L51_HSM_MODE, 0 },
351 { 1024, CS42L51_HSM_MODE, 0 }, { 1536, CS42L51_HSM_MODE, 0 },
352 { 128, CS42L51_SSM_MODE, 0 }, { 192, CS42L51_SSM_MODE, 0 },
353 { 256, CS42L51_SSM_MODE, 0 }, { 384, CS42L51_SSM_MODE, 0 },
354 { 512, CS42L51_SSM_MODE, 0 }, { 768, CS42L51_SSM_MODE, 0 },
355 { 128, CS42L51_DSM_MODE, 0 }, { 192, CS42L51_DSM_MODE, 0 },
356 { 256, CS42L51_DSM_MODE, 0 }, { 384, CS42L51_DSM_MODE, 0 },
357};
358
359static struct cs42l51_ratios slave_auto_ratios[] = {
360 { 1024, CS42L51_QSM_MODE, 0 }, { 1536, CS42L51_QSM_MODE, 0 },
361 { 2048, CS42L51_QSM_MODE, 1 }, { 3072, CS42L51_QSM_MODE, 1 },
362 { 512, CS42L51_HSM_MODE, 0 }, { 768, CS42L51_HSM_MODE, 0 },
363 { 1024, CS42L51_HSM_MODE, 1 }, { 1536, CS42L51_HSM_MODE, 1 },
364 { 256, CS42L51_SSM_MODE, 0 }, { 384, CS42L51_SSM_MODE, 0 },
365 { 512, CS42L51_SSM_MODE, 1 }, { 768, CS42L51_SSM_MODE, 1 },
366 { 128, CS42L51_DSM_MODE, 0 }, { 192, CS42L51_DSM_MODE, 0 },
367 { 256, CS42L51_DSM_MODE, 1 }, { 384, CS42L51_DSM_MODE, 1 },
368};
369
370/*
371 * Master mode mclk/fs ratios.
372 * Recommended configurations are SSM for 4-50khz and DSM for 50-100kHz ranges
373 * The table below provides support of following ratios:
374 * 128: SSM (%128) with div2 disabled
375 * 256: SSM (%128) with div2 enabled
376 * In both cases, if sampling rate is above 50kHz, SSM is overridden
377 * with DSM (%128) configuration
378 */
379static struct cs42l51_ratios master_ratios[] = {
380 { 128, CS42L51_SSM_MODE, 0 }, { 256, CS42L51_SSM_MODE, 1 },
381};
382
383static int cs42l51_set_dai_sysclk(struct snd_soc_dai *codec_dai,
384 int clk_id, unsigned int freq, int dir)
385{
386 struct snd_soc_component *component = codec_dai->component;
387 struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
388
389 cs42l51->mclk = freq;
390 return 0;
391}
392
393static int cs42l51_hw_params(struct snd_pcm_substream *substream,
394 struct snd_pcm_hw_params *params,
395 struct snd_soc_dai *dai)
396{
397 struct snd_soc_component *component = dai->component;
398 struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
399 int ret;
400 unsigned int i;
401 unsigned int rate;
402 unsigned int ratio;
403 struct cs42l51_ratios *ratios = NULL;
404 int nr_ratios = 0;
405 int intf_ctl, power_ctl, fmt, mode;
406
407 switch (cs42l51->func) {
408 case MODE_MASTER:
409 ratios = master_ratios;
410 nr_ratios = ARRAY_SIZE(master_ratios);
411 break;
412 case MODE_SLAVE:
413 ratios = slave_ratios;
414 nr_ratios = ARRAY_SIZE(slave_ratios);
415 break;
416 case MODE_SLAVE_AUTO:
417 ratios = slave_auto_ratios;
418 nr_ratios = ARRAY_SIZE(slave_auto_ratios);
419 break;
420 }
421
422 /* Figure out which MCLK/LRCK ratio to use */
423 rate = params_rate(params); /* Sampling rate, in Hz */
424 ratio = cs42l51->mclk / rate; /* MCLK/LRCK ratio */
425 for (i = 0; i < nr_ratios; i++) {
426 if (ratios[i].ratio == ratio)
427 break;
428 }
429
430 if (i == nr_ratios) {
431 /* We did not find a matching ratio */
432 dev_err(component->dev, "could not find matching ratio\n");
433 return -EINVAL;
434 }
435
436 intf_ctl = snd_soc_component_read(component, CS42L51_INTF_CTL);
437 power_ctl = snd_soc_component_read(component, CS42L51_MIC_POWER_CTL);
438
439 intf_ctl &= ~(CS42L51_INTF_CTL_MASTER | CS42L51_INTF_CTL_ADC_I2S
440 | CS42L51_INTF_CTL_DAC_FORMAT(7));
441 power_ctl &= ~(CS42L51_MIC_POWER_CTL_SPEED(3)
442 | CS42L51_MIC_POWER_CTL_MCLK_DIV2);
443
444 switch (cs42l51->func) {
445 case MODE_MASTER:
446 intf_ctl |= CS42L51_INTF_CTL_MASTER;
447 mode = ratios[i].speed_mode;
448 /* Force DSM mode if sampling rate is above 50kHz */
449 if (rate > 50000)
450 mode = CS42L51_DSM_MODE;
451 power_ctl |= CS42L51_MIC_POWER_CTL_SPEED(mode);
452 /*
453 * Auto detect mode is not applicable for master mode and has to
454 * be disabled. Otherwise SPEED[1:0] bits will be ignored.
455 */
456 power_ctl &= ~CS42L51_MIC_POWER_CTL_AUTO;
457 break;
458 case MODE_SLAVE:
459 power_ctl |= CS42L51_MIC_POWER_CTL_SPEED(ratios[i].speed_mode);
460 break;
461 case MODE_SLAVE_AUTO:
462 power_ctl |= CS42L51_MIC_POWER_CTL_AUTO;
463 break;
464 }
465
466 switch (cs42l51->audio_mode) {
467 case SND_SOC_DAIFMT_I2S:
468 intf_ctl |= CS42L51_INTF_CTL_ADC_I2S;
469 intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(CS42L51_DAC_DIF_I2S);
470 break;
471 case SND_SOC_DAIFMT_LEFT_J:
472 intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(CS42L51_DAC_DIF_LJ24);
473 break;
474 case SND_SOC_DAIFMT_RIGHT_J:
475 switch (params_width(params)) {
476 case 16:
477 fmt = CS42L51_DAC_DIF_RJ16;
478 break;
479 case 18:
480 fmt = CS42L51_DAC_DIF_RJ18;
481 break;
482 case 20:
483 fmt = CS42L51_DAC_DIF_RJ20;
484 break;
485 case 24:
486 fmt = CS42L51_DAC_DIF_RJ24;
487 break;
488 default:
489 dev_err(component->dev, "unknown format\n");
490 return -EINVAL;
491 }
492 intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(fmt);
493 break;
494 default:
495 dev_err(component->dev, "unknown format\n");
496 return -EINVAL;
497 }
498
499 if (ratios[i].mclk)
500 power_ctl |= CS42L51_MIC_POWER_CTL_MCLK_DIV2;
501
502 ret = snd_soc_component_write(component, CS42L51_INTF_CTL, intf_ctl);
503 if (ret < 0)
504 return ret;
505
506 ret = snd_soc_component_write(component, CS42L51_MIC_POWER_CTL, power_ctl);
507 if (ret < 0)
508 return ret;
509
510 return 0;
511}
512
513static int cs42l51_dai_mute(struct snd_soc_dai *dai, int mute, int direction)
514{
515 struct snd_soc_component *component = dai->component;
516 int reg;
517 int mask = CS42L51_DAC_OUT_CTL_DACA_MUTE|CS42L51_DAC_OUT_CTL_DACB_MUTE;
518
519 reg = snd_soc_component_read(component, CS42L51_DAC_OUT_CTL);
520
521 if (mute)
522 reg |= mask;
523 else
524 reg &= ~mask;
525
526 return snd_soc_component_write(component, CS42L51_DAC_OUT_CTL, reg);
527}
528
529static int cs42l51_of_xlate_dai_id(struct snd_soc_component *component,
530 struct device_node *endpoint)
531{
532 /* return dai id 0, whatever the endpoint index */
533 return 0;
534}
535
536static const struct snd_soc_dai_ops cs42l51_dai_ops = {
537 .hw_params = cs42l51_hw_params,
538 .set_sysclk = cs42l51_set_dai_sysclk,
539 .set_fmt = cs42l51_set_dai_fmt,
540 .mute_stream = cs42l51_dai_mute,
541 .no_capture_mute = 1,
542};
543
544static struct snd_soc_dai_driver cs42l51_dai = {
545 .name = "cs42l51-hifi",
546 .playback = {
547 .stream_name = "Playback",
548 .channels_min = 1,
549 .channels_max = 2,
550 .rates = SNDRV_PCM_RATE_8000_96000,
551 .formats = CS42L51_FORMATS,
552 },
553 .capture = {
554 .stream_name = "Capture",
555 .channels_min = 1,
556 .channels_max = 2,
557 .rates = SNDRV_PCM_RATE_8000_96000,
558 .formats = CS42L51_FORMATS,
559 },
560 .ops = &cs42l51_dai_ops,
561};
562
563static int cs42l51_component_probe(struct snd_soc_component *component)
564{
565 int ret, reg;
566 struct snd_soc_dapm_context *dapm;
567 struct cs42l51_private *cs42l51;
568
569 cs42l51 = snd_soc_component_get_drvdata(component);
570 dapm = snd_soc_component_get_dapm(component);
571
572 if (cs42l51->mclk_handle)
573 snd_soc_dapm_new_controls(dapm, cs42l51_dapm_mclk_widgets, 1);
574
575 /*
576 * DAC configuration
577 * - Use signal processor
578 * - auto mute
579 * - vol changes immediate
580 * - no de-emphasize
581 */
582 reg = CS42L51_DAC_CTL_DATA_SEL(1)
583 | CS42L51_DAC_CTL_AMUTE | CS42L51_DAC_CTL_DACSZ(0);
584 ret = snd_soc_component_write(component, CS42L51_DAC_CTL, reg);
585 if (ret < 0)
586 return ret;
587
588 return 0;
589}
590
591static const struct snd_soc_component_driver soc_component_device_cs42l51 = {
592 .probe = cs42l51_component_probe,
593 .controls = cs42l51_snd_controls,
594 .num_controls = ARRAY_SIZE(cs42l51_snd_controls),
595 .dapm_widgets = cs42l51_dapm_widgets,
596 .num_dapm_widgets = ARRAY_SIZE(cs42l51_dapm_widgets),
597 .dapm_routes = cs42l51_routes,
598 .num_dapm_routes = ARRAY_SIZE(cs42l51_routes),
599 .of_xlate_dai_id = cs42l51_of_xlate_dai_id,
600 .idle_bias_on = 1,
601 .use_pmdown_time = 1,
602 .endianness = 1,
603};
604
605static bool cs42l51_writeable_reg(struct device *dev, unsigned int reg)
606{
607 switch (reg) {
608 case CS42L51_POWER_CTL1:
609 case CS42L51_MIC_POWER_CTL:
610 case CS42L51_INTF_CTL:
611 case CS42L51_MIC_CTL:
612 case CS42L51_ADC_CTL:
613 case CS42L51_ADC_INPUT:
614 case CS42L51_DAC_OUT_CTL:
615 case CS42L51_DAC_CTL:
616 case CS42L51_ALC_PGA_CTL:
617 case CS42L51_ALC_PGB_CTL:
618 case CS42L51_ADCA_ATT:
619 case CS42L51_ADCB_ATT:
620 case CS42L51_ADCA_VOL:
621 case CS42L51_ADCB_VOL:
622 case CS42L51_PCMA_VOL:
623 case CS42L51_PCMB_VOL:
624 case CS42L51_BEEP_FREQ:
625 case CS42L51_BEEP_VOL:
626 case CS42L51_BEEP_CONF:
627 case CS42L51_TONE_CTL:
628 case CS42L51_AOUTA_VOL:
629 case CS42L51_AOUTB_VOL:
630 case CS42L51_PCM_MIXER:
631 case CS42L51_LIMIT_THRES_DIS:
632 case CS42L51_LIMIT_REL:
633 case CS42L51_LIMIT_ATT:
634 case CS42L51_ALC_EN:
635 case CS42L51_ALC_REL:
636 case CS42L51_ALC_THRES:
637 case CS42L51_NOISE_CONF:
638 case CS42L51_CHARGE_FREQ:
639 return true;
640 default:
641 return false;
642 }
643}
644
645static bool cs42l51_volatile_reg(struct device *dev, unsigned int reg)
646{
647 switch (reg) {
648 case CS42L51_STATUS:
649 return true;
650 default:
651 return false;
652 }
653}
654
655static bool cs42l51_readable_reg(struct device *dev, unsigned int reg)
656{
657 switch (reg) {
658 case CS42L51_CHIP_REV_ID:
659 case CS42L51_POWER_CTL1:
660 case CS42L51_MIC_POWER_CTL:
661 case CS42L51_INTF_CTL:
662 case CS42L51_MIC_CTL:
663 case CS42L51_ADC_CTL:
664 case CS42L51_ADC_INPUT:
665 case CS42L51_DAC_OUT_CTL:
666 case CS42L51_DAC_CTL:
667 case CS42L51_ALC_PGA_CTL:
668 case CS42L51_ALC_PGB_CTL:
669 case CS42L51_ADCA_ATT:
670 case CS42L51_ADCB_ATT:
671 case CS42L51_ADCA_VOL:
672 case CS42L51_ADCB_VOL:
673 case CS42L51_PCMA_VOL:
674 case CS42L51_PCMB_VOL:
675 case CS42L51_BEEP_FREQ:
676 case CS42L51_BEEP_VOL:
677 case CS42L51_BEEP_CONF:
678 case CS42L51_TONE_CTL:
679 case CS42L51_AOUTA_VOL:
680 case CS42L51_AOUTB_VOL:
681 case CS42L51_PCM_MIXER:
682 case CS42L51_LIMIT_THRES_DIS:
683 case CS42L51_LIMIT_REL:
684 case CS42L51_LIMIT_ATT:
685 case CS42L51_ALC_EN:
686 case CS42L51_ALC_REL:
687 case CS42L51_ALC_THRES:
688 case CS42L51_NOISE_CONF:
689 case CS42L51_STATUS:
690 case CS42L51_CHARGE_FREQ:
691 return true;
692 default:
693 return false;
694 }
695}
696
697const struct regmap_config cs42l51_regmap = {
698 .reg_bits = 8,
699 .reg_stride = 1,
700 .val_bits = 8,
701 .use_single_write = true,
702 .readable_reg = cs42l51_readable_reg,
703 .volatile_reg = cs42l51_volatile_reg,
704 .writeable_reg = cs42l51_writeable_reg,
705 .max_register = CS42L51_CHARGE_FREQ,
706 .cache_type = REGCACHE_MAPLE,
707};
708EXPORT_SYMBOL_GPL(cs42l51_regmap);
709
710int cs42l51_probe(struct device *dev, struct regmap *regmap)
711{
712 struct cs42l51_private *cs42l51;
713 unsigned int val;
714 int ret, i;
715
716 if (IS_ERR(regmap))
717 return PTR_ERR(regmap);
718
719 cs42l51 = devm_kzalloc(dev, sizeof(struct cs42l51_private),
720 GFP_KERNEL);
721 if (!cs42l51)
722 return -ENOMEM;
723
724 dev_set_drvdata(dev, cs42l51);
725 cs42l51->regmap = regmap;
726
727 cs42l51->mclk_handle = devm_clk_get_optional(dev, "MCLK");
728 if (IS_ERR(cs42l51->mclk_handle))
729 return PTR_ERR(cs42l51->mclk_handle);
730
731 for (i = 0; i < ARRAY_SIZE(cs42l51->supplies); i++)
732 cs42l51->supplies[i].supply = cs42l51_supply_names[i];
733
734 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs42l51->supplies),
735 cs42l51->supplies);
736 if (ret != 0) {
737 dev_err(dev, "Failed to request supplies: %d\n", ret);
738 return ret;
739 }
740
741 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l51->supplies),
742 cs42l51->supplies);
743 if (ret != 0) {
744 dev_err(dev, "Failed to enable supplies: %d\n", ret);
745 return ret;
746 }
747
748 cs42l51->reset_gpio = devm_gpiod_get_optional(dev, "reset",
749 GPIOD_OUT_LOW);
750 if (IS_ERR(cs42l51->reset_gpio)) {
751 ret = PTR_ERR(cs42l51->reset_gpio);
752 goto error;
753 }
754
755 if (cs42l51->reset_gpio) {
756 dev_dbg(dev, "Release reset gpio\n");
757 gpiod_set_value_cansleep(cs42l51->reset_gpio, 0);
758 mdelay(2);
759 }
760
761 /* Verify that we have a CS42L51 */
762 ret = regmap_read(regmap, CS42L51_CHIP_REV_ID, &val);
763 if (ret < 0) {
764 dev_err(dev, "failed to read I2C\n");
765 goto error;
766 }
767
768 if ((val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) &&
769 (val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) {
770 dev_err(dev, "Invalid chip id: %x\n", val);
771 ret = -ENODEV;
772 goto error;
773 }
774 dev_info(dev, "Cirrus Logic CS42L51, Revision: %02X\n",
775 val & CS42L51_CHIP_REV_MASK);
776
777 ret = devm_snd_soc_register_component(dev,
778 &soc_component_device_cs42l51, &cs42l51_dai, 1);
779 if (ret < 0)
780 goto error;
781
782 return 0;
783
784error:
785 gpiod_set_value_cansleep(cs42l51->reset_gpio, 1);
786 regulator_bulk_disable(ARRAY_SIZE(cs42l51->supplies),
787 cs42l51->supplies);
788 return ret;
789}
790EXPORT_SYMBOL_GPL(cs42l51_probe);
791
792void cs42l51_remove(struct device *dev)
793{
794 struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
795 int ret;
796
797 gpiod_set_value_cansleep(cs42l51->reset_gpio, 1);
798
799 ret = regulator_bulk_disable(ARRAY_SIZE(cs42l51->supplies),
800 cs42l51->supplies);
801 if (ret)
802 dev_warn(dev, "Failed to disable all regulators (%pe)\n",
803 ERR_PTR(ret));
804
805}
806EXPORT_SYMBOL_GPL(cs42l51_remove);
807
808int __maybe_unused cs42l51_suspend(struct device *dev)
809{
810 struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
811
812 regcache_cache_only(cs42l51->regmap, true);
813 regcache_mark_dirty(cs42l51->regmap);
814
815 return 0;
816}
817EXPORT_SYMBOL_GPL(cs42l51_suspend);
818
819int __maybe_unused cs42l51_resume(struct device *dev)
820{
821 struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
822
823 regcache_cache_only(cs42l51->regmap, false);
824
825 return regcache_sync(cs42l51->regmap);
826}
827EXPORT_SYMBOL_GPL(cs42l51_resume);
828
829MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
830MODULE_DESCRIPTION("Cirrus Logic CS42L51 ALSA SoC Codec Driver");
831MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * cs42l51.c
4 *
5 * ASoC Driver for Cirrus Logic CS42L51 codecs
6 *
7 * Copyright (c) 2010 Arnaud Patard <apatard@mandriva.com>
8 *
9 * Based on cs4270.c - Copyright (c) Freescale Semiconductor
10 *
11 * For now:
12 * - Only I2C is support. Not SPI
13 * - master mode *NOT* supported
14 */
15
16#include <linux/clk.h>
17#include <linux/module.h>
18#include <linux/slab.h>
19#include <sound/core.h>
20#include <sound/soc.h>
21#include <sound/tlv.h>
22#include <sound/initval.h>
23#include <sound/pcm_params.h>
24#include <sound/pcm.h>
25#include <linux/gpio/consumer.h>
26#include <linux/regmap.h>
27#include <linux/regulator/consumer.h>
28
29#include "cs42l51.h"
30
31enum master_slave_mode {
32 MODE_SLAVE,
33 MODE_SLAVE_AUTO,
34 MODE_MASTER,
35};
36
37static const char * const cs42l51_supply_names[] = {
38 "VL",
39 "VD",
40 "VA",
41 "VAHP",
42};
43
44struct cs42l51_private {
45 unsigned int mclk;
46 struct clk *mclk_handle;
47 unsigned int audio_mode; /* The mode (I2S or left-justified) */
48 enum master_slave_mode func;
49 struct regulator_bulk_data supplies[ARRAY_SIZE(cs42l51_supply_names)];
50 struct gpio_desc *reset_gpio;
51 struct regmap *regmap;
52};
53
54#define CS42L51_FORMATS ( \
55 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
56 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \
57 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \
58 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE)
59
60static int cs42l51_get_chan_mix(struct snd_kcontrol *kcontrol,
61 struct snd_ctl_elem_value *ucontrol)
62{
63 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
64 unsigned long value = snd_soc_component_read(component, CS42L51_PCM_MIXER)&3;
65
66 switch (value) {
67 default:
68 case 0:
69 ucontrol->value.enumerated.item[0] = 0;
70 break;
71 /* same value : (L+R)/2 and (R+L)/2 */
72 case 1:
73 case 2:
74 ucontrol->value.enumerated.item[0] = 1;
75 break;
76 case 3:
77 ucontrol->value.enumerated.item[0] = 2;
78 break;
79 }
80
81 return 0;
82}
83
84#define CHAN_MIX_NORMAL 0x00
85#define CHAN_MIX_BOTH 0x55
86#define CHAN_MIX_SWAP 0xFF
87
88static int cs42l51_set_chan_mix(struct snd_kcontrol *kcontrol,
89 struct snd_ctl_elem_value *ucontrol)
90{
91 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
92 unsigned char val;
93
94 switch (ucontrol->value.enumerated.item[0]) {
95 default:
96 case 0:
97 val = CHAN_MIX_NORMAL;
98 break;
99 case 1:
100 val = CHAN_MIX_BOTH;
101 break;
102 case 2:
103 val = CHAN_MIX_SWAP;
104 break;
105 }
106
107 snd_soc_component_write(component, CS42L51_PCM_MIXER, val);
108
109 return 1;
110}
111
112static const DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -5150, 50, 0);
113static const DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 150, 0);
114
115static const DECLARE_TLV_DB_SCALE(aout_tlv, -10200, 50, 0);
116
117static const DECLARE_TLV_DB_SCALE(boost_tlv, 1600, 1600, 0);
118static const DECLARE_TLV_DB_SCALE(adc_boost_tlv, 2000, 2000, 0);
119static const char *chan_mix[] = {
120 "L R",
121 "L+R",
122 "R L",
123};
124
125static SOC_ENUM_SINGLE_EXT_DECL(cs42l51_chan_mix, chan_mix);
126
127static const struct snd_kcontrol_new cs42l51_snd_controls[] = {
128 SOC_DOUBLE_R_SX_TLV("PCM Playback Volume",
129 CS42L51_PCMA_VOL, CS42L51_PCMB_VOL,
130 0, 0x19, 0x7F, adc_pcm_tlv),
131 SOC_DOUBLE_R("PCM Playback Switch",
132 CS42L51_PCMA_VOL, CS42L51_PCMB_VOL, 7, 1, 1),
133 SOC_DOUBLE_R_SX_TLV("Analog Playback Volume",
134 CS42L51_AOUTA_VOL, CS42L51_AOUTB_VOL,
135 0, 0x34, 0xE4, aout_tlv),
136 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
137 CS42L51_ADCA_VOL, CS42L51_ADCB_VOL,
138 0, 0x19, 0x7F, adc_pcm_tlv),
139 SOC_DOUBLE_R("ADC Mixer Switch",
140 CS42L51_ADCA_VOL, CS42L51_ADCB_VOL, 7, 1, 1),
141 SOC_SINGLE("Playback Deemphasis Switch", CS42L51_DAC_CTL, 3, 1, 0),
142 SOC_SINGLE("Auto-Mute Switch", CS42L51_DAC_CTL, 2, 1, 0),
143 SOC_SINGLE("Soft Ramp Switch", CS42L51_DAC_CTL, 1, 1, 0),
144 SOC_SINGLE("Zero Cross Switch", CS42L51_DAC_CTL, 0, 0, 0),
145 SOC_DOUBLE_TLV("Mic Boost Volume",
146 CS42L51_MIC_CTL, 0, 1, 1, 0, boost_tlv),
147 SOC_DOUBLE_TLV("ADC Boost Volume",
148 CS42L51_MIC_CTL, 5, 6, 1, 0, adc_boost_tlv),
149 SOC_SINGLE_TLV("Bass Volume", CS42L51_TONE_CTL, 0, 0xf, 1, tone_tlv),
150 SOC_SINGLE_TLV("Treble Volume", CS42L51_TONE_CTL, 4, 0xf, 1, tone_tlv),
151 SOC_ENUM_EXT("PCM channel mixer",
152 cs42l51_chan_mix,
153 cs42l51_get_chan_mix, cs42l51_set_chan_mix),
154};
155
156/*
157 * to power down, one must:
158 * 1.) Enable the PDN bit
159 * 2.) enable power-down for the select channels
160 * 3.) disable the PDN bit.
161 */
162static int cs42l51_pdn_event(struct snd_soc_dapm_widget *w,
163 struct snd_kcontrol *kcontrol, int event)
164{
165 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
166
167 switch (event) {
168 case SND_SOC_DAPM_PRE_PMD:
169 snd_soc_component_update_bits(component, CS42L51_POWER_CTL1,
170 CS42L51_POWER_CTL1_PDN,
171 CS42L51_POWER_CTL1_PDN);
172 break;
173 default:
174 case SND_SOC_DAPM_POST_PMD:
175 snd_soc_component_update_bits(component, CS42L51_POWER_CTL1,
176 CS42L51_POWER_CTL1_PDN, 0);
177 break;
178 }
179
180 return 0;
181}
182
183static const char *cs42l51_dac_names[] = {"Direct PCM",
184 "DSP PCM", "ADC"};
185static SOC_ENUM_SINGLE_DECL(cs42l51_dac_mux_enum,
186 CS42L51_DAC_CTL, 6, cs42l51_dac_names);
187static const struct snd_kcontrol_new cs42l51_dac_mux_controls =
188 SOC_DAPM_ENUM("Route", cs42l51_dac_mux_enum);
189
190static const char *cs42l51_adcl_names[] = {"AIN1 Left", "AIN2 Left",
191 "MIC Left", "MIC+preamp Left"};
192static SOC_ENUM_SINGLE_DECL(cs42l51_adcl_mux_enum,
193 CS42L51_ADC_INPUT, 4, cs42l51_adcl_names);
194static const struct snd_kcontrol_new cs42l51_adcl_mux_controls =
195 SOC_DAPM_ENUM("Route", cs42l51_adcl_mux_enum);
196
197static const char *cs42l51_adcr_names[] = {"AIN1 Right", "AIN2 Right",
198 "MIC Right", "MIC+preamp Right"};
199static SOC_ENUM_SINGLE_DECL(cs42l51_adcr_mux_enum,
200 CS42L51_ADC_INPUT, 6, cs42l51_adcr_names);
201static const struct snd_kcontrol_new cs42l51_adcr_mux_controls =
202 SOC_DAPM_ENUM("Route", cs42l51_adcr_mux_enum);
203
204static const struct snd_soc_dapm_widget cs42l51_dapm_widgets[] = {
205 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L51_MIC_POWER_CTL, 1, 1, NULL,
206 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
207 SND_SOC_DAPM_PGA_E("Left PGA", CS42L51_POWER_CTL1, 3, 1, NULL, 0,
208 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
209 SND_SOC_DAPM_PGA_E("Right PGA", CS42L51_POWER_CTL1, 4, 1, NULL, 0,
210 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
211 SND_SOC_DAPM_ADC_E("Left ADC", "Left HiFi Capture",
212 CS42L51_POWER_CTL1, 1, 1,
213 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
214 SND_SOC_DAPM_ADC_E("Right ADC", "Right HiFi Capture",
215 CS42L51_POWER_CTL1, 2, 1,
216 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
217 SND_SOC_DAPM_DAC_E("Left DAC", NULL, CS42L51_POWER_CTL1, 5, 1,
218 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
219 SND_SOC_DAPM_DAC_E("Right DAC", NULL, CS42L51_POWER_CTL1, 6, 1,
220 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
221
222 /* analog/mic */
223 SND_SOC_DAPM_INPUT("AIN1L"),
224 SND_SOC_DAPM_INPUT("AIN1R"),
225 SND_SOC_DAPM_INPUT("AIN2L"),
226 SND_SOC_DAPM_INPUT("AIN2R"),
227 SND_SOC_DAPM_INPUT("MICL"),
228 SND_SOC_DAPM_INPUT("MICR"),
229
230 SND_SOC_DAPM_MIXER("Mic Preamp Left",
231 CS42L51_MIC_POWER_CTL, 2, 1, NULL, 0),
232 SND_SOC_DAPM_MIXER("Mic Preamp Right",
233 CS42L51_MIC_POWER_CTL, 3, 1, NULL, 0),
234
235 /* HP */
236 SND_SOC_DAPM_OUTPUT("HPL"),
237 SND_SOC_DAPM_OUTPUT("HPR"),
238
239 /* mux */
240 SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
241 &cs42l51_dac_mux_controls),
242 SND_SOC_DAPM_MUX("PGA-ADC Mux Left", SND_SOC_NOPM, 0, 0,
243 &cs42l51_adcl_mux_controls),
244 SND_SOC_DAPM_MUX("PGA-ADC Mux Right", SND_SOC_NOPM, 0, 0,
245 &cs42l51_adcr_mux_controls),
246};
247
248static const struct snd_soc_dapm_widget cs42l51_dapm_mclk_widgets[] = {
249 SND_SOC_DAPM_CLOCK_SUPPLY("MCLK")
250};
251
252static const struct snd_soc_dapm_route cs42l51_routes[] = {
253 {"HPL", NULL, "Left DAC"},
254 {"HPR", NULL, "Right DAC"},
255
256 {"Right DAC", NULL, "DAC Mux"},
257 {"Left DAC", NULL, "DAC Mux"},
258
259 {"DAC Mux", "Direct PCM", "Playback"},
260 {"DAC Mux", "DSP PCM", "Playback"},
261
262 {"Left ADC", NULL, "Left PGA"},
263 {"Right ADC", NULL, "Right PGA"},
264
265 {"Mic Preamp Left", NULL, "MICL"},
266 {"Mic Preamp Right", NULL, "MICR"},
267
268 {"PGA-ADC Mux Left", "AIN1 Left", "AIN1L" },
269 {"PGA-ADC Mux Left", "AIN2 Left", "AIN2L" },
270 {"PGA-ADC Mux Left", "MIC Left", "MICL" },
271 {"PGA-ADC Mux Left", "MIC+preamp Left", "Mic Preamp Left" },
272 {"PGA-ADC Mux Right", "AIN1 Right", "AIN1R" },
273 {"PGA-ADC Mux Right", "AIN2 Right", "AIN2R" },
274 {"PGA-ADC Mux Right", "MIC Right", "MICR" },
275 {"PGA-ADC Mux Right", "MIC+preamp Right", "Mic Preamp Right" },
276
277 {"Left PGA", NULL, "PGA-ADC Mux Left"},
278 {"Right PGA", NULL, "PGA-ADC Mux Right"},
279};
280
281static int cs42l51_set_dai_fmt(struct snd_soc_dai *codec_dai,
282 unsigned int format)
283{
284 struct snd_soc_component *component = codec_dai->component;
285 struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
286
287 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
288 case SND_SOC_DAIFMT_I2S:
289 case SND_SOC_DAIFMT_LEFT_J:
290 case SND_SOC_DAIFMT_RIGHT_J:
291 cs42l51->audio_mode = format & SND_SOC_DAIFMT_FORMAT_MASK;
292 break;
293 default:
294 dev_err(component->dev, "invalid DAI format\n");
295 return -EINVAL;
296 }
297
298 switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
299 case SND_SOC_DAIFMT_CBM_CFM:
300 cs42l51->func = MODE_MASTER;
301 break;
302 case SND_SOC_DAIFMT_CBS_CFS:
303 cs42l51->func = MODE_SLAVE_AUTO;
304 break;
305 default:
306 dev_err(component->dev, "Unknown master/slave configuration\n");
307 return -EINVAL;
308 }
309
310 return 0;
311}
312
313struct cs42l51_ratios {
314 unsigned int ratio;
315 unsigned char speed_mode;
316 unsigned char mclk;
317};
318
319static struct cs42l51_ratios slave_ratios[] = {
320 { 512, CS42L51_QSM_MODE, 0 }, { 768, CS42L51_QSM_MODE, 0 },
321 { 1024, CS42L51_QSM_MODE, 0 }, { 1536, CS42L51_QSM_MODE, 0 },
322 { 2048, CS42L51_QSM_MODE, 0 }, { 3072, CS42L51_QSM_MODE, 0 },
323 { 256, CS42L51_HSM_MODE, 0 }, { 384, CS42L51_HSM_MODE, 0 },
324 { 512, CS42L51_HSM_MODE, 0 }, { 768, CS42L51_HSM_MODE, 0 },
325 { 1024, CS42L51_HSM_MODE, 0 }, { 1536, CS42L51_HSM_MODE, 0 },
326 { 128, CS42L51_SSM_MODE, 0 }, { 192, CS42L51_SSM_MODE, 0 },
327 { 256, CS42L51_SSM_MODE, 0 }, { 384, CS42L51_SSM_MODE, 0 },
328 { 512, CS42L51_SSM_MODE, 0 }, { 768, CS42L51_SSM_MODE, 0 },
329 { 128, CS42L51_DSM_MODE, 0 }, { 192, CS42L51_DSM_MODE, 0 },
330 { 256, CS42L51_DSM_MODE, 0 }, { 384, CS42L51_DSM_MODE, 0 },
331};
332
333static struct cs42l51_ratios slave_auto_ratios[] = {
334 { 1024, CS42L51_QSM_MODE, 0 }, { 1536, CS42L51_QSM_MODE, 0 },
335 { 2048, CS42L51_QSM_MODE, 1 }, { 3072, CS42L51_QSM_MODE, 1 },
336 { 512, CS42L51_HSM_MODE, 0 }, { 768, CS42L51_HSM_MODE, 0 },
337 { 1024, CS42L51_HSM_MODE, 1 }, { 1536, CS42L51_HSM_MODE, 1 },
338 { 256, CS42L51_SSM_MODE, 0 }, { 384, CS42L51_SSM_MODE, 0 },
339 { 512, CS42L51_SSM_MODE, 1 }, { 768, CS42L51_SSM_MODE, 1 },
340 { 128, CS42L51_DSM_MODE, 0 }, { 192, CS42L51_DSM_MODE, 0 },
341 { 256, CS42L51_DSM_MODE, 1 }, { 384, CS42L51_DSM_MODE, 1 },
342};
343
344/*
345 * Master mode mclk/fs ratios.
346 * Recommended configurations are SSM for 4-50khz and DSM for 50-100kHz ranges
347 * The table below provides support of following ratios:
348 * 128: SSM (%128) with div2 disabled
349 * 256: SSM (%128) with div2 enabled
350 * In both cases, if sampling rate is above 50kHz, SSM is overridden
351 * with DSM (%128) configuration
352 */
353static struct cs42l51_ratios master_ratios[] = {
354 { 128, CS42L51_SSM_MODE, 0 }, { 256, CS42L51_SSM_MODE, 1 },
355};
356
357static int cs42l51_set_dai_sysclk(struct snd_soc_dai *codec_dai,
358 int clk_id, unsigned int freq, int dir)
359{
360 struct snd_soc_component *component = codec_dai->component;
361 struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
362
363 cs42l51->mclk = freq;
364 return 0;
365}
366
367static int cs42l51_hw_params(struct snd_pcm_substream *substream,
368 struct snd_pcm_hw_params *params,
369 struct snd_soc_dai *dai)
370{
371 struct snd_soc_component *component = dai->component;
372 struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
373 int ret;
374 unsigned int i;
375 unsigned int rate;
376 unsigned int ratio;
377 struct cs42l51_ratios *ratios = NULL;
378 int nr_ratios = 0;
379 int intf_ctl, power_ctl, fmt, mode;
380
381 switch (cs42l51->func) {
382 case MODE_MASTER:
383 ratios = master_ratios;
384 nr_ratios = ARRAY_SIZE(master_ratios);
385 break;
386 case MODE_SLAVE:
387 ratios = slave_ratios;
388 nr_ratios = ARRAY_SIZE(slave_ratios);
389 break;
390 case MODE_SLAVE_AUTO:
391 ratios = slave_auto_ratios;
392 nr_ratios = ARRAY_SIZE(slave_auto_ratios);
393 break;
394 }
395
396 /* Figure out which MCLK/LRCK ratio to use */
397 rate = params_rate(params); /* Sampling rate, in Hz */
398 ratio = cs42l51->mclk / rate; /* MCLK/LRCK ratio */
399 for (i = 0; i < nr_ratios; i++) {
400 if (ratios[i].ratio == ratio)
401 break;
402 }
403
404 if (i == nr_ratios) {
405 /* We did not find a matching ratio */
406 dev_err(component->dev, "could not find matching ratio\n");
407 return -EINVAL;
408 }
409
410 intf_ctl = snd_soc_component_read(component, CS42L51_INTF_CTL);
411 power_ctl = snd_soc_component_read(component, CS42L51_MIC_POWER_CTL);
412
413 intf_ctl &= ~(CS42L51_INTF_CTL_MASTER | CS42L51_INTF_CTL_ADC_I2S
414 | CS42L51_INTF_CTL_DAC_FORMAT(7));
415 power_ctl &= ~(CS42L51_MIC_POWER_CTL_SPEED(3)
416 | CS42L51_MIC_POWER_CTL_MCLK_DIV2);
417
418 switch (cs42l51->func) {
419 case MODE_MASTER:
420 intf_ctl |= CS42L51_INTF_CTL_MASTER;
421 mode = ratios[i].speed_mode;
422 /* Force DSM mode if sampling rate is above 50kHz */
423 if (rate > 50000)
424 mode = CS42L51_DSM_MODE;
425 power_ctl |= CS42L51_MIC_POWER_CTL_SPEED(mode);
426 /*
427 * Auto detect mode is not applicable for master mode and has to
428 * be disabled. Otherwise SPEED[1:0] bits will be ignored.
429 */
430 power_ctl &= ~CS42L51_MIC_POWER_CTL_AUTO;
431 break;
432 case MODE_SLAVE:
433 power_ctl |= CS42L51_MIC_POWER_CTL_SPEED(ratios[i].speed_mode);
434 break;
435 case MODE_SLAVE_AUTO:
436 power_ctl |= CS42L51_MIC_POWER_CTL_AUTO;
437 break;
438 }
439
440 switch (cs42l51->audio_mode) {
441 case SND_SOC_DAIFMT_I2S:
442 intf_ctl |= CS42L51_INTF_CTL_ADC_I2S;
443 intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(CS42L51_DAC_DIF_I2S);
444 break;
445 case SND_SOC_DAIFMT_LEFT_J:
446 intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(CS42L51_DAC_DIF_LJ24);
447 break;
448 case SND_SOC_DAIFMT_RIGHT_J:
449 switch (params_width(params)) {
450 case 16:
451 fmt = CS42L51_DAC_DIF_RJ16;
452 break;
453 case 18:
454 fmt = CS42L51_DAC_DIF_RJ18;
455 break;
456 case 20:
457 fmt = CS42L51_DAC_DIF_RJ20;
458 break;
459 case 24:
460 fmt = CS42L51_DAC_DIF_RJ24;
461 break;
462 default:
463 dev_err(component->dev, "unknown format\n");
464 return -EINVAL;
465 }
466 intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(fmt);
467 break;
468 default:
469 dev_err(component->dev, "unknown format\n");
470 return -EINVAL;
471 }
472
473 if (ratios[i].mclk)
474 power_ctl |= CS42L51_MIC_POWER_CTL_MCLK_DIV2;
475
476 ret = snd_soc_component_write(component, CS42L51_INTF_CTL, intf_ctl);
477 if (ret < 0)
478 return ret;
479
480 ret = snd_soc_component_write(component, CS42L51_MIC_POWER_CTL, power_ctl);
481 if (ret < 0)
482 return ret;
483
484 return 0;
485}
486
487static int cs42l51_dai_mute(struct snd_soc_dai *dai, int mute, int direction)
488{
489 struct snd_soc_component *component = dai->component;
490 int reg;
491 int mask = CS42L51_DAC_OUT_CTL_DACA_MUTE|CS42L51_DAC_OUT_CTL_DACB_MUTE;
492
493 reg = snd_soc_component_read(component, CS42L51_DAC_OUT_CTL);
494
495 if (mute)
496 reg |= mask;
497 else
498 reg &= ~mask;
499
500 return snd_soc_component_write(component, CS42L51_DAC_OUT_CTL, reg);
501}
502
503static int cs42l51_of_xlate_dai_id(struct snd_soc_component *component,
504 struct device_node *endpoint)
505{
506 /* return dai id 0, whatever the endpoint index */
507 return 0;
508}
509
510static const struct snd_soc_dai_ops cs42l51_dai_ops = {
511 .hw_params = cs42l51_hw_params,
512 .set_sysclk = cs42l51_set_dai_sysclk,
513 .set_fmt = cs42l51_set_dai_fmt,
514 .mute_stream = cs42l51_dai_mute,
515 .no_capture_mute = 1,
516};
517
518static struct snd_soc_dai_driver cs42l51_dai = {
519 .name = "cs42l51-hifi",
520 .playback = {
521 .stream_name = "Playback",
522 .channels_min = 1,
523 .channels_max = 2,
524 .rates = SNDRV_PCM_RATE_8000_96000,
525 .formats = CS42L51_FORMATS,
526 },
527 .capture = {
528 .stream_name = "Capture",
529 .channels_min = 1,
530 .channels_max = 2,
531 .rates = SNDRV_PCM_RATE_8000_96000,
532 .formats = CS42L51_FORMATS,
533 },
534 .ops = &cs42l51_dai_ops,
535};
536
537static int cs42l51_component_probe(struct snd_soc_component *component)
538{
539 int ret, reg;
540 struct snd_soc_dapm_context *dapm;
541 struct cs42l51_private *cs42l51;
542
543 cs42l51 = snd_soc_component_get_drvdata(component);
544 dapm = snd_soc_component_get_dapm(component);
545
546 if (cs42l51->mclk_handle)
547 snd_soc_dapm_new_controls(dapm, cs42l51_dapm_mclk_widgets, 1);
548
549 /*
550 * DAC configuration
551 * - Use signal processor
552 * - auto mute
553 * - vol changes immediate
554 * - no de-emphasize
555 */
556 reg = CS42L51_DAC_CTL_DATA_SEL(1)
557 | CS42L51_DAC_CTL_AMUTE | CS42L51_DAC_CTL_DACSZ(0);
558 ret = snd_soc_component_write(component, CS42L51_DAC_CTL, reg);
559 if (ret < 0)
560 return ret;
561
562 return 0;
563}
564
565static const struct snd_soc_component_driver soc_component_device_cs42l51 = {
566 .probe = cs42l51_component_probe,
567 .controls = cs42l51_snd_controls,
568 .num_controls = ARRAY_SIZE(cs42l51_snd_controls),
569 .dapm_widgets = cs42l51_dapm_widgets,
570 .num_dapm_widgets = ARRAY_SIZE(cs42l51_dapm_widgets),
571 .dapm_routes = cs42l51_routes,
572 .num_dapm_routes = ARRAY_SIZE(cs42l51_routes),
573 .of_xlate_dai_id = cs42l51_of_xlate_dai_id,
574 .idle_bias_on = 1,
575 .use_pmdown_time = 1,
576 .endianness = 1,
577 .non_legacy_dai_naming = 1,
578};
579
580static bool cs42l51_writeable_reg(struct device *dev, unsigned int reg)
581{
582 switch (reg) {
583 case CS42L51_POWER_CTL1:
584 case CS42L51_MIC_POWER_CTL:
585 case CS42L51_INTF_CTL:
586 case CS42L51_MIC_CTL:
587 case CS42L51_ADC_CTL:
588 case CS42L51_ADC_INPUT:
589 case CS42L51_DAC_OUT_CTL:
590 case CS42L51_DAC_CTL:
591 case CS42L51_ALC_PGA_CTL:
592 case CS42L51_ALC_PGB_CTL:
593 case CS42L51_ADCA_ATT:
594 case CS42L51_ADCB_ATT:
595 case CS42L51_ADCA_VOL:
596 case CS42L51_ADCB_VOL:
597 case CS42L51_PCMA_VOL:
598 case CS42L51_PCMB_VOL:
599 case CS42L51_BEEP_FREQ:
600 case CS42L51_BEEP_VOL:
601 case CS42L51_BEEP_CONF:
602 case CS42L51_TONE_CTL:
603 case CS42L51_AOUTA_VOL:
604 case CS42L51_AOUTB_VOL:
605 case CS42L51_PCM_MIXER:
606 case CS42L51_LIMIT_THRES_DIS:
607 case CS42L51_LIMIT_REL:
608 case CS42L51_LIMIT_ATT:
609 case CS42L51_ALC_EN:
610 case CS42L51_ALC_REL:
611 case CS42L51_ALC_THRES:
612 case CS42L51_NOISE_CONF:
613 case CS42L51_CHARGE_FREQ:
614 return true;
615 default:
616 return false;
617 }
618}
619
620static bool cs42l51_volatile_reg(struct device *dev, unsigned int reg)
621{
622 switch (reg) {
623 case CS42L51_STATUS:
624 return true;
625 default:
626 return false;
627 }
628}
629
630static bool cs42l51_readable_reg(struct device *dev, unsigned int reg)
631{
632 switch (reg) {
633 case CS42L51_CHIP_REV_ID:
634 case CS42L51_POWER_CTL1:
635 case CS42L51_MIC_POWER_CTL:
636 case CS42L51_INTF_CTL:
637 case CS42L51_MIC_CTL:
638 case CS42L51_ADC_CTL:
639 case CS42L51_ADC_INPUT:
640 case CS42L51_DAC_OUT_CTL:
641 case CS42L51_DAC_CTL:
642 case CS42L51_ALC_PGA_CTL:
643 case CS42L51_ALC_PGB_CTL:
644 case CS42L51_ADCA_ATT:
645 case CS42L51_ADCB_ATT:
646 case CS42L51_ADCA_VOL:
647 case CS42L51_ADCB_VOL:
648 case CS42L51_PCMA_VOL:
649 case CS42L51_PCMB_VOL:
650 case CS42L51_BEEP_FREQ:
651 case CS42L51_BEEP_VOL:
652 case CS42L51_BEEP_CONF:
653 case CS42L51_TONE_CTL:
654 case CS42L51_AOUTA_VOL:
655 case CS42L51_AOUTB_VOL:
656 case CS42L51_PCM_MIXER:
657 case CS42L51_LIMIT_THRES_DIS:
658 case CS42L51_LIMIT_REL:
659 case CS42L51_LIMIT_ATT:
660 case CS42L51_ALC_EN:
661 case CS42L51_ALC_REL:
662 case CS42L51_ALC_THRES:
663 case CS42L51_NOISE_CONF:
664 case CS42L51_STATUS:
665 case CS42L51_CHARGE_FREQ:
666 return true;
667 default:
668 return false;
669 }
670}
671
672const struct regmap_config cs42l51_regmap = {
673 .reg_bits = 8,
674 .reg_stride = 1,
675 .val_bits = 8,
676 .use_single_write = true,
677 .readable_reg = cs42l51_readable_reg,
678 .volatile_reg = cs42l51_volatile_reg,
679 .writeable_reg = cs42l51_writeable_reg,
680 .max_register = CS42L51_CHARGE_FREQ,
681 .cache_type = REGCACHE_RBTREE,
682};
683EXPORT_SYMBOL_GPL(cs42l51_regmap);
684
685int cs42l51_probe(struct device *dev, struct regmap *regmap)
686{
687 struct cs42l51_private *cs42l51;
688 unsigned int val;
689 int ret, i;
690
691 if (IS_ERR(regmap))
692 return PTR_ERR(regmap);
693
694 cs42l51 = devm_kzalloc(dev, sizeof(struct cs42l51_private),
695 GFP_KERNEL);
696 if (!cs42l51)
697 return -ENOMEM;
698
699 dev_set_drvdata(dev, cs42l51);
700 cs42l51->regmap = regmap;
701
702 cs42l51->mclk_handle = devm_clk_get(dev, "MCLK");
703 if (IS_ERR(cs42l51->mclk_handle)) {
704 if (PTR_ERR(cs42l51->mclk_handle) != -ENOENT)
705 return PTR_ERR(cs42l51->mclk_handle);
706 cs42l51->mclk_handle = NULL;
707 }
708
709 for (i = 0; i < ARRAY_SIZE(cs42l51->supplies); i++)
710 cs42l51->supplies[i].supply = cs42l51_supply_names[i];
711
712 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs42l51->supplies),
713 cs42l51->supplies);
714 if (ret != 0) {
715 dev_err(dev, "Failed to request supplies: %d\n", ret);
716 return ret;
717 }
718
719 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l51->supplies),
720 cs42l51->supplies);
721 if (ret != 0) {
722 dev_err(dev, "Failed to enable supplies: %d\n", ret);
723 return ret;
724 }
725
726 cs42l51->reset_gpio = devm_gpiod_get_optional(dev, "reset",
727 GPIOD_OUT_LOW);
728 if (IS_ERR(cs42l51->reset_gpio))
729 return PTR_ERR(cs42l51->reset_gpio);
730
731 if (cs42l51->reset_gpio) {
732 dev_dbg(dev, "Release reset gpio\n");
733 gpiod_set_value_cansleep(cs42l51->reset_gpio, 0);
734 mdelay(2);
735 }
736
737 /* Verify that we have a CS42L51 */
738 ret = regmap_read(regmap, CS42L51_CHIP_REV_ID, &val);
739 if (ret < 0) {
740 dev_err(dev, "failed to read I2C\n");
741 goto error;
742 }
743
744 if ((val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) &&
745 (val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) {
746 dev_err(dev, "Invalid chip id: %x\n", val);
747 ret = -ENODEV;
748 goto error;
749 }
750 dev_info(dev, "Cirrus Logic CS42L51, Revision: %02X\n",
751 val & CS42L51_CHIP_REV_MASK);
752
753 ret = devm_snd_soc_register_component(dev,
754 &soc_component_device_cs42l51, &cs42l51_dai, 1);
755 if (ret < 0)
756 goto error;
757
758 return 0;
759
760error:
761 regulator_bulk_disable(ARRAY_SIZE(cs42l51->supplies),
762 cs42l51->supplies);
763 return ret;
764}
765EXPORT_SYMBOL_GPL(cs42l51_probe);
766
767int cs42l51_remove(struct device *dev)
768{
769 struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
770
771 gpiod_set_value_cansleep(cs42l51->reset_gpio, 1);
772
773 return regulator_bulk_disable(ARRAY_SIZE(cs42l51->supplies),
774 cs42l51->supplies);
775}
776EXPORT_SYMBOL_GPL(cs42l51_remove);
777
778int __maybe_unused cs42l51_suspend(struct device *dev)
779{
780 struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
781
782 regcache_cache_only(cs42l51->regmap, true);
783 regcache_mark_dirty(cs42l51->regmap);
784
785 return 0;
786}
787EXPORT_SYMBOL_GPL(cs42l51_suspend);
788
789int __maybe_unused cs42l51_resume(struct device *dev)
790{
791 struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
792
793 regcache_cache_only(cs42l51->regmap, false);
794
795 return regcache_sync(cs42l51->regmap);
796}
797EXPORT_SYMBOL_GPL(cs42l51_resume);
798
799const struct of_device_id cs42l51_of_match[] = {
800 { .compatible = "cirrus,cs42l51", },
801 { }
802};
803MODULE_DEVICE_TABLE(of, cs42l51_of_match);
804EXPORT_SYMBOL_GPL(cs42l51_of_match);
805
806MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
807MODULE_DESCRIPTION("Cirrus Logic CS42L51 ALSA SoC Codec Driver");
808MODULE_LICENSE("GPL");