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1// SPDX-License-Identifier: GPL-2.0-only
2
3#include <linux/completion.h>
4#include <linux/dma-mapping.h>
5#include <linux/interrupt.h>
6#include <linux/mod_devicetable.h>
7#include <linux/platform_device.h>
8#include <linux/regmap.h>
9#include <linux/spi/spi.h>
10#include <linux/spi/spi-mem.h>
11
12#define SNAFCFR 0x00
13#define SNAFCFR_DMA_IE BIT(20)
14#define SNAFCCR 0x04
15#define SNAFWCMR 0x08
16#define SNAFRCMR 0x0c
17#define SNAFRDR 0x10
18#define SNAFWDR 0x14
19#define SNAFDTR 0x18
20#define SNAFDRSAR 0x1c
21#define SNAFDIR 0x20
22#define SNAFDIR_DMA_IP BIT(0)
23#define SNAFDLR 0x24
24#define SNAFSR 0x40
25#define SNAFSR_NFCOS BIT(3)
26#define SNAFSR_NFDRS BIT(2)
27#define SNAFSR_NFDWS BIT(1)
28
29#define CMR_LEN(len) ((len) - 1)
30#define CMR_WID(width) (((width) >> 1) << 28)
31
32struct rtl_snand {
33 struct device *dev;
34 struct regmap *regmap;
35 struct completion comp;
36};
37
38static irqreturn_t rtl_snand_irq(int irq, void *data)
39{
40 struct rtl_snand *snand = data;
41 u32 val = 0;
42
43 regmap_read(snand->regmap, SNAFSR, &val);
44 if (val & (SNAFSR_NFCOS | SNAFSR_NFDRS | SNAFSR_NFDWS))
45 return IRQ_NONE;
46
47 regmap_write(snand->regmap, SNAFDIR, SNAFDIR_DMA_IP);
48 complete(&snand->comp);
49
50 return IRQ_HANDLED;
51}
52
53static bool rtl_snand_supports_op(struct spi_mem *mem,
54 const struct spi_mem_op *op)
55{
56 if (!spi_mem_default_supports_op(mem, op))
57 return false;
58 if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
59 return false;
60 return true;
61}
62
63static void rtl_snand_set_cs(struct rtl_snand *snand, int cs, bool active)
64{
65 u32 val;
66
67 if (active)
68 val = ~(1 << (4 * cs));
69 else
70 val = ~0;
71
72 regmap_write(snand->regmap, SNAFCCR, val);
73}
74
75static int rtl_snand_wait_ready(struct rtl_snand *snand)
76{
77 u32 val;
78
79 return regmap_read_poll_timeout(snand->regmap, SNAFSR, val, !(val & SNAFSR_NFCOS),
80 0, 2 * USEC_PER_MSEC);
81}
82
83static int rtl_snand_xfer_head(struct rtl_snand *snand, int cs, const struct spi_mem_op *op)
84{
85 int ret;
86 u32 val, len = 0;
87
88 rtl_snand_set_cs(snand, cs, true);
89
90 val = op->cmd.opcode << 24;
91 len = 1;
92 if (op->addr.nbytes && op->addr.buswidth == 1) {
93 val |= op->addr.val << ((3 - op->addr.nbytes) * 8);
94 len += op->addr.nbytes;
95 }
96
97 ret = rtl_snand_wait_ready(snand);
98 if (ret)
99 return ret;
100
101 ret = regmap_write(snand->regmap, SNAFWCMR, CMR_LEN(len));
102 if (ret)
103 return ret;
104
105 ret = regmap_write(snand->regmap, SNAFWDR, val);
106 if (ret)
107 return ret;
108
109 ret = rtl_snand_wait_ready(snand);
110 if (ret)
111 return ret;
112
113 if (op->addr.buswidth > 1) {
114 val = op->addr.val << ((3 - op->addr.nbytes) * 8);
115 len = op->addr.nbytes;
116
117 ret = regmap_write(snand->regmap, SNAFWCMR,
118 CMR_WID(op->addr.buswidth) | CMR_LEN(len));
119 if (ret)
120 return ret;
121
122 ret = regmap_write(snand->regmap, SNAFWDR, val);
123 if (ret)
124 return ret;
125
126 ret = rtl_snand_wait_ready(snand);
127 if (ret)
128 return ret;
129 }
130
131 if (op->dummy.nbytes) {
132 val = 0;
133
134 ret = regmap_write(snand->regmap, SNAFWCMR,
135 CMR_WID(op->dummy.buswidth) | CMR_LEN(op->dummy.nbytes));
136 if (ret)
137 return ret;
138
139 ret = regmap_write(snand->regmap, SNAFWDR, val);
140 if (ret)
141 return ret;
142
143 ret = rtl_snand_wait_ready(snand);
144 if (ret)
145 return ret;
146 }
147
148 return 0;
149}
150
151static void rtl_snand_xfer_tail(struct rtl_snand *snand, int cs)
152{
153 rtl_snand_set_cs(snand, cs, false);
154}
155
156static int rtl_snand_xfer(struct rtl_snand *snand, int cs, const struct spi_mem_op *op)
157{
158 unsigned int pos, nbytes;
159 int ret;
160 u32 val, len = 0;
161
162 ret = rtl_snand_xfer_head(snand, cs, op);
163 if (ret)
164 goto out_deselect;
165
166 if (op->data.dir == SPI_MEM_DATA_IN) {
167 pos = 0;
168 len = op->data.nbytes;
169
170 while (pos < len) {
171 nbytes = len - pos;
172 if (nbytes > 4)
173 nbytes = 4;
174
175 ret = rtl_snand_wait_ready(snand);
176 if (ret)
177 goto out_deselect;
178
179 ret = regmap_write(snand->regmap, SNAFRCMR,
180 CMR_WID(op->data.buswidth) | CMR_LEN(nbytes));
181 if (ret)
182 goto out_deselect;
183
184 ret = rtl_snand_wait_ready(snand);
185 if (ret)
186 goto out_deselect;
187
188 ret = regmap_read(snand->regmap, SNAFRDR, &val);
189 if (ret)
190 goto out_deselect;
191
192 memcpy(op->data.buf.in + pos, &val, nbytes);
193
194 pos += nbytes;
195 }
196 } else if (op->data.dir == SPI_MEM_DATA_OUT) {
197 pos = 0;
198 len = op->data.nbytes;
199
200 while (pos < len) {
201 nbytes = len - pos;
202 if (nbytes > 4)
203 nbytes = 4;
204
205 memcpy(&val, op->data.buf.out + pos, nbytes);
206
207 pos += nbytes;
208
209 ret = regmap_write(snand->regmap, SNAFWCMR, CMR_LEN(nbytes));
210 if (ret)
211 goto out_deselect;
212
213 ret = regmap_write(snand->regmap, SNAFWDR, val);
214 if (ret)
215 goto out_deselect;
216
217 ret = rtl_snand_wait_ready(snand);
218 if (ret)
219 goto out_deselect;
220 }
221 }
222
223out_deselect:
224 rtl_snand_xfer_tail(snand, cs);
225
226 if (ret)
227 dev_err(snand->dev, "transfer failed %d\n", ret);
228
229 return ret;
230}
231
232static int rtl_snand_dma_xfer(struct rtl_snand *snand, int cs, const struct spi_mem_op *op)
233{
234 unsigned int pos, nbytes;
235 int ret;
236 dma_addr_t buf_dma;
237 enum dma_data_direction dir;
238 u32 trig, len, maxlen;
239
240 ret = rtl_snand_xfer_head(snand, cs, op);
241 if (ret)
242 goto out_deselect;
243
244 if (op->data.dir == SPI_MEM_DATA_IN) {
245 maxlen = 2080;
246 dir = DMA_FROM_DEVICE;
247 trig = 0;
248 } else if (op->data.dir == SPI_MEM_DATA_OUT) {
249 maxlen = 520;
250 dir = DMA_TO_DEVICE;
251 trig = 1;
252 } else {
253 ret = -EOPNOTSUPP;
254 goto out_deselect;
255 }
256
257 buf_dma = dma_map_single(snand->dev, op->data.buf.in, op->data.nbytes, dir);
258 ret = dma_mapping_error(snand->dev, buf_dma);
259 if (ret)
260 goto out_deselect;
261
262 ret = regmap_write(snand->regmap, SNAFDIR, SNAFDIR_DMA_IP);
263 if (ret)
264 goto out_unmap;
265
266 ret = regmap_update_bits(snand->regmap, SNAFCFR, SNAFCFR_DMA_IE, SNAFCFR_DMA_IE);
267 if (ret)
268 goto out_unmap;
269
270 pos = 0;
271 len = op->data.nbytes;
272
273 while (pos < len) {
274 nbytes = len - pos;
275 if (nbytes > maxlen)
276 nbytes = maxlen;
277
278 reinit_completion(&snand->comp);
279
280 ret = regmap_write(snand->regmap, SNAFDRSAR, buf_dma + pos);
281 if (ret)
282 goto out_disable_int;
283
284 pos += nbytes;
285
286 ret = regmap_write(snand->regmap, SNAFDLR,
287 CMR_WID(op->data.buswidth) | nbytes);
288 if (ret)
289 goto out_disable_int;
290
291 ret = regmap_write(snand->regmap, SNAFDTR, trig);
292 if (ret)
293 goto out_disable_int;
294
295 if (!wait_for_completion_timeout(&snand->comp, usecs_to_jiffies(20000)))
296 ret = -ETIMEDOUT;
297
298 if (ret)
299 goto out_disable_int;
300 }
301
302out_disable_int:
303 regmap_update_bits(snand->regmap, SNAFCFR, SNAFCFR_DMA_IE, 0);
304out_unmap:
305 dma_unmap_single(snand->dev, buf_dma, op->data.nbytes, dir);
306out_deselect:
307 rtl_snand_xfer_tail(snand, cs);
308
309 if (ret)
310 dev_err(snand->dev, "transfer failed %d\n", ret);
311
312 return ret;
313}
314
315static bool rtl_snand_dma_op(const struct spi_mem_op *op)
316{
317 switch (op->data.dir) {
318 case SPI_MEM_DATA_IN:
319 case SPI_MEM_DATA_OUT:
320 return op->data.nbytes > 32;
321 default:
322 return false;
323 }
324}
325
326static int rtl_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
327{
328 struct rtl_snand *snand = spi_controller_get_devdata(mem->spi->controller);
329 int cs = spi_get_chipselect(mem->spi, 0);
330
331 dev_dbg(snand->dev, "cs %d op cmd %02x %d:%d, dummy %d:%d, addr %08llx@%d:%d, data %d:%d\n",
332 cs, op->cmd.opcode,
333 op->cmd.buswidth, op->cmd.nbytes, op->dummy.buswidth,
334 op->dummy.nbytes, op->addr.val, op->addr.buswidth,
335 op->addr.nbytes, op->data.buswidth, op->data.nbytes);
336
337 if (rtl_snand_dma_op(op))
338 return rtl_snand_dma_xfer(snand, cs, op);
339 else
340 return rtl_snand_xfer(snand, cs, op);
341}
342
343static const struct spi_controller_mem_ops rtl_snand_mem_ops = {
344 .supports_op = rtl_snand_supports_op,
345 .exec_op = rtl_snand_exec_op,
346};
347
348static const struct of_device_id rtl_snand_match[] = {
349 { .compatible = "realtek,rtl9301-snand" },
350 { .compatible = "realtek,rtl9302b-snand" },
351 { .compatible = "realtek,rtl9302c-snand" },
352 { .compatible = "realtek,rtl9303-snand" },
353 {},
354};
355MODULE_DEVICE_TABLE(of, rtl_snand_match);
356
357static int rtl_snand_probe(struct platform_device *pdev)
358{
359 struct rtl_snand *snand;
360 struct device *dev = &pdev->dev;
361 struct spi_controller *ctrl;
362 void __iomem *base;
363 const struct regmap_config rc = {
364 .reg_bits = 32,
365 .val_bits = 32,
366 .reg_stride = 4,
367 .cache_type = REGCACHE_NONE,
368 };
369 int irq, ret;
370
371 ctrl = devm_spi_alloc_host(dev, sizeof(*snand));
372 if (!ctrl)
373 return -ENOMEM;
374
375 snand = spi_controller_get_devdata(ctrl);
376 snand->dev = dev;
377
378 base = devm_platform_ioremap_resource(pdev, 0);
379 if (IS_ERR(base))
380 return PTR_ERR(base);
381
382 snand->regmap = devm_regmap_init_mmio(dev, base, &rc);
383 if (IS_ERR(snand->regmap))
384 return PTR_ERR(snand->regmap);
385
386 init_completion(&snand->comp);
387
388 irq = platform_get_irq(pdev, 0);
389 if (irq < 0)
390 return irq;
391
392 ret = dma_set_mask(snand->dev, DMA_BIT_MASK(32));
393 if (ret)
394 return dev_err_probe(dev, ret, "failed to set DMA mask\n");
395
396 ret = devm_request_irq(dev, irq, rtl_snand_irq, 0, "rtl-snand", snand);
397 if (ret)
398 return dev_err_probe(dev, ret, "failed to request irq\n");
399
400 ctrl->num_chipselect = 2;
401 ctrl->mem_ops = &rtl_snand_mem_ops;
402 ctrl->bits_per_word_mask = SPI_BPW_MASK(8);
403 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
404 device_set_node(&ctrl->dev, dev_fwnode(dev));
405
406 return devm_spi_register_controller(dev, ctrl);
407}
408
409static struct platform_driver rtl_snand_driver = {
410 .driver = {
411 .name = "realtek-rtl-snand",
412 .of_match_table = rtl_snand_match,
413 },
414 .probe = rtl_snand_probe,
415};
416module_platform_driver(rtl_snand_driver);
417
418MODULE_DESCRIPTION("Realtek SPI-NAND Flash Controller Driver");
419MODULE_LICENSE("GPL");