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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
9 */
10
11#include <linux/iopoll.h>
12#include <linux/irqchip/chained_irq.h>
13#include <linux/irqdomain.h>
14#include <linux/msi.h>
15#include <linux/of_address.h>
16#include <linux/of_pci.h>
17#include <linux/pci_regs.h>
18#include <linux/platform_device.h>
19
20#include "../../pci.h"
21#include "pcie-designware.h"
22
23static struct pci_ops dw_pcie_ops;
24static struct pci_ops dw_child_pcie_ops;
25
26static void dw_msi_ack_irq(struct irq_data *d)
27{
28 irq_chip_ack_parent(d);
29}
30
31static void dw_msi_mask_irq(struct irq_data *d)
32{
33 pci_msi_mask_irq(d);
34 irq_chip_mask_parent(d);
35}
36
37static void dw_msi_unmask_irq(struct irq_data *d)
38{
39 pci_msi_unmask_irq(d);
40 irq_chip_unmask_parent(d);
41}
42
43static struct irq_chip dw_pcie_msi_irq_chip = {
44 .name = "PCI-MSI",
45 .irq_ack = dw_msi_ack_irq,
46 .irq_mask = dw_msi_mask_irq,
47 .irq_unmask = dw_msi_unmask_irq,
48};
49
50static struct msi_domain_info dw_pcie_msi_domain_info = {
51 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
52 MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX |
53 MSI_FLAG_MULTI_PCI_MSI,
54 .chip = &dw_pcie_msi_irq_chip,
55};
56
57/* MSI int handler */
58irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
59{
60 int i, pos;
61 unsigned long val;
62 u32 status, num_ctrls;
63 irqreturn_t ret = IRQ_NONE;
64 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
65
66 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
67
68 for (i = 0; i < num_ctrls; i++) {
69 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
70 (i * MSI_REG_CTRL_BLOCK_SIZE));
71 if (!status)
72 continue;
73
74 ret = IRQ_HANDLED;
75 val = status;
76 pos = 0;
77 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
78 pos)) != MAX_MSI_IRQS_PER_CTRL) {
79 generic_handle_domain_irq(pp->irq_domain,
80 (i * MAX_MSI_IRQS_PER_CTRL) +
81 pos);
82 pos++;
83 }
84 }
85
86 return ret;
87}
88
89/* Chained MSI interrupt service routine */
90static void dw_chained_msi_isr(struct irq_desc *desc)
91{
92 struct irq_chip *chip = irq_desc_get_chip(desc);
93 struct dw_pcie_rp *pp;
94
95 chained_irq_enter(chip, desc);
96
97 pp = irq_desc_get_handler_data(desc);
98 dw_handle_msi_irq(pp);
99
100 chained_irq_exit(chip, desc);
101}
102
103static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
104{
105 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
106 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
107 u64 msi_target;
108
109 msi_target = (u64)pp->msi_data;
110
111 msg->address_lo = lower_32_bits(msi_target);
112 msg->address_hi = upper_32_bits(msi_target);
113
114 msg->data = d->hwirq;
115
116 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
117 (int)d->hwirq, msg->address_hi, msg->address_lo);
118}
119
120static void dw_pci_bottom_mask(struct irq_data *d)
121{
122 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
123 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
124 unsigned int res, bit, ctrl;
125 unsigned long flags;
126
127 raw_spin_lock_irqsave(&pp->lock, flags);
128
129 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
130 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
131 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
132
133 pp->irq_mask[ctrl] |= BIT(bit);
134 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
135
136 raw_spin_unlock_irqrestore(&pp->lock, flags);
137}
138
139static void dw_pci_bottom_unmask(struct irq_data *d)
140{
141 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
142 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
143 unsigned int res, bit, ctrl;
144 unsigned long flags;
145
146 raw_spin_lock_irqsave(&pp->lock, flags);
147
148 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
149 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
150 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
151
152 pp->irq_mask[ctrl] &= ~BIT(bit);
153 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
154
155 raw_spin_unlock_irqrestore(&pp->lock, flags);
156}
157
158static void dw_pci_bottom_ack(struct irq_data *d)
159{
160 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
161 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
162 unsigned int res, bit, ctrl;
163
164 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
165 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
166 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
167
168 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
169}
170
171static struct irq_chip dw_pci_msi_bottom_irq_chip = {
172 .name = "DWPCI-MSI",
173 .irq_ack = dw_pci_bottom_ack,
174 .irq_compose_msi_msg = dw_pci_setup_msi_msg,
175 .irq_mask = dw_pci_bottom_mask,
176 .irq_unmask = dw_pci_bottom_unmask,
177};
178
179static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
180 unsigned int virq, unsigned int nr_irqs,
181 void *args)
182{
183 struct dw_pcie_rp *pp = domain->host_data;
184 unsigned long flags;
185 u32 i;
186 int bit;
187
188 raw_spin_lock_irqsave(&pp->lock, flags);
189
190 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
191 order_base_2(nr_irqs));
192
193 raw_spin_unlock_irqrestore(&pp->lock, flags);
194
195 if (bit < 0)
196 return -ENOSPC;
197
198 for (i = 0; i < nr_irqs; i++)
199 irq_domain_set_info(domain, virq + i, bit + i,
200 pp->msi_irq_chip,
201 pp, handle_edge_irq,
202 NULL, NULL);
203
204 return 0;
205}
206
207static void dw_pcie_irq_domain_free(struct irq_domain *domain,
208 unsigned int virq, unsigned int nr_irqs)
209{
210 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
211 struct dw_pcie_rp *pp = domain->host_data;
212 unsigned long flags;
213
214 raw_spin_lock_irqsave(&pp->lock, flags);
215
216 bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
217 order_base_2(nr_irqs));
218
219 raw_spin_unlock_irqrestore(&pp->lock, flags);
220}
221
222static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
223 .alloc = dw_pcie_irq_domain_alloc,
224 .free = dw_pcie_irq_domain_free,
225};
226
227int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
228{
229 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
230 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
231
232 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
233 &dw_pcie_msi_domain_ops, pp);
234 if (!pp->irq_domain) {
235 dev_err(pci->dev, "Failed to create IRQ domain\n");
236 return -ENOMEM;
237 }
238
239 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
240
241 pp->msi_domain = pci_msi_create_irq_domain(fwnode,
242 &dw_pcie_msi_domain_info,
243 pp->irq_domain);
244 if (!pp->msi_domain) {
245 dev_err(pci->dev, "Failed to create MSI domain\n");
246 irq_domain_remove(pp->irq_domain);
247 return -ENOMEM;
248 }
249
250 return 0;
251}
252
253static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
254{
255 u32 ctrl;
256
257 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
258 if (pp->msi_irq[ctrl] > 0)
259 irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
260 NULL, NULL);
261 }
262
263 irq_domain_remove(pp->msi_domain);
264 irq_domain_remove(pp->irq_domain);
265}
266
267static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
268{
269 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
270 u64 msi_target = (u64)pp->msi_data;
271
272 if (!pci_msi_enabled() || !pp->has_msi_ctrl)
273 return;
274
275 /* Program the msi_data */
276 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
277 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
278}
279
280static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp)
281{
282 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
283 struct device *dev = pci->dev;
284 struct platform_device *pdev = to_platform_device(dev);
285 u32 ctrl, max_vectors;
286 int irq;
287
288 /* Parse any "msiX" IRQs described in the devicetree */
289 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
290 char msi_name[] = "msiX";
291
292 msi_name[3] = '0' + ctrl;
293 irq = platform_get_irq_byname_optional(pdev, msi_name);
294 if (irq == -ENXIO)
295 break;
296 if (irq < 0)
297 return dev_err_probe(dev, irq,
298 "Failed to parse MSI IRQ '%s'\n",
299 msi_name);
300
301 pp->msi_irq[ctrl] = irq;
302 }
303
304 /* If no "msiX" IRQs, caller should fallback to "msi" IRQ */
305 if (ctrl == 0)
306 return -ENXIO;
307
308 max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL;
309 if (pp->num_vectors > max_vectors) {
310 dev_warn(dev, "Exceeding number of MSI vectors, limiting to %u\n",
311 max_vectors);
312 pp->num_vectors = max_vectors;
313 }
314 if (!pp->num_vectors)
315 pp->num_vectors = max_vectors;
316
317 return 0;
318}
319
320static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
321{
322 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
323 struct device *dev = pci->dev;
324 struct platform_device *pdev = to_platform_device(dev);
325 u64 *msi_vaddr = NULL;
326 int ret;
327 u32 ctrl, num_ctrls;
328
329 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++)
330 pp->irq_mask[ctrl] = ~0;
331
332 if (!pp->msi_irq[0]) {
333 ret = dw_pcie_parse_split_msi_irq(pp);
334 if (ret < 0 && ret != -ENXIO)
335 return ret;
336 }
337
338 if (!pp->num_vectors)
339 pp->num_vectors = MSI_DEF_NUM_VECTORS;
340 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
341
342 if (!pp->msi_irq[0]) {
343 pp->msi_irq[0] = platform_get_irq_byname_optional(pdev, "msi");
344 if (pp->msi_irq[0] < 0) {
345 pp->msi_irq[0] = platform_get_irq(pdev, 0);
346 if (pp->msi_irq[0] < 0)
347 return pp->msi_irq[0];
348 }
349 }
350
351 dev_dbg(dev, "Using %d MSI vectors\n", pp->num_vectors);
352
353 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
354
355 ret = dw_pcie_allocate_domains(pp);
356 if (ret)
357 return ret;
358
359 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
360 if (pp->msi_irq[ctrl] > 0)
361 irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
362 dw_chained_msi_isr, pp);
363 }
364
365 /*
366 * Even though the iMSI-RX Module supports 64-bit addresses some
367 * peripheral PCIe devices may lack 64-bit message support. In
368 * order not to miss MSI TLPs from those devices the MSI target
369 * address has to be within the lowest 4GB.
370 *
371 * Note until there is a better alternative found the reservation is
372 * done by allocating from the artificially limited DMA-coherent
373 * memory.
374 */
375 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
376 if (!ret)
377 msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data,
378 GFP_KERNEL);
379
380 if (!msi_vaddr) {
381 dev_warn(dev, "Failed to allocate 32-bit MSI address\n");
382 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
383 msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data,
384 GFP_KERNEL);
385 if (!msi_vaddr) {
386 dev_err(dev, "Failed to allocate MSI address\n");
387 dw_pcie_free_msi(pp);
388 return -ENOMEM;
389 }
390 }
391
392 return 0;
393}
394
395static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)
396{
397 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
398 struct resource_entry *win;
399 struct resource *res;
400
401 win = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
402 if (win) {
403 res = devm_kzalloc(pci->dev, sizeof(*res), GFP_KERNEL);
404 if (!res)
405 return;
406
407 /*
408 * Allocate MSG TLP region of size 'region_align' at the end of
409 * the host bridge window.
410 */
411 res->start = win->res->end - pci->region_align + 1;
412 res->end = win->res->end;
413 res->name = "msg";
414 res->flags = win->res->flags | IORESOURCE_BUSY;
415
416 if (!devm_request_resource(pci->dev, win->res, res))
417 pp->msg_res = res;
418 }
419}
420
421int dw_pcie_host_init(struct dw_pcie_rp *pp)
422{
423 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
424 struct device *dev = pci->dev;
425 struct device_node *np = dev->of_node;
426 struct platform_device *pdev = to_platform_device(dev);
427 struct resource_entry *win;
428 struct pci_host_bridge *bridge;
429 struct resource *res;
430 int ret;
431
432 raw_spin_lock_init(&pp->lock);
433
434 ret = dw_pcie_get_resources(pci);
435 if (ret)
436 return ret;
437
438 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
439 if (res) {
440 pp->cfg0_size = resource_size(res);
441 pp->cfg0_base = res->start;
442
443 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res);
444 if (IS_ERR(pp->va_cfg0_base))
445 return PTR_ERR(pp->va_cfg0_base);
446 } else {
447 dev_err(dev, "Missing *config* reg space\n");
448 return -ENODEV;
449 }
450
451 bridge = devm_pci_alloc_host_bridge(dev, 0);
452 if (!bridge)
453 return -ENOMEM;
454
455 pp->bridge = bridge;
456
457 /* Get the I/O range from DT */
458 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
459 if (win) {
460 pp->io_size = resource_size(win->res);
461 pp->io_bus_addr = win->res->start - win->offset;
462 pp->io_base = pci_pio_to_address(win->res->start);
463 }
464
465 /* Set default bus ops */
466 bridge->ops = &dw_pcie_ops;
467 bridge->child_ops = &dw_child_pcie_ops;
468
469 if (pp->ops->init) {
470 ret = pp->ops->init(pp);
471 if (ret)
472 return ret;
473 }
474
475 if (pci_msi_enabled()) {
476 pp->has_msi_ctrl = !(pp->ops->msi_init ||
477 of_property_present(np, "msi-parent") ||
478 of_property_present(np, "msi-map"));
479
480 /*
481 * For the has_msi_ctrl case the default assignment is handled
482 * in the dw_pcie_msi_host_init().
483 */
484 if (!pp->has_msi_ctrl && !pp->num_vectors) {
485 pp->num_vectors = MSI_DEF_NUM_VECTORS;
486 } else if (pp->num_vectors > MAX_MSI_IRQS) {
487 dev_err(dev, "Invalid number of vectors\n");
488 ret = -EINVAL;
489 goto err_deinit_host;
490 }
491
492 if (pp->ops->msi_init) {
493 ret = pp->ops->msi_init(pp);
494 if (ret < 0)
495 goto err_deinit_host;
496 } else if (pp->has_msi_ctrl) {
497 ret = dw_pcie_msi_host_init(pp);
498 if (ret < 0)
499 goto err_deinit_host;
500 }
501 }
502
503 dw_pcie_version_detect(pci);
504
505 dw_pcie_iatu_detect(pci);
506
507 /*
508 * Allocate the resource for MSG TLP before programming the iATU
509 * outbound window in dw_pcie_setup_rc(). Since the allocation depends
510 * on the value of 'region_align', this has to be done after
511 * dw_pcie_iatu_detect().
512 *
513 * Glue drivers need to set 'use_atu_msg' before dw_pcie_host_init() to
514 * make use of the generic MSG TLP implementation.
515 */
516 if (pp->use_atu_msg)
517 dw_pcie_host_request_msg_tlp_res(pp);
518
519 ret = dw_pcie_edma_detect(pci);
520 if (ret)
521 goto err_free_msi;
522
523 ret = dw_pcie_setup_rc(pp);
524 if (ret)
525 goto err_remove_edma;
526
527 if (!dw_pcie_link_up(pci)) {
528 ret = dw_pcie_start_link(pci);
529 if (ret)
530 goto err_remove_edma;
531 }
532
533 /* Ignore errors, the link may come up later */
534 dw_pcie_wait_for_link(pci);
535
536 bridge->sysdata = pp;
537
538 ret = pci_host_probe(bridge);
539 if (ret)
540 goto err_stop_link;
541
542 if (pp->ops->post_init)
543 pp->ops->post_init(pp);
544
545 return 0;
546
547err_stop_link:
548 dw_pcie_stop_link(pci);
549
550err_remove_edma:
551 dw_pcie_edma_remove(pci);
552
553err_free_msi:
554 if (pp->has_msi_ctrl)
555 dw_pcie_free_msi(pp);
556
557err_deinit_host:
558 if (pp->ops->deinit)
559 pp->ops->deinit(pp);
560
561 return ret;
562}
563EXPORT_SYMBOL_GPL(dw_pcie_host_init);
564
565void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
566{
567 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
568
569 pci_stop_root_bus(pp->bridge->bus);
570 pci_remove_root_bus(pp->bridge->bus);
571
572 dw_pcie_stop_link(pci);
573
574 dw_pcie_edma_remove(pci);
575
576 if (pp->has_msi_ctrl)
577 dw_pcie_free_msi(pp);
578
579 if (pp->ops->deinit)
580 pp->ops->deinit(pp);
581}
582EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
583
584static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
585 unsigned int devfn, int where)
586{
587 struct dw_pcie_rp *pp = bus->sysdata;
588 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
589 struct dw_pcie_ob_atu_cfg atu = { 0 };
590 int type, ret;
591 u32 busdev;
592
593 /*
594 * Checking whether the link is up here is a last line of defense
595 * against platforms that forward errors on the system bus as
596 * SError upon PCI configuration transactions issued when the link
597 * is down. This check is racy by definition and does not stop
598 * the system from triggering an SError if the link goes down
599 * after this check is performed.
600 */
601 if (!dw_pcie_link_up(pci))
602 return NULL;
603
604 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
605 PCIE_ATU_FUNC(PCI_FUNC(devfn));
606
607 if (pci_is_root_bus(bus->parent))
608 type = PCIE_ATU_TYPE_CFG0;
609 else
610 type = PCIE_ATU_TYPE_CFG1;
611
612 atu.type = type;
613 atu.cpu_addr = pp->cfg0_base;
614 atu.pci_addr = busdev;
615 atu.size = pp->cfg0_size;
616
617 ret = dw_pcie_prog_outbound_atu(pci, &atu);
618 if (ret)
619 return NULL;
620
621 return pp->va_cfg0_base + where;
622}
623
624static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
625 int where, int size, u32 *val)
626{
627 struct dw_pcie_rp *pp = bus->sysdata;
628 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
629 struct dw_pcie_ob_atu_cfg atu = { 0 };
630 int ret;
631
632 ret = pci_generic_config_read(bus, devfn, where, size, val);
633 if (ret != PCIBIOS_SUCCESSFUL)
634 return ret;
635
636 if (pp->cfg0_io_shared) {
637 atu.type = PCIE_ATU_TYPE_IO;
638 atu.cpu_addr = pp->io_base;
639 atu.pci_addr = pp->io_bus_addr;
640 atu.size = pp->io_size;
641
642 ret = dw_pcie_prog_outbound_atu(pci, &atu);
643 if (ret)
644 return PCIBIOS_SET_FAILED;
645 }
646
647 return PCIBIOS_SUCCESSFUL;
648}
649
650static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
651 int where, int size, u32 val)
652{
653 struct dw_pcie_rp *pp = bus->sysdata;
654 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
655 struct dw_pcie_ob_atu_cfg atu = { 0 };
656 int ret;
657
658 ret = pci_generic_config_write(bus, devfn, where, size, val);
659 if (ret != PCIBIOS_SUCCESSFUL)
660 return ret;
661
662 if (pp->cfg0_io_shared) {
663 atu.type = PCIE_ATU_TYPE_IO;
664 atu.cpu_addr = pp->io_base;
665 atu.pci_addr = pp->io_bus_addr;
666 atu.size = pp->io_size;
667
668 ret = dw_pcie_prog_outbound_atu(pci, &atu);
669 if (ret)
670 return PCIBIOS_SET_FAILED;
671 }
672
673 return PCIBIOS_SUCCESSFUL;
674}
675
676static struct pci_ops dw_child_pcie_ops = {
677 .map_bus = dw_pcie_other_conf_map_bus,
678 .read = dw_pcie_rd_other_conf,
679 .write = dw_pcie_wr_other_conf,
680};
681
682void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
683{
684 struct dw_pcie_rp *pp = bus->sysdata;
685 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
686
687 if (PCI_SLOT(devfn) > 0)
688 return NULL;
689
690 return pci->dbi_base + where;
691}
692EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus);
693
694static struct pci_ops dw_pcie_ops = {
695 .map_bus = dw_pcie_own_conf_map_bus,
696 .read = pci_generic_config_read,
697 .write = pci_generic_config_write,
698};
699
700static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
701{
702 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
703 struct dw_pcie_ob_atu_cfg atu = { 0 };
704 struct resource_entry *entry;
705 int i, ret;
706
707 /* Note the very first outbound ATU is used for CFG IOs */
708 if (!pci->num_ob_windows) {
709 dev_err(pci->dev, "No outbound iATU found\n");
710 return -EINVAL;
711 }
712
713 /*
714 * Ensure all out/inbound windows are disabled before proceeding with
715 * the MEM/IO (dma-)ranges setups.
716 */
717 for (i = 0; i < pci->num_ob_windows; i++)
718 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, i);
719
720 for (i = 0; i < pci->num_ib_windows; i++)
721 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, i);
722
723 i = 0;
724 resource_list_for_each_entry(entry, &pp->bridge->windows) {
725 if (resource_type(entry->res) != IORESOURCE_MEM)
726 continue;
727
728 if (pci->num_ob_windows <= ++i)
729 break;
730
731 atu.index = i;
732 atu.type = PCIE_ATU_TYPE_MEM;
733 atu.cpu_addr = entry->res->start;
734 atu.pci_addr = entry->res->start - entry->offset;
735
736 /* Adjust iATU size if MSG TLP region was allocated before */
737 if (pp->msg_res && pp->msg_res->parent == entry->res)
738 atu.size = resource_size(entry->res) -
739 resource_size(pp->msg_res);
740 else
741 atu.size = resource_size(entry->res);
742
743 ret = dw_pcie_prog_outbound_atu(pci, &atu);
744 if (ret) {
745 dev_err(pci->dev, "Failed to set MEM range %pr\n",
746 entry->res);
747 return ret;
748 }
749 }
750
751 if (pp->io_size) {
752 if (pci->num_ob_windows > ++i) {
753 atu.index = i;
754 atu.type = PCIE_ATU_TYPE_IO;
755 atu.cpu_addr = pp->io_base;
756 atu.pci_addr = pp->io_bus_addr;
757 atu.size = pp->io_size;
758
759 ret = dw_pcie_prog_outbound_atu(pci, &atu);
760 if (ret) {
761 dev_err(pci->dev, "Failed to set IO range %pr\n",
762 entry->res);
763 return ret;
764 }
765 } else {
766 pp->cfg0_io_shared = true;
767 }
768 }
769
770 if (pci->num_ob_windows <= i)
771 dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
772 pci->num_ob_windows);
773
774 pp->msg_atu_index = i;
775
776 i = 0;
777 resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
778 if (resource_type(entry->res) != IORESOURCE_MEM)
779 continue;
780
781 if (pci->num_ib_windows <= i)
782 break;
783
784 ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM,
785 entry->res->start,
786 entry->res->start - entry->offset,
787 resource_size(entry->res));
788 if (ret) {
789 dev_err(pci->dev, "Failed to set DMA range %pr\n",
790 entry->res);
791 return ret;
792 }
793 }
794
795 if (pci->num_ib_windows <= i)
796 dev_warn(pci->dev, "Dma-ranges exceed inbound iATU size (%u)\n",
797 pci->num_ib_windows);
798
799 return 0;
800}
801
802int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
803{
804 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
805 u32 val, ctrl, num_ctrls;
806 int ret;
807
808 /*
809 * Enable DBI read-only registers for writing/updating configuration.
810 * Write permission gets disabled towards the end of this function.
811 */
812 dw_pcie_dbi_ro_wr_en(pci);
813
814 dw_pcie_setup(pci);
815
816 if (pp->has_msi_ctrl) {
817 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
818
819 /* Initialize IRQ Status array */
820 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
821 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
822 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
823 pp->irq_mask[ctrl]);
824 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
825 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
826 ~0);
827 }
828 }
829
830 dw_pcie_msi_init(pp);
831
832 /* Setup RC BARs */
833 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
834 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
835
836 /* Setup interrupt pins */
837 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
838 val &= 0xffff00ff;
839 val |= 0x00000100;
840 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
841
842 /* Setup bus numbers */
843 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
844 val &= 0xff000000;
845 val |= 0x00ff0100;
846 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
847
848 /* Setup command register */
849 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
850 val &= 0xffff0000;
851 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
852 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
853 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
854
855 /*
856 * If the platform provides its own child bus config accesses, it means
857 * the platform uses its own address translation component rather than
858 * ATU, so we should not program the ATU here.
859 */
860 if (pp->bridge->child_ops == &dw_child_pcie_ops) {
861 ret = dw_pcie_iatu_setup(pp);
862 if (ret)
863 return ret;
864 }
865
866 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
867
868 /* Program correct class for RC */
869 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
870
871 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
872 val |= PORT_LOGIC_SPEED_CHANGE;
873 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
874
875 dw_pcie_dbi_ro_wr_dis(pci);
876
877 return 0;
878}
879EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
880
881static int dw_pcie_pme_turn_off(struct dw_pcie *pci)
882{
883 struct dw_pcie_ob_atu_cfg atu = { 0 };
884 void __iomem *mem;
885 int ret;
886
887 if (pci->num_ob_windows <= pci->pp.msg_atu_index)
888 return -ENOSPC;
889
890 if (!pci->pp.msg_res)
891 return -ENOSPC;
892
893 atu.code = PCIE_MSG_CODE_PME_TURN_OFF;
894 atu.routing = PCIE_MSG_TYPE_R_BC;
895 atu.type = PCIE_ATU_TYPE_MSG;
896 atu.size = resource_size(pci->pp.msg_res);
897 atu.index = pci->pp.msg_atu_index;
898
899 atu.cpu_addr = pci->pp.msg_res->start;
900
901 ret = dw_pcie_prog_outbound_atu(pci, &atu);
902 if (ret)
903 return ret;
904
905 mem = ioremap(atu.cpu_addr, pci->region_align);
906 if (!mem)
907 return -ENOMEM;
908
909 /* A dummy write is converted to a Msg TLP */
910 writel(0, mem);
911
912 iounmap(mem);
913
914 return 0;
915}
916
917int dw_pcie_suspend_noirq(struct dw_pcie *pci)
918{
919 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
920 u32 val;
921 int ret = 0;
922
923 /*
924 * If L1SS is supported, then do not put the link into L2 as some
925 * devices such as NVMe expect low resume latency.
926 */
927 if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1)
928 return 0;
929
930 if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT)
931 return 0;
932
933 if (pci->pp.ops->pme_turn_off)
934 pci->pp.ops->pme_turn_off(&pci->pp);
935 else
936 ret = dw_pcie_pme_turn_off(pci);
937
938 if (ret)
939 return ret;
940
941 ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE,
942 PCIE_PME_TO_L2_TIMEOUT_US/10,
943 PCIE_PME_TO_L2_TIMEOUT_US, false, pci);
944 if (ret) {
945 dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val);
946 return ret;
947 }
948
949 dw_pcie_stop_link(pci);
950 if (pci->pp.ops->deinit)
951 pci->pp.ops->deinit(&pci->pp);
952
953 pci->suspended = true;
954
955 return ret;
956}
957EXPORT_SYMBOL_GPL(dw_pcie_suspend_noirq);
958
959int dw_pcie_resume_noirq(struct dw_pcie *pci)
960{
961 int ret;
962
963 if (!pci->suspended)
964 return 0;
965
966 pci->suspended = false;
967
968 if (pci->pp.ops->init) {
969 ret = pci->pp.ops->init(&pci->pp);
970 if (ret) {
971 dev_err(pci->dev, "Host init failed: %d\n", ret);
972 return ret;
973 }
974 }
975
976 dw_pcie_setup_rc(&pci->pp);
977
978 ret = dw_pcie_start_link(pci);
979 if (ret)
980 return ret;
981
982 ret = dw_pcie_wait_for_link(pci);
983 if (ret)
984 return ret;
985
986 return ret;
987}
988EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
9 */
10
11#include <linux/irqchip/chained_irq.h>
12#include <linux/irqdomain.h>
13#include <linux/msi.h>
14#include <linux/of_address.h>
15#include <linux/of_pci.h>
16#include <linux/pci_regs.h>
17#include <linux/platform_device.h>
18
19#include "../../pci.h"
20#include "pcie-designware.h"
21
22static struct pci_ops dw_pcie_ops;
23
24static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
25 u32 *val)
26{
27 struct dw_pcie *pci;
28
29 if (pp->ops->rd_own_conf)
30 return pp->ops->rd_own_conf(pp, where, size, val);
31
32 pci = to_dw_pcie_from_pp(pp);
33 return dw_pcie_read(pci->dbi_base + where, size, val);
34}
35
36static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
37 u32 val)
38{
39 struct dw_pcie *pci;
40
41 if (pp->ops->wr_own_conf)
42 return pp->ops->wr_own_conf(pp, where, size, val);
43
44 pci = to_dw_pcie_from_pp(pp);
45 return dw_pcie_write(pci->dbi_base + where, size, val);
46}
47
48static void dw_msi_ack_irq(struct irq_data *d)
49{
50 irq_chip_ack_parent(d);
51}
52
53static void dw_msi_mask_irq(struct irq_data *d)
54{
55 pci_msi_mask_irq(d);
56 irq_chip_mask_parent(d);
57}
58
59static void dw_msi_unmask_irq(struct irq_data *d)
60{
61 pci_msi_unmask_irq(d);
62 irq_chip_unmask_parent(d);
63}
64
65static struct irq_chip dw_pcie_msi_irq_chip = {
66 .name = "PCI-MSI",
67 .irq_ack = dw_msi_ack_irq,
68 .irq_mask = dw_msi_mask_irq,
69 .irq_unmask = dw_msi_unmask_irq,
70};
71
72static struct msi_domain_info dw_pcie_msi_domain_info = {
73 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
74 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
75 .chip = &dw_pcie_msi_irq_chip,
76};
77
78/* MSI int handler */
79irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
80{
81 int i, pos, irq;
82 unsigned long val;
83 u32 status, num_ctrls;
84 irqreturn_t ret = IRQ_NONE;
85
86 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
87
88 for (i = 0; i < num_ctrls; i++) {
89 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS +
90 (i * MSI_REG_CTRL_BLOCK_SIZE),
91 4, &status);
92 if (!status)
93 continue;
94
95 ret = IRQ_HANDLED;
96 val = status;
97 pos = 0;
98 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
99 pos)) != MAX_MSI_IRQS_PER_CTRL) {
100 irq = irq_find_mapping(pp->irq_domain,
101 (i * MAX_MSI_IRQS_PER_CTRL) +
102 pos);
103 generic_handle_irq(irq);
104 pos++;
105 }
106 }
107
108 return ret;
109}
110
111/* Chained MSI interrupt service routine */
112static void dw_chained_msi_isr(struct irq_desc *desc)
113{
114 struct irq_chip *chip = irq_desc_get_chip(desc);
115 struct pcie_port *pp;
116
117 chained_irq_enter(chip, desc);
118
119 pp = irq_desc_get_handler_data(desc);
120 dw_handle_msi_irq(pp);
121
122 chained_irq_exit(chip, desc);
123}
124
125static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
126{
127 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
128 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
129 u64 msi_target;
130
131 msi_target = (u64)pp->msi_data;
132
133 msg->address_lo = lower_32_bits(msi_target);
134 msg->address_hi = upper_32_bits(msi_target);
135
136 msg->data = d->hwirq;
137
138 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
139 (int)d->hwirq, msg->address_hi, msg->address_lo);
140}
141
142static int dw_pci_msi_set_affinity(struct irq_data *d,
143 const struct cpumask *mask, bool force)
144{
145 return -EINVAL;
146}
147
148static void dw_pci_bottom_mask(struct irq_data *d)
149{
150 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
151 unsigned int res, bit, ctrl;
152 unsigned long flags;
153
154 raw_spin_lock_irqsave(&pp->lock, flags);
155
156 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
157 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
158 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
159
160 pp->irq_mask[ctrl] |= BIT(bit);
161 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
162 pp->irq_mask[ctrl]);
163
164 raw_spin_unlock_irqrestore(&pp->lock, flags);
165}
166
167static void dw_pci_bottom_unmask(struct irq_data *d)
168{
169 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
170 unsigned int res, bit, ctrl;
171 unsigned long flags;
172
173 raw_spin_lock_irqsave(&pp->lock, flags);
174
175 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
176 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
177 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
178
179 pp->irq_mask[ctrl] &= ~BIT(bit);
180 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
181 pp->irq_mask[ctrl]);
182
183 raw_spin_unlock_irqrestore(&pp->lock, flags);
184}
185
186static void dw_pci_bottom_ack(struct irq_data *d)
187{
188 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
189 unsigned int res, bit, ctrl;
190
191 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
192 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
193 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
194
195 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit));
196}
197
198static struct irq_chip dw_pci_msi_bottom_irq_chip = {
199 .name = "DWPCI-MSI",
200 .irq_ack = dw_pci_bottom_ack,
201 .irq_compose_msi_msg = dw_pci_setup_msi_msg,
202 .irq_set_affinity = dw_pci_msi_set_affinity,
203 .irq_mask = dw_pci_bottom_mask,
204 .irq_unmask = dw_pci_bottom_unmask,
205};
206
207static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
208 unsigned int virq, unsigned int nr_irqs,
209 void *args)
210{
211 struct pcie_port *pp = domain->host_data;
212 unsigned long flags;
213 u32 i;
214 int bit;
215
216 raw_spin_lock_irqsave(&pp->lock, flags);
217
218 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
219 order_base_2(nr_irqs));
220
221 raw_spin_unlock_irqrestore(&pp->lock, flags);
222
223 if (bit < 0)
224 return -ENOSPC;
225
226 for (i = 0; i < nr_irqs; i++)
227 irq_domain_set_info(domain, virq + i, bit + i,
228 pp->msi_irq_chip,
229 pp, handle_edge_irq,
230 NULL, NULL);
231
232 return 0;
233}
234
235static void dw_pcie_irq_domain_free(struct irq_domain *domain,
236 unsigned int virq, unsigned int nr_irqs)
237{
238 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
239 struct pcie_port *pp = domain->host_data;
240 unsigned long flags;
241
242 raw_spin_lock_irqsave(&pp->lock, flags);
243
244 bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
245 order_base_2(nr_irqs));
246
247 raw_spin_unlock_irqrestore(&pp->lock, flags);
248}
249
250static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
251 .alloc = dw_pcie_irq_domain_alloc,
252 .free = dw_pcie_irq_domain_free,
253};
254
255int dw_pcie_allocate_domains(struct pcie_port *pp)
256{
257 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
258 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
259
260 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
261 &dw_pcie_msi_domain_ops, pp);
262 if (!pp->irq_domain) {
263 dev_err(pci->dev, "Failed to create IRQ domain\n");
264 return -ENOMEM;
265 }
266
267 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
268
269 pp->msi_domain = pci_msi_create_irq_domain(fwnode,
270 &dw_pcie_msi_domain_info,
271 pp->irq_domain);
272 if (!pp->msi_domain) {
273 dev_err(pci->dev, "Failed to create MSI domain\n");
274 irq_domain_remove(pp->irq_domain);
275 return -ENOMEM;
276 }
277
278 return 0;
279}
280
281void dw_pcie_free_msi(struct pcie_port *pp)
282{
283 if (pp->msi_irq) {
284 irq_set_chained_handler(pp->msi_irq, NULL);
285 irq_set_handler_data(pp->msi_irq, NULL);
286 }
287
288 irq_domain_remove(pp->msi_domain);
289 irq_domain_remove(pp->irq_domain);
290
291 if (pp->msi_page)
292 __free_page(pp->msi_page);
293}
294
295void dw_pcie_msi_init(struct pcie_port *pp)
296{
297 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
298 struct device *dev = pci->dev;
299 u64 msi_target;
300
301 pp->msi_page = alloc_page(GFP_KERNEL);
302 pp->msi_data = dma_map_page(dev, pp->msi_page, 0, PAGE_SIZE,
303 DMA_FROM_DEVICE);
304 if (dma_mapping_error(dev, pp->msi_data)) {
305 dev_err(dev, "Failed to map MSI data\n");
306 __free_page(pp->msi_page);
307 pp->msi_page = NULL;
308 return;
309 }
310 msi_target = (u64)pp->msi_data;
311
312 /* Program the msi_data */
313 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
314 lower_32_bits(msi_target));
315 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
316 upper_32_bits(msi_target));
317}
318EXPORT_SYMBOL_GPL(dw_pcie_msi_init);
319
320int dw_pcie_host_init(struct pcie_port *pp)
321{
322 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
323 struct device *dev = pci->dev;
324 struct device_node *np = dev->of_node;
325 struct platform_device *pdev = to_platform_device(dev);
326 struct resource_entry *win;
327 struct pci_bus *child;
328 struct pci_host_bridge *bridge;
329 struct resource *cfg_res;
330 u32 hdr_type;
331 int ret;
332
333 raw_spin_lock_init(&pci->pp.lock);
334
335 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
336 if (cfg_res) {
337 pp->cfg0_size = resource_size(cfg_res) >> 1;
338 pp->cfg1_size = resource_size(cfg_res) >> 1;
339 pp->cfg0_base = cfg_res->start;
340 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
341 } else if (!pp->va_cfg0_base) {
342 dev_err(dev, "Missing *config* reg space\n");
343 }
344
345 bridge = devm_pci_alloc_host_bridge(dev, 0);
346 if (!bridge)
347 return -ENOMEM;
348
349 /* Get the I/O and memory ranges from DT */
350 resource_list_for_each_entry(win, &bridge->windows) {
351 switch (resource_type(win->res)) {
352 case IORESOURCE_IO:
353 pp->io = win->res;
354 pp->io->name = "I/O";
355 pp->io_size = resource_size(pp->io);
356 pp->io_bus_addr = pp->io->start - win->offset;
357 pp->io_base = pci_pio_to_address(pp->io->start);
358 break;
359 case IORESOURCE_MEM:
360 pp->mem = win->res;
361 pp->mem->name = "MEM";
362 pp->mem_size = resource_size(pp->mem);
363 pp->mem_bus_addr = pp->mem->start - win->offset;
364 break;
365 case 0:
366 pp->cfg = win->res;
367 pp->cfg0_size = resource_size(pp->cfg) >> 1;
368 pp->cfg1_size = resource_size(pp->cfg) >> 1;
369 pp->cfg0_base = pp->cfg->start;
370 pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
371 break;
372 case IORESOURCE_BUS:
373 pp->busn = win->res;
374 break;
375 }
376 }
377
378 if (!pci->dbi_base) {
379 pci->dbi_base = devm_pci_remap_cfgspace(dev,
380 pp->cfg->start,
381 resource_size(pp->cfg));
382 if (!pci->dbi_base) {
383 dev_err(dev, "Error with ioremap\n");
384 return -ENOMEM;
385 }
386 }
387
388 pp->mem_base = pp->mem->start;
389
390 if (!pp->va_cfg0_base) {
391 pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
392 pp->cfg0_base, pp->cfg0_size);
393 if (!pp->va_cfg0_base) {
394 dev_err(dev, "Error with ioremap in function\n");
395 return -ENOMEM;
396 }
397 }
398
399 if (!pp->va_cfg1_base) {
400 pp->va_cfg1_base = devm_pci_remap_cfgspace(dev,
401 pp->cfg1_base,
402 pp->cfg1_size);
403 if (!pp->va_cfg1_base) {
404 dev_err(dev, "Error with ioremap\n");
405 return -ENOMEM;
406 }
407 }
408
409 ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
410 if (ret)
411 pci->num_viewport = 2;
412
413 if (pci_msi_enabled()) {
414 /*
415 * If a specific SoC driver needs to change the
416 * default number of vectors, it needs to implement
417 * the set_num_vectors callback.
418 */
419 if (!pp->ops->set_num_vectors) {
420 pp->num_vectors = MSI_DEF_NUM_VECTORS;
421 } else {
422 pp->ops->set_num_vectors(pp);
423
424 if (pp->num_vectors > MAX_MSI_IRQS ||
425 pp->num_vectors == 0) {
426 dev_err(dev,
427 "Invalid number of vectors\n");
428 return -EINVAL;
429 }
430 }
431
432 if (!pp->ops->msi_host_init) {
433 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
434
435 ret = dw_pcie_allocate_domains(pp);
436 if (ret)
437 return ret;
438
439 if (pp->msi_irq)
440 irq_set_chained_handler_and_data(pp->msi_irq,
441 dw_chained_msi_isr,
442 pp);
443 } else {
444 ret = pp->ops->msi_host_init(pp);
445 if (ret < 0)
446 return ret;
447 }
448 }
449
450 if (pp->ops->host_init) {
451 ret = pp->ops->host_init(pp);
452 if (ret)
453 goto err_free_msi;
454 }
455
456 ret = dw_pcie_rd_own_conf(pp, PCI_HEADER_TYPE, 1, &hdr_type);
457 if (ret != PCIBIOS_SUCCESSFUL) {
458 dev_err(pci->dev, "Failed reading PCI_HEADER_TYPE cfg space reg (ret: 0x%x)\n",
459 ret);
460 ret = pcibios_err_to_errno(ret);
461 goto err_free_msi;
462 }
463 if (hdr_type != PCI_HEADER_TYPE_BRIDGE) {
464 dev_err(pci->dev,
465 "PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n",
466 hdr_type);
467 ret = -EIO;
468 goto err_free_msi;
469 }
470
471 bridge->sysdata = pp;
472 bridge->ops = &dw_pcie_ops;
473
474 ret = pci_scan_root_bus_bridge(bridge);
475 if (ret)
476 goto err_free_msi;
477
478 pp->root_bus = bridge->bus;
479
480 if (pp->ops->scan_bus)
481 pp->ops->scan_bus(pp);
482
483 pci_bus_size_bridges(pp->root_bus);
484 pci_bus_assign_resources(pp->root_bus);
485
486 list_for_each_entry(child, &pp->root_bus->children, node)
487 pcie_bus_configure_settings(child);
488
489 pci_bus_add_devices(pp->root_bus);
490 return 0;
491
492err_free_msi:
493 if (pci_msi_enabled() && !pp->ops->msi_host_init)
494 dw_pcie_free_msi(pp);
495 return ret;
496}
497EXPORT_SYMBOL_GPL(dw_pcie_host_init);
498
499void dw_pcie_host_deinit(struct pcie_port *pp)
500{
501 pci_stop_root_bus(pp->root_bus);
502 pci_remove_root_bus(pp->root_bus);
503 if (pci_msi_enabled() && !pp->ops->msi_host_init)
504 dw_pcie_free_msi(pp);
505}
506EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
507
508static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus,
509 u32 devfn, int where, int size, u32 *val,
510 bool write)
511{
512 int ret, type;
513 u32 busdev, cfg_size;
514 u64 cpu_addr;
515 void __iomem *va_cfg_base;
516 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
517
518 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
519 PCIE_ATU_FUNC(PCI_FUNC(devfn));
520
521 if (pci_is_root_bus(bus->parent)) {
522 type = PCIE_ATU_TYPE_CFG0;
523 cpu_addr = pp->cfg0_base;
524 cfg_size = pp->cfg0_size;
525 va_cfg_base = pp->va_cfg0_base;
526 } else {
527 type = PCIE_ATU_TYPE_CFG1;
528 cpu_addr = pp->cfg1_base;
529 cfg_size = pp->cfg1_size;
530 va_cfg_base = pp->va_cfg1_base;
531 }
532
533 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
534 type, cpu_addr,
535 busdev, cfg_size);
536 if (write)
537 ret = dw_pcie_write(va_cfg_base + where, size, *val);
538 else
539 ret = dw_pcie_read(va_cfg_base + where, size, val);
540
541 if (pci->num_viewport <= 2)
542 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
543 PCIE_ATU_TYPE_IO, pp->io_base,
544 pp->io_bus_addr, pp->io_size);
545
546 return ret;
547}
548
549static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
550 u32 devfn, int where, int size, u32 *val)
551{
552 if (pp->ops->rd_other_conf)
553 return pp->ops->rd_other_conf(pp, bus, devfn, where,
554 size, val);
555
556 return dw_pcie_access_other_conf(pp, bus, devfn, where, size, val,
557 false);
558}
559
560static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
561 u32 devfn, int where, int size, u32 val)
562{
563 if (pp->ops->wr_other_conf)
564 return pp->ops->wr_other_conf(pp, bus, devfn, where,
565 size, val);
566
567 return dw_pcie_access_other_conf(pp, bus, devfn, where, size, &val,
568 true);
569}
570
571static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
572 int dev)
573{
574 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
575
576 /* If there is no link, then there is no device */
577 if (!pci_is_root_bus(bus)) {
578 if (!dw_pcie_link_up(pci))
579 return 0;
580 } else if (dev > 0)
581 /* Access only one slot on each root port */
582 return 0;
583
584 return 1;
585}
586
587static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
588 int size, u32 *val)
589{
590 struct pcie_port *pp = bus->sysdata;
591
592 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
593 *val = 0xffffffff;
594 return PCIBIOS_DEVICE_NOT_FOUND;
595 }
596
597 if (pci_is_root_bus(bus))
598 return dw_pcie_rd_own_conf(pp, where, size, val);
599
600 return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
601}
602
603static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
604 int where, int size, u32 val)
605{
606 struct pcie_port *pp = bus->sysdata;
607
608 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
609 return PCIBIOS_DEVICE_NOT_FOUND;
610
611 if (pci_is_root_bus(bus))
612 return dw_pcie_wr_own_conf(pp, where, size, val);
613
614 return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
615}
616
617static struct pci_ops dw_pcie_ops = {
618 .read = dw_pcie_rd_conf,
619 .write = dw_pcie_wr_conf,
620};
621
622void dw_pcie_setup_rc(struct pcie_port *pp)
623{
624 u32 val, ctrl, num_ctrls;
625 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
626
627 /*
628 * Enable DBI read-only registers for writing/updating configuration.
629 * Write permission gets disabled towards the end of this function.
630 */
631 dw_pcie_dbi_ro_wr_en(pci);
632
633 dw_pcie_setup(pci);
634
635 if (!pp->ops->msi_host_init) {
636 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
637
638 /* Initialize IRQ Status array */
639 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
640 pp->irq_mask[ctrl] = ~0;
641 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK +
642 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
643 4, pp->irq_mask[ctrl]);
644 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
645 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
646 4, ~0);
647 }
648 }
649
650 /* Setup RC BARs */
651 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
652 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
653
654 /* Setup interrupt pins */
655 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
656 val &= 0xffff00ff;
657 val |= 0x00000100;
658 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
659
660 /* Setup bus numbers */
661 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
662 val &= 0xff000000;
663 val |= 0x00ff0100;
664 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
665
666 /* Setup command register */
667 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
668 val &= 0xffff0000;
669 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
670 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
671 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
672
673 /*
674 * If the platform provides ->rd_other_conf, it means the platform
675 * uses its own address translation component rather than ATU, so
676 * we should not program the ATU here.
677 */
678 if (!pp->ops->rd_other_conf) {
679 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
680 PCIE_ATU_TYPE_MEM, pp->mem_base,
681 pp->mem_bus_addr, pp->mem_size);
682 if (pci->num_viewport > 2)
683 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,
684 PCIE_ATU_TYPE_IO, pp->io_base,
685 pp->io_bus_addr, pp->io_size);
686 }
687
688 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
689
690 /* Program correct class for RC */
691 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
692
693 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
694 val |= PORT_LOGIC_SPEED_CHANGE;
695 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
696
697 dw_pcie_dbi_ro_wr_dis(pci);
698}
699EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);