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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Intel IXP4xx HSS (synchronous serial port) driver for Linux
4 *
5 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/module.h>
11#include <linux/bitops.h>
12#include <linux/cdev.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmapool.h>
15#include <linux/fs.h>
16#include <linux/hdlc.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/mfd/syscon.h>
20#include <linux/platform_device.h>
21#include <linux/poll.h>
22#include <linux/regmap.h>
23#include <linux/slab.h>
24#include <linux/gpio/consumer.h>
25#include <linux/of.h>
26#include <linux/soc/ixp4xx/npe.h>
27#include <linux/soc/ixp4xx/qmgr.h>
28#include <linux/soc/ixp4xx/cpu.h>
29
30/* This is what all IXP4xx platforms we know uses, if more frequencies
31 * are needed, we need to migrate to the clock framework.
32 */
33#define IXP4XX_TIMER_FREQ 66666000
34
35#define DEBUG_DESC 0
36#define DEBUG_RX 0
37#define DEBUG_TX 0
38#define DEBUG_PKT_BYTES 0
39#define DEBUG_CLOSE 0
40
41#define DRV_NAME "ixp4xx_hss"
42
43#define PKT_EXTRA_FLAGS 0 /* orig 1 */
44#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
45#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
46
47#define RX_DESCS 16 /* also length of all RX queues */
48#define TX_DESCS 16 /* also length of all TX queues */
49
50#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
51#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
52#define MAX_CLOSE_WAIT 1000 /* microseconds */
53#define HSS_COUNT 2
54#define FRAME_SIZE 256 /* doesn't matter at this point */
55#define FRAME_OFFSET 0
56#define MAX_CHANNELS (FRAME_SIZE / 8)
57
58#define NAPI_WEIGHT 16
59
60/* Queue IDs */
61#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
62#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
63#define HSS0_PKT_TX1_QUEUE 15
64#define HSS0_PKT_TX2_QUEUE 16
65#define HSS0_PKT_TX3_QUEUE 17
66#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
67#define HSS0_PKT_RXFREE1_QUEUE 19
68#define HSS0_PKT_RXFREE2_QUEUE 20
69#define HSS0_PKT_RXFREE3_QUEUE 21
70#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
71
72#define HSS1_PKT_RX_QUEUE 0
73#define HSS1_PKT_TX0_QUEUE 5
74#define HSS1_PKT_TX1_QUEUE 6
75#define HSS1_PKT_TX2_QUEUE 7
76#define HSS1_PKT_TX3_QUEUE 8
77#define HSS1_PKT_RXFREE0_QUEUE 1
78#define HSS1_PKT_RXFREE1_QUEUE 2
79#define HSS1_PKT_RXFREE2_QUEUE 3
80#define HSS1_PKT_RXFREE3_QUEUE 4
81#define HSS1_PKT_TXDONE_QUEUE 9
82
83#define NPE_PKT_MODE_HDLC 0
84#define NPE_PKT_MODE_RAW 1
85#define NPE_PKT_MODE_56KMODE 2
86#define NPE_PKT_MODE_56KENDIAN_MSB 4
87
88/* PKT_PIPE_HDLC_CFG_WRITE flags */
89#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
90#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
91#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
92
93/* hss_config, PCRs */
94/* Frame sync sampling, default = active low */
95#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
96#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
97#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
98
99/* Frame sync pin: input (default) or output generated off a given clk edge */
100#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
101#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
102
103/* Frame and data clock sampling on edge, default = falling */
104#define PCR_FCLK_EDGE_RISING 0x08000000
105#define PCR_DCLK_EDGE_RISING 0x04000000
106
107/* Clock direction, default = input */
108#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
109
110/* Generate/Receive frame pulses, default = enabled */
111#define PCR_FRM_PULSE_DISABLED 0x01000000
112
113 /* Data rate is full (default) or half the configured clk speed */
114#define PCR_HALF_CLK_RATE 0x00200000
115
116/* Invert data between NPE and HSS FIFOs? (default = no) */
117#define PCR_DATA_POLARITY_INVERT 0x00100000
118
119/* TX/RX endianness, default = LSB */
120#define PCR_MSB_ENDIAN 0x00080000
121
122/* Normal (default) / open drain mode (TX only) */
123#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
124
125/* No framing bit transmitted and expected on RX? (default = framing bit) */
126#define PCR_SOF_NO_FBIT 0x00020000
127
128/* Drive data pins? */
129#define PCR_TX_DATA_ENABLE 0x00010000
130
131/* Voice 56k type: drive the data pins low (default), high, high Z */
132#define PCR_TX_V56K_HIGH 0x00002000
133#define PCR_TX_V56K_HIGH_IMP 0x00004000
134
135/* Unassigned type: drive the data pins low (default), high, high Z */
136#define PCR_TX_UNASS_HIGH 0x00000800
137#define PCR_TX_UNASS_HIGH_IMP 0x00001000
138
139/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
140#define PCR_TX_FB_HIGH_IMP 0x00000400
141
142/* 56k data endiannes - which bit unused: high (default) or low */
143#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
144
145/* 56k data transmission type: 32/8 bit data (default) or 56K data */
146#define PCR_TX_56KS_56K_DATA 0x00000100
147
148/* hss_config, cCR */
149/* Number of packetized clients, default = 1 */
150#define CCR_NPE_HFIFO_2_HDLC 0x04000000
151#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
152
153/* default = no loopback */
154#define CCR_LOOPBACK 0x02000000
155
156/* HSS number, default = 0 (first) */
157#define CCR_SECOND_HSS 0x01000000
158
159/* hss_config, clkCR: main:10, num:10, denom:12 */
160#define CLK42X_SPEED_EXP ((0x3FF << 22) | (2 << 12) | 15) /*65 KHz*/
161
162#define CLK42X_SPEED_512KHZ ((130 << 22) | (2 << 12) | 15)
163#define CLK42X_SPEED_1536KHZ ((43 << 22) | (18 << 12) | 47)
164#define CLK42X_SPEED_1544KHZ ((43 << 22) | (33 << 12) | 192)
165#define CLK42X_SPEED_2048KHZ ((32 << 22) | (34 << 12) | 63)
166#define CLK42X_SPEED_4096KHZ ((16 << 22) | (34 << 12) | 127)
167#define CLK42X_SPEED_8192KHZ ((8 << 22) | (34 << 12) | 255)
168
169#define CLK46X_SPEED_512KHZ ((130 << 22) | (24 << 12) | 127)
170#define CLK46X_SPEED_1536KHZ ((43 << 22) | (152 << 12) | 383)
171#define CLK46X_SPEED_1544KHZ ((43 << 22) | (66 << 12) | 385)
172#define CLK46X_SPEED_2048KHZ ((32 << 22) | (280 << 12) | 511)
173#define CLK46X_SPEED_4096KHZ ((16 << 22) | (280 << 12) | 1023)
174#define CLK46X_SPEED_8192KHZ ((8 << 22) | (280 << 12) | 2047)
175
176/* HSS_CONFIG_CLOCK_CR register consists of 3 parts:
177 * A (10 bits), B (10 bits) and C (12 bits).
178 * IXP42x HSS clock generator operation (verified with an oscilloscope):
179 * Each clock bit takes 7.5 ns (1 / 133.xx MHz).
180 * The clock sequence consists of (C - B) states of 0s and 1s, each state is
181 * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is
182 * (A + 1) bits wide.
183 *
184 * The resulting average clock frequency (assuming 33.333 MHz oscillator) is:
185 * freq = 66.666 MHz / (A + (B + 1) / (C + 1))
186 * minimum freq = 66.666 MHz / (A + 1)
187 * maximum freq = 66.666 MHz / A
188 *
189 * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7
190 * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s).
191 * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples).
192 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits
193 * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats).
194 * The sequence consists of 4 complete clock periods, thus the average
195 * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s).
196 * (max specified clock rate for IXP42x HSS is 8.192 Mb/s).
197 */
198
199/* hss_config, LUT entries */
200#define TDMMAP_UNASSIGNED 0
201#define TDMMAP_HDLC 1 /* HDLC - packetized */
202#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
203#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
204
205/* offsets into HSS config */
206#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
207#define HSS_CONFIG_RX_PCR 0x04
208#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
209#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
210#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
211#define HSS_CONFIG_RX_FCR 0x14
212#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
213#define HSS_CONFIG_RX_LUT 0x38
214
215/* NPE command codes */
216/* writes the ConfigWord value to the location specified by offset */
217#define PORT_CONFIG_WRITE 0x40
218
219/* triggers the NPE to load the contents of the configuration table */
220#define PORT_CONFIG_LOAD 0x41
221
222/* triggers the NPE to return an HssErrorReadResponse message */
223#define PORT_ERROR_READ 0x42
224
225/* triggers the NPE to reset internal status and enable the HssPacketized
226 * operation for the flow specified by pPipe
227 */
228#define PKT_PIPE_FLOW_ENABLE 0x50
229#define PKT_PIPE_FLOW_DISABLE 0x51
230#define PKT_NUM_PIPES_WRITE 0x52
231#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
232#define PKT_PIPE_HDLC_CFG_WRITE 0x54
233#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
234#define PKT_PIPE_RX_SIZE_WRITE 0x56
235#define PKT_PIPE_MODE_WRITE 0x57
236
237/* HDLC packet status values - desc->status */
238#define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */
239#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
240#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
241#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
242 * this packet (if buf_len < pkt_len)
243 */
244#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
245#define ERR_HDLC_ABORT 6 /* abort sequence received */
246#define ERR_DISCONNECTING 7 /* disconnect is in progress */
247
248#ifdef __ARMEB__
249typedef struct sk_buff buffer_t;
250#define free_buffer dev_kfree_skb
251#define free_buffer_irq dev_consume_skb_irq
252#else
253typedef void buffer_t;
254#define free_buffer kfree
255#define free_buffer_irq kfree
256#endif
257
258struct port {
259 struct device *dev;
260 struct npe *npe;
261 unsigned int txreadyq;
262 unsigned int rxtrigq;
263 unsigned int rxfreeq;
264 unsigned int rxq;
265 unsigned int txq;
266 unsigned int txdoneq;
267 struct gpio_desc *cts;
268 struct gpio_desc *rts;
269 struct gpio_desc *dcd;
270 struct gpio_desc *dtr;
271 struct gpio_desc *clk_internal;
272 struct net_device *netdev;
273 struct napi_struct napi;
274 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
275 struct desc *desc_tab; /* coherent */
276 dma_addr_t desc_tab_phys;
277 unsigned int id;
278 unsigned int clock_type, clock_rate, loopback;
279 unsigned int initialized, carrier;
280 u8 hdlc_cfg;
281 u32 clock_reg;
282};
283
284/* NPE message structure */
285struct msg {
286#ifdef __ARMEB__
287 u8 cmd, unused, hss_port, index;
288 union {
289 struct { u8 data8a, data8b, data8c, data8d; };
290 struct { u16 data16a, data16b; };
291 struct { u32 data32; };
292 };
293#else
294 u8 index, hss_port, unused, cmd;
295 union {
296 struct { u8 data8d, data8c, data8b, data8a; };
297 struct { u16 data16b, data16a; };
298 struct { u32 data32; };
299 };
300#endif
301};
302
303/* HDLC packet descriptor */
304struct desc {
305 u32 next; /* pointer to next buffer, unused */
306
307#ifdef __ARMEB__
308 u16 buf_len; /* buffer length */
309 u16 pkt_len; /* packet length */
310 u32 data; /* pointer to data buffer in RAM */
311 u8 status;
312 u8 error_count;
313 u16 __reserved;
314#else
315 u16 pkt_len; /* packet length */
316 u16 buf_len; /* buffer length */
317 u32 data; /* pointer to data buffer in RAM */
318 u16 __reserved;
319 u8 error_count;
320 u8 status;
321#endif
322 u32 __reserved1[4];
323};
324
325#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
326 (n) * sizeof(struct desc))
327#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
328
329#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
330 ((n) + RX_DESCS) * sizeof(struct desc))
331#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
332
333/*****************************************************************************
334 * global variables
335 ****************************************************************************/
336
337static int ports_open;
338static struct dma_pool *dma_pool;
339static DEFINE_SPINLOCK(npe_lock);
340
341/*****************************************************************************
342 * utility functions
343 ****************************************************************************/
344
345static inline struct port *dev_to_port(struct net_device *dev)
346{
347 return dev_to_hdlc(dev)->priv;
348}
349
350#ifndef __ARMEB__
351static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
352{
353 int i;
354
355 for (i = 0; i < cnt; i++)
356 dest[i] = swab32(src[i]);
357}
358#endif
359
360/*****************************************************************************
361 * HSS access
362 ****************************************************************************/
363
364static void hss_npe_send(struct port *port, struct msg *msg, const char *what)
365{
366 u32 *val = (u32 *)msg;
367
368 if (npe_send_message(port->npe, msg, what)) {
369 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n",
370 port->id, val[0], val[1], npe_name(port->npe));
371 BUG();
372 }
373}
374
375static void hss_config_set_lut(struct port *port)
376{
377 struct msg msg;
378 int ch;
379
380 memset(&msg, 0, sizeof(msg));
381 msg.cmd = PORT_CONFIG_WRITE;
382 msg.hss_port = port->id;
383
384 for (ch = 0; ch < MAX_CHANNELS; ch++) {
385 msg.data32 >>= 2;
386 msg.data32 |= TDMMAP_HDLC << 30;
387
388 if (ch % 16 == 15) {
389 msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
390 hss_npe_send(port, &msg, "HSS_SET_TX_LUT");
391
392 msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
393 hss_npe_send(port, &msg, "HSS_SET_RX_LUT");
394 }
395 }
396}
397
398static void hss_config(struct port *port)
399{
400 struct msg msg;
401
402 memset(&msg, 0, sizeof(msg));
403 msg.cmd = PORT_CONFIG_WRITE;
404 msg.hss_port = port->id;
405 msg.index = HSS_CONFIG_TX_PCR;
406 msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN |
407 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT;
408 if (port->clock_type == CLOCK_INT)
409 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
410 hss_npe_send(port, &msg, "HSS_SET_TX_PCR");
411
412 msg.index = HSS_CONFIG_RX_PCR;
413 msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
414 hss_npe_send(port, &msg, "HSS_SET_RX_PCR");
415
416 memset(&msg, 0, sizeof(msg));
417 msg.cmd = PORT_CONFIG_WRITE;
418 msg.hss_port = port->id;
419 msg.index = HSS_CONFIG_CORE_CR;
420 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
421 (port->id ? CCR_SECOND_HSS : 0);
422 hss_npe_send(port, &msg, "HSS_SET_CORE_CR");
423
424 memset(&msg, 0, sizeof(msg));
425 msg.cmd = PORT_CONFIG_WRITE;
426 msg.hss_port = port->id;
427 msg.index = HSS_CONFIG_CLOCK_CR;
428 msg.data32 = port->clock_reg;
429 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
430
431 memset(&msg, 0, sizeof(msg));
432 msg.cmd = PORT_CONFIG_WRITE;
433 msg.hss_port = port->id;
434 msg.index = HSS_CONFIG_TX_FCR;
435 msg.data16a = FRAME_OFFSET;
436 msg.data16b = FRAME_SIZE - 1;
437 hss_npe_send(port, &msg, "HSS_SET_TX_FCR");
438
439 memset(&msg, 0, sizeof(msg));
440 msg.cmd = PORT_CONFIG_WRITE;
441 msg.hss_port = port->id;
442 msg.index = HSS_CONFIG_RX_FCR;
443 msg.data16a = FRAME_OFFSET;
444 msg.data16b = FRAME_SIZE - 1;
445 hss_npe_send(port, &msg, "HSS_SET_RX_FCR");
446
447 hss_config_set_lut(port);
448
449 memset(&msg, 0, sizeof(msg));
450 msg.cmd = PORT_CONFIG_LOAD;
451 msg.hss_port = port->id;
452 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG");
453
454 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") ||
455 /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
456 msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
457 pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id);
458 BUG();
459 }
460
461 /* HDLC may stop working without this - check FIXME */
462 npe_recv_message(port->npe, &msg, "FLUSH_IT");
463}
464
465static void hss_set_hdlc_cfg(struct port *port)
466{
467 struct msg msg;
468
469 memset(&msg, 0, sizeof(msg));
470 msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
471 msg.hss_port = port->id;
472 msg.data8a = port->hdlc_cfg; /* rx_cfg */
473 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
474 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG");
475}
476
477static u32 hss_get_status(struct port *port)
478{
479 struct msg msg;
480
481 memset(&msg, 0, sizeof(msg));
482 msg.cmd = PORT_ERROR_READ;
483 msg.hss_port = port->id;
484 hss_npe_send(port, &msg, "PORT_ERROR_READ");
485 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) {
486 pr_crit("HSS-%i: unable to read HSS status\n", port->id);
487 BUG();
488 }
489
490 return msg.data32;
491}
492
493static void hss_start_hdlc(struct port *port)
494{
495 struct msg msg;
496
497 memset(&msg, 0, sizeof(msg));
498 msg.cmd = PKT_PIPE_FLOW_ENABLE;
499 msg.hss_port = port->id;
500 msg.data32 = 0;
501 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE");
502}
503
504static void hss_stop_hdlc(struct port *port)
505{
506 struct msg msg;
507
508 memset(&msg, 0, sizeof(msg));
509 msg.cmd = PKT_PIPE_FLOW_DISABLE;
510 msg.hss_port = port->id;
511 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE");
512 hss_get_status(port); /* make sure it's halted */
513}
514
515static int hss_load_firmware(struct port *port)
516{
517 struct msg msg;
518 int err;
519
520 if (port->initialized)
521 return 0;
522
523 if (!npe_running(port->npe)) {
524 err = npe_load_firmware(port->npe, npe_name(port->npe),
525 port->dev);
526 if (err)
527 return err;
528 }
529
530 /* HDLC mode configuration */
531 memset(&msg, 0, sizeof(msg));
532 msg.cmd = PKT_NUM_PIPES_WRITE;
533 msg.hss_port = port->id;
534 msg.data8a = PKT_NUM_PIPES;
535 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
536
537 msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
538 msg.data8a = PKT_PIPE_FIFO_SIZEW;
539 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO");
540
541 msg.cmd = PKT_PIPE_MODE_WRITE;
542 msg.data8a = NPE_PKT_MODE_HDLC;
543 /* msg.data8b = inv_mask */
544 /* msg.data8c = or_mask */
545 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE");
546
547 msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
548 msg.data16a = HDLC_MAX_MRU; /* including CRC */
549 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE");
550
551 msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
552 msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
553 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE");
554
555 port->initialized = 1;
556 return 0;
557}
558
559/*****************************************************************************
560 * packetized (HDLC) operation
561 ****************************************************************************/
562
563static inline void debug_pkt(struct net_device *dev, const char *func,
564 u8 *data, int len)
565{
566#if DEBUG_PKT_BYTES
567 int i;
568
569 printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len);
570 for (i = 0; i < len; i++) {
571 if (i >= DEBUG_PKT_BYTES)
572 break;
573 printk("%s%02X", !(i % 4) ? " " : "", data[i]);
574 }
575 printk("\n");
576#endif
577}
578
579static inline void debug_desc(u32 phys, struct desc *desc)
580{
581#if DEBUG_DESC
582 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
583 phys, desc->next, desc->buf_len, desc->pkt_len,
584 desc->data, desc->status, desc->error_count);
585#endif
586}
587
588static inline int queue_get_desc(unsigned int queue, struct port *port,
589 int is_tx)
590{
591 u32 phys, tab_phys, n_desc;
592 struct desc *tab;
593
594 phys = qmgr_get_entry(queue);
595 if (!phys)
596 return -1;
597
598 BUG_ON(phys & 0x1F);
599 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
600 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
601 n_desc = (phys - tab_phys) / sizeof(struct desc);
602 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
603 debug_desc(phys, &tab[n_desc]);
604 BUG_ON(tab[n_desc].next);
605 return n_desc;
606}
607
608static inline void queue_put_desc(unsigned int queue, u32 phys,
609 struct desc *desc)
610{
611 debug_desc(phys, desc);
612 BUG_ON(phys & 0x1F);
613 qmgr_put_entry(queue, phys);
614 /* Don't check for queue overflow here, we've allocated sufficient
615 * length and queues >= 32 don't support this check anyway.
616 */
617}
618
619static inline void dma_unmap_tx(struct port *port, struct desc *desc)
620{
621#ifdef __ARMEB__
622 dma_unmap_single(&port->netdev->dev, desc->data,
623 desc->buf_len, DMA_TO_DEVICE);
624#else
625 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
626 ALIGN((desc->data & 3) + desc->buf_len, 4),
627 DMA_TO_DEVICE);
628#endif
629}
630
631static void hss_hdlc_set_carrier(void *pdev, int carrier)
632{
633 struct net_device *netdev = pdev;
634 struct port *port = dev_to_port(netdev);
635 unsigned long flags;
636
637 spin_lock_irqsave(&npe_lock, flags);
638 port->carrier = carrier;
639 if (!port->loopback) {
640 if (carrier)
641 netif_carrier_on(netdev);
642 else
643 netif_carrier_off(netdev);
644 }
645 spin_unlock_irqrestore(&npe_lock, flags);
646}
647
648static void hss_hdlc_rx_irq(void *pdev)
649{
650 struct net_device *dev = pdev;
651 struct port *port = dev_to_port(dev);
652
653#if DEBUG_RX
654 printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
655#endif
656 qmgr_disable_irq(port->rxq);
657 napi_schedule(&port->napi);
658}
659
660static int hss_hdlc_poll(struct napi_struct *napi, int budget)
661{
662 struct port *port = container_of(napi, struct port, napi);
663 struct net_device *dev = port->netdev;
664 unsigned int rxq = port->rxq;
665 unsigned int rxfreeq = port->rxfreeq;
666 int received = 0;
667
668#if DEBUG_RX
669 printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
670#endif
671
672 while (received < budget) {
673 struct sk_buff *skb;
674 struct desc *desc;
675 int n;
676#ifdef __ARMEB__
677 struct sk_buff *temp;
678 u32 phys;
679#endif
680
681 n = queue_get_desc(rxq, port, 0);
682 if (n < 0) {
683#if DEBUG_RX
684 printk(KERN_DEBUG "%s: hss_hdlc_poll"
685 " napi_complete\n", dev->name);
686#endif
687 napi_complete(napi);
688 qmgr_enable_irq(rxq);
689 if (!qmgr_stat_empty(rxq) &&
690 napi_schedule(napi)) {
691#if DEBUG_RX
692 printk(KERN_DEBUG "%s: hss_hdlc_poll"
693 " napi_schedule succeeded\n",
694 dev->name);
695#endif
696 qmgr_disable_irq(rxq);
697 continue;
698 }
699#if DEBUG_RX
700 printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
701 dev->name);
702#endif
703 return received; /* all work done */
704 }
705
706 desc = rx_desc_ptr(port, n);
707#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
708 if (desc->error_count)
709 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
710 " errors %u\n", dev->name, desc->status,
711 desc->error_count);
712#endif
713 skb = NULL;
714 switch (desc->status) {
715 case 0:
716#ifdef __ARMEB__
717 skb = netdev_alloc_skb(dev, RX_SIZE);
718 if (skb) {
719 phys = dma_map_single(&dev->dev, skb->data,
720 RX_SIZE,
721 DMA_FROM_DEVICE);
722 if (dma_mapping_error(&dev->dev, phys)) {
723 dev_kfree_skb(skb);
724 skb = NULL;
725 }
726 }
727#else
728 skb = netdev_alloc_skb(dev, desc->pkt_len);
729#endif
730 if (!skb)
731 dev->stats.rx_dropped++;
732 break;
733 case ERR_HDLC_ALIGN:
734 case ERR_HDLC_ABORT:
735 dev->stats.rx_frame_errors++;
736 dev->stats.rx_errors++;
737 break;
738 case ERR_HDLC_FCS:
739 dev->stats.rx_crc_errors++;
740 dev->stats.rx_errors++;
741 break;
742 case ERR_HDLC_TOO_LONG:
743 dev->stats.rx_length_errors++;
744 dev->stats.rx_errors++;
745 break;
746 default: /* FIXME - remove printk */
747 netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n",
748 desc->status, desc->error_count);
749 dev->stats.rx_errors++;
750 }
751
752 if (!skb) {
753 /* put the desc back on RX-ready queue */
754 desc->buf_len = RX_SIZE;
755 desc->pkt_len = desc->status = 0;
756 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
757 continue;
758 }
759
760 /* process received frame */
761#ifdef __ARMEB__
762 temp = skb;
763 skb = port->rx_buff_tab[n];
764 dma_unmap_single(&dev->dev, desc->data,
765 RX_SIZE, DMA_FROM_DEVICE);
766#else
767 dma_sync_single_for_cpu(&dev->dev, desc->data,
768 RX_SIZE, DMA_FROM_DEVICE);
769 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
770 ALIGN(desc->pkt_len, 4) / 4);
771#endif
772 skb_put(skb, desc->pkt_len);
773
774 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
775
776 skb->protocol = hdlc_type_trans(skb, dev);
777 dev->stats.rx_packets++;
778 dev->stats.rx_bytes += skb->len;
779 netif_receive_skb(skb);
780
781 /* put the new buffer on RX-free queue */
782#ifdef __ARMEB__
783 port->rx_buff_tab[n] = temp;
784 desc->data = phys;
785#endif
786 desc->buf_len = RX_SIZE;
787 desc->pkt_len = 0;
788 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
789 received++;
790 }
791#if DEBUG_RX
792 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
793#endif
794 return received; /* not all work done */
795}
796
797static void hss_hdlc_txdone_irq(void *pdev)
798{
799 struct net_device *dev = pdev;
800 struct port *port = dev_to_port(dev);
801 int n_desc;
802
803#if DEBUG_TX
804 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
805#endif
806 while ((n_desc = queue_get_desc(port->txdoneq,
807 port, 1)) >= 0) {
808 struct desc *desc;
809 int start;
810
811 desc = tx_desc_ptr(port, n_desc);
812
813 dev->stats.tx_packets++;
814 dev->stats.tx_bytes += desc->pkt_len;
815
816 dma_unmap_tx(port, desc);
817#if DEBUG_TX
818 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
819 dev->name, port->tx_buff_tab[n_desc]);
820#endif
821 free_buffer_irq(port->tx_buff_tab[n_desc]);
822 port->tx_buff_tab[n_desc] = NULL;
823
824 start = qmgr_stat_below_low_watermark(port->txreadyq);
825 queue_put_desc(port->txreadyq,
826 tx_desc_phys(port, n_desc), desc);
827 if (start) { /* TX-ready queue was empty */
828#if DEBUG_TX
829 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
830 " ready\n", dev->name);
831#endif
832 netif_wake_queue(dev);
833 }
834 }
835}
836
837static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
838{
839 struct port *port = dev_to_port(dev);
840 unsigned int txreadyq = port->txreadyq;
841 int len, offset, bytes, n;
842 void *mem;
843 u32 phys;
844 struct desc *desc;
845
846#if DEBUG_TX
847 printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
848#endif
849
850 if (unlikely(skb->len > HDLC_MAX_MRU)) {
851 dev_kfree_skb(skb);
852 dev->stats.tx_errors++;
853 return NETDEV_TX_OK;
854 }
855
856 debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
857
858 len = skb->len;
859#ifdef __ARMEB__
860 offset = 0; /* no need to keep alignment */
861 bytes = len;
862 mem = skb->data;
863#else
864 offset = (int)skb->data & 3; /* keep 32-bit alignment */
865 bytes = ALIGN(offset + len, 4);
866 mem = kmalloc(bytes, GFP_ATOMIC);
867 if (!mem) {
868 dev_kfree_skb(skb);
869 dev->stats.tx_dropped++;
870 return NETDEV_TX_OK;
871 }
872 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4);
873 dev_kfree_skb(skb);
874#endif
875
876 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
877 if (dma_mapping_error(&dev->dev, phys)) {
878#ifdef __ARMEB__
879 dev_kfree_skb(skb);
880#else
881 kfree(mem);
882#endif
883 dev->stats.tx_dropped++;
884 return NETDEV_TX_OK;
885 }
886
887 n = queue_get_desc(txreadyq, port, 1);
888 BUG_ON(n < 0);
889 desc = tx_desc_ptr(port, n);
890
891#ifdef __ARMEB__
892 port->tx_buff_tab[n] = skb;
893#else
894 port->tx_buff_tab[n] = mem;
895#endif
896 desc->data = phys + offset;
897 desc->buf_len = desc->pkt_len = len;
898
899 wmb();
900 queue_put_desc(port->txq, tx_desc_phys(port, n), desc);
901
902 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
903#if DEBUG_TX
904 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
905#endif
906 netif_stop_queue(dev);
907 /* we could miss TX ready interrupt */
908 if (!qmgr_stat_below_low_watermark(txreadyq)) {
909#if DEBUG_TX
910 printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
911 dev->name);
912#endif
913 netif_wake_queue(dev);
914 }
915 }
916
917#if DEBUG_TX
918 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
919#endif
920 return NETDEV_TX_OK;
921}
922
923static int request_hdlc_queues(struct port *port)
924{
925 int err;
926
927 err = qmgr_request_queue(port->rxfreeq, RX_DESCS, 0, 0,
928 "%s:RX-free", port->netdev->name);
929 if (err)
930 return err;
931
932 err = qmgr_request_queue(port->rxq, RX_DESCS, 0, 0,
933 "%s:RX", port->netdev->name);
934 if (err)
935 goto rel_rxfree;
936
937 err = qmgr_request_queue(port->txq, TX_DESCS, 0, 0,
938 "%s:TX", port->netdev->name);
939 if (err)
940 goto rel_rx;
941
942 err = qmgr_request_queue(port->txreadyq, TX_DESCS, 0, 0,
943 "%s:TX-ready", port->netdev->name);
944 if (err)
945 goto rel_tx;
946
947 err = qmgr_request_queue(port->txdoneq, TX_DESCS, 0, 0,
948 "%s:TX-done", port->netdev->name);
949 if (err)
950 goto rel_txready;
951 return 0;
952
953rel_txready:
954 qmgr_release_queue(port->txreadyq);
955rel_tx:
956 qmgr_release_queue(port->txq);
957rel_rx:
958 qmgr_release_queue(port->rxq);
959rel_rxfree:
960 qmgr_release_queue(port->rxfreeq);
961 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
962 port->netdev->name);
963 return err;
964}
965
966static void release_hdlc_queues(struct port *port)
967{
968 qmgr_release_queue(port->rxfreeq);
969 qmgr_release_queue(port->rxq);
970 qmgr_release_queue(port->txdoneq);
971 qmgr_release_queue(port->txq);
972 qmgr_release_queue(port->txreadyq);
973}
974
975static int init_hdlc_queues(struct port *port)
976{
977 int i;
978
979 if (!ports_open) {
980 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
981 POOL_ALLOC_SIZE, 32, 0);
982 if (!dma_pool)
983 return -ENOMEM;
984 }
985
986 port->desc_tab = dma_pool_zalloc(dma_pool, GFP_KERNEL,
987 &port->desc_tab_phys);
988 if (!port->desc_tab)
989 return -ENOMEM;
990 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
991 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
992
993 /* Setup RX buffers */
994 for (i = 0; i < RX_DESCS; i++) {
995 struct desc *desc = rx_desc_ptr(port, i);
996 buffer_t *buff;
997 void *data;
998#ifdef __ARMEB__
999 buff = netdev_alloc_skb(port->netdev, RX_SIZE);
1000 if (!buff)
1001 return -ENOMEM;
1002 data = buff->data;
1003#else
1004 buff = kmalloc(RX_SIZE, GFP_KERNEL);
1005 if (!buff)
1006 return -ENOMEM;
1007 data = buff;
1008#endif
1009 desc->buf_len = RX_SIZE;
1010 desc->data = dma_map_single(&port->netdev->dev, data,
1011 RX_SIZE, DMA_FROM_DEVICE);
1012 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1013 free_buffer(buff);
1014 return -EIO;
1015 }
1016 port->rx_buff_tab[i] = buff;
1017 }
1018
1019 return 0;
1020}
1021
1022static void destroy_hdlc_queues(struct port *port)
1023{
1024 int i;
1025
1026 if (port->desc_tab) {
1027 for (i = 0; i < RX_DESCS; i++) {
1028 struct desc *desc = rx_desc_ptr(port, i);
1029 buffer_t *buff = port->rx_buff_tab[i];
1030
1031 if (buff) {
1032 dma_unmap_single(&port->netdev->dev,
1033 desc->data, RX_SIZE,
1034 DMA_FROM_DEVICE);
1035 free_buffer(buff);
1036 }
1037 }
1038 for (i = 0; i < TX_DESCS; i++) {
1039 struct desc *desc = tx_desc_ptr(port, i);
1040 buffer_t *buff = port->tx_buff_tab[i];
1041
1042 if (buff) {
1043 dma_unmap_tx(port, desc);
1044 free_buffer(buff);
1045 }
1046 }
1047 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1048 port->desc_tab = NULL;
1049 }
1050
1051 if (!ports_open && dma_pool) {
1052 dma_pool_destroy(dma_pool);
1053 dma_pool = NULL;
1054 }
1055}
1056
1057static irqreturn_t hss_hdlc_dcd_irq(int irq, void *data)
1058{
1059 struct net_device *dev = data;
1060 struct port *port = dev_to_port(dev);
1061 int val;
1062
1063 val = gpiod_get_value(port->dcd);
1064 hss_hdlc_set_carrier(dev, val);
1065
1066 return IRQ_HANDLED;
1067}
1068
1069static int hss_hdlc_open(struct net_device *dev)
1070{
1071 struct port *port = dev_to_port(dev);
1072 unsigned long flags;
1073 int i, err = 0;
1074 int val;
1075
1076 err = hdlc_open(dev);
1077 if (err)
1078 return err;
1079
1080 err = hss_load_firmware(port);
1081 if (err)
1082 goto err_hdlc_close;
1083
1084 err = request_hdlc_queues(port);
1085 if (err)
1086 goto err_hdlc_close;
1087
1088 err = init_hdlc_queues(port);
1089 if (err)
1090 goto err_destroy_queues;
1091
1092 spin_lock_irqsave(&npe_lock, flags);
1093
1094 /* Set the carrier, the GPIO is flagged active low so this will return
1095 * 1 if DCD is asserted.
1096 */
1097 val = gpiod_get_value(port->dcd);
1098 hss_hdlc_set_carrier(dev, val);
1099
1100 /* Set up an IRQ for DCD */
1101 err = request_irq(gpiod_to_irq(port->dcd), hss_hdlc_dcd_irq, 0, "IXP4xx HSS", dev);
1102 if (err) {
1103 dev_err(&dev->dev, "ixp4xx_hss: failed to request DCD IRQ (%i)\n", err);
1104 goto err_unlock;
1105 }
1106
1107 /* GPIOs are flagged active low so this asserts DTR and RTS */
1108 gpiod_set_value(port->dtr, 1);
1109 gpiod_set_value(port->rts, 1);
1110
1111 spin_unlock_irqrestore(&npe_lock, flags);
1112
1113 /* Populate queues with buffers, no failure after this point */
1114 for (i = 0; i < TX_DESCS; i++)
1115 queue_put_desc(port->txreadyq,
1116 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1117
1118 for (i = 0; i < RX_DESCS; i++)
1119 queue_put_desc(port->rxfreeq,
1120 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1121
1122 napi_enable(&port->napi);
1123 netif_start_queue(dev);
1124
1125 qmgr_set_irq(port->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1126 hss_hdlc_rx_irq, dev);
1127
1128 qmgr_set_irq(port->txdoneq, QUEUE_IRQ_SRC_NOT_EMPTY,
1129 hss_hdlc_txdone_irq, dev);
1130 qmgr_enable_irq(port->txdoneq);
1131
1132 ports_open++;
1133
1134 hss_set_hdlc_cfg(port);
1135 hss_config(port);
1136
1137 hss_start_hdlc(port);
1138
1139 /* we may already have RX data, enables IRQ */
1140 napi_schedule(&port->napi);
1141 return 0;
1142
1143err_unlock:
1144 spin_unlock_irqrestore(&npe_lock, flags);
1145err_destroy_queues:
1146 destroy_hdlc_queues(port);
1147 release_hdlc_queues(port);
1148err_hdlc_close:
1149 hdlc_close(dev);
1150 return err;
1151}
1152
1153static int hss_hdlc_close(struct net_device *dev)
1154{
1155 struct port *port = dev_to_port(dev);
1156 unsigned long flags;
1157 int i, buffs = RX_DESCS; /* allocated RX buffers */
1158
1159 spin_lock_irqsave(&npe_lock, flags);
1160 ports_open--;
1161 qmgr_disable_irq(port->rxq);
1162 netif_stop_queue(dev);
1163 napi_disable(&port->napi);
1164
1165 hss_stop_hdlc(port);
1166
1167 while (queue_get_desc(port->rxfreeq, port, 0) >= 0)
1168 buffs--;
1169 while (queue_get_desc(port->rxq, port, 0) >= 0)
1170 buffs--;
1171
1172 if (buffs)
1173 netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n",
1174 buffs);
1175
1176 buffs = TX_DESCS;
1177 while (queue_get_desc(port->txq, port, 1) >= 0)
1178 buffs--; /* cancel TX */
1179
1180 i = 0;
1181 do {
1182 while (queue_get_desc(port->txreadyq, port, 1) >= 0)
1183 buffs--;
1184 if (!buffs)
1185 break;
1186 } while (++i < MAX_CLOSE_WAIT);
1187
1188 if (buffs)
1189 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n",
1190 buffs);
1191#if DEBUG_CLOSE
1192 if (!buffs)
1193 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1194#endif
1195 qmgr_disable_irq(port->txdoneq);
1196
1197 free_irq(gpiod_to_irq(port->dcd), dev);
1198 /* GPIOs are flagged active low so this de-asserts DTR and RTS */
1199 gpiod_set_value(port->dtr, 0);
1200 gpiod_set_value(port->rts, 0);
1201 spin_unlock_irqrestore(&npe_lock, flags);
1202
1203 destroy_hdlc_queues(port);
1204 release_hdlc_queues(port);
1205 hdlc_close(dev);
1206 return 0;
1207}
1208
1209static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1210 unsigned short parity)
1211{
1212 struct port *port = dev_to_port(dev);
1213
1214 if (encoding != ENCODING_NRZ)
1215 return -EINVAL;
1216
1217 switch (parity) {
1218 case PARITY_CRC16_PR1_CCITT:
1219 port->hdlc_cfg = 0;
1220 return 0;
1221
1222 case PARITY_CRC32_PR1_CCITT:
1223 port->hdlc_cfg = PKT_HDLC_CRC_32;
1224 return 0;
1225
1226 default:
1227 return -EINVAL;
1228 }
1229}
1230
1231static u32 check_clock(u32 timer_freq, u32 rate, u32 a, u32 b, u32 c,
1232 u32 *best, u32 *best_diff, u32 *reg)
1233{
1234 /* a is 10-bit, b is 10-bit, c is 12-bit */
1235 u64 new_rate;
1236 u32 new_diff;
1237
1238 new_rate = timer_freq * (u64)(c + 1);
1239 do_div(new_rate, a * (c + 1) + b + 1);
1240 new_diff = abs((u32)new_rate - rate);
1241
1242 if (new_diff < *best_diff) {
1243 *best = new_rate;
1244 *best_diff = new_diff;
1245 *reg = (a << 22) | (b << 12) | c;
1246 }
1247 return new_diff;
1248}
1249
1250static void find_best_clock(u32 timer_freq, u32 rate, u32 *best, u32 *reg)
1251{
1252 u32 a, b, diff = 0xFFFFFFFF;
1253
1254 a = timer_freq / rate;
1255
1256 if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */
1257 check_clock(timer_freq, rate, 0x3FF, 1, 1, best, &diff, reg);
1258 return;
1259 }
1260 if (a == 0) { /* > 66.666 MHz */
1261 a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */
1262 rate = timer_freq;
1263 }
1264
1265 if (rate * a == timer_freq) { /* don't divide by 0 later */
1266 check_clock(timer_freq, rate, a - 1, 1, 1, best, &diff, reg);
1267 return;
1268 }
1269
1270 for (b = 0; b < 0x400; b++) {
1271 u64 c = (b + 1) * (u64)rate;
1272
1273 do_div(c, timer_freq - rate * a);
1274 c--;
1275 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
1276 if (b == 0 && /* also try a bit higher rate */
1277 !check_clock(timer_freq, rate, a - 1, 1, 1, best,
1278 &diff, reg))
1279 return;
1280 check_clock(timer_freq, rate, a, b, 0xFFF, best,
1281 &diff, reg);
1282 return;
1283 }
1284 if (!check_clock(timer_freq, rate, a, b, c, best, &diff, reg))
1285 return;
1286 if (!check_clock(timer_freq, rate, a, b, c + 1, best, &diff,
1287 reg))
1288 return;
1289 }
1290}
1291
1292static int hss_hdlc_set_clock(struct port *port, unsigned int clock_type)
1293{
1294 switch (clock_type) {
1295 case CLOCK_DEFAULT:
1296 case CLOCK_EXT:
1297 gpiod_set_value(port->clk_internal, 0);
1298 return CLOCK_EXT;
1299 case CLOCK_INT:
1300 gpiod_set_value(port->clk_internal, 1);
1301 return CLOCK_INT;
1302 default:
1303 return -EINVAL;
1304 }
1305}
1306
1307static int hss_hdlc_ioctl(struct net_device *dev, struct if_settings *ifs)
1308{
1309 const size_t size = sizeof(sync_serial_settings);
1310 sync_serial_settings new_line;
1311 sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
1312 struct port *port = dev_to_port(dev);
1313 unsigned long flags;
1314 int clk;
1315
1316 switch (ifs->type) {
1317 case IF_GET_IFACE:
1318 ifs->type = IF_IFACE_V35;
1319 if (ifs->size < size) {
1320 ifs->size = size; /* data size wanted */
1321 return -ENOBUFS;
1322 }
1323 memset(&new_line, 0, sizeof(new_line));
1324 new_line.clock_type = port->clock_type;
1325 new_line.clock_rate = port->clock_rate;
1326 new_line.loopback = port->loopback;
1327 if (copy_to_user(line, &new_line, size))
1328 return -EFAULT;
1329 return 0;
1330
1331 case IF_IFACE_SYNC_SERIAL:
1332 case IF_IFACE_V35:
1333 if (!capable(CAP_NET_ADMIN))
1334 return -EPERM;
1335 if (copy_from_user(&new_line, line, size))
1336 return -EFAULT;
1337
1338 clk = new_line.clock_type;
1339 hss_hdlc_set_clock(port, clk);
1340
1341 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1342 return -EINVAL; /* No such clock setting */
1343
1344 if (new_line.loopback != 0 && new_line.loopback != 1)
1345 return -EINVAL;
1346
1347 port->clock_type = clk; /* Update settings */
1348 if (clk == CLOCK_INT) {
1349 find_best_clock(IXP4XX_TIMER_FREQ,
1350 new_line.clock_rate,
1351 &port->clock_rate, &port->clock_reg);
1352 } else {
1353 port->clock_rate = 0;
1354 port->clock_reg = CLK42X_SPEED_2048KHZ;
1355 }
1356 port->loopback = new_line.loopback;
1357
1358 spin_lock_irqsave(&npe_lock, flags);
1359
1360 if (dev->flags & IFF_UP)
1361 hss_config(port);
1362
1363 if (port->loopback || port->carrier)
1364 netif_carrier_on(port->netdev);
1365 else
1366 netif_carrier_off(port->netdev);
1367 spin_unlock_irqrestore(&npe_lock, flags);
1368
1369 return 0;
1370
1371 default:
1372 return hdlc_ioctl(dev, ifs);
1373 }
1374}
1375
1376/*****************************************************************************
1377 * initialization
1378 ****************************************************************************/
1379
1380static const struct net_device_ops hss_hdlc_ops = {
1381 .ndo_open = hss_hdlc_open,
1382 .ndo_stop = hss_hdlc_close,
1383 .ndo_start_xmit = hdlc_start_xmit,
1384 .ndo_siocwandev = hss_hdlc_ioctl,
1385};
1386
1387static int ixp4xx_hss_probe(struct platform_device *pdev)
1388{
1389 struct of_phandle_args queue_spec;
1390 struct of_phandle_args npe_spec;
1391 struct device *dev = &pdev->dev;
1392 struct net_device *ndev;
1393 struct device_node *np;
1394 struct regmap *rmap;
1395 struct port *port;
1396 hdlc_device *hdlc;
1397 int err;
1398 u32 val;
1399
1400 /*
1401 * Go into the syscon and check if we have the HSS and HDLC
1402 * features available, else this will not work.
1403 */
1404 rmap = syscon_regmap_lookup_by_compatible("syscon");
1405 if (IS_ERR(rmap))
1406 return dev_err_probe(dev, PTR_ERR(rmap),
1407 "failed to look up syscon\n");
1408
1409 val = cpu_ixp4xx_features(rmap);
1410
1411 if ((val & (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
1412 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) {
1413 dev_err(dev, "HDLC and HSS feature unavailable in platform\n");
1414 return -ENODEV;
1415 }
1416
1417 np = dev->of_node;
1418
1419 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
1420 if (!port)
1421 return -ENOMEM;
1422
1423 err = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0,
1424 &npe_spec);
1425 if (err)
1426 return dev_err_probe(dev, err, "no NPE engine specified\n");
1427 /* NPE ID 0x00, 0x10, 0x20... */
1428 port->npe = npe_request(npe_spec.args[0] << 4);
1429 if (!port->npe) {
1430 dev_err(dev, "unable to obtain NPE instance\n");
1431 return -ENODEV;
1432 }
1433
1434 /* Get the TX ready queue as resource from queue manager */
1435 err = of_parse_phandle_with_fixed_args(np, "intek,queue-chl-txready", 1, 0,
1436 &queue_spec);
1437 if (err)
1438 return dev_err_probe(dev, err, "no txready queue phandle\n");
1439 port->txreadyq = queue_spec.args[0];
1440 /* Get the RX trig queue as resource from queue manager */
1441 err = of_parse_phandle_with_fixed_args(np, "intek,queue-chl-rxtrig", 1, 0,
1442 &queue_spec);
1443 if (err)
1444 return dev_err_probe(dev, err, "no rxtrig queue phandle\n");
1445 port->rxtrigq = queue_spec.args[0];
1446 /* Get the RX queue as resource from queue manager */
1447 err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-rx", 1, 0,
1448 &queue_spec);
1449 if (err)
1450 return dev_err_probe(dev, err, "no RX queue phandle\n");
1451 port->rxq = queue_spec.args[0];
1452 /* Get the TX queue as resource from queue manager */
1453 err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-tx", 1, 0,
1454 &queue_spec);
1455 if (err)
1456 return dev_err_probe(dev, err, "no RX queue phandle\n");
1457 port->txq = queue_spec.args[0];
1458 /* Get the RX free queue as resource from queue manager */
1459 err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-rxfree", 1, 0,
1460 &queue_spec);
1461 if (err)
1462 return dev_err_probe(dev, err, "no RX free queue phandle\n");
1463 port->rxfreeq = queue_spec.args[0];
1464 /* Get the TX done queue as resource from queue manager */
1465 err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-txdone", 1, 0,
1466 &queue_spec);
1467 if (err)
1468 return dev_err_probe(dev, err, "no TX done queue phandle\n");
1469 port->txdoneq = queue_spec.args[0];
1470
1471 /* Obtain all the line control GPIOs */
1472 port->cts = devm_gpiod_get(dev, "cts", GPIOD_OUT_LOW);
1473 if (IS_ERR(port->cts))
1474 return dev_err_probe(dev, PTR_ERR(port->cts), "unable to get CTS GPIO\n");
1475 port->rts = devm_gpiod_get(dev, "rts", GPIOD_OUT_LOW);
1476 if (IS_ERR(port->rts))
1477 return dev_err_probe(dev, PTR_ERR(port->rts), "unable to get RTS GPIO\n");
1478 port->dcd = devm_gpiod_get(dev, "dcd", GPIOD_IN);
1479 if (IS_ERR(port->dcd))
1480 return dev_err_probe(dev, PTR_ERR(port->dcd), "unable to get DCD GPIO\n");
1481 port->dtr = devm_gpiod_get(dev, "dtr", GPIOD_OUT_LOW);
1482 if (IS_ERR(port->dtr))
1483 return dev_err_probe(dev, PTR_ERR(port->dtr), "unable to get DTR GPIO\n");
1484 port->clk_internal = devm_gpiod_get(dev, "clk-internal", GPIOD_OUT_LOW);
1485 if (IS_ERR(port->clk_internal))
1486 return dev_err_probe(dev, PTR_ERR(port->clk_internal),
1487 "unable to get CLK internal GPIO\n");
1488
1489 ndev = alloc_hdlcdev(port);
1490 port->netdev = alloc_hdlcdev(port);
1491 if (!port->netdev) {
1492 err = -ENOMEM;
1493 goto err_plat;
1494 }
1495
1496 SET_NETDEV_DEV(ndev, &pdev->dev);
1497 hdlc = dev_to_hdlc(ndev);
1498 hdlc->attach = hss_hdlc_attach;
1499 hdlc->xmit = hss_hdlc_xmit;
1500 ndev->netdev_ops = &hss_hdlc_ops;
1501 ndev->tx_queue_len = 100;
1502 port->clock_type = CLOCK_EXT;
1503 port->clock_rate = 0;
1504 port->clock_reg = CLK42X_SPEED_2048KHZ;
1505 port->id = pdev->id;
1506 port->dev = &pdev->dev;
1507 netif_napi_add_weight(ndev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1508
1509 err = register_hdlc_device(ndev);
1510 if (err)
1511 goto err_free_netdev;
1512
1513 platform_set_drvdata(pdev, port);
1514
1515 netdev_info(ndev, "initialized\n");
1516 return 0;
1517
1518err_free_netdev:
1519 free_netdev(ndev);
1520err_plat:
1521 npe_release(port->npe);
1522 return err;
1523}
1524
1525static void ixp4xx_hss_remove(struct platform_device *pdev)
1526{
1527 struct port *port = platform_get_drvdata(pdev);
1528
1529 unregister_hdlc_device(port->netdev);
1530 free_netdev(port->netdev);
1531 npe_release(port->npe);
1532}
1533
1534static struct platform_driver ixp4xx_hss_driver = {
1535 .driver.name = DRV_NAME,
1536 .probe = ixp4xx_hss_probe,
1537 .remove = ixp4xx_hss_remove,
1538};
1539module_platform_driver(ixp4xx_hss_driver);
1540
1541MODULE_AUTHOR("Krzysztof Halasa");
1542MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
1543MODULE_LICENSE("GPL v2");
1544MODULE_ALIAS("platform:ixp4xx_hss");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Intel IXP4xx HSS (synchronous serial port) driver for Linux
4 *
5 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/module.h>
11#include <linux/bitops.h>
12#include <linux/cdev.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmapool.h>
15#include <linux/fs.h>
16#include <linux/hdlc.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/platform_data/wan_ixp4xx_hss.h>
21#include <linux/poll.h>
22#include <linux/slab.h>
23#include <linux/soc/ixp4xx/npe.h>
24#include <linux/soc/ixp4xx/qmgr.h>
25
26#define DEBUG_DESC 0
27#define DEBUG_RX 0
28#define DEBUG_TX 0
29#define DEBUG_PKT_BYTES 0
30#define DEBUG_CLOSE 0
31
32#define DRV_NAME "ixp4xx_hss"
33
34#define PKT_EXTRA_FLAGS 0 /* orig 1 */
35#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
36#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
37
38#define RX_DESCS 16 /* also length of all RX queues */
39#define TX_DESCS 16 /* also length of all TX queues */
40
41#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
42#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
43#define MAX_CLOSE_WAIT 1000 /* microseconds */
44#define HSS_COUNT 2
45#define FRAME_SIZE 256 /* doesn't matter at this point */
46#define FRAME_OFFSET 0
47#define MAX_CHANNELS (FRAME_SIZE / 8)
48
49#define NAPI_WEIGHT 16
50
51/* Queue IDs */
52#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
53#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
54#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
55#define HSS0_PKT_TX1_QUEUE 15
56#define HSS0_PKT_TX2_QUEUE 16
57#define HSS0_PKT_TX3_QUEUE 17
58#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
59#define HSS0_PKT_RXFREE1_QUEUE 19
60#define HSS0_PKT_RXFREE2_QUEUE 20
61#define HSS0_PKT_RXFREE3_QUEUE 21
62#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
63
64#define HSS1_CHL_RXTRIG_QUEUE 10
65#define HSS1_PKT_RX_QUEUE 0
66#define HSS1_PKT_TX0_QUEUE 5
67#define HSS1_PKT_TX1_QUEUE 6
68#define HSS1_PKT_TX2_QUEUE 7
69#define HSS1_PKT_TX3_QUEUE 8
70#define HSS1_PKT_RXFREE0_QUEUE 1
71#define HSS1_PKT_RXFREE1_QUEUE 2
72#define HSS1_PKT_RXFREE2_QUEUE 3
73#define HSS1_PKT_RXFREE3_QUEUE 4
74#define HSS1_PKT_TXDONE_QUEUE 9
75
76#define NPE_PKT_MODE_HDLC 0
77#define NPE_PKT_MODE_RAW 1
78#define NPE_PKT_MODE_56KMODE 2
79#define NPE_PKT_MODE_56KENDIAN_MSB 4
80
81/* PKT_PIPE_HDLC_CFG_WRITE flags */
82#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
83#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
84#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
85
86
87/* hss_config, PCRs */
88/* Frame sync sampling, default = active low */
89#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
90#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
91#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
92
93/* Frame sync pin: input (default) or output generated off a given clk edge */
94#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
95#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
96
97/* Frame and data clock sampling on edge, default = falling */
98#define PCR_FCLK_EDGE_RISING 0x08000000
99#define PCR_DCLK_EDGE_RISING 0x04000000
100
101/* Clock direction, default = input */
102#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
103
104/* Generate/Receive frame pulses, default = enabled */
105#define PCR_FRM_PULSE_DISABLED 0x01000000
106
107 /* Data rate is full (default) or half the configured clk speed */
108#define PCR_HALF_CLK_RATE 0x00200000
109
110/* Invert data between NPE and HSS FIFOs? (default = no) */
111#define PCR_DATA_POLARITY_INVERT 0x00100000
112
113/* TX/RX endianness, default = LSB */
114#define PCR_MSB_ENDIAN 0x00080000
115
116/* Normal (default) / open drain mode (TX only) */
117#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
118
119/* No framing bit transmitted and expected on RX? (default = framing bit) */
120#define PCR_SOF_NO_FBIT 0x00020000
121
122/* Drive data pins? */
123#define PCR_TX_DATA_ENABLE 0x00010000
124
125/* Voice 56k type: drive the data pins low (default), high, high Z */
126#define PCR_TX_V56K_HIGH 0x00002000
127#define PCR_TX_V56K_HIGH_IMP 0x00004000
128
129/* Unassigned type: drive the data pins low (default), high, high Z */
130#define PCR_TX_UNASS_HIGH 0x00000800
131#define PCR_TX_UNASS_HIGH_IMP 0x00001000
132
133/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
134#define PCR_TX_FB_HIGH_IMP 0x00000400
135
136/* 56k data endiannes - which bit unused: high (default) or low */
137#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
138
139/* 56k data transmission type: 32/8 bit data (default) or 56K data */
140#define PCR_TX_56KS_56K_DATA 0x00000100
141
142/* hss_config, cCR */
143/* Number of packetized clients, default = 1 */
144#define CCR_NPE_HFIFO_2_HDLC 0x04000000
145#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
146
147/* default = no loopback */
148#define CCR_LOOPBACK 0x02000000
149
150/* HSS number, default = 0 (first) */
151#define CCR_SECOND_HSS 0x01000000
152
153
154/* hss_config, clkCR: main:10, num:10, denom:12 */
155#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
156
157#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
158#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
159#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
160#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
161#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
162#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
163
164#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
165#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
166#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
167#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
168#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
169#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
170
171/*
172 * HSS_CONFIG_CLOCK_CR register consists of 3 parts:
173 * A (10 bits), B (10 bits) and C (12 bits).
174 * IXP42x HSS clock generator operation (verified with an oscilloscope):
175 * Each clock bit takes 7.5 ns (1 / 133.xx MHz).
176 * The clock sequence consists of (C - B) states of 0s and 1s, each state is
177 * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is
178 * (A + 1) bits wide.
179 *
180 * The resulting average clock frequency (assuming 33.333 MHz oscillator) is:
181 * freq = 66.666 MHz / (A + (B + 1) / (C + 1))
182 * minimum freq = 66.666 MHz / (A + 1)
183 * maximum freq = 66.666 MHz / A
184 *
185 * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7
186 * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s).
187 * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples).
188 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits
189 * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats).
190 * The sequence consists of 4 complete clock periods, thus the average
191 * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s).
192 * (max specified clock rate for IXP42x HSS is 8.192 Mb/s).
193 */
194
195/* hss_config, LUT entries */
196#define TDMMAP_UNASSIGNED 0
197#define TDMMAP_HDLC 1 /* HDLC - packetized */
198#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
199#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
200
201/* offsets into HSS config */
202#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
203#define HSS_CONFIG_RX_PCR 0x04
204#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
205#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
206#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
207#define HSS_CONFIG_RX_FCR 0x14
208#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
209#define HSS_CONFIG_RX_LUT 0x38
210
211
212/* NPE command codes */
213/* writes the ConfigWord value to the location specified by offset */
214#define PORT_CONFIG_WRITE 0x40
215
216/* triggers the NPE to load the contents of the configuration table */
217#define PORT_CONFIG_LOAD 0x41
218
219/* triggers the NPE to return an HssErrorReadResponse message */
220#define PORT_ERROR_READ 0x42
221
222/* triggers the NPE to reset internal status and enable the HssPacketized
223 operation for the flow specified by pPipe */
224#define PKT_PIPE_FLOW_ENABLE 0x50
225#define PKT_PIPE_FLOW_DISABLE 0x51
226#define PKT_NUM_PIPES_WRITE 0x52
227#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
228#define PKT_PIPE_HDLC_CFG_WRITE 0x54
229#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
230#define PKT_PIPE_RX_SIZE_WRITE 0x56
231#define PKT_PIPE_MODE_WRITE 0x57
232
233/* HDLC packet status values - desc->status */
234#define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */
235#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
236#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
237#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
238 this packet (if buf_len < pkt_len) */
239#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
240#define ERR_HDLC_ABORT 6 /* abort sequence received */
241#define ERR_DISCONNECTING 7 /* disconnect is in progress */
242
243
244#ifdef __ARMEB__
245typedef struct sk_buff buffer_t;
246#define free_buffer dev_kfree_skb
247#define free_buffer_irq dev_consume_skb_irq
248#else
249typedef void buffer_t;
250#define free_buffer kfree
251#define free_buffer_irq kfree
252#endif
253
254struct port {
255 struct device *dev;
256 struct npe *npe;
257 struct net_device *netdev;
258 struct napi_struct napi;
259 struct hss_plat_info *plat;
260 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
261 struct desc *desc_tab; /* coherent */
262 dma_addr_t desc_tab_phys;
263 unsigned int id;
264 unsigned int clock_type, clock_rate, loopback;
265 unsigned int initialized, carrier;
266 u8 hdlc_cfg;
267 u32 clock_reg;
268};
269
270/* NPE message structure */
271struct msg {
272#ifdef __ARMEB__
273 u8 cmd, unused, hss_port, index;
274 union {
275 struct { u8 data8a, data8b, data8c, data8d; };
276 struct { u16 data16a, data16b; };
277 struct { u32 data32; };
278 };
279#else
280 u8 index, hss_port, unused, cmd;
281 union {
282 struct { u8 data8d, data8c, data8b, data8a; };
283 struct { u16 data16b, data16a; };
284 struct { u32 data32; };
285 };
286#endif
287};
288
289/* HDLC packet descriptor */
290struct desc {
291 u32 next; /* pointer to next buffer, unused */
292
293#ifdef __ARMEB__
294 u16 buf_len; /* buffer length */
295 u16 pkt_len; /* packet length */
296 u32 data; /* pointer to data buffer in RAM */
297 u8 status;
298 u8 error_count;
299 u16 __reserved;
300#else
301 u16 pkt_len; /* packet length */
302 u16 buf_len; /* buffer length */
303 u32 data; /* pointer to data buffer in RAM */
304 u16 __reserved;
305 u8 error_count;
306 u8 status;
307#endif
308 u32 __reserved1[4];
309};
310
311
312#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
313 (n) * sizeof(struct desc))
314#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
315
316#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
317 ((n) + RX_DESCS) * sizeof(struct desc))
318#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
319
320/*****************************************************************************
321 * global variables
322 ****************************************************************************/
323
324static int ports_open;
325static struct dma_pool *dma_pool;
326static spinlock_t npe_lock;
327
328static const struct {
329 int tx, txdone, rx, rxfree;
330}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
331 HSS0_PKT_RXFREE0_QUEUE},
332 {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
333 HSS1_PKT_RXFREE0_QUEUE},
334};
335
336/*****************************************************************************
337 * utility functions
338 ****************************************************************************/
339
340static inline struct port* dev_to_port(struct net_device *dev)
341{
342 return dev_to_hdlc(dev)->priv;
343}
344
345#ifndef __ARMEB__
346static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
347{
348 int i;
349 for (i = 0; i < cnt; i++)
350 dest[i] = swab32(src[i]);
351}
352#endif
353
354/*****************************************************************************
355 * HSS access
356 ****************************************************************************/
357
358static void hss_npe_send(struct port *port, struct msg *msg, const char* what)
359{
360 u32 *val = (u32*)msg;
361 if (npe_send_message(port->npe, msg, what)) {
362 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n",
363 port->id, val[0], val[1], npe_name(port->npe));
364 BUG();
365 }
366}
367
368static void hss_config_set_lut(struct port *port)
369{
370 struct msg msg;
371 int ch;
372
373 memset(&msg, 0, sizeof(msg));
374 msg.cmd = PORT_CONFIG_WRITE;
375 msg.hss_port = port->id;
376
377 for (ch = 0; ch < MAX_CHANNELS; ch++) {
378 msg.data32 >>= 2;
379 msg.data32 |= TDMMAP_HDLC << 30;
380
381 if (ch % 16 == 15) {
382 msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
383 hss_npe_send(port, &msg, "HSS_SET_TX_LUT");
384
385 msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
386 hss_npe_send(port, &msg, "HSS_SET_RX_LUT");
387 }
388 }
389}
390
391static void hss_config(struct port *port)
392{
393 struct msg msg;
394
395 memset(&msg, 0, sizeof(msg));
396 msg.cmd = PORT_CONFIG_WRITE;
397 msg.hss_port = port->id;
398 msg.index = HSS_CONFIG_TX_PCR;
399 msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN |
400 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT;
401 if (port->clock_type == CLOCK_INT)
402 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
403 hss_npe_send(port, &msg, "HSS_SET_TX_PCR");
404
405 msg.index = HSS_CONFIG_RX_PCR;
406 msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
407 hss_npe_send(port, &msg, "HSS_SET_RX_PCR");
408
409 memset(&msg, 0, sizeof(msg));
410 msg.cmd = PORT_CONFIG_WRITE;
411 msg.hss_port = port->id;
412 msg.index = HSS_CONFIG_CORE_CR;
413 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
414 (port->id ? CCR_SECOND_HSS : 0);
415 hss_npe_send(port, &msg, "HSS_SET_CORE_CR");
416
417 memset(&msg, 0, sizeof(msg));
418 msg.cmd = PORT_CONFIG_WRITE;
419 msg.hss_port = port->id;
420 msg.index = HSS_CONFIG_CLOCK_CR;
421 msg.data32 = port->clock_reg;
422 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
423
424 memset(&msg, 0, sizeof(msg));
425 msg.cmd = PORT_CONFIG_WRITE;
426 msg.hss_port = port->id;
427 msg.index = HSS_CONFIG_TX_FCR;
428 msg.data16a = FRAME_OFFSET;
429 msg.data16b = FRAME_SIZE - 1;
430 hss_npe_send(port, &msg, "HSS_SET_TX_FCR");
431
432 memset(&msg, 0, sizeof(msg));
433 msg.cmd = PORT_CONFIG_WRITE;
434 msg.hss_port = port->id;
435 msg.index = HSS_CONFIG_RX_FCR;
436 msg.data16a = FRAME_OFFSET;
437 msg.data16b = FRAME_SIZE - 1;
438 hss_npe_send(port, &msg, "HSS_SET_RX_FCR");
439
440 hss_config_set_lut(port);
441
442 memset(&msg, 0, sizeof(msg));
443 msg.cmd = PORT_CONFIG_LOAD;
444 msg.hss_port = port->id;
445 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG");
446
447 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") ||
448 /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
449 msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
450 pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id);
451 BUG();
452 }
453
454 /* HDLC may stop working without this - check FIXME */
455 npe_recv_message(port->npe, &msg, "FLUSH_IT");
456}
457
458static void hss_set_hdlc_cfg(struct port *port)
459{
460 struct msg msg;
461
462 memset(&msg, 0, sizeof(msg));
463 msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
464 msg.hss_port = port->id;
465 msg.data8a = port->hdlc_cfg; /* rx_cfg */
466 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
467 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG");
468}
469
470static u32 hss_get_status(struct port *port)
471{
472 struct msg msg;
473
474 memset(&msg, 0, sizeof(msg));
475 msg.cmd = PORT_ERROR_READ;
476 msg.hss_port = port->id;
477 hss_npe_send(port, &msg, "PORT_ERROR_READ");
478 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) {
479 pr_crit("HSS-%i: unable to read HSS status\n", port->id);
480 BUG();
481 }
482
483 return msg.data32;
484}
485
486static void hss_start_hdlc(struct port *port)
487{
488 struct msg msg;
489
490 memset(&msg, 0, sizeof(msg));
491 msg.cmd = PKT_PIPE_FLOW_ENABLE;
492 msg.hss_port = port->id;
493 msg.data32 = 0;
494 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE");
495}
496
497static void hss_stop_hdlc(struct port *port)
498{
499 struct msg msg;
500
501 memset(&msg, 0, sizeof(msg));
502 msg.cmd = PKT_PIPE_FLOW_DISABLE;
503 msg.hss_port = port->id;
504 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE");
505 hss_get_status(port); /* make sure it's halted */
506}
507
508static int hss_load_firmware(struct port *port)
509{
510 struct msg msg;
511 int err;
512
513 if (port->initialized)
514 return 0;
515
516 if (!npe_running(port->npe) &&
517 (err = npe_load_firmware(port->npe, npe_name(port->npe),
518 port->dev)))
519 return err;
520
521 /* HDLC mode configuration */
522 memset(&msg, 0, sizeof(msg));
523 msg.cmd = PKT_NUM_PIPES_WRITE;
524 msg.hss_port = port->id;
525 msg.data8a = PKT_NUM_PIPES;
526 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
527
528 msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
529 msg.data8a = PKT_PIPE_FIFO_SIZEW;
530 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO");
531
532 msg.cmd = PKT_PIPE_MODE_WRITE;
533 msg.data8a = NPE_PKT_MODE_HDLC;
534 /* msg.data8b = inv_mask */
535 /* msg.data8c = or_mask */
536 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE");
537
538 msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
539 msg.data16a = HDLC_MAX_MRU; /* including CRC */
540 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE");
541
542 msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
543 msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
544 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE");
545
546 port->initialized = 1;
547 return 0;
548}
549
550/*****************************************************************************
551 * packetized (HDLC) operation
552 ****************************************************************************/
553
554static inline void debug_pkt(struct net_device *dev, const char *func,
555 u8 *data, int len)
556{
557#if DEBUG_PKT_BYTES
558 int i;
559
560 printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len);
561 for (i = 0; i < len; i++) {
562 if (i >= DEBUG_PKT_BYTES)
563 break;
564 printk("%s%02X", !(i % 4) ? " " : "", data[i]);
565 }
566 printk("\n");
567#endif
568}
569
570
571static inline void debug_desc(u32 phys, struct desc *desc)
572{
573#if DEBUG_DESC
574 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
575 phys, desc->next, desc->buf_len, desc->pkt_len,
576 desc->data, desc->status, desc->error_count);
577#endif
578}
579
580static inline int queue_get_desc(unsigned int queue, struct port *port,
581 int is_tx)
582{
583 u32 phys, tab_phys, n_desc;
584 struct desc *tab;
585
586 if (!(phys = qmgr_get_entry(queue)))
587 return -1;
588
589 BUG_ON(phys & 0x1F);
590 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
591 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
592 n_desc = (phys - tab_phys) / sizeof(struct desc);
593 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
594 debug_desc(phys, &tab[n_desc]);
595 BUG_ON(tab[n_desc].next);
596 return n_desc;
597}
598
599static inline void queue_put_desc(unsigned int queue, u32 phys,
600 struct desc *desc)
601{
602 debug_desc(phys, desc);
603 BUG_ON(phys & 0x1F);
604 qmgr_put_entry(queue, phys);
605 /* Don't check for queue overflow here, we've allocated sufficient
606 length and queues >= 32 don't support this check anyway. */
607}
608
609
610static inline void dma_unmap_tx(struct port *port, struct desc *desc)
611{
612#ifdef __ARMEB__
613 dma_unmap_single(&port->netdev->dev, desc->data,
614 desc->buf_len, DMA_TO_DEVICE);
615#else
616 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
617 ALIGN((desc->data & 3) + desc->buf_len, 4),
618 DMA_TO_DEVICE);
619#endif
620}
621
622
623static void hss_hdlc_set_carrier(void *pdev, int carrier)
624{
625 struct net_device *netdev = pdev;
626 struct port *port = dev_to_port(netdev);
627 unsigned long flags;
628
629 spin_lock_irqsave(&npe_lock, flags);
630 port->carrier = carrier;
631 if (!port->loopback) {
632 if (carrier)
633 netif_carrier_on(netdev);
634 else
635 netif_carrier_off(netdev);
636 }
637 spin_unlock_irqrestore(&npe_lock, flags);
638}
639
640static void hss_hdlc_rx_irq(void *pdev)
641{
642 struct net_device *dev = pdev;
643 struct port *port = dev_to_port(dev);
644
645#if DEBUG_RX
646 printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
647#endif
648 qmgr_disable_irq(queue_ids[port->id].rx);
649 napi_schedule(&port->napi);
650}
651
652static int hss_hdlc_poll(struct napi_struct *napi, int budget)
653{
654 struct port *port = container_of(napi, struct port, napi);
655 struct net_device *dev = port->netdev;
656 unsigned int rxq = queue_ids[port->id].rx;
657 unsigned int rxfreeq = queue_ids[port->id].rxfree;
658 int received = 0;
659
660#if DEBUG_RX
661 printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
662#endif
663
664 while (received < budget) {
665 struct sk_buff *skb;
666 struct desc *desc;
667 int n;
668#ifdef __ARMEB__
669 struct sk_buff *temp;
670 u32 phys;
671#endif
672
673 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
674#if DEBUG_RX
675 printk(KERN_DEBUG "%s: hss_hdlc_poll"
676 " napi_complete\n", dev->name);
677#endif
678 napi_complete(napi);
679 qmgr_enable_irq(rxq);
680 if (!qmgr_stat_empty(rxq) &&
681 napi_reschedule(napi)) {
682#if DEBUG_RX
683 printk(KERN_DEBUG "%s: hss_hdlc_poll"
684 " napi_reschedule succeeded\n",
685 dev->name);
686#endif
687 qmgr_disable_irq(rxq);
688 continue;
689 }
690#if DEBUG_RX
691 printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
692 dev->name);
693#endif
694 return received; /* all work done */
695 }
696
697 desc = rx_desc_ptr(port, n);
698#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
699 if (desc->error_count)
700 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
701 " errors %u\n", dev->name, desc->status,
702 desc->error_count);
703#endif
704 skb = NULL;
705 switch (desc->status) {
706 case 0:
707#ifdef __ARMEB__
708 if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
709 phys = dma_map_single(&dev->dev, skb->data,
710 RX_SIZE,
711 DMA_FROM_DEVICE);
712 if (dma_mapping_error(&dev->dev, phys)) {
713 dev_kfree_skb(skb);
714 skb = NULL;
715 }
716 }
717#else
718 skb = netdev_alloc_skb(dev, desc->pkt_len);
719#endif
720 if (!skb)
721 dev->stats.rx_dropped++;
722 break;
723 case ERR_HDLC_ALIGN:
724 case ERR_HDLC_ABORT:
725 dev->stats.rx_frame_errors++;
726 dev->stats.rx_errors++;
727 break;
728 case ERR_HDLC_FCS:
729 dev->stats.rx_crc_errors++;
730 dev->stats.rx_errors++;
731 break;
732 case ERR_HDLC_TOO_LONG:
733 dev->stats.rx_length_errors++;
734 dev->stats.rx_errors++;
735 break;
736 default: /* FIXME - remove printk */
737 netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n",
738 desc->status, desc->error_count);
739 dev->stats.rx_errors++;
740 }
741
742 if (!skb) {
743 /* put the desc back on RX-ready queue */
744 desc->buf_len = RX_SIZE;
745 desc->pkt_len = desc->status = 0;
746 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
747 continue;
748 }
749
750 /* process received frame */
751#ifdef __ARMEB__
752 temp = skb;
753 skb = port->rx_buff_tab[n];
754 dma_unmap_single(&dev->dev, desc->data,
755 RX_SIZE, DMA_FROM_DEVICE);
756#else
757 dma_sync_single_for_cpu(&dev->dev, desc->data,
758 RX_SIZE, DMA_FROM_DEVICE);
759 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
760 ALIGN(desc->pkt_len, 4) / 4);
761#endif
762 skb_put(skb, desc->pkt_len);
763
764 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
765
766 skb->protocol = hdlc_type_trans(skb, dev);
767 dev->stats.rx_packets++;
768 dev->stats.rx_bytes += skb->len;
769 netif_receive_skb(skb);
770
771 /* put the new buffer on RX-free queue */
772#ifdef __ARMEB__
773 port->rx_buff_tab[n] = temp;
774 desc->data = phys;
775#endif
776 desc->buf_len = RX_SIZE;
777 desc->pkt_len = 0;
778 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
779 received++;
780 }
781#if DEBUG_RX
782 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
783#endif
784 return received; /* not all work done */
785}
786
787
788static void hss_hdlc_txdone_irq(void *pdev)
789{
790 struct net_device *dev = pdev;
791 struct port *port = dev_to_port(dev);
792 int n_desc;
793
794#if DEBUG_TX
795 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
796#endif
797 while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
798 port, 1)) >= 0) {
799 struct desc *desc;
800 int start;
801
802 desc = tx_desc_ptr(port, n_desc);
803
804 dev->stats.tx_packets++;
805 dev->stats.tx_bytes += desc->pkt_len;
806
807 dma_unmap_tx(port, desc);
808#if DEBUG_TX
809 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
810 dev->name, port->tx_buff_tab[n_desc]);
811#endif
812 free_buffer_irq(port->tx_buff_tab[n_desc]);
813 port->tx_buff_tab[n_desc] = NULL;
814
815 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
816 queue_put_desc(port->plat->txreadyq,
817 tx_desc_phys(port, n_desc), desc);
818 if (start) { /* TX-ready queue was empty */
819#if DEBUG_TX
820 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
821 " ready\n", dev->name);
822#endif
823 netif_wake_queue(dev);
824 }
825 }
826}
827
828static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
829{
830 struct port *port = dev_to_port(dev);
831 unsigned int txreadyq = port->plat->txreadyq;
832 int len, offset, bytes, n;
833 void *mem;
834 u32 phys;
835 struct desc *desc;
836
837#if DEBUG_TX
838 printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
839#endif
840
841 if (unlikely(skb->len > HDLC_MAX_MRU)) {
842 dev_kfree_skb(skb);
843 dev->stats.tx_errors++;
844 return NETDEV_TX_OK;
845 }
846
847 debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
848
849 len = skb->len;
850#ifdef __ARMEB__
851 offset = 0; /* no need to keep alignment */
852 bytes = len;
853 mem = skb->data;
854#else
855 offset = (int)skb->data & 3; /* keep 32-bit alignment */
856 bytes = ALIGN(offset + len, 4);
857 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
858 dev_kfree_skb(skb);
859 dev->stats.tx_dropped++;
860 return NETDEV_TX_OK;
861 }
862 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4);
863 dev_kfree_skb(skb);
864#endif
865
866 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
867 if (dma_mapping_error(&dev->dev, phys)) {
868#ifdef __ARMEB__
869 dev_kfree_skb(skb);
870#else
871 kfree(mem);
872#endif
873 dev->stats.tx_dropped++;
874 return NETDEV_TX_OK;
875 }
876
877 n = queue_get_desc(txreadyq, port, 1);
878 BUG_ON(n < 0);
879 desc = tx_desc_ptr(port, n);
880
881#ifdef __ARMEB__
882 port->tx_buff_tab[n] = skb;
883#else
884 port->tx_buff_tab[n] = mem;
885#endif
886 desc->data = phys + offset;
887 desc->buf_len = desc->pkt_len = len;
888
889 wmb();
890 queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
891
892 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
893#if DEBUG_TX
894 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
895#endif
896 netif_stop_queue(dev);
897 /* we could miss TX ready interrupt */
898 if (!qmgr_stat_below_low_watermark(txreadyq)) {
899#if DEBUG_TX
900 printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
901 dev->name);
902#endif
903 netif_wake_queue(dev);
904 }
905 }
906
907#if DEBUG_TX
908 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
909#endif
910 return NETDEV_TX_OK;
911}
912
913
914static int request_hdlc_queues(struct port *port)
915{
916 int err;
917
918 err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0,
919 "%s:RX-free", port->netdev->name);
920 if (err)
921 return err;
922
923 err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0,
924 "%s:RX", port->netdev->name);
925 if (err)
926 goto rel_rxfree;
927
928 err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0,
929 "%s:TX", port->netdev->name);
930 if (err)
931 goto rel_rx;
932
933 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
934 "%s:TX-ready", port->netdev->name);
935 if (err)
936 goto rel_tx;
937
938 err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0,
939 "%s:TX-done", port->netdev->name);
940 if (err)
941 goto rel_txready;
942 return 0;
943
944rel_txready:
945 qmgr_release_queue(port->plat->txreadyq);
946rel_tx:
947 qmgr_release_queue(queue_ids[port->id].tx);
948rel_rx:
949 qmgr_release_queue(queue_ids[port->id].rx);
950rel_rxfree:
951 qmgr_release_queue(queue_ids[port->id].rxfree);
952 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
953 port->netdev->name);
954 return err;
955}
956
957static void release_hdlc_queues(struct port *port)
958{
959 qmgr_release_queue(queue_ids[port->id].rxfree);
960 qmgr_release_queue(queue_ids[port->id].rx);
961 qmgr_release_queue(queue_ids[port->id].txdone);
962 qmgr_release_queue(queue_ids[port->id].tx);
963 qmgr_release_queue(port->plat->txreadyq);
964}
965
966static int init_hdlc_queues(struct port *port)
967{
968 int i;
969
970 if (!ports_open) {
971 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
972 POOL_ALLOC_SIZE, 32, 0);
973 if (!dma_pool)
974 return -ENOMEM;
975 }
976
977 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
978 &port->desc_tab_phys)))
979 return -ENOMEM;
980 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
981 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
982 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
983
984 /* Setup RX buffers */
985 for (i = 0; i < RX_DESCS; i++) {
986 struct desc *desc = rx_desc_ptr(port, i);
987 buffer_t *buff;
988 void *data;
989#ifdef __ARMEB__
990 if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
991 return -ENOMEM;
992 data = buff->data;
993#else
994 if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
995 return -ENOMEM;
996 data = buff;
997#endif
998 desc->buf_len = RX_SIZE;
999 desc->data = dma_map_single(&port->netdev->dev, data,
1000 RX_SIZE, DMA_FROM_DEVICE);
1001 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1002 free_buffer(buff);
1003 return -EIO;
1004 }
1005 port->rx_buff_tab[i] = buff;
1006 }
1007
1008 return 0;
1009}
1010
1011static void destroy_hdlc_queues(struct port *port)
1012{
1013 int i;
1014
1015 if (port->desc_tab) {
1016 for (i = 0; i < RX_DESCS; i++) {
1017 struct desc *desc = rx_desc_ptr(port, i);
1018 buffer_t *buff = port->rx_buff_tab[i];
1019 if (buff) {
1020 dma_unmap_single(&port->netdev->dev,
1021 desc->data, RX_SIZE,
1022 DMA_FROM_DEVICE);
1023 free_buffer(buff);
1024 }
1025 }
1026 for (i = 0; i < TX_DESCS; i++) {
1027 struct desc *desc = tx_desc_ptr(port, i);
1028 buffer_t *buff = port->tx_buff_tab[i];
1029 if (buff) {
1030 dma_unmap_tx(port, desc);
1031 free_buffer(buff);
1032 }
1033 }
1034 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1035 port->desc_tab = NULL;
1036 }
1037
1038 if (!ports_open && dma_pool) {
1039 dma_pool_destroy(dma_pool);
1040 dma_pool = NULL;
1041 }
1042}
1043
1044static int hss_hdlc_open(struct net_device *dev)
1045{
1046 struct port *port = dev_to_port(dev);
1047 unsigned long flags;
1048 int i, err = 0;
1049
1050 if ((err = hdlc_open(dev)))
1051 return err;
1052
1053 if ((err = hss_load_firmware(port)))
1054 goto err_hdlc_close;
1055
1056 if ((err = request_hdlc_queues(port)))
1057 goto err_hdlc_close;
1058
1059 if ((err = init_hdlc_queues(port)))
1060 goto err_destroy_queues;
1061
1062 spin_lock_irqsave(&npe_lock, flags);
1063 if (port->plat->open)
1064 if ((err = port->plat->open(port->id, dev,
1065 hss_hdlc_set_carrier)))
1066 goto err_unlock;
1067 spin_unlock_irqrestore(&npe_lock, flags);
1068
1069 /* Populate queues with buffers, no failure after this point */
1070 for (i = 0; i < TX_DESCS; i++)
1071 queue_put_desc(port->plat->txreadyq,
1072 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1073
1074 for (i = 0; i < RX_DESCS; i++)
1075 queue_put_desc(queue_ids[port->id].rxfree,
1076 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1077
1078 napi_enable(&port->napi);
1079 netif_start_queue(dev);
1080
1081 qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
1082 hss_hdlc_rx_irq, dev);
1083
1084 qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
1085 hss_hdlc_txdone_irq, dev);
1086 qmgr_enable_irq(queue_ids[port->id].txdone);
1087
1088 ports_open++;
1089
1090 hss_set_hdlc_cfg(port);
1091 hss_config(port);
1092
1093 hss_start_hdlc(port);
1094
1095 /* we may already have RX data, enables IRQ */
1096 napi_schedule(&port->napi);
1097 return 0;
1098
1099err_unlock:
1100 spin_unlock_irqrestore(&npe_lock, flags);
1101err_destroy_queues:
1102 destroy_hdlc_queues(port);
1103 release_hdlc_queues(port);
1104err_hdlc_close:
1105 hdlc_close(dev);
1106 return err;
1107}
1108
1109static int hss_hdlc_close(struct net_device *dev)
1110{
1111 struct port *port = dev_to_port(dev);
1112 unsigned long flags;
1113 int i, buffs = RX_DESCS; /* allocated RX buffers */
1114
1115 spin_lock_irqsave(&npe_lock, flags);
1116 ports_open--;
1117 qmgr_disable_irq(queue_ids[port->id].rx);
1118 netif_stop_queue(dev);
1119 napi_disable(&port->napi);
1120
1121 hss_stop_hdlc(port);
1122
1123 while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
1124 buffs--;
1125 while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
1126 buffs--;
1127
1128 if (buffs)
1129 netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n",
1130 buffs);
1131
1132 buffs = TX_DESCS;
1133 while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
1134 buffs--; /* cancel TX */
1135
1136 i = 0;
1137 do {
1138 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1139 buffs--;
1140 if (!buffs)
1141 break;
1142 } while (++i < MAX_CLOSE_WAIT);
1143
1144 if (buffs)
1145 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n",
1146 buffs);
1147#if DEBUG_CLOSE
1148 if (!buffs)
1149 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1150#endif
1151 qmgr_disable_irq(queue_ids[port->id].txdone);
1152
1153 if (port->plat->close)
1154 port->plat->close(port->id, dev);
1155 spin_unlock_irqrestore(&npe_lock, flags);
1156
1157 destroy_hdlc_queues(port);
1158 release_hdlc_queues(port);
1159 hdlc_close(dev);
1160 return 0;
1161}
1162
1163
1164static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1165 unsigned short parity)
1166{
1167 struct port *port = dev_to_port(dev);
1168
1169 if (encoding != ENCODING_NRZ)
1170 return -EINVAL;
1171
1172 switch(parity) {
1173 case PARITY_CRC16_PR1_CCITT:
1174 port->hdlc_cfg = 0;
1175 return 0;
1176
1177 case PARITY_CRC32_PR1_CCITT:
1178 port->hdlc_cfg = PKT_HDLC_CRC_32;
1179 return 0;
1180
1181 default:
1182 return -EINVAL;
1183 }
1184}
1185
1186static u32 check_clock(u32 timer_freq, u32 rate, u32 a, u32 b, u32 c,
1187 u32 *best, u32 *best_diff, u32 *reg)
1188{
1189 /* a is 10-bit, b is 10-bit, c is 12-bit */
1190 u64 new_rate;
1191 u32 new_diff;
1192
1193 new_rate = timer_freq * (u64)(c + 1);
1194 do_div(new_rate, a * (c + 1) + b + 1);
1195 new_diff = abs((u32)new_rate - rate);
1196
1197 if (new_diff < *best_diff) {
1198 *best = new_rate;
1199 *best_diff = new_diff;
1200 *reg = (a << 22) | (b << 12) | c;
1201 }
1202 return new_diff;
1203}
1204
1205static void find_best_clock(u32 timer_freq, u32 rate, u32 *best, u32 *reg)
1206{
1207 u32 a, b, diff = 0xFFFFFFFF;
1208
1209 a = timer_freq / rate;
1210
1211 if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */
1212 check_clock(timer_freq, rate, 0x3FF, 1, 1, best, &diff, reg);
1213 return;
1214 }
1215 if (a == 0) { /* > 66.666 MHz */
1216 a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */
1217 rate = timer_freq;
1218 }
1219
1220 if (rate * a == timer_freq) { /* don't divide by 0 later */
1221 check_clock(timer_freq, rate, a - 1, 1, 1, best, &diff, reg);
1222 return;
1223 }
1224
1225 for (b = 0; b < 0x400; b++) {
1226 u64 c = (b + 1) * (u64)rate;
1227 do_div(c, timer_freq - rate * a);
1228 c--;
1229 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
1230 if (b == 0 && /* also try a bit higher rate */
1231 !check_clock(timer_freq, rate, a - 1, 1, 1, best,
1232 &diff, reg))
1233 return;
1234 check_clock(timer_freq, rate, a, b, 0xFFF, best,
1235 &diff, reg);
1236 return;
1237 }
1238 if (!check_clock(timer_freq, rate, a, b, c, best, &diff, reg))
1239 return;
1240 if (!check_clock(timer_freq, rate, a, b, c + 1, best, &diff,
1241 reg))
1242 return;
1243 }
1244}
1245
1246static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1247{
1248 const size_t size = sizeof(sync_serial_settings);
1249 sync_serial_settings new_line;
1250 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1251 struct port *port = dev_to_port(dev);
1252 unsigned long flags;
1253 int clk;
1254
1255 if (cmd != SIOCWANDEV)
1256 return hdlc_ioctl(dev, ifr, cmd);
1257
1258 switch(ifr->ifr_settings.type) {
1259 case IF_GET_IFACE:
1260 ifr->ifr_settings.type = IF_IFACE_V35;
1261 if (ifr->ifr_settings.size < size) {
1262 ifr->ifr_settings.size = size; /* data size wanted */
1263 return -ENOBUFS;
1264 }
1265 memset(&new_line, 0, sizeof(new_line));
1266 new_line.clock_type = port->clock_type;
1267 new_line.clock_rate = port->clock_rate;
1268 new_line.loopback = port->loopback;
1269 if (copy_to_user(line, &new_line, size))
1270 return -EFAULT;
1271 return 0;
1272
1273 case IF_IFACE_SYNC_SERIAL:
1274 case IF_IFACE_V35:
1275 if(!capable(CAP_NET_ADMIN))
1276 return -EPERM;
1277 if (copy_from_user(&new_line, line, size))
1278 return -EFAULT;
1279
1280 clk = new_line.clock_type;
1281 if (port->plat->set_clock)
1282 clk = port->plat->set_clock(port->id, clk);
1283
1284 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1285 return -EINVAL; /* No such clock setting */
1286
1287 if (new_line.loopback != 0 && new_line.loopback != 1)
1288 return -EINVAL;
1289
1290 port->clock_type = clk; /* Update settings */
1291 if (clk == CLOCK_INT)
1292 find_best_clock(port->plat->timer_freq,
1293 new_line.clock_rate,
1294 &port->clock_rate, &port->clock_reg);
1295 else {
1296 port->clock_rate = 0;
1297 port->clock_reg = CLK42X_SPEED_2048KHZ;
1298 }
1299 port->loopback = new_line.loopback;
1300
1301 spin_lock_irqsave(&npe_lock, flags);
1302
1303 if (dev->flags & IFF_UP)
1304 hss_config(port);
1305
1306 if (port->loopback || port->carrier)
1307 netif_carrier_on(port->netdev);
1308 else
1309 netif_carrier_off(port->netdev);
1310 spin_unlock_irqrestore(&npe_lock, flags);
1311
1312 return 0;
1313
1314 default:
1315 return hdlc_ioctl(dev, ifr, cmd);
1316 }
1317}
1318
1319/*****************************************************************************
1320 * initialization
1321 ****************************************************************************/
1322
1323static const struct net_device_ops hss_hdlc_ops = {
1324 .ndo_open = hss_hdlc_open,
1325 .ndo_stop = hss_hdlc_close,
1326 .ndo_start_xmit = hdlc_start_xmit,
1327 .ndo_do_ioctl = hss_hdlc_ioctl,
1328};
1329
1330static int hss_init_one(struct platform_device *pdev)
1331{
1332 struct port *port;
1333 struct net_device *dev;
1334 hdlc_device *hdlc;
1335 int err;
1336
1337 if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
1338 return -ENOMEM;
1339
1340 if ((port->npe = npe_request(0)) == NULL) {
1341 err = -ENODEV;
1342 goto err_free;
1343 }
1344
1345 if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
1346 err = -ENOMEM;
1347 goto err_plat;
1348 }
1349
1350 SET_NETDEV_DEV(dev, &pdev->dev);
1351 hdlc = dev_to_hdlc(dev);
1352 hdlc->attach = hss_hdlc_attach;
1353 hdlc->xmit = hss_hdlc_xmit;
1354 dev->netdev_ops = &hss_hdlc_ops;
1355 dev->tx_queue_len = 100;
1356 port->clock_type = CLOCK_EXT;
1357 port->clock_rate = 0;
1358 port->clock_reg = CLK42X_SPEED_2048KHZ;
1359 port->id = pdev->id;
1360 port->dev = &pdev->dev;
1361 port->plat = pdev->dev.platform_data;
1362 netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1363
1364 if ((err = register_hdlc_device(dev)))
1365 goto err_free_netdev;
1366
1367 platform_set_drvdata(pdev, port);
1368
1369 netdev_info(dev, "initialized\n");
1370 return 0;
1371
1372err_free_netdev:
1373 free_netdev(dev);
1374err_plat:
1375 npe_release(port->npe);
1376err_free:
1377 kfree(port);
1378 return err;
1379}
1380
1381static int hss_remove_one(struct platform_device *pdev)
1382{
1383 struct port *port = platform_get_drvdata(pdev);
1384
1385 unregister_hdlc_device(port->netdev);
1386 free_netdev(port->netdev);
1387 npe_release(port->npe);
1388 kfree(port);
1389 return 0;
1390}
1391
1392static struct platform_driver ixp4xx_hss_driver = {
1393 .driver.name = DRV_NAME,
1394 .probe = hss_init_one,
1395 .remove = hss_remove_one,
1396};
1397
1398static int __init hss_init_module(void)
1399{
1400 if ((ixp4xx_read_feature_bits() &
1401 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
1402 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
1403 return -ENODEV;
1404
1405 spin_lock_init(&npe_lock);
1406
1407 return platform_driver_register(&ixp4xx_hss_driver);
1408}
1409
1410static void __exit hss_cleanup_module(void)
1411{
1412 platform_driver_unregister(&ixp4xx_hss_driver);
1413}
1414
1415MODULE_AUTHOR("Krzysztof Halasa");
1416MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
1417MODULE_LICENSE("GPL v2");
1418MODULE_ALIAS("platform:ixp4xx_hss");
1419module_init(hss_init_module);
1420module_exit(hss_cleanup_module);