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1/**********************************************************************
2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
6 *
7 * Copyright (c) 2003-2016 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
17 ***********************************************************************/
18/*! \file octeon_config.h
19 * \brief Host Driver: Configuration data structures for the host driver.
20 */
21
22#ifndef __OCTEON_CONFIG_H__
23#define __OCTEON_CONFIG_H__
24
25/*--------------------------CONFIG VALUES------------------------*/
26
27/* The following macros affect the way the driver data structures
28 * are generated for Octeon devices.
29 * They can be modified.
30 */
31
32/* Maximum octeon devices defined as MAX_OCTEON_NICIF to support
33 * multiple(<= MAX_OCTEON_NICIF) Miniports
34 */
35#define MAX_OCTEON_NICIF 128
36#define MAX_OCTEON_DEVICES MAX_OCTEON_NICIF
37#define MAX_OCTEON_LINKS MAX_OCTEON_NICIF
38#define MAX_OCTEON_MULTICAST_ADDR 32
39
40#define MAX_OCTEON_FILL_COUNT 8
41
42/* CN6xxx IQ configuration macros */
43#define CN6XXX_MAX_INPUT_QUEUES 32
44#define CN6XXX_MAX_IQ_DESCRIPTORS 2048
45#define CN6XXX_DB_MIN 1
46#define CN6XXX_DB_MAX 8
47#define CN6XXX_DB_TIMEOUT 1
48
49/* CN6xxx OQ configuration macros */
50#define CN6XXX_MAX_OUTPUT_QUEUES 32
51#define CN6XXX_MAX_OQ_DESCRIPTORS 2048
52#define CN6XXX_OQ_BUF_SIZE 1664
53#define CN6XXX_OQ_PKTSPER_INTR ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
54 (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
55#define CN6XXX_OQ_REFIL_THRESHOLD ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
56 (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
57
58#define CN6XXX_OQ_INTR_PKT 64
59#define CN6XXX_OQ_INTR_TIME 100
60#define DEFAULT_NUM_NIC_PORTS_66XX 2
61#define DEFAULT_NUM_NIC_PORTS_68XX 4
62#define DEFAULT_NUM_NIC_PORTS_68XX_210NV 2
63
64/* CN23xx IQ configuration macros */
65#define CN23XX_MAX_VFS_PER_PF_PASS_1_0 8
66#define CN23XX_MAX_VFS_PER_PF_PASS_1_1 31
67#define CN23XX_MAX_VFS_PER_PF 63
68#define CN23XX_MAX_RINGS_PER_VF 8
69
70#define CN23XX_MAX_RINGS_PER_PF_PASS_1_0 12
71#define CN23XX_MAX_RINGS_PER_PF_PASS_1_1 32
72#define CN23XX_MAX_RINGS_PER_PF 64
73#define CN23XX_MAX_RINGS_PER_VF 8
74
75#define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
76#define CN23XX_MAX_IQ_DESCRIPTORS 2048
77#define CN23XX_DEFAULT_IQ_DESCRIPTORS 512
78#define CN23XX_MIN_IQ_DESCRIPTORS 128
79#define CN23XX_DB_MIN 1
80#define CN23XX_DB_MAX 8
81#define CN23XX_DB_TIMEOUT 1
82
83#define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
84#define CN23XX_MAX_OQ_DESCRIPTORS 2048
85#define CN23XX_DEFAULT_OQ_DESCRIPTORS 512
86#define CN23XX_MIN_OQ_DESCRIPTORS 128
87#define CN23XX_OQ_BUF_SIZE 1664
88#define CN23XX_OQ_PKTSPER_INTR 128
89/*#define CAVIUM_ONLY_CN23XX_RX_PERF*/
90#define CN23XX_OQ_REFIL_THRESHOLD 16
91
92#define CN23XX_OQ_INTR_PKT 64
93#define CN23XX_OQ_INTR_TIME 100
94#define DEFAULT_NUM_NIC_PORTS_23XX 1
95
96#define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF
97/* PEMs count */
98#define CN23XX_MAX_MACS 4
99
100#define CN23XX_DEF_IQ_INTR_THRESHOLD 32
101#define CN23XX_DEF_IQ_INTR_BYTE_THRESHOLD (64 * 1024)
102/* common OCTEON configuration macros */
103#define CN6XXX_CFG_IO_QUEUES 32
104#define OCTEON_32BYTE_INSTR 32
105#define OCTEON_64BYTE_INSTR 64
106#define OCTEON_MAX_BASE_IOQ 4
107
108#define OCTEON_DMA_INTR_PKT 64
109#define OCTEON_DMA_INTR_TIME 1000
110
111#define MAX_TXQS_PER_INTF 8
112#define MAX_RXQS_PER_INTF 8
113#define DEF_TXQS_PER_INTF 4
114#define DEF_RXQS_PER_INTF 4
115
116#define INVALID_IOQ_NO 0xff
117
118#define DEFAULT_POW_GRP 0
119
120/* Macros to get octeon config params */
121#define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
122#define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs)
123#define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size)
124#define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
125#define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
126#define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout)
127
128#define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt)
129#define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val
130
131#define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs)
132#define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr)
133#define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold)
134#define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt)
135#define CFG_GET_OQ_INTR_TIME(cfg) ((cfg)->oq.oq_intr_time)
136#define CFG_SET_OQ_INTR_PKT(cfg, val) (cfg)->oq.oq_intr_pkt = val
137#define CFG_SET_OQ_INTR_TIME(cfg, val) (cfg)->oq.oq_intr_time = val
138
139#define CFG_GET_DMA_INTR_PKT(cfg) ((cfg)->dma.dma_intr_pkt)
140#define CFG_GET_DMA_INTR_TIME(cfg) ((cfg)->dma.dma_intr_time)
141#define CFG_GET_NUM_NIC_PORTS(cfg) ((cfg)->num_nic_ports)
142#define CFG_GET_NUM_DEF_TX_DESCS(cfg) ((cfg)->num_def_tx_descs)
143#define CFG_GET_NUM_DEF_RX_DESCS(cfg) ((cfg)->num_def_rx_descs)
144#define CFG_GET_DEF_RX_BUF_SIZE(cfg) ((cfg)->def_rx_buf_size)
145
146#define CFG_GET_MAX_TXQS_NIC_IF(cfg, idx) \
147 ((cfg)->nic_if_cfg[idx].max_txqs)
148#define CFG_GET_NUM_TXQS_NIC_IF(cfg, idx) \
149 ((cfg)->nic_if_cfg[idx].num_txqs)
150#define CFG_GET_MAX_RXQS_NIC_IF(cfg, idx) \
151 ((cfg)->nic_if_cfg[idx].max_rxqs)
152#define CFG_GET_NUM_RXQS_NIC_IF(cfg, idx) \
153 ((cfg)->nic_if_cfg[idx].num_rxqs)
154#define CFG_GET_NUM_RX_DESCS_NIC_IF(cfg, idx) \
155 ((cfg)->nic_if_cfg[idx].num_rx_descs)
156#define CFG_GET_NUM_TX_DESCS_NIC_IF(cfg, idx) \
157 ((cfg)->nic_if_cfg[idx].num_tx_descs)
158#define CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(cfg, idx) \
159 ((cfg)->nic_if_cfg[idx].rx_buf_size)
160#define CFG_GET_BASE_QUE_NIC_IF(cfg, idx) \
161 ((cfg)->nic_if_cfg[idx].base_queue)
162#define CFG_GET_GMXID_NIC_IF(cfg, idx) \
163 ((cfg)->nic_if_cfg[idx].gmx_port_id)
164
165#define CFG_GET_CTRL_Q_GRP(cfg) ((cfg)->misc.ctrlq_grp)
166#define CFG_GET_HOST_LINK_QUERY_INTERVAL(cfg) \
167 ((cfg)->misc.host_link_query_interval)
168#define CFG_GET_OCT_LINK_QUERY_INTERVAL(cfg) \
169 ((cfg)->misc.oct_link_query_interval)
170#define CFG_GET_IS_SLI_BP_ON(cfg) ((cfg)->misc.enable_sli_oq_bp)
171
172#define CFG_SET_NUM_RX_DESCS_NIC_IF(cfg, idx, value) \
173 ((cfg)->nic_if_cfg[idx].num_rx_descs = value)
174#define CFG_SET_NUM_TX_DESCS_NIC_IF(cfg, idx, value) \
175 ((cfg)->nic_if_cfg[idx].num_tx_descs = value)
176
177/* Max IOQs per OCTEON Link */
178#define MAX_IOQS_PER_NICIF 64
179
180enum lio_card_type {
181 LIO_210SV = 0, /* Two port, 66xx */
182 LIO_210NV, /* Two port, 68xx */
183 LIO_410NV, /* Four port, 68xx */
184 LIO_23XX /* 23xx */
185};
186
187#define LIO_210SV_NAME "210sv"
188#define LIO_210NV_NAME "210nv"
189#define LIO_410NV_NAME "410nv"
190#define LIO_23XX_NAME "23xx"
191
192/** Structure to define the configuration attributes for each Input queue.
193 * Applicable to all Octeon processors
194 **/
195struct octeon_iq_config {
196#ifdef __BIG_ENDIAN_BITFIELD
197 u64 reserved:16;
198
199 /** Tx interrupt packets. Applicable to 23xx only */
200 u64 iq_intr_pkt:16;
201
202 /** Minimum ticks to wait before checking for pending instructions. */
203 u64 db_timeout:16;
204
205 /** Minimum number of commands pending to be posted to Octeon
206 * before driver hits the Input queue doorbell.
207 */
208 u64 db_min:8;
209
210 /** Command size - 32 or 64 bytes */
211 u64 instr_type:32;
212
213 /** Pending list size (usually set to the sum of the size of all Input
214 * queues)
215 */
216 u64 pending_list_size:32;
217
218 /* Max number of IQs available */
219 u64 max_iqs:8;
220#else
221 /* Max number of IQs available */
222 u64 max_iqs:8;
223
224 /** Pending list size (usually set to the sum of the size of all Input
225 * queues)
226 */
227 u64 pending_list_size:32;
228
229 /** Command size - 32 or 64 bytes */
230 u64 instr_type:32;
231
232 /** Minimum number of commands pending to be posted to Octeon
233 * before driver hits the Input queue doorbell.
234 */
235 u64 db_min:8;
236
237 /** Minimum ticks to wait before checking for pending instructions. */
238 u64 db_timeout:16;
239
240 /** Tx interrupt packets. Applicable to 23xx only */
241 u64 iq_intr_pkt:16;
242
243 u64 reserved:16;
244#endif
245};
246
247/** Structure to define the configuration attributes for each Output queue.
248 * Applicable to all Octeon processors
249 **/
250struct octeon_oq_config {
251#ifdef __BIG_ENDIAN_BITFIELD
252 u64 reserved:16;
253
254 u64 pkts_per_intr:16;
255
256 /** Interrupt Coalescing (Time Interval). Octeon will interrupt the
257 * host if atleast one packet was sent in the time interval specified
258 * by this field. The driver uses time interval interrupt coalescing
259 * by default. The time is specified in microseconds.
260 */
261 u64 oq_intr_time:16;
262
263 /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
264 * only if it sent as many packets as specified by this field.
265 * The driver
266 * usually does not use packet count interrupt coalescing.
267 */
268 u64 oq_intr_pkt:16;
269
270 /** The number of buffers that were consumed during packet processing by
271 * the driver on this Output queue before the driver attempts to
272 * replenish
273 * the descriptor ring with new buffers.
274 */
275 u64 refill_threshold:16;
276
277 /* Max number of OQs available */
278 u64 max_oqs:8;
279
280#else
281 /* Max number of OQs available */
282 u64 max_oqs:8;
283
284 /** The number of buffers that were consumed during packet processing by
285 * the driver on this Output queue before the driver attempts to
286 * replenish
287 * the descriptor ring with new buffers.
288 */
289 u64 refill_threshold:16;
290
291 /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
292 * only if it sent as many packets as specified by this field.
293 * The driver
294 * usually does not use packet count interrupt coalescing.
295 */
296 u64 oq_intr_pkt:16;
297
298 /** Interrupt Coalescing (Time Interval). Octeon will interrupt the
299 * host if atleast one packet was sent in the time interval specified
300 * by this field. The driver uses time interval interrupt coalescing
301 * by default. The time is specified in microseconds.
302 */
303 u64 oq_intr_time:16;
304
305 u64 pkts_per_intr:16;
306
307 u64 reserved:16;
308#endif
309
310};
311
312/** This structure conatins the NIC link configuration attributes,
313 * common for all the OCTEON Modles.
314 */
315struct octeon_nic_if_config {
316#ifdef __BIG_ENDIAN_BITFIELD
317 u64 reserved:56;
318
319 u64 base_queue:16;
320
321 u64 gmx_port_id:8;
322
323 /* SKB size, We need not change buf size even for Jumbo frames.
324 * Octeon can send jumbo frames in 4 consecutive descriptors,
325 */
326 u64 rx_buf_size:16;
327
328 /* Num of desc for tx rings */
329 u64 num_tx_descs:16;
330
331 /* Num of desc for rx rings */
332 u64 num_rx_descs:16;
333
334 /* Actual configured value. Range could be: 1...max_rxqs */
335 u64 num_rxqs:16;
336
337 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
338 u64 max_rxqs:16;
339
340 /* Actual configured value. Range could be: 1...max_txqs */
341 u64 num_txqs:16;
342
343 /* Max Txqs: Half for each of the two ports :max_iq/2 */
344 u64 max_txqs:16;
345#else
346 /* Max Txqs: Half for each of the two ports :max_iq/2 */
347 u64 max_txqs:16;
348
349 /* Actual configured value. Range could be: 1...max_txqs */
350 u64 num_txqs:16;
351
352 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
353 u64 max_rxqs:16;
354
355 /* Actual configured value. Range could be: 1...max_rxqs */
356 u64 num_rxqs:16;
357
358 /* Num of desc for rx rings */
359 u64 num_rx_descs:16;
360
361 /* Num of desc for tx rings */
362 u64 num_tx_descs:16;
363
364 /* SKB size, We need not change buf size even for Jumbo frames.
365 * Octeon can send jumbo frames in 4 consecutive descriptors,
366 */
367 u64 rx_buf_size:16;
368
369 u64 gmx_port_id:8;
370
371 u64 base_queue:16;
372
373 u64 reserved:56;
374#endif
375
376};
377
378/** Structure to define the configuration attributes for meta data.
379 * Applicable to all Octeon processors.
380 */
381
382struct octeon_misc_config {
383#ifdef __BIG_ENDIAN_BITFIELD
384 /** Host link status polling period */
385 u64 host_link_query_interval:32;
386 /** Oct link status polling period */
387 u64 oct_link_query_interval:32;
388
389 u64 enable_sli_oq_bp:1;
390 /** Control IQ Group */
391 u64 ctrlq_grp:4;
392#else
393 /** Control IQ Group */
394 u64 ctrlq_grp:4;
395 /** BP for SLI OQ */
396 u64 enable_sli_oq_bp:1;
397 /** Host link status polling period */
398 u64 oct_link_query_interval:32;
399 /** Oct link status polling period */
400 u64 host_link_query_interval:32;
401#endif
402};
403
404/** Structure to define the configuration for all OCTEON processors. */
405struct octeon_config {
406 u16 card_type;
407 char *card_name;
408
409 /** Input Queue attributes. */
410 struct octeon_iq_config iq;
411
412 /** Output Queue attributes. */
413 struct octeon_oq_config oq;
414
415 /** NIC Port Configuration */
416 struct octeon_nic_if_config nic_if_cfg[MAX_OCTEON_NICIF];
417
418 /** Miscellaneous attributes */
419 struct octeon_misc_config misc;
420
421 int num_nic_ports;
422
423 int num_def_tx_descs;
424
425 /* Num of desc for rx rings */
426 int num_def_rx_descs;
427
428 int def_rx_buf_size;
429
430};
431
432/* The following config values are fixed and should not be modified. */
433
434#define BAR1_INDEX_DYNAMIC_MAP 2
435#define BAR1_INDEX_STATIC_MAP 15
436#define OCTEON_BAR1_ENTRY_SIZE (4 * 1024 * 1024)
437
438#define MAX_BAR1_IOREMAP_SIZE (16 * OCTEON_BAR1_ENTRY_SIZE)
439
440/* Response lists - 1 ordered, 1 unordered-blocking, 1 unordered-nonblocking
441 * 1 process done list, 1 zombie lists(timeouted sc list)
442 * NoResponse Lists are now maintained with each IQ. (Dec' 2007).
443 */
444#define MAX_RESPONSE_LISTS 6
445
446/* Opcode hash bits. The opcode is hashed on the lower 6-bits to lookup the
447 * dispatch table.
448 */
449#define OPCODE_MASK_BITS 6
450
451/* Mask for the 6-bit lookup hash */
452#define OCTEON_OPCODE_MASK 0x3f
453
454/* Size of the dispatch table. The 6-bit hash can index into 2^6 entries */
455#define DISPATCH_LIST_SIZE BIT(OPCODE_MASK_BITS)
456
457/* Maximum number of Octeon Instruction (command) queues */
458#define MAX_OCTEON_INSTR_QUEUES(oct) \
459 (OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_INPUT_QUEUES : \
460 CN6XXX_MAX_INPUT_QUEUES)
461
462/* Maximum number of Octeon Instruction (command) queues */
463#define MAX_OCTEON_OUTPUT_QUEUES(oct) \
464 (OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_OUTPUT_QUEUES : \
465 CN6XXX_MAX_OUTPUT_QUEUES)
466
467#define MAX_POSSIBLE_OCTEON_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES
468#define MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES
469
470#define MAX_POSSIBLE_VFS 64
471
472#endif /* __OCTEON_CONFIG_H__ */
1/**********************************************************************
2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
6 *
7 * Copyright (c) 2003-2016 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
17 ***********************************************************************/
18/*! \file octeon_config.h
19 * \brief Host Driver: Configuration data structures for the host driver.
20 */
21
22#ifndef __OCTEON_CONFIG_H__
23#define __OCTEON_CONFIG_H__
24
25/*--------------------------CONFIG VALUES------------------------*/
26
27/* The following macros affect the way the driver data structures
28 * are generated for Octeon devices.
29 * They can be modified.
30 */
31
32/* Maximum octeon devices defined as MAX_OCTEON_NICIF to support
33 * multiple(<= MAX_OCTEON_NICIF) Miniports
34 */
35#define MAX_OCTEON_NICIF 128
36#define MAX_OCTEON_DEVICES MAX_OCTEON_NICIF
37#define MAX_OCTEON_LINKS MAX_OCTEON_NICIF
38#define MAX_OCTEON_MULTICAST_ADDR 32
39
40#define MAX_OCTEON_FILL_COUNT 8
41
42/* CN6xxx IQ configuration macros */
43#define CN6XXX_MAX_INPUT_QUEUES 32
44#define CN6XXX_MAX_IQ_DESCRIPTORS 2048
45#define CN6XXX_DB_MIN 1
46#define CN6XXX_DB_MAX 8
47#define CN6XXX_DB_TIMEOUT 1
48
49/* CN6xxx OQ configuration macros */
50#define CN6XXX_MAX_OUTPUT_QUEUES 32
51#define CN6XXX_MAX_OQ_DESCRIPTORS 2048
52#define CN6XXX_OQ_BUF_SIZE 1664
53#define CN6XXX_OQ_PKTSPER_INTR ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
54 (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
55#define CN6XXX_OQ_REFIL_THRESHOLD ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
56 (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
57
58#define CN6XXX_OQ_INTR_PKT 64
59#define CN6XXX_OQ_INTR_TIME 100
60#define DEFAULT_NUM_NIC_PORTS_66XX 2
61#define DEFAULT_NUM_NIC_PORTS_68XX 4
62#define DEFAULT_NUM_NIC_PORTS_68XX_210NV 2
63
64/* CN23xx IQ configuration macros */
65#define CN23XX_MAX_VFS_PER_PF_PASS_1_0 8
66#define CN23XX_MAX_VFS_PER_PF_PASS_1_1 31
67#define CN23XX_MAX_VFS_PER_PF 63
68#define CN23XX_MAX_RINGS_PER_VF 8
69
70#define CN23XX_MAX_RINGS_PER_PF_PASS_1_0 12
71#define CN23XX_MAX_RINGS_PER_PF_PASS_1_1 32
72#define CN23XX_MAX_RINGS_PER_PF 64
73#define CN23XX_MAX_RINGS_PER_VF 8
74
75#define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
76#define CN23XX_MAX_IQ_DESCRIPTORS 2048
77#define CN23XX_DEFAULT_IQ_DESCRIPTORS 512
78#define CN23XX_MIN_IQ_DESCRIPTORS 128
79#define CN23XX_DB_MIN 1
80#define CN23XX_DB_MAX 8
81#define CN23XX_DB_TIMEOUT 1
82
83#define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
84#define CN23XX_MAX_OQ_DESCRIPTORS 2048
85#define CN23XX_DEFAULT_OQ_DESCRIPTORS 512
86#define CN23XX_MIN_OQ_DESCRIPTORS 128
87#define CN23XX_OQ_BUF_SIZE 1664
88#define CN23XX_OQ_PKTSPER_INTR 128
89/*#define CAVIUM_ONLY_CN23XX_RX_PERF*/
90#define CN23XX_OQ_REFIL_THRESHOLD 16
91
92#define CN23XX_OQ_INTR_PKT 64
93#define CN23XX_OQ_INTR_TIME 100
94#define DEFAULT_NUM_NIC_PORTS_23XX 1
95
96#define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF
97/* PEMs count */
98#define CN23XX_MAX_MACS 4
99
100#define CN23XX_DEF_IQ_INTR_THRESHOLD 32
101#define CN23XX_DEF_IQ_INTR_BYTE_THRESHOLD (64 * 1024)
102/* common OCTEON configuration macros */
103#define CN6XXX_CFG_IO_QUEUES 32
104#define OCTEON_32BYTE_INSTR 32
105#define OCTEON_64BYTE_INSTR 64
106#define OCTEON_MAX_BASE_IOQ 4
107
108#define OCTEON_DMA_INTR_PKT 64
109#define OCTEON_DMA_INTR_TIME 1000
110
111#define MAX_TXQS_PER_INTF 8
112#define MAX_RXQS_PER_INTF 8
113#define DEF_TXQS_PER_INTF 4
114#define DEF_RXQS_PER_INTF 4
115
116#define INVALID_IOQ_NO 0xff
117
118#define DEFAULT_POW_GRP 0
119
120/* Macros to get octeon config params */
121#define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
122#define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs)
123#define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size)
124#define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
125#define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
126#define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout)
127
128#define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt)
129#define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val
130
131#define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs)
132#define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr)
133#define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold)
134#define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt)
135#define CFG_GET_OQ_INTR_TIME(cfg) ((cfg)->oq.oq_intr_time)
136#define CFG_SET_OQ_INTR_PKT(cfg, val) (cfg)->oq.oq_intr_pkt = val
137#define CFG_SET_OQ_INTR_TIME(cfg, val) (cfg)->oq.oq_intr_time = val
138
139#define CFG_GET_DMA_INTR_PKT(cfg) ((cfg)->dma.dma_intr_pkt)
140#define CFG_GET_DMA_INTR_TIME(cfg) ((cfg)->dma.dma_intr_time)
141#define CFG_GET_NUM_NIC_PORTS(cfg) ((cfg)->num_nic_ports)
142#define CFG_GET_NUM_DEF_TX_DESCS(cfg) ((cfg)->num_def_tx_descs)
143#define CFG_GET_NUM_DEF_RX_DESCS(cfg) ((cfg)->num_def_rx_descs)
144#define CFG_GET_DEF_RX_BUF_SIZE(cfg) ((cfg)->def_rx_buf_size)
145
146#define CFG_GET_MAX_TXQS_NIC_IF(cfg, idx) \
147 ((cfg)->nic_if_cfg[idx].max_txqs)
148#define CFG_GET_NUM_TXQS_NIC_IF(cfg, idx) \
149 ((cfg)->nic_if_cfg[idx].num_txqs)
150#define CFG_GET_MAX_RXQS_NIC_IF(cfg, idx) \
151 ((cfg)->nic_if_cfg[idx].max_rxqs)
152#define CFG_GET_NUM_RXQS_NIC_IF(cfg, idx) \
153 ((cfg)->nic_if_cfg[idx].num_rxqs)
154#define CFG_GET_NUM_RX_DESCS_NIC_IF(cfg, idx) \
155 ((cfg)->nic_if_cfg[idx].num_rx_descs)
156#define CFG_GET_NUM_TX_DESCS_NIC_IF(cfg, idx) \
157 ((cfg)->nic_if_cfg[idx].num_tx_descs)
158#define CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(cfg, idx) \
159 ((cfg)->nic_if_cfg[idx].rx_buf_size)
160#define CFG_GET_BASE_QUE_NIC_IF(cfg, idx) \
161 ((cfg)->nic_if_cfg[idx].base_queue)
162#define CFG_GET_GMXID_NIC_IF(cfg, idx) \
163 ((cfg)->nic_if_cfg[idx].gmx_port_id)
164
165#define CFG_GET_CTRL_Q_GRP(cfg) ((cfg)->misc.ctrlq_grp)
166#define CFG_GET_HOST_LINK_QUERY_INTERVAL(cfg) \
167 ((cfg)->misc.host_link_query_interval)
168#define CFG_GET_OCT_LINK_QUERY_INTERVAL(cfg) \
169 ((cfg)->misc.oct_link_query_interval)
170#define CFG_GET_IS_SLI_BP_ON(cfg) ((cfg)->misc.enable_sli_oq_bp)
171
172#define CFG_SET_NUM_RX_DESCS_NIC_IF(cfg, idx, value) \
173 ((cfg)->nic_if_cfg[idx].num_rx_descs = value)
174#define CFG_SET_NUM_TX_DESCS_NIC_IF(cfg, idx, value) \
175 ((cfg)->nic_if_cfg[idx].num_tx_descs = value)
176
177/* Max IOQs per OCTEON Link */
178#define MAX_IOQS_PER_NICIF 64
179
180enum lio_card_type {
181 LIO_210SV = 0, /* Two port, 66xx */
182 LIO_210NV, /* Two port, 68xx */
183 LIO_410NV, /* Four port, 68xx */
184 LIO_23XX /* 23xx */
185};
186
187#define LIO_210SV_NAME "210sv"
188#define LIO_210NV_NAME "210nv"
189#define LIO_410NV_NAME "410nv"
190#define LIO_23XX_NAME "23xx"
191
192/** Structure to define the configuration attributes for each Input queue.
193 * Applicable to all Octeon processors
194 **/
195struct octeon_iq_config {
196#ifdef __BIG_ENDIAN_BITFIELD
197 u64 reserved:16;
198
199 /** Tx interrupt packets. Applicable to 23xx only */
200 u64 iq_intr_pkt:16;
201
202 /** Minimum ticks to wait before checking for pending instructions. */
203 u64 db_timeout:16;
204
205 /** Minimum number of commands pending to be posted to Octeon
206 * before driver hits the Input queue doorbell.
207 */
208 u64 db_min:8;
209
210 /** Command size - 32 or 64 bytes */
211 u64 instr_type:32;
212
213 /** Pending list size (usually set to the sum of the size of all Input
214 * queues)
215 */
216 u64 pending_list_size:32;
217
218 /* Max number of IQs available */
219 u64 max_iqs:8;
220#else
221 /* Max number of IQs available */
222 u64 max_iqs:8;
223
224 /** Pending list size (usually set to the sum of the size of all Input
225 * queues)
226 */
227 u64 pending_list_size:32;
228
229 /** Command size - 32 or 64 bytes */
230 u64 instr_type:32;
231
232 /** Minimum number of commands pending to be posted to Octeon
233 * before driver hits the Input queue doorbell.
234 */
235 u64 db_min:8;
236
237 /** Minimum ticks to wait before checking for pending instructions. */
238 u64 db_timeout:16;
239
240 /** Tx interrupt packets. Applicable to 23xx only */
241 u64 iq_intr_pkt:16;
242
243 u64 reserved:16;
244#endif
245};
246
247/** Structure to define the configuration attributes for each Output queue.
248 * Applicable to all Octeon processors
249 **/
250struct octeon_oq_config {
251#ifdef __BIG_ENDIAN_BITFIELD
252 u64 reserved:16;
253
254 u64 pkts_per_intr:16;
255
256 /** Interrupt Coalescing (Time Interval). Octeon will interrupt the
257 * host if atleast one packet was sent in the time interval specified
258 * by this field. The driver uses time interval interrupt coalescing
259 * by default. The time is specified in microseconds.
260 */
261 u64 oq_intr_time:16;
262
263 /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
264 * only if it sent as many packets as specified by this field.
265 * The driver
266 * usually does not use packet count interrupt coalescing.
267 */
268 u64 oq_intr_pkt:16;
269
270 /** The number of buffers that were consumed during packet processing by
271 * the driver on this Output queue before the driver attempts to
272 * replenish
273 * the descriptor ring with new buffers.
274 */
275 u64 refill_threshold:16;
276
277 /* Max number of OQs available */
278 u64 max_oqs:8;
279
280#else
281 /* Max number of OQs available */
282 u64 max_oqs:8;
283
284 /** The number of buffers that were consumed during packet processing by
285 * the driver on this Output queue before the driver attempts to
286 * replenish
287 * the descriptor ring with new buffers.
288 */
289 u64 refill_threshold:16;
290
291 /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
292 * only if it sent as many packets as specified by this field.
293 * The driver
294 * usually does not use packet count interrupt coalescing.
295 */
296 u64 oq_intr_pkt:16;
297
298 /** Interrupt Coalescing (Time Interval). Octeon will interrupt the
299 * host if atleast one packet was sent in the time interval specified
300 * by this field. The driver uses time interval interrupt coalescing
301 * by default. The time is specified in microseconds.
302 */
303 u64 oq_intr_time:16;
304
305 u64 pkts_per_intr:16;
306
307 u64 reserved:16;
308#endif
309
310};
311
312/** This structure conatins the NIC link configuration attributes,
313 * common for all the OCTEON Modles.
314 */
315struct octeon_nic_if_config {
316#ifdef __BIG_ENDIAN_BITFIELD
317 u64 reserved:56;
318
319 u64 base_queue:16;
320
321 u64 gmx_port_id:8;
322
323 /* SKB size, We need not change buf size even for Jumbo frames.
324 * Octeon can send jumbo frames in 4 consecutive descriptors,
325 */
326 u64 rx_buf_size:16;
327
328 /* Num of desc for tx rings */
329 u64 num_tx_descs:16;
330
331 /* Num of desc for rx rings */
332 u64 num_rx_descs:16;
333
334 /* Actual configured value. Range could be: 1...max_rxqs */
335 u64 num_rxqs:16;
336
337 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
338 u64 max_rxqs:16;
339
340 /* Actual configured value. Range could be: 1...max_txqs */
341 u64 num_txqs:16;
342
343 /* Max Txqs: Half for each of the two ports :max_iq/2 */
344 u64 max_txqs:16;
345#else
346 /* Max Txqs: Half for each of the two ports :max_iq/2 */
347 u64 max_txqs:16;
348
349 /* Actual configured value. Range could be: 1...max_txqs */
350 u64 num_txqs:16;
351
352 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
353 u64 max_rxqs:16;
354
355 /* Actual configured value. Range could be: 1...max_rxqs */
356 u64 num_rxqs:16;
357
358 /* Num of desc for rx rings */
359 u64 num_rx_descs:16;
360
361 /* Num of desc for tx rings */
362 u64 num_tx_descs:16;
363
364 /* SKB size, We need not change buf size even for Jumbo frames.
365 * Octeon can send jumbo frames in 4 consecutive descriptors,
366 */
367 u64 rx_buf_size:16;
368
369 u64 gmx_port_id:8;
370
371 u64 base_queue:16;
372
373 u64 reserved:56;
374#endif
375
376};
377
378/** Structure to define the configuration attributes for meta data.
379 * Applicable to all Octeon processors.
380 */
381
382struct octeon_misc_config {
383#ifdef __BIG_ENDIAN_BITFIELD
384 /** Host link status polling period */
385 u64 host_link_query_interval:32;
386 /** Oct link status polling period */
387 u64 oct_link_query_interval:32;
388
389 u64 enable_sli_oq_bp:1;
390 /** Control IQ Group */
391 u64 ctrlq_grp:4;
392#else
393 /** Control IQ Group */
394 u64 ctrlq_grp:4;
395 /** BP for SLI OQ */
396 u64 enable_sli_oq_bp:1;
397 /** Host link status polling period */
398 u64 oct_link_query_interval:32;
399 /** Oct link status polling period */
400 u64 host_link_query_interval:32;
401#endif
402};
403
404/** Structure to define the configuration for all OCTEON processors. */
405struct octeon_config {
406 u16 card_type;
407 char *card_name;
408
409 /** Input Queue attributes. */
410 struct octeon_iq_config iq;
411
412 /** Output Queue attributes. */
413 struct octeon_oq_config oq;
414
415 /** NIC Port Configuration */
416 struct octeon_nic_if_config nic_if_cfg[MAX_OCTEON_NICIF];
417
418 /** Miscellaneous attributes */
419 struct octeon_misc_config misc;
420
421 int num_nic_ports;
422
423 int num_def_tx_descs;
424
425 /* Num of desc for rx rings */
426 int num_def_rx_descs;
427
428 int def_rx_buf_size;
429
430};
431
432/* The following config values are fixed and should not be modified. */
433
434#define BAR1_INDEX_DYNAMIC_MAP 2
435#define BAR1_INDEX_STATIC_MAP 15
436#define OCTEON_BAR1_ENTRY_SIZE (4 * 1024 * 1024)
437
438#define MAX_BAR1_IOREMAP_SIZE (16 * OCTEON_BAR1_ENTRY_SIZE)
439
440/* Response lists - 1 ordered, 1 unordered-blocking, 1 unordered-nonblocking
441 * 1 process done list, 1 zombie lists(timeouted sc list)
442 * NoResponse Lists are now maintained with each IQ. (Dec' 2007).
443 */
444#define MAX_RESPONSE_LISTS 6
445
446/* Opcode hash bits. The opcode is hashed on the lower 6-bits to lookup the
447 * dispatch table.
448 */
449#define OPCODE_MASK_BITS 6
450
451/* Mask for the 6-bit lookup hash */
452#define OCTEON_OPCODE_MASK 0x3f
453
454/* Size of the dispatch table. The 6-bit hash can index into 2^6 entries */
455#define DISPATCH_LIST_SIZE BIT(OPCODE_MASK_BITS)
456
457/* Maximum number of Octeon Instruction (command) queues */
458#define MAX_OCTEON_INSTR_QUEUES(oct) \
459 (OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_INPUT_QUEUES : \
460 CN6XXX_MAX_INPUT_QUEUES)
461
462/* Maximum number of Octeon Instruction (command) queues */
463#define MAX_OCTEON_OUTPUT_QUEUES(oct) \
464 (OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_OUTPUT_QUEUES : \
465 CN6XXX_MAX_OUTPUT_QUEUES)
466
467#define MAX_POSSIBLE_OCTEON_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES
468#define MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES
469
470#define MAX_POSSIBLE_VFS 64
471
472#endif /* __OCTEON_CONFIG_H__ */