1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright 2016 Linaro Ltd.
  4 * Copyright 2016 ZTE Corporation.
  5 */
  6
  7#ifndef __ZX_VOU_REGS_H__
  8#define __ZX_VOU_REGS_H__
  9
 10/* Sub-module offset */
 11#define MAIN_GL_OFFSET			0x130
 12#define MAIN_GL_CSC_OFFSET		0x580
 13#define MAIN_CHN_CSC_OFFSET		0x6c0
 14#define MAIN_HBSC_OFFSET		0x820
 15#define MAIN_DITHER_OFFSET		0x960
 16#define MAIN_RSZ_OFFSET			0x600 /* OTFPPU sub-module */
 17
 18#define AUX_GL_OFFSET			0x200
 19#define AUX_GL_CSC_OFFSET		0x5d0
 20#define AUX_CHN_CSC_OFFSET		0x710
 21#define AUX_HBSC_OFFSET			0x860
 22#define AUX_DITHER_OFFSET		0x970
 23#define AUX_RSZ_OFFSET			0x800
 24
 25#define OSD_VL0_OFFSET			0x040
 26#define OSD_VL_OFFSET(i)		(OSD_VL0_OFFSET + 0x050 * (i))
 27
 28#define HBSC_VL0_OFFSET			0x760
 29#define HBSC_VL_OFFSET(i)		(HBSC_VL0_OFFSET + 0x040 * (i))
 30
 31#define RSZ_VL1_U0			0xa00
 32#define RSZ_VL_OFFSET(i)		(RSZ_VL1_U0 + 0x200 * (i))
 33
 34/* OSD (GPC_GLOBAL) registers */
 35#define OSD_INT_STA			0x04
 36#define OSD_INT_CLRSTA			0x08
 37#define OSD_INT_MSK			0x0c
 38#define OSD_INT_AUX_UPT			BIT(14)
 39#define OSD_INT_MAIN_UPT		BIT(13)
 40#define OSD_INT_GL1_LBW			BIT(10)
 41#define OSD_INT_GL0_LBW			BIT(9)
 42#define OSD_INT_VL2_LBW			BIT(8)
 43#define OSD_INT_VL1_LBW			BIT(7)
 44#define OSD_INT_VL0_LBW			BIT(6)
 45#define OSD_INT_BUS_ERR			BIT(3)
 46#define OSD_INT_CFG_ERR			BIT(2)
 47#define OSD_INT_ERROR (\
 48	OSD_INT_GL1_LBW | OSD_INT_GL0_LBW | \
 49	OSD_INT_VL2_LBW | OSD_INT_VL1_LBW | OSD_INT_VL0_LBW | \
 50	OSD_INT_BUS_ERR | OSD_INT_CFG_ERR \
 51)
 52#define OSD_INT_ENABLE (OSD_INT_ERROR | OSD_INT_AUX_UPT | OSD_INT_MAIN_UPT)
 53#define OSD_CTRL0			0x10
 54#define OSD_CTRL0_VL0_EN		BIT(13)
 55#define OSD_CTRL0_VL0_SEL		BIT(12)
 56#define OSD_CTRL0_VL1_EN		BIT(11)
 57#define OSD_CTRL0_VL1_SEL		BIT(10)
 58#define OSD_CTRL0_VL2_EN		BIT(9)
 59#define OSD_CTRL0_VL2_SEL		BIT(8)
 60#define OSD_CTRL0_GL0_EN		BIT(7)
 61#define OSD_CTRL0_GL0_SEL		BIT(6)
 62#define OSD_CTRL0_GL1_EN		BIT(5)
 63#define OSD_CTRL0_GL1_SEL		BIT(4)
 64#define OSD_RST_CLR			0x1c
 65#define RST_PER_FRAME			BIT(19)
 66
 67/* Main/Aux channel registers */
 68#define OSD_MAIN_CHN			0x470
 69#define OSD_AUX_CHN			0x4d0
 70#define CHN_CTRL0			0x00
 71#define CHN_ENABLE			BIT(0)
 72#define CHN_CTRL1			0x04
 73#define CHN_SCREEN_W_SHIFT		18
 74#define CHN_SCREEN_W_MASK		(0x1fff << CHN_SCREEN_W_SHIFT)
 75#define CHN_SCREEN_H_SHIFT		5
 76#define CHN_SCREEN_H_MASK		(0x1fff << CHN_SCREEN_H_SHIFT)
 77#define CHN_UPDATE			0x08
 78#define CHN_INTERLACE_BUF_CTRL		0x24
 79#define CHN_INTERLACE_EN		BIT(2)
 80
 81/* Dither registers */
 82#define OSD_DITHER_CTRL0		0x00
 83#define DITHER_BYSPASS			BIT(31)
 84
 85/* TIMING_CTRL registers */
 86#define TIMING_TC_ENABLE		0x04
 87#define AUX_TC_EN			BIT(1)
 88#define MAIN_TC_EN			BIT(0)
 89#define FIR_MAIN_ACTIVE			0x08
 90#define FIR_AUX_ACTIVE			0x0c
 91#define V_ACTIVE_SHIFT			16
 92#define V_ACTIVE_MASK			(0xffff << V_ACTIVE_SHIFT)
 93#define H_ACTIVE_SHIFT			0
 94#define H_ACTIVE_MASK			(0xffff << H_ACTIVE_SHIFT)
 95#define FIR_MAIN_H_TIMING		0x10
 96#define FIR_MAIN_V_TIMING		0x14
 97#define FIR_AUX_H_TIMING		0x18
 98#define FIR_AUX_V_TIMING		0x1c
 99#define SYNC_WIDE_SHIFT			22
100#define SYNC_WIDE_MASK			(0x3ff << SYNC_WIDE_SHIFT)
101#define BACK_PORCH_SHIFT		11
102#define BACK_PORCH_MASK			(0x7ff << BACK_PORCH_SHIFT)
103#define FRONT_PORCH_SHIFT		0
104#define FRONT_PORCH_MASK		(0x7ff << FRONT_PORCH_SHIFT)
105#define TIMING_CTRL			0x20
106#define AUX_POL_SHIFT			3
107#define AUX_POL_MASK			(0x7 << AUX_POL_SHIFT)
108#define MAIN_POL_SHIFT			0
109#define MAIN_POL_MASK			(0x7 << MAIN_POL_SHIFT)
110#define POL_DE_SHIFT			2
111#define POL_VSYNC_SHIFT			1
112#define POL_HSYNC_SHIFT			0
113#define TIMING_INT_CTRL			0x24
114#define TIMING_INT_STATE		0x28
115#define TIMING_INT_AUX_FRAME		BIT(3)
116#define TIMING_INT_MAIN_FRAME		BIT(1)
117#define TIMING_INT_AUX_FRAME_SEL_VSW	(0x2 << 10)
118#define TIMING_INT_MAIN_FRAME_SEL_VSW	(0x2 << 6)
119#define TIMING_INT_ENABLE (\
120	TIMING_INT_MAIN_FRAME_SEL_VSW | TIMING_INT_AUX_FRAME_SEL_VSW | \
121	TIMING_INT_MAIN_FRAME | TIMING_INT_AUX_FRAME \
122)
123#define TIMING_MAIN_SHIFT		0x2c
124#define TIMING_AUX_SHIFT		0x30
125#define H_SHIFT_VAL			0x0048
126#define V_SHIFT_VAL			0x0001
127#define SCAN_CTRL			0x34
128#define AUX_PI_EN			BIT(19)
129#define MAIN_PI_EN			BIT(18)
130#define AUX_INTERLACE_SEL		BIT(1)
131#define MAIN_INTERLACE_SEL		BIT(0)
132#define SEC_V_ACTIVE			0x38
133#define SEC_VACT_MAIN_SHIFT		0
134#define SEC_VACT_MAIN_MASK		(0xffff << SEC_VACT_MAIN_SHIFT)
135#define SEC_VACT_AUX_SHIFT		16
136#define SEC_VACT_AUX_MASK		(0xffff << SEC_VACT_AUX_SHIFT)
137#define SEC_MAIN_V_TIMING		0x3c
138#define SEC_AUX_V_TIMING		0x40
139#define TIMING_MAIN_PI_SHIFT		0x68
140#define TIMING_AUX_PI_SHIFT		0x6c
141#define H_PI_SHIFT_VAL			0x000f
142
143#define V_ACTIVE(x)	(((x) << V_ACTIVE_SHIFT) & V_ACTIVE_MASK)
144#define H_ACTIVE(x)	(((x) << H_ACTIVE_SHIFT) & H_ACTIVE_MASK)
145
146#define SYNC_WIDE(x)	(((x) << SYNC_WIDE_SHIFT) & SYNC_WIDE_MASK)
147#define BACK_PORCH(x)	(((x) << BACK_PORCH_SHIFT) & BACK_PORCH_MASK)
148#define FRONT_PORCH(x)	(((x) << FRONT_PORCH_SHIFT) & FRONT_PORCH_MASK)
149
150/* DTRC registers */
151#define DTRC_F0_CTRL			0x2c
152#define DTRC_F1_CTRL			0x5c
153#define DTRC_DECOMPRESS_BYPASS		BIT(17)
154#define DTRC_DETILE_CTRL		0x68
155#define TILE2RASTESCAN_BYPASS_MODE	BIT(30)
156#define DETILE_ARIDR_MODE_MASK		(0x3 << 0)
157#define DETILE_ARID_ALL			0
158#define DETILE_ARID_IN_ARIDR		1
159#define DETILE_ARID_BYP_BUT_ARIDR	2
160#define DETILE_ARID_IN_ARIDR2		3
161#define DTRC_ARID			0x6c
162#define DTRC_ARID3_SHIFT		24
163#define DTRC_ARID3_MASK			(0xff << DTRC_ARID3_SHIFT)
164#define DTRC_ARID2_SHIFT		16
165#define DTRC_ARID2_MASK			(0xff << DTRC_ARID2_SHIFT)
166#define DTRC_ARID1_SHIFT		8
167#define DTRC_ARID1_MASK			(0xff << DTRC_ARID1_SHIFT)
168#define DTRC_ARID0_SHIFT		0
169#define DTRC_ARID0_MASK			(0xff << DTRC_ARID0_SHIFT)
170#define DTRC_DEC2DDR_ARID		0x70
171
172#define DTRC_ARID3(x)	(((x) << DTRC_ARID3_SHIFT) & DTRC_ARID3_MASK)
173#define DTRC_ARID2(x)	(((x) << DTRC_ARID2_SHIFT) & DTRC_ARID2_MASK)
174#define DTRC_ARID1(x)	(((x) << DTRC_ARID1_SHIFT) & DTRC_ARID1_MASK)
175#define DTRC_ARID0(x)	(((x) << DTRC_ARID0_SHIFT) & DTRC_ARID0_MASK)
176
177/* VOU_CTRL registers */
178#define VOU_INF_EN			0x00
179#define VOU_INF_CH_SEL			0x04
180#define VOU_INF_DATA_SEL		0x08
181#define VOU_SOFT_RST			0x14
182#define VOU_CLK_SEL			0x18
183#define VGA_AUX_DIV_SHIFT		29
184#define VGA_MAIN_DIV_SHIFT		26
185#define PIC_MAIN_DIV_SHIFT		23
186#define PIC_AUX_DIV_SHIFT		20
187#define VOU_CLK_VL2_SEL			BIT(8)
188#define VOU_CLK_VL1_SEL			BIT(7)
189#define VOU_CLK_VL0_SEL			BIT(6)
190#define VOU_CLK_GL1_SEL			BIT(5)
191#define VOU_CLK_GL0_SEL			BIT(4)
192#define VOU_DIV_PARA			0x1c
193#define DIV_PARA_UPDATE			BIT(31)
194#define TVENC_AUX_DIV_SHIFT		28
195#define HDMI_AUX_PNX_DIV_SHIFT		25
196#define HDMI_MAIN_PNX_DIV_SHIFT		22
197#define HDMI_AUX_DIV_SHIFT		19
198#define HDMI_MAIN_DIV_SHIFT		16
199#define TVENC_MAIN_DIV_SHIFT		13
200#define INF_AUX_DIV_SHIFT		9
201#define INF_MAIN_DIV_SHIFT		6
202#define LAYER_AUX_DIV_SHIFT		3
203#define LAYER_MAIN_DIV_SHIFT		0
204#define VOU_CLK_REQEN			0x20
205#define VOU_CLK_EN			0x24
206#define VOU_INF_HDMI_CTRL		0x30
207#define VOU_HDMI_AUD_MASK		0x1f
208
209/* OTFPPU_CTRL registers */
210#define OTFPPU_RSZ_DATA_SOURCE		0x04
211
212#endif /* __ZX_VOU_REGS_H__ */