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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Zheng Yang <zhengyang@rock-chips.com>
5 */
6
7#include <drm/drm_atomic.h>
8#include <drm/drm_edid.h>
9#include <drm/drm_of.h>
10#include <drm/drm_probe_helper.h>
11#include <drm/drm_simple_kms_helper.h>
12
13#include <linux/clk.h>
14#include <linux/mfd/syscon.h>
15#include <linux/platform_device.h>
16#include <linux/regmap.h>
17
18#include "rk3066_hdmi.h"
19
20#include "rockchip_drm_drv.h"
21
22#define DEFAULT_PLLA_RATE 30000000
23
24struct hdmi_data_info {
25 int vic; /* The CEA Video ID (VIC) of the current drm display mode. */
26 unsigned int enc_out_format;
27 unsigned int colorimetry;
28};
29
30struct rk3066_hdmi_i2c {
31 struct i2c_adapter adap;
32
33 u8 ddc_addr;
34 u8 segment_addr;
35 u8 stat;
36
37 struct mutex i2c_lock; /* For i2c operation. */
38 struct completion cmpltn;
39};
40
41struct rk3066_hdmi {
42 struct device *dev;
43 struct drm_device *drm_dev;
44 struct regmap *grf_regmap;
45 int irq;
46 struct clk *hclk;
47 void __iomem *regs;
48
49 struct drm_connector connector;
50 struct rockchip_encoder encoder;
51
52 struct rk3066_hdmi_i2c *i2c;
53 struct i2c_adapter *ddc;
54
55 unsigned int tmdsclk;
56
57 struct hdmi_data_info hdmi_data;
58};
59
60static struct rk3066_hdmi *encoder_to_rk3066_hdmi(struct drm_encoder *encoder)
61{
62 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
63
64 return container_of(rkencoder, struct rk3066_hdmi, encoder);
65}
66
67static struct rk3066_hdmi *connector_to_rk3066_hdmi(struct drm_connector *connector)
68{
69 return container_of(connector, struct rk3066_hdmi, connector);
70}
71
72static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset)
73{
74 return readl_relaxed(hdmi->regs + offset);
75}
76
77static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val)
78{
79 writel_relaxed(val, hdmi->regs + offset);
80}
81
82static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset,
83 u32 msk, u32 val)
84{
85 u8 temp = hdmi_readb(hdmi, offset) & ~msk;
86
87 temp |= val & msk;
88 hdmi_writeb(hdmi, offset, temp);
89}
90
91static void rk3066_hdmi_i2c_init(struct rk3066_hdmi *hdmi)
92{
93 int ddc_bus_freq;
94
95 ddc_bus_freq = (hdmi->tmdsclk >> 2) / HDMI_SCL_RATE;
96
97 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
98 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
99
100 /* Clear the EDID interrupt flag and mute the interrupt. */
101 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
102 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK);
103}
104
105static inline u8 rk3066_hdmi_get_power_mode(struct rk3066_hdmi *hdmi)
106{
107 return hdmi_readb(hdmi, HDMI_SYS_CTRL) & HDMI_SYS_POWER_MODE_MASK;
108}
109
110static void rk3066_hdmi_set_power_mode(struct rk3066_hdmi *hdmi, int mode)
111{
112 u8 current_mode, next_mode;
113 u8 i = 0;
114
115 current_mode = rk3066_hdmi_get_power_mode(hdmi);
116
117 DRM_DEV_DEBUG(hdmi->dev, "mode :%d\n", mode);
118 DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode);
119
120 if (current_mode == mode)
121 return;
122
123 do {
124 if (current_mode > mode) {
125 next_mode = current_mode / 2;
126 } else {
127 if (current_mode < HDMI_SYS_POWER_MODE_A)
128 next_mode = HDMI_SYS_POWER_MODE_A;
129 else
130 next_mode = current_mode * 2;
131 }
132
133 DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode);
134
135 if (next_mode != HDMI_SYS_POWER_MODE_D) {
136 hdmi_modb(hdmi, HDMI_SYS_CTRL,
137 HDMI_SYS_POWER_MODE_MASK, next_mode);
138 } else {
139 hdmi_writeb(hdmi, HDMI_SYS_CTRL,
140 HDMI_SYS_POWER_MODE_D |
141 HDMI_SYS_PLL_RESET_MASK);
142 usleep_range(90, 100);
143 hdmi_writeb(hdmi, HDMI_SYS_CTRL,
144 HDMI_SYS_POWER_MODE_D |
145 HDMI_SYS_PLLB_RESET);
146 usleep_range(90, 100);
147 hdmi_writeb(hdmi, HDMI_SYS_CTRL,
148 HDMI_SYS_POWER_MODE_D);
149 }
150 current_mode = next_mode;
151 i = i + 1;
152 } while ((next_mode != mode) && (i < 5));
153
154 /*
155 * When the IP controller isn't configured with accurate video timing,
156 * DDC_CLK should be equal to the PLLA frequency, which is 30MHz,
157 * so we need to init the TMDS rate to the PCLK rate and reconfigure
158 * the DDC clock.
159 */
160 if (mode < HDMI_SYS_POWER_MODE_D)
161 hdmi->tmdsclk = DEFAULT_PLLA_RATE;
162}
163
164static int
165rk3066_hdmi_upload_frame(struct rk3066_hdmi *hdmi, int setup_rc,
166 union hdmi_infoframe *frame, u32 frame_index,
167 u32 mask, u32 disable, u32 enable)
168{
169 if (mask)
170 hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, disable);
171
172 hdmi_writeb(hdmi, HDMI_CP_BUF_INDEX, frame_index);
173
174 if (setup_rc >= 0) {
175 u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
176 ssize_t rc, i;
177
178 rc = hdmi_infoframe_pack(frame, packed_frame,
179 sizeof(packed_frame));
180 if (rc < 0)
181 return rc;
182
183 for (i = 0; i < rc; i++)
184 hdmi_writeb(hdmi, HDMI_CP_BUF_ACC_HB0 + i * 4,
185 packed_frame[i]);
186
187 if (mask)
188 hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, enable);
189 }
190
191 return setup_rc;
192}
193
194static int rk3066_hdmi_config_avi(struct rk3066_hdmi *hdmi,
195 struct drm_display_mode *mode)
196{
197 union hdmi_infoframe frame;
198 int rc;
199
200 rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
201 &hdmi->connector, mode);
202
203 if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444)
204 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
205 else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422)
206 frame.avi.colorspace = HDMI_COLORSPACE_YUV422;
207 else
208 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
209
210 frame.avi.colorimetry = hdmi->hdmi_data.colorimetry;
211 frame.avi.scan_mode = HDMI_SCAN_MODE_NONE;
212
213 return rk3066_hdmi_upload_frame(hdmi, rc, &frame,
214 HDMI_INFOFRAME_AVI, 0, 0, 0);
215}
216
217static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi,
218 struct drm_display_mode *mode)
219{
220 int value, vsync_offset;
221
222 /* Set the details for the external polarity and interlace mode. */
223 value = HDMI_EXT_VIDEO_SET_EN;
224 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
225 HDMI_VIDEO_HSYNC_ACTIVE_HIGH : HDMI_VIDEO_HSYNC_ACTIVE_LOW;
226 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
227 HDMI_VIDEO_VSYNC_ACTIVE_HIGH : HDMI_VIDEO_VSYNC_ACTIVE_LOW;
228 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
229 HDMI_VIDEO_MODE_INTERLACE : HDMI_VIDEO_MODE_PROGRESSIVE;
230
231 if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3)
232 vsync_offset = 6;
233 else
234 vsync_offset = 0;
235
236 value |= vsync_offset << HDMI_VIDEO_VSYNC_OFFSET_SHIFT;
237 hdmi_writeb(hdmi, HDMI_EXT_VIDEO_PARA, value);
238
239 /* Set the details for the external video timing. */
240 value = mode->htotal;
241 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_L, value & 0xFF);
242 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_H, (value >> 8) & 0xFF);
243
244 value = mode->htotal - mode->hdisplay;
245 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_L, value & 0xFF);
246 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_H, (value >> 8) & 0xFF);
247
248 value = mode->htotal - mode->hsync_start;
249 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_L, value & 0xFF);
250 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_H, (value >> 8) & 0xFF);
251
252 value = mode->hsync_end - mode->hsync_start;
253 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_L, value & 0xFF);
254 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_H, (value >> 8) & 0xFF);
255
256 value = mode->vtotal;
257 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_L, value & 0xFF);
258 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_H, (value >> 8) & 0xFF);
259
260 value = mode->vtotal - mode->vdisplay;
261 hdmi_writeb(hdmi, HDMI_EXT_VBLANK_L, value & 0xFF);
262
263 value = mode->vtotal - mode->vsync_start + vsync_offset;
264 hdmi_writeb(hdmi, HDMI_EXT_VDELAY, value & 0xFF);
265
266 value = mode->vsync_end - mode->vsync_start;
267 hdmi_writeb(hdmi, HDMI_EXT_VDURATION, value & 0xFF);
268
269 return 0;
270}
271
272static void
273rk3066_hdmi_phy_write(struct rk3066_hdmi *hdmi, u16 offset, u8 value)
274{
275 hdmi_writeb(hdmi, offset, value);
276 hdmi_modb(hdmi, HDMI_SYS_CTRL,
277 HDMI_SYS_PLL_RESET_MASK, HDMI_SYS_PLL_RESET);
278 usleep_range(90, 100);
279 hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_PLL_RESET_MASK, 0);
280 usleep_range(900, 1000);
281}
282
283static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi)
284{
285 /* TMDS uses the same frequency as dclk. */
286 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x22);
287
288 /*
289 * The semi-public documentation does not describe the hdmi registers
290 * used by the function rk3066_hdmi_phy_write(), so we keep using
291 * these magic values for now.
292 */
293 if (hdmi->tmdsclk > 100000000) {
294 rk3066_hdmi_phy_write(hdmi, 0x158, 0x0E);
295 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
296 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
297 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
298 rk3066_hdmi_phy_write(hdmi, 0x168, 0xDA);
299 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA1);
300 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
301 rk3066_hdmi_phy_write(hdmi, 0x174, 0x22);
302 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
303 } else if (hdmi->tmdsclk > 50000000) {
304 rk3066_hdmi_phy_write(hdmi, 0x158, 0x06);
305 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
306 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
307 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
308 rk3066_hdmi_phy_write(hdmi, 0x168, 0xCA);
309 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA3);
310 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
311 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20);
312 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
313 } else {
314 rk3066_hdmi_phy_write(hdmi, 0x158, 0x02);
315 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
316 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
317 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
318 rk3066_hdmi_phy_write(hdmi, 0x168, 0xC2);
319 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA2);
320 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
321 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20);
322 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
323 }
324}
325
326static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi,
327 struct drm_display_mode *mode)
328{
329 struct drm_display_info *display = &hdmi->connector.display_info;
330
331 hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
332 hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB;
333
334 if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 ||
335 hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 ||
336 hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 ||
337 hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18)
338 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
339 else
340 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
341
342 hdmi->tmdsclk = mode->clock * 1000;
343
344 /* Mute video and audio output. */
345 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK,
346 HDMI_AUDIO_DISABLE | HDMI_VIDEO_DISABLE);
347
348 /* Set power state to mode B. */
349 if (rk3066_hdmi_get_power_mode(hdmi) != HDMI_SYS_POWER_MODE_B)
350 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
351
352 /* Input video mode is RGB 24 bit. Use external data enable signal. */
353 hdmi_modb(hdmi, HDMI_AV_CTRL1,
354 HDMI_VIDEO_DE_MASK, HDMI_VIDEO_EXTERNAL_DE);
355 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL1,
356 HDMI_VIDEO_OUTPUT_RGB444 |
357 HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT |
358 HDMI_VIDEO_INPUT_COLOR_RGB);
359 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x20);
360
361 rk3066_hdmi_config_video_timing(hdmi, mode);
362
363 if (display->is_hdmi) {
364 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK,
365 HDMI_VIDEO_MODE_HDMI);
366 rk3066_hdmi_config_avi(hdmi, mode);
367 } else {
368 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0);
369 }
370
371 rk3066_hdmi_config_phy(hdmi);
372
373 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_E);
374
375 /*
376 * When the IP controller is configured with accurate video
377 * timing, the TMDS clock source should be switched to
378 * DCLK_LCDC, so we need to init the TMDS rate to the pixel mode
379 * clock rate and reconfigure the DDC clock.
380 */
381 rk3066_hdmi_i2c_init(hdmi);
382
383 /* Unmute video output. */
384 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
385 HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE);
386 return 0;
387}
388
389static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder,
390 struct drm_atomic_state *state)
391{
392 struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder);
393 struct drm_connector_state *conn_state;
394 struct drm_crtc_state *crtc_state;
395 int mux, val;
396
397 conn_state = drm_atomic_get_new_connector_state(state, &hdmi->connector);
398 if (WARN_ON(!conn_state))
399 return;
400
401 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
402 if (WARN_ON(!crtc_state))
403 return;
404
405 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
406 if (mux)
407 val = (HDMI_VIDEO_SEL << 16) | HDMI_VIDEO_SEL;
408 else
409 val = HDMI_VIDEO_SEL << 16;
410
411 regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val);
412
413 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder enable select: vop%s\n",
414 (mux) ? "1" : "0");
415
416 rk3066_hdmi_setup(hdmi, &crtc_state->adjusted_mode);
417}
418
419static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder,
420 struct drm_atomic_state *state)
421{
422 struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder);
423
424 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n");
425
426 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) {
427 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL2,
428 HDMI_VIDEO_AUDIO_DISABLE_MASK);
429 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
430 HDMI_AUDIO_CP_LOGIC_RESET_MASK,
431 HDMI_AUDIO_CP_LOGIC_RESET);
432 usleep_range(500, 510);
433 }
434 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A);
435}
436
437static int
438rk3066_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
439 struct drm_crtc_state *crtc_state,
440 struct drm_connector_state *conn_state)
441{
442 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
443
444 s->output_mode = ROCKCHIP_OUT_MODE_P888;
445 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
446
447 return 0;
448}
449
450static const
451struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = {
452 .atomic_check = rk3066_hdmi_encoder_atomic_check,
453 .atomic_enable = rk3066_hdmi_encoder_enable,
454 .atomic_disable = rk3066_hdmi_encoder_disable,
455};
456
457static enum drm_connector_status
458rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force)
459{
460 struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
461
462 return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ?
463 connector_status_connected : connector_status_disconnected;
464}
465
466static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector)
467{
468 struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
469 const struct drm_edid *drm_edid;
470 int ret = 0;
471
472 if (!hdmi->ddc)
473 return 0;
474
475 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc);
476 drm_edid_connector_update(connector, drm_edid);
477 ret = drm_edid_connector_add_modes(connector);
478 drm_edid_free(drm_edid);
479
480 return ret;
481}
482
483static enum drm_mode_status
484rk3066_hdmi_connector_mode_valid(struct drm_connector *connector,
485 struct drm_display_mode *mode)
486{
487 u32 vic = drm_match_cea_mode(mode);
488
489 if (vic > 1)
490 return MODE_OK;
491 else
492 return MODE_BAD;
493}
494
495static struct drm_encoder *
496rk3066_hdmi_connector_best_encoder(struct drm_connector *connector)
497{
498 struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
499
500 return &hdmi->encoder.encoder;
501}
502
503static int
504rk3066_hdmi_probe_single_connector_modes(struct drm_connector *connector,
505 uint32_t maxX, uint32_t maxY)
506{
507 if (maxX > 1920)
508 maxX = 1920;
509 if (maxY > 1080)
510 maxY = 1080;
511
512 return drm_helper_probe_single_connector_modes(connector, maxX, maxY);
513}
514
515static void rk3066_hdmi_connector_destroy(struct drm_connector *connector)
516{
517 drm_connector_unregister(connector);
518 drm_connector_cleanup(connector);
519}
520
521static const struct drm_connector_funcs rk3066_hdmi_connector_funcs = {
522 .fill_modes = rk3066_hdmi_probe_single_connector_modes,
523 .detect = rk3066_hdmi_connector_detect,
524 .destroy = rk3066_hdmi_connector_destroy,
525 .reset = drm_atomic_helper_connector_reset,
526 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
527 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
528};
529
530static const
531struct drm_connector_helper_funcs rk3066_hdmi_connector_helper_funcs = {
532 .get_modes = rk3066_hdmi_connector_get_modes,
533 .mode_valid = rk3066_hdmi_connector_mode_valid,
534 .best_encoder = rk3066_hdmi_connector_best_encoder,
535};
536
537static int
538rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi)
539{
540 struct drm_encoder *encoder = &hdmi->encoder.encoder;
541 struct device *dev = hdmi->dev;
542
543 encoder->possible_crtcs =
544 drm_of_find_possible_crtcs(drm, dev->of_node);
545
546 /*
547 * If we failed to find the CRTC(s) which this encoder is
548 * supposed to be connected to, it's because the CRTC has
549 * not been registered yet. Defer probing, and hope that
550 * the required CRTC is added later.
551 */
552 if (encoder->possible_crtcs == 0)
553 return -EPROBE_DEFER;
554
555 drm_encoder_helper_add(encoder, &rk3066_hdmi_encoder_helper_funcs);
556 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
557
558 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
559
560 drm_connector_helper_add(&hdmi->connector,
561 &rk3066_hdmi_connector_helper_funcs);
562 drm_connector_init_with_ddc(drm, &hdmi->connector,
563 &rk3066_hdmi_connector_funcs,
564 DRM_MODE_CONNECTOR_HDMIA,
565 hdmi->ddc);
566
567 drm_connector_attach_encoder(&hdmi->connector, encoder);
568
569 return 0;
570}
571
572static irqreturn_t rk3066_hdmi_hardirq(int irq, void *dev_id)
573{
574 struct rk3066_hdmi *hdmi = dev_id;
575 irqreturn_t ret = IRQ_NONE;
576 u8 interrupt;
577
578 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_A)
579 hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_B);
580
581 interrupt = hdmi_readb(hdmi, HDMI_INTR_STATUS1);
582 if (interrupt)
583 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, interrupt);
584
585 if (interrupt & HDMI_INTR_EDID_MASK) {
586 hdmi->i2c->stat = interrupt;
587 complete(&hdmi->i2c->cmpltn);
588 }
589
590 if (interrupt & (HDMI_INTR_HOTPLUG | HDMI_INTR_MSENS))
591 ret = IRQ_WAKE_THREAD;
592
593 return ret;
594}
595
596static irqreturn_t rk3066_hdmi_irq(int irq, void *dev_id)
597{
598 struct rk3066_hdmi *hdmi = dev_id;
599
600 drm_helper_hpd_irq_event(hdmi->connector.dev);
601
602 return IRQ_HANDLED;
603}
604
605static int rk3066_hdmi_i2c_read(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
606{
607 int length = msgs->len;
608 u8 *buf = msgs->buf;
609 int ret;
610
611 ret = wait_for_completion_timeout(&hdmi->i2c->cmpltn, HZ / 10);
612 if (!ret || hdmi->i2c->stat & HDMI_INTR_EDID_ERR)
613 return -EAGAIN;
614
615 while (length--)
616 *buf++ = hdmi_readb(hdmi, HDMI_DDC_READ_FIFO_ADDR);
617
618 return 0;
619}
620
621static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
622{
623 /*
624 * The DDC module only supports read EDID message, so
625 * we assume that each word write to this i2c adapter
626 * should be the offset of the EDID word address.
627 */
628 if (msgs->len != 1 ||
629 (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR))
630 return -EINVAL;
631
632 reinit_completion(&hdmi->i2c->cmpltn);
633
634 if (msgs->addr == DDC_SEGMENT_ADDR)
635 hdmi->i2c->segment_addr = msgs->buf[0];
636 if (msgs->addr == DDC_ADDR)
637 hdmi->i2c->ddc_addr = msgs->buf[0];
638
639 /* Set edid fifo first address. */
640 hdmi_writeb(hdmi, HDMI_EDID_FIFO_ADDR, 0x00);
641
642 /* Set edid word address 0x00/0x80. */
643 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
644
645 /* Set edid segment pointer. */
646 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
647
648 return 0;
649}
650
651static int rk3066_hdmi_i2c_xfer(struct i2c_adapter *adap,
652 struct i2c_msg *msgs, int num)
653{
654 struct rk3066_hdmi *hdmi = i2c_get_adapdata(adap);
655 struct rk3066_hdmi_i2c *i2c = hdmi->i2c;
656 int i, ret = 0;
657
658 mutex_lock(&i2c->i2c_lock);
659
660 rk3066_hdmi_i2c_init(hdmi);
661
662 /* Unmute HDMI EDID interrupt. */
663 hdmi_modb(hdmi, HDMI_INTR_MASK1,
664 HDMI_INTR_EDID_MASK, HDMI_INTR_EDID_MASK);
665 i2c->stat = 0;
666
667 for (i = 0; i < num; i++) {
668 DRM_DEV_DEBUG(hdmi->dev,
669 "xfer: num: %d/%d, len: %d, flags: %#x\n",
670 i + 1, num, msgs[i].len, msgs[i].flags);
671
672 if (msgs[i].flags & I2C_M_RD)
673 ret = rk3066_hdmi_i2c_read(hdmi, &msgs[i]);
674 else
675 ret = rk3066_hdmi_i2c_write(hdmi, &msgs[i]);
676
677 if (ret < 0)
678 break;
679 }
680
681 if (!ret)
682 ret = num;
683
684 /* Mute HDMI EDID interrupt. */
685 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
686
687 mutex_unlock(&i2c->i2c_lock);
688
689 return ret;
690}
691
692static u32 rk3066_hdmi_i2c_func(struct i2c_adapter *adapter)
693{
694 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
695}
696
697static const struct i2c_algorithm rk3066_hdmi_algorithm = {
698 .master_xfer = rk3066_hdmi_i2c_xfer,
699 .functionality = rk3066_hdmi_i2c_func,
700};
701
702static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi)
703{
704 struct i2c_adapter *adap;
705 struct rk3066_hdmi_i2c *i2c;
706 int ret;
707
708 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
709 if (!i2c)
710 return ERR_PTR(-ENOMEM);
711
712 mutex_init(&i2c->i2c_lock);
713 init_completion(&i2c->cmpltn);
714
715 adap = &i2c->adap;
716 adap->owner = THIS_MODULE;
717 adap->dev.parent = hdmi->dev;
718 adap->dev.of_node = hdmi->dev->of_node;
719 adap->algo = &rk3066_hdmi_algorithm;
720 strscpy(adap->name, "RK3066 HDMI", sizeof(adap->name));
721 i2c_set_adapdata(adap, hdmi);
722
723 ret = i2c_add_adapter(adap);
724 if (ret) {
725 DRM_DEV_ERROR(hdmi->dev, "cannot add %s I2C adapter\n",
726 adap->name);
727 devm_kfree(hdmi->dev, i2c);
728 return ERR_PTR(ret);
729 }
730
731 hdmi->i2c = i2c;
732
733 DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
734
735 return adap;
736}
737
738static int rk3066_hdmi_bind(struct device *dev, struct device *master,
739 void *data)
740{
741 struct platform_device *pdev = to_platform_device(dev);
742 struct drm_device *drm = data;
743 struct rk3066_hdmi *hdmi;
744 int irq;
745 int ret;
746
747 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
748 if (!hdmi)
749 return -ENOMEM;
750
751 hdmi->dev = dev;
752 hdmi->drm_dev = drm;
753 hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
754 if (IS_ERR(hdmi->regs))
755 return PTR_ERR(hdmi->regs);
756
757 irq = platform_get_irq(pdev, 0);
758 if (irq < 0)
759 return irq;
760
761 hdmi->hclk = devm_clk_get(dev, "hclk");
762 if (IS_ERR(hdmi->hclk)) {
763 DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n");
764 return PTR_ERR(hdmi->hclk);
765 }
766
767 ret = clk_prepare_enable(hdmi->hclk);
768 if (ret) {
769 DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret);
770 return ret;
771 }
772
773 hdmi->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
774 "rockchip,grf");
775 if (IS_ERR(hdmi->grf_regmap)) {
776 DRM_DEV_ERROR(dev, "unable to get rockchip,grf\n");
777 ret = PTR_ERR(hdmi->grf_regmap);
778 goto err_disable_hclk;
779 }
780
781 /* internal hclk = hdmi_hclk / 25 */
782 hdmi_writeb(hdmi, HDMI_INTERNAL_CLK_DIVIDER, 25);
783
784 hdmi->ddc = rk3066_hdmi_i2c_adapter(hdmi);
785 if (IS_ERR(hdmi->ddc)) {
786 ret = PTR_ERR(hdmi->ddc);
787 hdmi->ddc = NULL;
788 goto err_disable_hclk;
789 }
790
791 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
792 usleep_range(999, 1000);
793 hdmi_writeb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_HOTPLUG);
794 hdmi_writeb(hdmi, HDMI_INTR_MASK2, 0);
795 hdmi_writeb(hdmi, HDMI_INTR_MASK3, 0);
796 hdmi_writeb(hdmi, HDMI_INTR_MASK4, 0);
797 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A);
798
799 ret = rk3066_hdmi_register(drm, hdmi);
800 if (ret)
801 goto err_disable_i2c;
802
803 dev_set_drvdata(dev, hdmi);
804
805 ret = devm_request_threaded_irq(dev, irq, rk3066_hdmi_hardirq,
806 rk3066_hdmi_irq, IRQF_SHARED,
807 dev_name(dev), hdmi);
808 if (ret) {
809 DRM_DEV_ERROR(dev, "failed to request hdmi irq: %d\n", ret);
810 goto err_cleanup_hdmi;
811 }
812
813 return 0;
814
815err_cleanup_hdmi:
816 hdmi->connector.funcs->destroy(&hdmi->connector);
817 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
818err_disable_i2c:
819 i2c_put_adapter(hdmi->ddc);
820err_disable_hclk:
821 clk_disable_unprepare(hdmi->hclk);
822
823 return ret;
824}
825
826static void rk3066_hdmi_unbind(struct device *dev, struct device *master,
827 void *data)
828{
829 struct rk3066_hdmi *hdmi = dev_get_drvdata(dev);
830
831 hdmi->connector.funcs->destroy(&hdmi->connector);
832 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
833
834 i2c_put_adapter(hdmi->ddc);
835 clk_disable_unprepare(hdmi->hclk);
836}
837
838static const struct component_ops rk3066_hdmi_ops = {
839 .bind = rk3066_hdmi_bind,
840 .unbind = rk3066_hdmi_unbind,
841};
842
843static int rk3066_hdmi_probe(struct platform_device *pdev)
844{
845 return component_add(&pdev->dev, &rk3066_hdmi_ops);
846}
847
848static void rk3066_hdmi_remove(struct platform_device *pdev)
849{
850 component_del(&pdev->dev, &rk3066_hdmi_ops);
851}
852
853static const struct of_device_id rk3066_hdmi_dt_ids[] = {
854 { .compatible = "rockchip,rk3066-hdmi" },
855 { /* sentinel */ },
856};
857MODULE_DEVICE_TABLE(of, rk3066_hdmi_dt_ids);
858
859struct platform_driver rk3066_hdmi_driver = {
860 .probe = rk3066_hdmi_probe,
861 .remove = rk3066_hdmi_remove,
862 .driver = {
863 .name = "rockchip-rk3066-hdmi",
864 .of_match_table = rk3066_hdmi_dt_ids,
865 },
866};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Zheng Yang <zhengyang@rock-chips.com>
5 */
6
7#include <drm/drm_of.h>
8#include <drm/drm_probe_helper.h>
9#include <drm/drm_simple_kms_helper.h>
10
11#include <linux/clk.h>
12#include <linux/mfd/syscon.h>
13#include <linux/platform_device.h>
14#include <linux/regmap.h>
15
16#include "rk3066_hdmi.h"
17
18#include "rockchip_drm_drv.h"
19#include "rockchip_drm_vop.h"
20
21#define DEFAULT_PLLA_RATE 30000000
22
23struct hdmi_data_info {
24 int vic; /* The CEA Video ID (VIC) of the current drm display mode. */
25 bool sink_is_hdmi;
26 unsigned int enc_out_format;
27 unsigned int colorimetry;
28};
29
30struct rk3066_hdmi_i2c {
31 struct i2c_adapter adap;
32
33 u8 ddc_addr;
34 u8 segment_addr;
35 u8 stat;
36
37 struct mutex i2c_lock; /* For i2c operation. */
38 struct completion cmpltn;
39};
40
41struct rk3066_hdmi {
42 struct device *dev;
43 struct drm_device *drm_dev;
44 struct regmap *grf_regmap;
45 int irq;
46 struct clk *hclk;
47 void __iomem *regs;
48
49 struct drm_connector connector;
50 struct drm_encoder encoder;
51
52 struct rk3066_hdmi_i2c *i2c;
53 struct i2c_adapter *ddc;
54
55 unsigned int tmdsclk;
56
57 struct hdmi_data_info hdmi_data;
58 struct drm_display_mode previous_mode;
59};
60
61#define to_rk3066_hdmi(x) container_of(x, struct rk3066_hdmi, x)
62
63static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset)
64{
65 return readl_relaxed(hdmi->regs + offset);
66}
67
68static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val)
69{
70 writel_relaxed(val, hdmi->regs + offset);
71}
72
73static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset,
74 u32 msk, u32 val)
75{
76 u8 temp = hdmi_readb(hdmi, offset) & ~msk;
77
78 temp |= val & msk;
79 hdmi_writeb(hdmi, offset, temp);
80}
81
82static void rk3066_hdmi_i2c_init(struct rk3066_hdmi *hdmi)
83{
84 int ddc_bus_freq;
85
86 ddc_bus_freq = (hdmi->tmdsclk >> 2) / HDMI_SCL_RATE;
87
88 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
89 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
90
91 /* Clear the EDID interrupt flag and mute the interrupt. */
92 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
93 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK);
94}
95
96static inline u8 rk3066_hdmi_get_power_mode(struct rk3066_hdmi *hdmi)
97{
98 return hdmi_readb(hdmi, HDMI_SYS_CTRL) & HDMI_SYS_POWER_MODE_MASK;
99}
100
101static void rk3066_hdmi_set_power_mode(struct rk3066_hdmi *hdmi, int mode)
102{
103 u8 current_mode, next_mode;
104 u8 i = 0;
105
106 current_mode = rk3066_hdmi_get_power_mode(hdmi);
107
108 DRM_DEV_DEBUG(hdmi->dev, "mode :%d\n", mode);
109 DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode);
110
111 if (current_mode == mode)
112 return;
113
114 do {
115 if (current_mode > mode) {
116 next_mode = current_mode / 2;
117 } else {
118 if (current_mode < HDMI_SYS_POWER_MODE_A)
119 next_mode = HDMI_SYS_POWER_MODE_A;
120 else
121 next_mode = current_mode * 2;
122 }
123
124 DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode);
125
126 if (next_mode != HDMI_SYS_POWER_MODE_D) {
127 hdmi_modb(hdmi, HDMI_SYS_CTRL,
128 HDMI_SYS_POWER_MODE_MASK, next_mode);
129 } else {
130 hdmi_writeb(hdmi, HDMI_SYS_CTRL,
131 HDMI_SYS_POWER_MODE_D |
132 HDMI_SYS_PLL_RESET_MASK);
133 usleep_range(90, 100);
134 hdmi_writeb(hdmi, HDMI_SYS_CTRL,
135 HDMI_SYS_POWER_MODE_D |
136 HDMI_SYS_PLLB_RESET);
137 usleep_range(90, 100);
138 hdmi_writeb(hdmi, HDMI_SYS_CTRL,
139 HDMI_SYS_POWER_MODE_D);
140 }
141 current_mode = next_mode;
142 i = i + 1;
143 } while ((next_mode != mode) && (i < 5));
144
145 /*
146 * When the IP controller isn't configured with accurate video timing,
147 * DDC_CLK should be equal to the PLLA frequency, which is 30MHz,
148 * so we need to init the TMDS rate to the PCLK rate and reconfigure
149 * the DDC clock.
150 */
151 if (mode < HDMI_SYS_POWER_MODE_D)
152 hdmi->tmdsclk = DEFAULT_PLLA_RATE;
153}
154
155static int
156rk3066_hdmi_upload_frame(struct rk3066_hdmi *hdmi, int setup_rc,
157 union hdmi_infoframe *frame, u32 frame_index,
158 u32 mask, u32 disable, u32 enable)
159{
160 if (mask)
161 hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, disable);
162
163 hdmi_writeb(hdmi, HDMI_CP_BUF_INDEX, frame_index);
164
165 if (setup_rc >= 0) {
166 u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
167 ssize_t rc, i;
168
169 rc = hdmi_infoframe_pack(frame, packed_frame,
170 sizeof(packed_frame));
171 if (rc < 0)
172 return rc;
173
174 for (i = 0; i < rc; i++)
175 hdmi_writeb(hdmi, HDMI_CP_BUF_ACC_HB0 + i * 4,
176 packed_frame[i]);
177
178 if (mask)
179 hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, enable);
180 }
181
182 return setup_rc;
183}
184
185static int rk3066_hdmi_config_avi(struct rk3066_hdmi *hdmi,
186 struct drm_display_mode *mode)
187{
188 union hdmi_infoframe frame;
189 int rc;
190
191 rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
192 &hdmi->connector, mode);
193
194 if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444)
195 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
196 else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422)
197 frame.avi.colorspace = HDMI_COLORSPACE_YUV422;
198 else
199 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
200
201 frame.avi.colorimetry = hdmi->hdmi_data.colorimetry;
202 frame.avi.scan_mode = HDMI_SCAN_MODE_NONE;
203
204 return rk3066_hdmi_upload_frame(hdmi, rc, &frame,
205 HDMI_INFOFRAME_AVI, 0, 0, 0);
206}
207
208static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi,
209 struct drm_display_mode *mode)
210{
211 int value, vsync_offset;
212
213 /* Set the details for the external polarity and interlace mode. */
214 value = HDMI_EXT_VIDEO_SET_EN;
215 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
216 HDMI_VIDEO_HSYNC_ACTIVE_HIGH : HDMI_VIDEO_HSYNC_ACTIVE_LOW;
217 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
218 HDMI_VIDEO_VSYNC_ACTIVE_HIGH : HDMI_VIDEO_VSYNC_ACTIVE_LOW;
219 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
220 HDMI_VIDEO_MODE_INTERLACE : HDMI_VIDEO_MODE_PROGRESSIVE;
221
222 if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3)
223 vsync_offset = 6;
224 else
225 vsync_offset = 0;
226
227 value |= vsync_offset << HDMI_VIDEO_VSYNC_OFFSET_SHIFT;
228 hdmi_writeb(hdmi, HDMI_EXT_VIDEO_PARA, value);
229
230 /* Set the details for the external video timing. */
231 value = mode->htotal;
232 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_L, value & 0xFF);
233 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_H, (value >> 8) & 0xFF);
234
235 value = mode->htotal - mode->hdisplay;
236 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_L, value & 0xFF);
237 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_H, (value >> 8) & 0xFF);
238
239 value = mode->htotal - mode->hsync_start;
240 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_L, value & 0xFF);
241 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_H, (value >> 8) & 0xFF);
242
243 value = mode->hsync_end - mode->hsync_start;
244 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_L, value & 0xFF);
245 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_H, (value >> 8) & 0xFF);
246
247 value = mode->vtotal;
248 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_L, value & 0xFF);
249 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_H, (value >> 8) & 0xFF);
250
251 value = mode->vtotal - mode->vdisplay;
252 hdmi_writeb(hdmi, HDMI_EXT_VBLANK_L, value & 0xFF);
253
254 value = mode->vtotal - mode->vsync_start + vsync_offset;
255 hdmi_writeb(hdmi, HDMI_EXT_VDELAY, value & 0xFF);
256
257 value = mode->vsync_end - mode->vsync_start;
258 hdmi_writeb(hdmi, HDMI_EXT_VDURATION, value & 0xFF);
259
260 return 0;
261}
262
263static void
264rk3066_hdmi_phy_write(struct rk3066_hdmi *hdmi, u16 offset, u8 value)
265{
266 hdmi_writeb(hdmi, offset, value);
267 hdmi_modb(hdmi, HDMI_SYS_CTRL,
268 HDMI_SYS_PLL_RESET_MASK, HDMI_SYS_PLL_RESET);
269 usleep_range(90, 100);
270 hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_PLL_RESET_MASK, 0);
271 usleep_range(900, 1000);
272}
273
274static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi)
275{
276 /* TMDS uses the same frequency as dclk. */
277 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x22);
278
279 /*
280 * The semi-public documentation does not describe the hdmi registers
281 * used by the function rk3066_hdmi_phy_write(), so we keep using
282 * these magic values for now.
283 */
284 if (hdmi->tmdsclk > 100000000) {
285 rk3066_hdmi_phy_write(hdmi, 0x158, 0x0E);
286 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
287 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
288 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
289 rk3066_hdmi_phy_write(hdmi, 0x168, 0xDA);
290 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA1);
291 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
292 rk3066_hdmi_phy_write(hdmi, 0x174, 0x22);
293 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
294 } else if (hdmi->tmdsclk > 50000000) {
295 rk3066_hdmi_phy_write(hdmi, 0x158, 0x06);
296 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
297 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
298 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
299 rk3066_hdmi_phy_write(hdmi, 0x168, 0xCA);
300 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA3);
301 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
302 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20);
303 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
304 } else {
305 rk3066_hdmi_phy_write(hdmi, 0x158, 0x02);
306 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
307 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
308 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
309 rk3066_hdmi_phy_write(hdmi, 0x168, 0xC2);
310 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA2);
311 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
312 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20);
313 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
314 }
315}
316
317static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi,
318 struct drm_display_mode *mode)
319{
320 hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
321 hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB;
322
323 if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 ||
324 hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 ||
325 hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 ||
326 hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18)
327 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
328 else
329 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
330
331 hdmi->tmdsclk = mode->clock * 1000;
332
333 /* Mute video and audio output. */
334 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK,
335 HDMI_AUDIO_DISABLE | HDMI_VIDEO_DISABLE);
336
337 /* Set power state to mode B. */
338 if (rk3066_hdmi_get_power_mode(hdmi) != HDMI_SYS_POWER_MODE_B)
339 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
340
341 /* Input video mode is RGB 24 bit. Use external data enable signal. */
342 hdmi_modb(hdmi, HDMI_AV_CTRL1,
343 HDMI_VIDEO_DE_MASK, HDMI_VIDEO_EXTERNAL_DE);
344 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL1,
345 HDMI_VIDEO_OUTPUT_RGB444 |
346 HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT |
347 HDMI_VIDEO_INPUT_COLOR_RGB);
348 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x20);
349
350 rk3066_hdmi_config_video_timing(hdmi, mode);
351
352 if (hdmi->hdmi_data.sink_is_hdmi) {
353 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK,
354 HDMI_VIDEO_MODE_HDMI);
355 rk3066_hdmi_config_avi(hdmi, mode);
356 } else {
357 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0);
358 }
359
360 rk3066_hdmi_config_phy(hdmi);
361
362 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_E);
363
364 /*
365 * When the IP controller is configured with accurate video
366 * timing, the TMDS clock source should be switched to
367 * DCLK_LCDC, so we need to init the TMDS rate to the pixel mode
368 * clock rate and reconfigure the DDC clock.
369 */
370 rk3066_hdmi_i2c_init(hdmi);
371
372 /* Unmute video output. */
373 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
374 HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE);
375 return 0;
376}
377
378static void
379rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder,
380 struct drm_display_mode *mode,
381 struct drm_display_mode *adj_mode)
382{
383 struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
384
385 /* Store the display mode for plugin/DPMS poweron events. */
386 memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode));
387}
388
389static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder)
390{
391 struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
392 int mux, val;
393
394 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
395 if (mux)
396 val = (HDMI_VIDEO_SEL << 16) | HDMI_VIDEO_SEL;
397 else
398 val = HDMI_VIDEO_SEL << 16;
399
400 regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val);
401
402 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder enable select: vop%s\n",
403 (mux) ? "1" : "0");
404
405 rk3066_hdmi_setup(hdmi, &hdmi->previous_mode);
406}
407
408static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder)
409{
410 struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
411
412 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n");
413
414 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) {
415 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL2,
416 HDMI_VIDEO_AUDIO_DISABLE_MASK);
417 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
418 HDMI_AUDIO_CP_LOGIC_RESET_MASK,
419 HDMI_AUDIO_CP_LOGIC_RESET);
420 usleep_range(500, 510);
421 }
422 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A);
423}
424
425static bool
426rk3066_hdmi_encoder_mode_fixup(struct drm_encoder *encoder,
427 const struct drm_display_mode *mode,
428 struct drm_display_mode *adj_mode)
429{
430 return true;
431}
432
433static int
434rk3066_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
435 struct drm_crtc_state *crtc_state,
436 struct drm_connector_state *conn_state)
437{
438 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
439
440 s->output_mode = ROCKCHIP_OUT_MODE_P888;
441 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
442
443 return 0;
444}
445
446static const
447struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = {
448 .enable = rk3066_hdmi_encoder_enable,
449 .disable = rk3066_hdmi_encoder_disable,
450 .mode_fixup = rk3066_hdmi_encoder_mode_fixup,
451 .mode_set = rk3066_hdmi_encoder_mode_set,
452 .atomic_check = rk3066_hdmi_encoder_atomic_check,
453};
454
455static enum drm_connector_status
456rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force)
457{
458 struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
459
460 return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ?
461 connector_status_connected : connector_status_disconnected;
462}
463
464static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector)
465{
466 struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
467 struct edid *edid;
468 int ret = 0;
469
470 if (!hdmi->ddc)
471 return 0;
472
473 edid = drm_get_edid(connector, hdmi->ddc);
474 if (edid) {
475 hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid);
476 drm_connector_update_edid_property(connector, edid);
477 ret = drm_add_edid_modes(connector, edid);
478 kfree(edid);
479 }
480
481 return ret;
482}
483
484static enum drm_mode_status
485rk3066_hdmi_connector_mode_valid(struct drm_connector *connector,
486 struct drm_display_mode *mode)
487{
488 u32 vic = drm_match_cea_mode(mode);
489
490 if (vic > 1)
491 return MODE_OK;
492 else
493 return MODE_BAD;
494}
495
496static struct drm_encoder *
497rk3066_hdmi_connector_best_encoder(struct drm_connector *connector)
498{
499 struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
500
501 return &hdmi->encoder;
502}
503
504static int
505rk3066_hdmi_probe_single_connector_modes(struct drm_connector *connector,
506 uint32_t maxX, uint32_t maxY)
507{
508 if (maxX > 1920)
509 maxX = 1920;
510 if (maxY > 1080)
511 maxY = 1080;
512
513 return drm_helper_probe_single_connector_modes(connector, maxX, maxY);
514}
515
516static void rk3066_hdmi_connector_destroy(struct drm_connector *connector)
517{
518 drm_connector_unregister(connector);
519 drm_connector_cleanup(connector);
520}
521
522static const struct drm_connector_funcs rk3066_hdmi_connector_funcs = {
523 .fill_modes = rk3066_hdmi_probe_single_connector_modes,
524 .detect = rk3066_hdmi_connector_detect,
525 .destroy = rk3066_hdmi_connector_destroy,
526 .reset = drm_atomic_helper_connector_reset,
527 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
528 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
529};
530
531static const
532struct drm_connector_helper_funcs rk3066_hdmi_connector_helper_funcs = {
533 .get_modes = rk3066_hdmi_connector_get_modes,
534 .mode_valid = rk3066_hdmi_connector_mode_valid,
535 .best_encoder = rk3066_hdmi_connector_best_encoder,
536};
537
538static int
539rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi)
540{
541 struct drm_encoder *encoder = &hdmi->encoder;
542 struct device *dev = hdmi->dev;
543
544 encoder->possible_crtcs =
545 drm_of_find_possible_crtcs(drm, dev->of_node);
546
547 /*
548 * If we failed to find the CRTC(s) which this encoder is
549 * supposed to be connected to, it's because the CRTC has
550 * not been registered yet. Defer probing, and hope that
551 * the required CRTC is added later.
552 */
553 if (encoder->possible_crtcs == 0)
554 return -EPROBE_DEFER;
555
556 drm_encoder_helper_add(encoder, &rk3066_hdmi_encoder_helper_funcs);
557 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
558
559 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
560
561 drm_connector_helper_add(&hdmi->connector,
562 &rk3066_hdmi_connector_helper_funcs);
563 drm_connector_init_with_ddc(drm, &hdmi->connector,
564 &rk3066_hdmi_connector_funcs,
565 DRM_MODE_CONNECTOR_HDMIA,
566 hdmi->ddc);
567
568 drm_connector_attach_encoder(&hdmi->connector, encoder);
569
570 return 0;
571}
572
573static irqreturn_t rk3066_hdmi_hardirq(int irq, void *dev_id)
574{
575 struct rk3066_hdmi *hdmi = dev_id;
576 irqreturn_t ret = IRQ_NONE;
577 u8 interrupt;
578
579 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_A)
580 hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_B);
581
582 interrupt = hdmi_readb(hdmi, HDMI_INTR_STATUS1);
583 if (interrupt)
584 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, interrupt);
585
586 if (interrupt & HDMI_INTR_EDID_MASK) {
587 hdmi->i2c->stat = interrupt;
588 complete(&hdmi->i2c->cmpltn);
589 }
590
591 if (interrupt & (HDMI_INTR_HOTPLUG | HDMI_INTR_MSENS))
592 ret = IRQ_WAKE_THREAD;
593
594 return ret;
595}
596
597static irqreturn_t rk3066_hdmi_irq(int irq, void *dev_id)
598{
599 struct rk3066_hdmi *hdmi = dev_id;
600
601 drm_helper_hpd_irq_event(hdmi->connector.dev);
602
603 return IRQ_HANDLED;
604}
605
606static int rk3066_hdmi_i2c_read(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
607{
608 int length = msgs->len;
609 u8 *buf = msgs->buf;
610 int ret;
611
612 ret = wait_for_completion_timeout(&hdmi->i2c->cmpltn, HZ / 10);
613 if (!ret || hdmi->i2c->stat & HDMI_INTR_EDID_ERR)
614 return -EAGAIN;
615
616 while (length--)
617 *buf++ = hdmi_readb(hdmi, HDMI_DDC_READ_FIFO_ADDR);
618
619 return 0;
620}
621
622static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
623{
624 /*
625 * The DDC module only supports read EDID message, so
626 * we assume that each word write to this i2c adapter
627 * should be the offset of the EDID word address.
628 */
629 if (msgs->len != 1 ||
630 (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR))
631 return -EINVAL;
632
633 reinit_completion(&hdmi->i2c->cmpltn);
634
635 if (msgs->addr == DDC_SEGMENT_ADDR)
636 hdmi->i2c->segment_addr = msgs->buf[0];
637 if (msgs->addr == DDC_ADDR)
638 hdmi->i2c->ddc_addr = msgs->buf[0];
639
640 /* Set edid fifo first address. */
641 hdmi_writeb(hdmi, HDMI_EDID_FIFO_ADDR, 0x00);
642
643 /* Set edid word address 0x00/0x80. */
644 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
645
646 /* Set edid segment pointer. */
647 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
648
649 return 0;
650}
651
652static int rk3066_hdmi_i2c_xfer(struct i2c_adapter *adap,
653 struct i2c_msg *msgs, int num)
654{
655 struct rk3066_hdmi *hdmi = i2c_get_adapdata(adap);
656 struct rk3066_hdmi_i2c *i2c = hdmi->i2c;
657 int i, ret = 0;
658
659 mutex_lock(&i2c->i2c_lock);
660
661 rk3066_hdmi_i2c_init(hdmi);
662
663 /* Unmute HDMI EDID interrupt. */
664 hdmi_modb(hdmi, HDMI_INTR_MASK1,
665 HDMI_INTR_EDID_MASK, HDMI_INTR_EDID_MASK);
666 i2c->stat = 0;
667
668 for (i = 0; i < num; i++) {
669 DRM_DEV_DEBUG(hdmi->dev,
670 "xfer: num: %d/%d, len: %d, flags: %#x\n",
671 i + 1, num, msgs[i].len, msgs[i].flags);
672
673 if (msgs[i].flags & I2C_M_RD)
674 ret = rk3066_hdmi_i2c_read(hdmi, &msgs[i]);
675 else
676 ret = rk3066_hdmi_i2c_write(hdmi, &msgs[i]);
677
678 if (ret < 0)
679 break;
680 }
681
682 if (!ret)
683 ret = num;
684
685 /* Mute HDMI EDID interrupt. */
686 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
687
688 mutex_unlock(&i2c->i2c_lock);
689
690 return ret;
691}
692
693static u32 rk3066_hdmi_i2c_func(struct i2c_adapter *adapter)
694{
695 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
696}
697
698static const struct i2c_algorithm rk3066_hdmi_algorithm = {
699 .master_xfer = rk3066_hdmi_i2c_xfer,
700 .functionality = rk3066_hdmi_i2c_func,
701};
702
703static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi)
704{
705 struct i2c_adapter *adap;
706 struct rk3066_hdmi_i2c *i2c;
707 int ret;
708
709 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
710 if (!i2c)
711 return ERR_PTR(-ENOMEM);
712
713 mutex_init(&i2c->i2c_lock);
714 init_completion(&i2c->cmpltn);
715
716 adap = &i2c->adap;
717 adap->class = I2C_CLASS_DDC;
718 adap->owner = THIS_MODULE;
719 adap->dev.parent = hdmi->dev;
720 adap->dev.of_node = hdmi->dev->of_node;
721 adap->algo = &rk3066_hdmi_algorithm;
722 strlcpy(adap->name, "RK3066 HDMI", sizeof(adap->name));
723 i2c_set_adapdata(adap, hdmi);
724
725 ret = i2c_add_adapter(adap);
726 if (ret) {
727 DRM_DEV_ERROR(hdmi->dev, "cannot add %s I2C adapter\n",
728 adap->name);
729 devm_kfree(hdmi->dev, i2c);
730 return ERR_PTR(ret);
731 }
732
733 hdmi->i2c = i2c;
734
735 DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
736
737 return adap;
738}
739
740static int rk3066_hdmi_bind(struct device *dev, struct device *master,
741 void *data)
742{
743 struct platform_device *pdev = to_platform_device(dev);
744 struct drm_device *drm = data;
745 struct rk3066_hdmi *hdmi;
746 int irq;
747 int ret;
748
749 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
750 if (!hdmi)
751 return -ENOMEM;
752
753 hdmi->dev = dev;
754 hdmi->drm_dev = drm;
755 hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
756 if (IS_ERR(hdmi->regs))
757 return PTR_ERR(hdmi->regs);
758
759 irq = platform_get_irq(pdev, 0);
760 if (irq < 0)
761 return irq;
762
763 hdmi->hclk = devm_clk_get(dev, "hclk");
764 if (IS_ERR(hdmi->hclk)) {
765 DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n");
766 return PTR_ERR(hdmi->hclk);
767 }
768
769 ret = clk_prepare_enable(hdmi->hclk);
770 if (ret) {
771 DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret);
772 return ret;
773 }
774
775 hdmi->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
776 "rockchip,grf");
777 if (IS_ERR(hdmi->grf_regmap)) {
778 DRM_DEV_ERROR(dev, "unable to get rockchip,grf\n");
779 ret = PTR_ERR(hdmi->grf_regmap);
780 goto err_disable_hclk;
781 }
782
783 /* internal hclk = hdmi_hclk / 25 */
784 hdmi_writeb(hdmi, HDMI_INTERNAL_CLK_DIVIDER, 25);
785
786 hdmi->ddc = rk3066_hdmi_i2c_adapter(hdmi);
787 if (IS_ERR(hdmi->ddc)) {
788 ret = PTR_ERR(hdmi->ddc);
789 hdmi->ddc = NULL;
790 goto err_disable_hclk;
791 }
792
793 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
794 usleep_range(999, 1000);
795 hdmi_writeb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_HOTPLUG);
796 hdmi_writeb(hdmi, HDMI_INTR_MASK2, 0);
797 hdmi_writeb(hdmi, HDMI_INTR_MASK3, 0);
798 hdmi_writeb(hdmi, HDMI_INTR_MASK4, 0);
799 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A);
800
801 ret = rk3066_hdmi_register(drm, hdmi);
802 if (ret)
803 goto err_disable_i2c;
804
805 dev_set_drvdata(dev, hdmi);
806
807 ret = devm_request_threaded_irq(dev, irq, rk3066_hdmi_hardirq,
808 rk3066_hdmi_irq, IRQF_SHARED,
809 dev_name(dev), hdmi);
810 if (ret) {
811 DRM_DEV_ERROR(dev, "failed to request hdmi irq: %d\n", ret);
812 goto err_cleanup_hdmi;
813 }
814
815 return 0;
816
817err_cleanup_hdmi:
818 hdmi->connector.funcs->destroy(&hdmi->connector);
819 hdmi->encoder.funcs->destroy(&hdmi->encoder);
820err_disable_i2c:
821 i2c_put_adapter(hdmi->ddc);
822err_disable_hclk:
823 clk_disable_unprepare(hdmi->hclk);
824
825 return ret;
826}
827
828static void rk3066_hdmi_unbind(struct device *dev, struct device *master,
829 void *data)
830{
831 struct rk3066_hdmi *hdmi = dev_get_drvdata(dev);
832
833 hdmi->connector.funcs->destroy(&hdmi->connector);
834 hdmi->encoder.funcs->destroy(&hdmi->encoder);
835
836 i2c_put_adapter(hdmi->ddc);
837 clk_disable_unprepare(hdmi->hclk);
838}
839
840static const struct component_ops rk3066_hdmi_ops = {
841 .bind = rk3066_hdmi_bind,
842 .unbind = rk3066_hdmi_unbind,
843};
844
845static int rk3066_hdmi_probe(struct platform_device *pdev)
846{
847 return component_add(&pdev->dev, &rk3066_hdmi_ops);
848}
849
850static int rk3066_hdmi_remove(struct platform_device *pdev)
851{
852 component_del(&pdev->dev, &rk3066_hdmi_ops);
853
854 return 0;
855}
856
857static const struct of_device_id rk3066_hdmi_dt_ids[] = {
858 { .compatible = "rockchip,rk3066-hdmi" },
859 { /* sentinel */ },
860};
861MODULE_DEVICE_TABLE(of, rk3066_hdmi_dt_ids);
862
863struct platform_driver rk3066_hdmi_driver = {
864 .probe = rk3066_hdmi_probe,
865 .remove = rk3066_hdmi_remove,
866 .driver = {
867 .name = "rockchip-rk3066-hdmi",
868 .of_match_table = rk3066_hdmi_dt_ids,
869 },
870};