1/*
  2 * Copyright 2008 Advanced Micro Devices, Inc.
  3 * Copyright 2008 Red Hat Inc.
  4 * Copyright 2009 Jerome Glisse.
  5 *
  6 * Permission is hereby granted, free of charge, to any person obtaining a
  7 * copy of this software and associated documentation files (the "Software"),
  8 * to deal in the Software without restriction, including without limitation
  9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 10 * and/or sell copies of the Software, and to permit persons to whom the
 11 * Software is furnished to do so, subject to the following conditions:
 12 *
 13 * The above copyright notice and this permission notice shall be included in
 14 * all copies or substantial portions of the Software.
 15 *
 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 22 * OTHER DEALINGS IN THE SOFTWARE.
 23 *
 24 * Authors: Dave Airlie
 25 *          Alex Deucher
 26 *          Jerome Glisse
 27 *          Christian König
 28 */
 29
 30#include <linux/debugfs.h>
 31
 32#include <drm/drm_device.h>
 33#include <drm/drm_file.h>
 34
 35#include "radeon.h"
 36
 37/*
 38 * Rings
 39 * Most engines on the GPU are fed via ring buffers.  Ring
 40 * buffers are areas of GPU accessible memory that the host
 41 * writes commands into and the GPU reads commands out of.
 42 * There is a rptr (read pointer) that determines where the
 43 * GPU is currently reading, and a wptr (write pointer)
 44 * which determines where the host has written.  When the
 45 * pointers are equal, the ring is idle.  When the host
 46 * writes commands to the ring buffer, it increments the
 47 * wptr.  The GPU then starts fetching commands and executes
 48 * them until the pointers are equal again.
 49 */
 50static void radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
 51
 52/**
 53 * radeon_ring_supports_scratch_reg - check if the ring supports
 54 * writing to scratch registers
 55 *
 56 * @rdev: radeon_device pointer
 57 * @ring: radeon_ring structure holding ring information
 58 *
 59 * Check if a specific ring supports writing to scratch registers (all asics).
 60 * Returns true if the ring supports writing to scratch regs, false if not.
 61 */
 62bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
 63				      struct radeon_ring *ring)
 64{
 65	switch (ring->idx) {
 66	case RADEON_RING_TYPE_GFX_INDEX:
 67	case CAYMAN_RING_TYPE_CP1_INDEX:
 68	case CAYMAN_RING_TYPE_CP2_INDEX:
 69		return true;
 70	default:
 71		return false;
 72	}
 73}
 74
 75/**
 76 * radeon_ring_free_size - update the free size
 77 *
 78 * @rdev: radeon_device pointer
 79 * @ring: radeon_ring structure holding ring information
 80 *
 81 * Update the free dw slots in the ring buffer (all asics).
 82 */
 83void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
 84{
 85	uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
 86
 87	/* This works because ring_size is a power of 2 */
 88	ring->ring_free_dw = rptr + (ring->ring_size / 4);
 89	ring->ring_free_dw -= ring->wptr;
 90	ring->ring_free_dw &= ring->ptr_mask;
 91	if (!ring->ring_free_dw) {
 92		/* this is an empty ring */
 93		ring->ring_free_dw = ring->ring_size / 4;
 94		/*  update lockup info to avoid false positive */
 95		radeon_ring_lockup_update(rdev, ring);
 96	}
 97}
 98
 99/**
100 * radeon_ring_alloc - allocate space on the ring buffer
101 *
102 * @rdev: radeon_device pointer
103 * @ring: radeon_ring structure holding ring information
104 * @ndw: number of dwords to allocate in the ring buffer
105 *
106 * Allocate @ndw dwords in the ring buffer (all asics).
107 * Returns 0 on success, error on failure.
108 */
109int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
110{
111	int r;
112
113	/* make sure we aren't trying to allocate more space than there is on the ring */
114	if (ndw > (ring->ring_size / 4))
115		return -ENOMEM;
116	/* Align requested size with padding so unlock_commit can
117	 * pad safely */
118	radeon_ring_free_size(rdev, ring);
119	ndw = (ndw + ring->align_mask) & ~ring->align_mask;
120	while (ndw > (ring->ring_free_dw - 1)) {
121		radeon_ring_free_size(rdev, ring);
122		if (ndw < ring->ring_free_dw) {
123			break;
124		}
125		r = radeon_fence_wait_next(rdev, ring->idx);
126		if (r)
127			return r;
128	}
129	ring->count_dw = ndw;
130	ring->wptr_old = ring->wptr;
131	return 0;
132}
133
134/**
135 * radeon_ring_lock - lock the ring and allocate space on it
136 *
137 * @rdev: radeon_device pointer
138 * @ring: radeon_ring structure holding ring information
139 * @ndw: number of dwords to allocate in the ring buffer
140 *
141 * Lock the ring and allocate @ndw dwords in the ring buffer
142 * (all asics).
143 * Returns 0 on success, error on failure.
144 */
145int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
146{
147	int r;
148
149	mutex_lock(&rdev->ring_lock);
150	r = radeon_ring_alloc(rdev, ring, ndw);
151	if (r) {
152		mutex_unlock(&rdev->ring_lock);
153		return r;
154	}
155	return 0;
156}
157
158/**
159 * radeon_ring_commit - tell the GPU to execute the new
160 * commands on the ring buffer
161 *
162 * @rdev: radeon_device pointer
163 * @ring: radeon_ring structure holding ring information
164 * @hdp_flush: Whether or not to perform an HDP cache flush
165 *
166 * Update the wptr (write pointer) to tell the GPU to
167 * execute new commands on the ring buffer (all asics).
168 */
169void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring,
170			bool hdp_flush)
171{
172	/* If we are emitting the HDP flush via the ring buffer, we need to
173	 * do it before padding.
174	 */
175	if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush)
176		rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring);
177	/* We pad to match fetch size */
178	while (ring->wptr & ring->align_mask) {
179		radeon_ring_write(ring, ring->nop);
180	}
181	mb();
182	/* If we are emitting the HDP flush via MMIO, we need to do it after
183	 * all CPU writes to VRAM finished.
184	 */
185	if (hdp_flush && rdev->asic->mmio_hdp_flush)
186		rdev->asic->mmio_hdp_flush(rdev);
187	radeon_ring_set_wptr(rdev, ring);
188}
189
190/**
191 * radeon_ring_unlock_commit - tell the GPU to execute the new
192 * commands on the ring buffer and unlock it
193 *
194 * @rdev: radeon_device pointer
195 * @ring: radeon_ring structure holding ring information
196 * @hdp_flush: Whether or not to perform an HDP cache flush
197 *
198 * Call radeon_ring_commit() then unlock the ring (all asics).
199 */
200void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring,
201			       bool hdp_flush)
202{
203	radeon_ring_commit(rdev, ring, hdp_flush);
204	mutex_unlock(&rdev->ring_lock);
205}
206
207/**
208 * radeon_ring_undo - reset the wptr
209 *
210 * @ring: radeon_ring structure holding ring information
211 *
212 * Reset the driver's copy of the wptr (all asics).
213 */
214void radeon_ring_undo(struct radeon_ring *ring)
215{
216	ring->wptr = ring->wptr_old;
217}
218
219/**
220 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
221 *
222 * @rdev:       radeon device structure
223 * @ring: radeon_ring structure holding ring information
224 *
225 * Call radeon_ring_undo() then unlock the ring (all asics).
226 */
227void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
228{
229	radeon_ring_undo(ring);
230	mutex_unlock(&rdev->ring_lock);
231}
232
233/**
234 * radeon_ring_lockup_update - update lockup variables
235 *
236 * @rdev:       radeon device structure
237 * @ring: radeon_ring structure holding ring information
238 *
239 * Update the last rptr value and timestamp (all asics).
240 */
241void radeon_ring_lockup_update(struct radeon_device *rdev,
242			       struct radeon_ring *ring)
243{
244	atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring));
245	atomic64_set(&ring->last_activity, jiffies_64);
246}
247
248/**
249 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
250 * @rdev:       radeon device structure
251 * @ring:       radeon_ring structure holding ring information
252 *
253 */
254bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
255{
256	uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
257	uint64_t last = atomic64_read(&ring->last_activity);
258	uint64_t elapsed;
259
260	if (rptr != atomic_read(&ring->last_rptr)) {
261		/* ring is still working, no lockup */
262		radeon_ring_lockup_update(rdev, ring);
263		return false;
264	}
265
266	elapsed = jiffies_to_msecs(jiffies_64 - last);
267	if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
268		dev_err(rdev->dev, "ring %d stalled for more than %llumsec\n",
269			ring->idx, elapsed);
270		return true;
271	}
272	/* give a chance to the GPU ... */
273	return false;
274}
275
276/**
277 * radeon_ring_backup - Back up the content of a ring
278 *
279 * @rdev: radeon_device pointer
280 * @ring: the ring we want to back up
281 * @data: placeholder for returned commit data
282 *
283 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
284 */
285unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
286			    uint32_t **data)
287{
288	unsigned size, ptr, i;
289
290	/* just in case lock the ring */
291	mutex_lock(&rdev->ring_lock);
292	*data = NULL;
293
294	if (ring->ring_obj == NULL) {
295		mutex_unlock(&rdev->ring_lock);
296		return 0;
297	}
298
299	/* it doesn't make sense to save anything if all fences are signaled */
300	if (!radeon_fence_count_emitted(rdev, ring->idx)) {
301		mutex_unlock(&rdev->ring_lock);
302		return 0;
303	}
304
305	/* calculate the number of dw on the ring */
306	if (ring->rptr_save_reg)
307		ptr = RREG32(ring->rptr_save_reg);
308	else if (rdev->wb.enabled)
309		ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
310	else {
311		/* no way to read back the next rptr */
312		mutex_unlock(&rdev->ring_lock);
313		return 0;
314	}
315
316	size = ring->wptr + (ring->ring_size / 4);
317	size -= ptr;
318	size &= ring->ptr_mask;
319	if (size == 0) {
320		mutex_unlock(&rdev->ring_lock);
321		return 0;
322	}
323
324	/* and then save the content of the ring */
325	*data = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
326	if (!*data) {
327		mutex_unlock(&rdev->ring_lock);
328		return 0;
329	}
330	for (i = 0; i < size; ++i) {
331		(*data)[i] = ring->ring[ptr++];
332		ptr &= ring->ptr_mask;
333	}
334
335	mutex_unlock(&rdev->ring_lock);
336	return size;
337}
338
339/**
340 * radeon_ring_restore - append saved commands to the ring again
341 *
342 * @rdev: radeon_device pointer
343 * @ring: ring to append commands to
344 * @size: number of dwords we want to write
345 * @data: saved commands
346 *
347 * Allocates space on the ring and restore the previously saved commands.
348 */
349int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
350			unsigned size, uint32_t *data)
351{
352	int i, r;
353
354	if (!size || !data)
355		return 0;
356
357	/* restore the saved ring content */
358	r = radeon_ring_lock(rdev, ring, size);
359	if (r)
360		return r;
361
362	for (i = 0; i < size; ++i) {
363		radeon_ring_write(ring, data[i]);
364	}
365
366	radeon_ring_unlock_commit(rdev, ring, false);
367	kvfree(data);
368	return 0;
369}
370
371/**
372 * radeon_ring_init - init driver ring struct.
373 *
374 * @rdev: radeon_device pointer
375 * @ring: radeon_ring structure holding ring information
376 * @ring_size: size of the ring
377 * @rptr_offs: offset of the rptr writeback location in the WB buffer
378 * @nop: nop packet for this ring
379 *
380 * Initialize the driver information for the selected ring (all asics).
381 * Returns 0 on success, error on failure.
382 */
383int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
384		     unsigned rptr_offs, u32 nop)
385{
386	int r;
387
388	ring->ring_size = ring_size;
389	ring->rptr_offs = rptr_offs;
390	ring->nop = nop;
391	ring->rdev = rdev;
392	/* Allocate ring buffer */
393	if (ring->ring_obj == NULL) {
394		r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
395				     RADEON_GEM_DOMAIN_GTT, 0, NULL,
396				     NULL, &ring->ring_obj);
397		if (r) {
398			dev_err(rdev->dev, "(%d) ring create failed\n", r);
399			return r;
400		}
401		r = radeon_bo_reserve(ring->ring_obj, false);
402		if (unlikely(r != 0))
403			return r;
404		r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
405					&ring->gpu_addr);
406		if (r) {
407			radeon_bo_unreserve(ring->ring_obj);
408			dev_err(rdev->dev, "(%d) ring pin failed\n", r);
409			return r;
410		}
411		r = radeon_bo_kmap(ring->ring_obj,
412				       (void **)&ring->ring);
413		radeon_bo_unreserve(ring->ring_obj);
414		if (r) {
415			dev_err(rdev->dev, "(%d) ring map failed\n", r);
416			return r;
417		}
418		radeon_debugfs_ring_init(rdev, ring);
419	}
420	ring->ptr_mask = (ring->ring_size / 4) - 1;
421	ring->ring_free_dw = ring->ring_size / 4;
422	if (rdev->wb.enabled) {
423		u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
424		ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
425		ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
426	}
 
 
 
427	radeon_ring_lockup_update(rdev, ring);
428	return 0;
429}
430
431/**
432 * radeon_ring_fini - tear down the driver ring struct.
433 *
434 * @rdev: radeon_device pointer
435 * @ring: radeon_ring structure holding ring information
436 *
437 * Tear down the driver information for the selected ring (all asics).
438 */
439void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
440{
441	int r;
442	struct radeon_bo *ring_obj;
443
444	mutex_lock(&rdev->ring_lock);
445	ring_obj = ring->ring_obj;
446	ring->ready = false;
447	ring->ring = NULL;
448	ring->ring_obj = NULL;
449	mutex_unlock(&rdev->ring_lock);
450
451	if (ring_obj) {
452		r = radeon_bo_reserve(ring_obj, false);
453		if (likely(r == 0)) {
454			radeon_bo_kunmap(ring_obj);
455			radeon_bo_unpin(ring_obj);
456			radeon_bo_unreserve(ring_obj);
457		}
458		radeon_bo_unref(&ring_obj);
459	}
460}
461
462/*
463 * Debugfs info
464 */
465#if defined(CONFIG_DEBUG_FS)
466
467static int radeon_debugfs_ring_info_show(struct seq_file *m, void *unused)
468{
469	struct radeon_ring *ring = m->private;
470	struct radeon_device *rdev = ring->rdev;
 
 
 
471
472	uint32_t rptr, wptr, rptr_next;
473	unsigned count, i, j;
474
475	radeon_ring_free_size(rdev, ring);
476	count = (ring->ring_size / 4) - ring->ring_free_dw;
477
478	wptr = radeon_ring_get_wptr(rdev, ring);
479	seq_printf(m, "wptr: 0x%08x [%5d]\n",
480		   wptr, wptr);
481
482	rptr = radeon_ring_get_rptr(rdev, ring);
483	seq_printf(m, "rptr: 0x%08x [%5d]\n",
484		   rptr, rptr);
485
486	if (ring->rptr_save_reg) {
487		rptr_next = RREG32(ring->rptr_save_reg);
488		seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n",
489			   ring->rptr_save_reg, rptr_next, rptr_next);
490	} else
491		rptr_next = ~0;
492
493	seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
494		   ring->wptr, ring->wptr);
495	seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
496		   ring->last_semaphore_signal_addr);
497	seq_printf(m, "last semaphore wait addr   : 0x%016llx\n",
498		   ring->last_semaphore_wait_addr);
499	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
500	seq_printf(m, "%u dwords in ring\n", count);
501
502	if (!ring->ring)
503		return 0;
504
505	/* print 8 dw before current rptr as often it's the last executed
506	 * packet that is the root issue
507	 */
508	i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
509	for (j = 0; j <= (count + 32); j++) {
510		seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
511		if (rptr == i)
512			seq_puts(m, " *");
513		if (rptr_next == i)
514			seq_puts(m, " #");
515		seq_puts(m, "\n");
516		i = (i + 1) & ring->ptr_mask;
517	}
518	return 0;
519}
520
521DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_ring_info);
522
523static const char *radeon_debugfs_ring_idx_to_name(uint32_t ridx)
524{
525	switch (ridx) {
526	case RADEON_RING_TYPE_GFX_INDEX:
527		return "radeon_ring_gfx";
528	case CAYMAN_RING_TYPE_CP1_INDEX:
529		return "radeon_ring_cp1";
530	case CAYMAN_RING_TYPE_CP2_INDEX:
531		return "radeon_ring_cp2";
532	case R600_RING_TYPE_DMA_INDEX:
533		return "radeon_ring_dma1";
534	case CAYMAN_RING_TYPE_DMA1_INDEX:
535		return "radeon_ring_dma2";
536	case R600_RING_TYPE_UVD_INDEX:
537		return "radeon_ring_uvd";
538	case TN_RING_TYPE_VCE1_INDEX:
539		return "radeon_ring_vce1";
540	case TN_RING_TYPE_VCE2_INDEX:
541		return "radeon_ring_vce2";
542	default:
543		return NULL;
544
545	}
546}
547#endif
548
549static void radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
550{
551#if defined(CONFIG_DEBUG_FS)
552	const char *ring_name = radeon_debugfs_ring_idx_to_name(ring->idx);
553	struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root;
 
 
 
554
555	if (ring_name)
556		debugfs_create_file(ring_name, 0444, root, ring,
557				    &radeon_debugfs_ring_info_fops);
558
 
 
 
 
559#endif
 
560}

  1/*
  2 * Copyright 2008 Advanced Micro Devices, Inc.
  3 * Copyright 2008 Red Hat Inc.
  4 * Copyright 2009 Jerome Glisse.
  5 *
  6 * Permission is hereby granted, free of charge, to any person obtaining a
  7 * copy of this software and associated documentation files (the "Software"),
  8 * to deal in the Software without restriction, including without limitation
  9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 10 * and/or sell copies of the Software, and to permit persons to whom the
 11 * Software is furnished to do so, subject to the following conditions:
 12 *
 13 * The above copyright notice and this permission notice shall be included in
 14 * all copies or substantial portions of the Software.
 15 *
 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 22 * OTHER DEALINGS IN THE SOFTWARE.
 23 *
 24 * Authors: Dave Airlie
 25 *          Alex Deucher
 26 *          Jerome Glisse
 27 *          Christian König
 28 */
 29
 30#include <drm/drm_debugfs.h>
 
 31#include <drm/drm_device.h>
 32#include <drm/drm_file.h>
 33
 34#include "radeon.h"
 35
 36/*
 37 * Rings
 38 * Most engines on the GPU are fed via ring buffers.  Ring
 39 * buffers are areas of GPU accessible memory that the host
 40 * writes commands into and the GPU reads commands out of.
 41 * There is a rptr (read pointer) that determines where the
 42 * GPU is currently reading, and a wptr (write pointer)
 43 * which determines where the host has written.  When the
 44 * pointers are equal, the ring is idle.  When the host
 45 * writes commands to the ring buffer, it increments the
 46 * wptr.  The GPU then starts fetching commands and executes
 47 * them until the pointers are equal again.
 48 */
 49static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
 50
 51/**
 52 * radeon_ring_supports_scratch_reg - check if the ring supports
 53 * writing to scratch registers
 54 *
 55 * @rdev: radeon_device pointer
 56 * @ring: radeon_ring structure holding ring information
 57 *
 58 * Check if a specific ring supports writing to scratch registers (all asics).
 59 * Returns true if the ring supports writing to scratch regs, false if not.
 60 */
 61bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
 62				      struct radeon_ring *ring)
 63{
 64	switch (ring->idx) {
 65	case RADEON_RING_TYPE_GFX_INDEX:
 66	case CAYMAN_RING_TYPE_CP1_INDEX:
 67	case CAYMAN_RING_TYPE_CP2_INDEX:
 68		return true;
 69	default:
 70		return false;
 71	}
 72}
 73
 74/**
 75 * radeon_ring_free_size - update the free size
 76 *
 77 * @rdev: radeon_device pointer
 78 * @ring: radeon_ring structure holding ring information
 79 *
 80 * Update the free dw slots in the ring buffer (all asics).
 81 */
 82void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
 83{
 84	uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
 85
 86	/* This works because ring_size is a power of 2 */
 87	ring->ring_free_dw = rptr + (ring->ring_size / 4);
 88	ring->ring_free_dw -= ring->wptr;
 89	ring->ring_free_dw &= ring->ptr_mask;
 90	if (!ring->ring_free_dw) {
 91		/* this is an empty ring */
 92		ring->ring_free_dw = ring->ring_size / 4;
 93		/*  update lockup info to avoid false positive */
 94		radeon_ring_lockup_update(rdev, ring);
 95	}
 96}
 97
 98/**
 99 * radeon_ring_alloc - allocate space on the ring buffer
100 *
101 * @rdev: radeon_device pointer
102 * @ring: radeon_ring structure holding ring information
103 * @ndw: number of dwords to allocate in the ring buffer
104 *
105 * Allocate @ndw dwords in the ring buffer (all asics).
106 * Returns 0 on success, error on failure.
107 */
108int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
109{
110	int r;
111
112	/* make sure we aren't trying to allocate more space than there is on the ring */
113	if (ndw > (ring->ring_size / 4))
114		return -ENOMEM;
115	/* Align requested size with padding so unlock_commit can
116	 * pad safely */
117	radeon_ring_free_size(rdev, ring);
118	ndw = (ndw + ring->align_mask) & ~ring->align_mask;
119	while (ndw > (ring->ring_free_dw - 1)) {
120		radeon_ring_free_size(rdev, ring);
121		if (ndw < ring->ring_free_dw) {
122			break;
123		}
124		r = radeon_fence_wait_next(rdev, ring->idx);
125		if (r)
126			return r;
127	}
128	ring->count_dw = ndw;
129	ring->wptr_old = ring->wptr;
130	return 0;
131}
132
133/**
134 * radeon_ring_lock - lock the ring and allocate space on it
135 *
136 * @rdev: radeon_device pointer
137 * @ring: radeon_ring structure holding ring information
138 * @ndw: number of dwords to allocate in the ring buffer
139 *
140 * Lock the ring and allocate @ndw dwords in the ring buffer
141 * (all asics).
142 * Returns 0 on success, error on failure.
143 */
144int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
145{
146	int r;
147
148	mutex_lock(&rdev->ring_lock);
149	r = radeon_ring_alloc(rdev, ring, ndw);
150	if (r) {
151		mutex_unlock(&rdev->ring_lock);
152		return r;
153	}
154	return 0;
155}
156
157/**
158 * radeon_ring_commit - tell the GPU to execute the new
159 * commands on the ring buffer
160 *
161 * @rdev: radeon_device pointer
162 * @ring: radeon_ring structure holding ring information
163 * @hdp_flush: Whether or not to perform an HDP cache flush
164 *
165 * Update the wptr (write pointer) to tell the GPU to
166 * execute new commands on the ring buffer (all asics).
167 */
168void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring,
169			bool hdp_flush)
170{
171	/* If we are emitting the HDP flush via the ring buffer, we need to
172	 * do it before padding.
173	 */
174	if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush)
175		rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring);
176	/* We pad to match fetch size */
177	while (ring->wptr & ring->align_mask) {
178		radeon_ring_write(ring, ring->nop);
179	}
180	mb();
181	/* If we are emitting the HDP flush via MMIO, we need to do it after
182	 * all CPU writes to VRAM finished.
183	 */
184	if (hdp_flush && rdev->asic->mmio_hdp_flush)
185		rdev->asic->mmio_hdp_flush(rdev);
186	radeon_ring_set_wptr(rdev, ring);
187}
188
189/**
190 * radeon_ring_unlock_commit - tell the GPU to execute the new
191 * commands on the ring buffer and unlock it
192 *
193 * @rdev: radeon_device pointer
194 * @ring: radeon_ring structure holding ring information
195 * @hdp_flush: Whether or not to perform an HDP cache flush
196 *
197 * Call radeon_ring_commit() then unlock the ring (all asics).
198 */
199void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring,
200			       bool hdp_flush)
201{
202	radeon_ring_commit(rdev, ring, hdp_flush);
203	mutex_unlock(&rdev->ring_lock);
204}
205
206/**
207 * radeon_ring_undo - reset the wptr
208 *
209 * @ring: radeon_ring structure holding ring information
210 *
211 * Reset the driver's copy of the wptr (all asics).
212 */
213void radeon_ring_undo(struct radeon_ring *ring)
214{
215	ring->wptr = ring->wptr_old;
216}
217
218/**
219 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
220 *
 
221 * @ring: radeon_ring structure holding ring information
222 *
223 * Call radeon_ring_undo() then unlock the ring (all asics).
224 */
225void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
226{
227	radeon_ring_undo(ring);
228	mutex_unlock(&rdev->ring_lock);
229}
230
231/**
232 * radeon_ring_lockup_update - update lockup variables
233 *
 
234 * @ring: radeon_ring structure holding ring information
235 *
236 * Update the last rptr value and timestamp (all asics).
237 */
238void radeon_ring_lockup_update(struct radeon_device *rdev,
239			       struct radeon_ring *ring)
240{
241	atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring));
242	atomic64_set(&ring->last_activity, jiffies_64);
243}
244
245/**
246 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
247 * @rdev:       radeon device structure
248 * @ring:       radeon_ring structure holding ring information
249 *
250 */
251bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
252{
253	uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
254	uint64_t last = atomic64_read(&ring->last_activity);
255	uint64_t elapsed;
256
257	if (rptr != atomic_read(&ring->last_rptr)) {
258		/* ring is still working, no lockup */
259		radeon_ring_lockup_update(rdev, ring);
260		return false;
261	}
262
263	elapsed = jiffies_to_msecs(jiffies_64 - last);
264	if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
265		dev_err(rdev->dev, "ring %d stalled for more than %llumsec\n",
266			ring->idx, elapsed);
267		return true;
268	}
269	/* give a chance to the GPU ... */
270	return false;
271}
272
273/**
274 * radeon_ring_backup - Back up the content of a ring
275 *
276 * @rdev: radeon_device pointer
277 * @ring: the ring we want to back up
 
278 *
279 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
280 */
281unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
282			    uint32_t **data)
283{
284	unsigned size, ptr, i;
285
286	/* just in case lock the ring */
287	mutex_lock(&rdev->ring_lock);
288	*data = NULL;
289
290	if (ring->ring_obj == NULL) {
291		mutex_unlock(&rdev->ring_lock);
292		return 0;
293	}
294
295	/* it doesn't make sense to save anything if all fences are signaled */
296	if (!radeon_fence_count_emitted(rdev, ring->idx)) {
297		mutex_unlock(&rdev->ring_lock);
298		return 0;
299	}
300
301	/* calculate the number of dw on the ring */
302	if (ring->rptr_save_reg)
303		ptr = RREG32(ring->rptr_save_reg);
304	else if (rdev->wb.enabled)
305		ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
306	else {
307		/* no way to read back the next rptr */
308		mutex_unlock(&rdev->ring_lock);
309		return 0;
310	}
311
312	size = ring->wptr + (ring->ring_size / 4);
313	size -= ptr;
314	size &= ring->ptr_mask;
315	if (size == 0) {
316		mutex_unlock(&rdev->ring_lock);
317		return 0;
318	}
319
320	/* and then save the content of the ring */
321	*data = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
322	if (!*data) {
323		mutex_unlock(&rdev->ring_lock);
324		return 0;
325	}
326	for (i = 0; i < size; ++i) {
327		(*data)[i] = ring->ring[ptr++];
328		ptr &= ring->ptr_mask;
329	}
330
331	mutex_unlock(&rdev->ring_lock);
332	return size;
333}
334
335/**
336 * radeon_ring_restore - append saved commands to the ring again
337 *
338 * @rdev: radeon_device pointer
339 * @ring: ring to append commands to
340 * @size: number of dwords we want to write
341 * @data: saved commands
342 *
343 * Allocates space on the ring and restore the previously saved commands.
344 */
345int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
346			unsigned size, uint32_t *data)
347{
348	int i, r;
349
350	if (!size || !data)
351		return 0;
352
353	/* restore the saved ring content */
354	r = radeon_ring_lock(rdev, ring, size);
355	if (r)
356		return r;
357
358	for (i = 0; i < size; ++i) {
359		radeon_ring_write(ring, data[i]);
360	}
361
362	radeon_ring_unlock_commit(rdev, ring, false);
363	kvfree(data);
364	return 0;
365}
366
367/**
368 * radeon_ring_init - init driver ring struct.
369 *
370 * @rdev: radeon_device pointer
371 * @ring: radeon_ring structure holding ring information
372 * @ring_size: size of the ring
373 * @rptr_offs: offset of the rptr writeback location in the WB buffer
374 * @nop: nop packet for this ring
375 *
376 * Initialize the driver information for the selected ring (all asics).
377 * Returns 0 on success, error on failure.
378 */
379int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
380		     unsigned rptr_offs, u32 nop)
381{
382	int r;
383
384	ring->ring_size = ring_size;
385	ring->rptr_offs = rptr_offs;
386	ring->nop = nop;
 
387	/* Allocate ring buffer */
388	if (ring->ring_obj == NULL) {
389		r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
390				     RADEON_GEM_DOMAIN_GTT, 0, NULL,
391				     NULL, &ring->ring_obj);
392		if (r) {
393			dev_err(rdev->dev, "(%d) ring create failed\n", r);
394			return r;
395		}
396		r = radeon_bo_reserve(ring->ring_obj, false);
397		if (unlikely(r != 0))
398			return r;
399		r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
400					&ring->gpu_addr);
401		if (r) {
402			radeon_bo_unreserve(ring->ring_obj);
403			dev_err(rdev->dev, "(%d) ring pin failed\n", r);
404			return r;
405		}
406		r = radeon_bo_kmap(ring->ring_obj,
407				       (void **)&ring->ring);
408		radeon_bo_unreserve(ring->ring_obj);
409		if (r) {
410			dev_err(rdev->dev, "(%d) ring map failed\n", r);
411			return r;
412		}
 
413	}
414	ring->ptr_mask = (ring->ring_size / 4) - 1;
415	ring->ring_free_dw = ring->ring_size / 4;
416	if (rdev->wb.enabled) {
417		u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
418		ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
419		ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
420	}
421	if (radeon_debugfs_ring_init(rdev, ring)) {
422		DRM_ERROR("Failed to register debugfs file for rings !\n");
423	}
424	radeon_ring_lockup_update(rdev, ring);
425	return 0;
426}
427
428/**
429 * radeon_ring_fini - tear down the driver ring struct.
430 *
431 * @rdev: radeon_device pointer
432 * @ring: radeon_ring structure holding ring information
433 *
434 * Tear down the driver information for the selected ring (all asics).
435 */
436void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
437{
438	int r;
439	struct radeon_bo *ring_obj;
440
441	mutex_lock(&rdev->ring_lock);
442	ring_obj = ring->ring_obj;
443	ring->ready = false;
444	ring->ring = NULL;
445	ring->ring_obj = NULL;
446	mutex_unlock(&rdev->ring_lock);
447
448	if (ring_obj) {
449		r = radeon_bo_reserve(ring_obj, false);
450		if (likely(r == 0)) {
451			radeon_bo_kunmap(ring_obj);
452			radeon_bo_unpin(ring_obj);
453			radeon_bo_unreserve(ring_obj);
454		}
455		radeon_bo_unref(&ring_obj);
456	}
457}
458
459/*
460 * Debugfs info
461 */
462#if defined(CONFIG_DEBUG_FS)
463
464static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
465{
466	struct drm_info_node *node = (struct drm_info_node *) m->private;
467	struct drm_device *dev = node->minor->dev;
468	struct radeon_device *rdev = dev->dev_private;
469	int ridx = *(int*)node->info_ent->data;
470	struct radeon_ring *ring = &rdev->ring[ridx];
471
472	uint32_t rptr, wptr, rptr_next;
473	unsigned count, i, j;
474
475	radeon_ring_free_size(rdev, ring);
476	count = (ring->ring_size / 4) - ring->ring_free_dw;
477
478	wptr = radeon_ring_get_wptr(rdev, ring);
479	seq_printf(m, "wptr: 0x%08x [%5d]\n",
480		   wptr, wptr);
481
482	rptr = radeon_ring_get_rptr(rdev, ring);
483	seq_printf(m, "rptr: 0x%08x [%5d]\n",
484		   rptr, rptr);
485
486	if (ring->rptr_save_reg) {
487		rptr_next = RREG32(ring->rptr_save_reg);
488		seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n",
489			   ring->rptr_save_reg, rptr_next, rptr_next);
490	} else
491		rptr_next = ~0;
492
493	seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
494		   ring->wptr, ring->wptr);
495	seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
496		   ring->last_semaphore_signal_addr);
497	seq_printf(m, "last semaphore wait addr   : 0x%016llx\n",
498		   ring->last_semaphore_wait_addr);
499	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
500	seq_printf(m, "%u dwords in ring\n", count);
501
502	if (!ring->ring)
503		return 0;
504
505	/* print 8 dw before current rptr as often it's the last executed
506	 * packet that is the root issue
507	 */
508	i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
509	for (j = 0; j <= (count + 32); j++) {
510		seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
511		if (rptr == i)
512			seq_puts(m, " *");
513		if (rptr_next == i)
514			seq_puts(m, " #");
515		seq_puts(m, "\n");
516		i = (i + 1) & ring->ptr_mask;
517	}
518	return 0;
519}
520
521static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
522static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
523static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
524static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
525static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
526static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
527static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX;
528static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX;
529
530static struct drm_info_list radeon_debugfs_ring_info_list[] = {
531	{"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
532	{"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index},
533	{"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index},
534	{"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
535	{"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
536	{"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
537	{"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index},
538	{"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index},
539};
 
 
 
 
540
 
 
541#endif
542
543static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
544{
545#if defined(CONFIG_DEBUG_FS)
546	unsigned i;
547	for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
548		struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
549		int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
550		unsigned r;
551
552		if (&rdev->ring[ridx] != ring)
553			continue;
 
554
555		r = radeon_debugfs_add_files(rdev, info, 1);
556		if (r)
557			return r;
558	}
559#endif
560	return 0;
561}